59. Management data input/output (MDIOS)

59.1 MDIOS introduction

An MDIO bus can be useful in systems where a master chip needs to manage (configure and get status data from) one or multiple slave chips. The bus protocol uses only two signals:

• • MDC: the management data clock
• • MDIO: the data line carrying the opcode (write or read), the slave (port) address, the MDIOS register address, and the data

In each transaction, the master either reads the contents of an MDIOS register in one of its slaves, or it writes data to an MDIOS register in one of its slaves.

The MDIOS peripheral serves as a slave interface to an MDIO bus. An MDIO master can use the MDC/MDIO lines to write and read 32 16-bit MDIOS registers which are held in the MDIOS. These MDIOS registers are managed by the firmware, thus allowing the MDIO master to configure the application running on the STM32 and get status information from it.

The MDIOS can operate in Stop mode, optionally waking up the STM32 if the MDIO master performs a read or a write to one of its MDIOS registers.

59.2 MDIOS main features

The MDIOS includes the following features:

• • 32 MDIOS registers addresses, each of which is managed using separate input and output data registers:
  • – 32 x 16-bit firmware read/write, MDIOS read-only output data registers
  • – 32 x 16-bit firmware read-only, MDIOS write-only input data registers
• • Configurable slave (port) address
• • Independently maskable interrupts/events:
  • – MDIOS register write
  • – MDIOS register read
  • – MDIOS protocol error
• • Able to operate in and wake up from Stop mode

59.3 MDIOS functional description

59.3.1 MDIOS block diagram

Figure 726. MDIOS block diagram

59.3.2 MDIOS pins and internal signals

Table 468 lists the MDIOS inputs and output signals connected to package pins or balls, while Table 469 shows the internal PWR signals.

Table 468. MDIOS input/output signals connected to package pins or balls

Table 469. MDIOS internal input/output signals

59.3.3 MDIOS protocol

The MDIOS protocol uses two signals:

1. 1. MDIOS_MDC: the clock, always driven by the master
2. 2. MDIOS_MDIO: signal carrying the opcode, address, and bidirectional data

Each transaction is performed using a “frame”. Each frame contains 32 bits: 14 control bits, 2 turn-around bits, and then 16 data bits, each passed serially.

• • 14 control bits, driven by the master
  • – 2 start bits: always “01”
  • – 2 opcode bits: read=“10”, write=“01”
  • – 5 port address bits, indicating which slave device is being addressed
  • – 5 MDIOS register address bits, up to 32 MDIOS registers can be addressed in each slave
• • 2 turn-around state bits
  • – On write operations, the master drives “10”
  • – On read operations, the first bit is high-impedance, and the second bit is driven by the slave to ‘0’
• • 16 data bits
  • – On write operations, data written to slave’s MDIOS register is driven by the master
  • – On read operations, data read from slave’s MDIOS register is driven by the slave

Each frame is usually preceded by a preamble, where the MDIOS stays at ‘1’ for 32 MDC clocks. The master can continue to keep MDIO at ‘1’, indicating the “idle” condition, when it has no frame to send.

When MDIO signal is driven by the master, MDIOS samples it using the rising edge of MDC. When MDIOS drives MDIO, the output changes on the rising edge of MDC.

Figure 727. MDIO protocol write frame waveform

Figure 728. MDIO protocol read frame waveform

59.3.4 MDIOS enabling and disabling

The MDIOS is enabled by setting the EN bit in the MDIOS_CR register. When EN=1, the MDIOS monitors the MDIO bus and service frames addressed to one of its MDIOS registers.

When the MDIOS is enabled (setting EN to '1'), the same write operation to the MDIOS_CR register must properly set the PORT_ADDRESS[4:0] field to indicate the slave port address. A frame is ignored by the MDIOS if its port address is not the same as PORT_ADDRESS[4:0] (presumably intended for another slave).

When EN=0, the MDIOS ignores the frames being transmitted on the MDC/MDIO lines, and the IP is in a reduced consumption mode. Clearing EN also clears all of the DIN registers. If EN is cleared while the MDIOS is driving read data, it immediately releases the bus and does not drive the rest of the data. If EN is cleared while the MDIOS is receiving a frame, the frame is aborted and the data is lost.

When the MDIOS is enabled, then disabled and subsequently re-enabled, the status flags are not cleared. For a correct operation the firmware shall clear the status flag before re-enabling the MDIOS.

59.3.5 MDIOS data

From the point of view of the MDIO master, there are 32 16-bit MDIOS registers in the MDIOS which can be written and read. In reality, for each MDIOS register 'n' there are two sets of registers: DINn[15:0] and DOUTn[15:0].

Input data

When the MDIO master transmits a frame which writes to MDIOS register 'n' in the MDIOS, it is the DINn[15:0] register which is updated with the incoming data. The DIN registers (DIN0 - DIN31) can be read by the firmware, but they can be written only by the MDIO master via the MDIO bus.

The contents of DINn change immediately after the MDC rising edge when the last data bit is sampled.

If the firmware happens to read the contents of DINn at the moment that it is being updated, there is a possibility that the value read is corrupted (a bit-by-bit cross between the old value and the new value). For this reason, the firmware must assure that two subsequent reads from the same DINn register give the same value and assure that the data is stable when it is read . In the very worst case, the firmware needs to read DINn four times: first to get the old value, second to get an incoherent value (when reading at the moment the register changes), third to get the new value, and fourth to confirm the new value.

If the firmware uses the WRF interrupt and can guarantee that it reads the DINn register before any new MDIOS write frame completes, the firmware can perform a single read.

If the MDIO master performs a write operation with a register address that is greater than 31, the MDIOS ignores the frame (the data is not saved and no flag is set).

Output data

When the MDIOS receives a frame which requests to read register 'n', it returns the value found in the DOUTn[15:0] register. Thus, if the MDIO master expects to read the same value which it previously wrote to MDIOS register 'n', the firmware must copy the data from DINn to DOUTn each time new data is written to DINn. For correct operation, the firmware must copy the data to the DOUTn register within a preamble (if the master sends preambles before each frame) plus 15 cycles time.

When an MDIOS register is read via the MDIO bus, the MDIOS passes the 16-bit value (from the corresponding DOUTn register) to the MDIOS clock domain during the 15th cycle of the read frame. If the firmware attempts to write the DOUTn register while the MDIO Master is currently reading MDIOS register 'n', then the firmware write operation is ignored if it occurs during the 15th cycle of the frame (during a one-MDC-cycle window). Therefore, after writing a DOUTn register, the firmware must read back the same DOUTn register and confirm that the value was actually written. If the DOUTn register does not contain the value which was written, then the firmware can simply try writing and re-reading again.

If the MDIOS frequency is very slow compared to the mdios_pclk frequency, then it might be best not to tie up the CPU by continuously writing and re-reading a DOUT register. Please note that the read flag (RDFn) is set as soon as the DOUTn value is passed to the MDIOS clock domain. Thus, when a write to DOUTn is ignored (when the value read back is not the value which was just written), then the firmware can use a read interrupt to know when it is able to write DOUTn.

Here is a procedure which can be used if the MDC clock is very slow:

1. 1. Write DOUTn.
2. 2. Assure that all of the read flags are zero (MDIOS_RDFR = 0x0000). Clear the flags if necessary using MDIOS_CRDFR.
3. 3. Read back the same DOUTn register and compare the value with the value which was written in step 1.
4. 4. If the values are the same, then the procedure is done. Otherwise, continue to step 5.
5. 5. Enable read interrupts by setting the RDIE bit in MDIOS_CR1.
6. 6. In the interrupt routine, assure that RDFn is set. (no other read flags are set before bit n).
7. 7. There is a 31 cycle + preamble time window (if the master sends a preamble before each frame) to write DOUTn safely without doing a read-back and compare. If this maximum delay cannot be guaranteed, go back to step #1.

If the MDIO master performs a read operation with a register address which is greater than 31, the MDIOS returns a data value of all zeros.

59.3.6 MDIOS APB frequency

Whenever the firmware reads from an MDIOS_DINRn register or writes to an MDIOS_DOUTRn register, the frequency of the APB bus must be at least 1.5 times the MDC frequency. For example, if MDC is at 20MHz, the APB must be at 30MHz or faster.

59.3.7 Write/read flags and interrupts

When MDIOS register 'n' is written via the MDIO bus, the WRFn bit in the MDIOS_WRFR register is set. WRFn becomes '1' at the moment that DINn is updated, which is when the last data bit is sampled on a write frame. An interrupt is generated if WRIEN=1 (in the MDIOS_CR register). WRFn is cleared by software by writing '1' to CWRFn (in the MDIOS_CWRFR register).

When MDIOS register 'n' is read via the MDIO bus, the RDFn bit in the MDIOS_RDFR register is set. RDFn becomes '1' at the moment that DOUTn is copied to the MDC clock domain, which is on the 15th cycle of a read frame. An interrupt is generated if RDIEN=1 (in the MDIOS_CR register). RDFn is cleared by software by writing '1' to CRDFn (in the MDIOS_CRDFR register).

59.3.8 MDIOS error management

There are three types of errors with their corresponding error flags:

• • Preamble error: PERF (bit 0 of MDIOS_SR register)
• • Start error: SERF (bit 1 of MDIOS_SR register)
• • Turnaround error: TERF (bit 2 of MDIOS_SR register)

Each error flag is set by hardware when the corresponding error condition occurs. Each flag can be cleared by writing '1' to the corresponding bit in the clear flag register ( MDIOS_CLRFR ).

An interrupt occurs if any of the three error flags is set while EIE=1 ( MDIOS_CR ).

Besides setting an error flag, the MDIOS performs no action for a frame in which an error is detected: the DINn registers are not updated and the MDIO line is not forced during the data phase.

For a given frame, errors do not accumulate. For example, if a preamble error is detected, no check is done for a start error or a turnaround error for the rest of the current frame.

When DPC=0, following an detected error, all new frames and errors are ignored until a complete full preamble has been detected.

When DPC=1 (Disable Preamble Check, MDIOS_CR[7] ), all frames and new errors are ignored as long as one of the error flags is set. As soon as the error bit is cleared, the MDIOS starts looking for a start sequence. Thus, the application must clear the error flag only when it is sure that no frame is currently in progress. Otherwise, the MDIOS likely misinterprets the bits being sent and becomes desynchronized with the master.

Preamble errors

A preamble error occurs when a start sequence begins (with MDIO sampled at '0') without being immediately preceded by a preamble (MDIO sampled at '1' for at least 32 consecutive clocks).

Preamble errors are not reported after the MDIOS is first enabled (EN=1 in MDIOS_CR) until after a full preamble is received. This is to avoid an error condition when the peripheral frame detection is enabled while a preamble or frame is already in progress. In this case, the MDIOS ignores the first frame (since it did not first detect a full preamble), but does not set PERF.

If the DPC bit (Disable Preamble Check, MDIOS_CR[7]) is set, then the MDIO Master can send frames without preceding preambles and no preamble error is signaled. When DPC=1, the application must assure that the master is not in the process of sending a frame at the moment that the MDIOS is enabled (EN is set). Otherwise, the slave might become desynchronized with the master.

Start errors

A start error occurs when an illegal start sequence occurs or if an illegal command is given. The start sequence must always be “01”, and the command must be either “01” (write) or “10” (read).

As with preamble errors, start errors are not reported until after a full preamble is received.

Turnaround errors

A turnaround error occurs when an error is detected in the turnaround bits of write frames. The 15th bit of the write frame must be ‘1’ and the 16th bit must be ‘0’.

Turnaround errors are only reported after a full preamble is received, there is no start error, the port address in the current frame matches and the register address is in the supported range 0 to 31.

59.3.9 MDIOS in Stop mode

The MDIOS can operate in Stop mode, responding to all reads, performing all writes, and causing the STM32 to wakeup from Stop mode on MDIOS interrupts.

59.3.10 MDIOS interrupts

There is a single interrupt vector for the three types of interrupts (write, read, and error). Any of these interrupt sources can wake the STM32 up from Stop mode. All interrupt flags need to be cleared in order to clear the interrupt line.

Table 470. Interrupt control bits

59.4 MDIOS registers

59.4.1 MDIOS configuration register (MDIOS_CR)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 PORT_ADDRESS[4:0] : slave address

Can be written only when the peripheral is disabled (EN=0).

If the address given by the MDIO master matches PORT_ADDRESS[4:0], then the MDIOS services the frame. Otherwise the frame is ignored.

Bit 7 DPC : disable preamble check

0: MDIO master must give preamble before each frame.

1: MDIO master can send each frame without a preceding preamble, and the MDIOS does not signal a preamble error.

Note: When this bit is set, the application must be sure that no frame is currently in progress when the MDIOS is enabled. Otherwise, the MDIOS can become desynchronized with the master.

This bit cannot be changed unless EN = 0 (though it can be changed at the same time that EN is being set).

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 EIE : error interrupt enable

0: Interrupt is disabled.

1: Interrupt is enabled.

Note: When this bit is set, an interrupt is generated if any of the error flags (PERF, SERF, or TERF in the MDIOS_SR register) is set.

Bit 2 RDIE : register read interrupt enable

0: Interrupt is disabled.

1: Interrupt is enabled.

Note: When this bit is set, an interrupt is generated if any of the read flags (RDF[31:0] in the MDIOS_RDFR register) is set.

Bit 1 WRIE : register write interrupt enable

0: Interrupt is disabled.

1: Interrupt is enabled.

Note: When this bit is set, an interrupt is generated if any of the read flags (WRF[31:0] in the MDIOS_WRFR register) is set.

Bit 0 EN : peripheral enable

0: MDIOS is disabled.

1: MDIOS is enabled and monitoring the MDIO bus (MDC/MDIO).

59.4.2 MDIOS write flag register (MDIOS_WRFR)

Address offset: 0x04

Power-on reset value: 0x0000 0000

Bits 31:0 WRF[31:0] : write flags for MDIOS registers 0 to 31.

Each bit is set by hardware when the MDIO master performs a write to the corresponding MDIOS register. An interrupt is generated if WRIE (in MDIOS_CR) is set.

Each bit is cleared by software by writing '1' to the corresponding CWRF bit in the MDIOS_CWRFR register.

For WRFn:

0: MDIOS register n is not written by the MDIO master.

1: MDIOS register n is written by the MDIO master and the data is available in DINn[15:0] in the MDIOS_DINRn register.

59.4.3 MDIOS clear write flag register (MDIOS_CWRFR)

Address offset: 0x08

Power-on reset value: 0x0000 0000

Bits 31:0 CWRF[31:0] : clear the write flag

Writing 1 to CWRFn clears the WRFn bit in the MDIOS_WRF register.

59.4.4 MDIOS read flag register (MDIOS_RDFR)

Address offset: 0x0C

Power-on reset value: 0x0000 0000

Bits 31:0 RDF[31:0] : read flags for MDIOS registers 0 to 31.

Each bit is set by hardware when the MDIO master performs a read from the corresponding MDIOS register. An interrupt is generated if RDIE (in MDIOS_CR) is set.

Each bit is cleared by software by writing '1' to the corresponding CRDF bit in the MDIOS_CRDFR register.

For RDFn:

0: MDIOS register n is not read by the MDIO master.

1: MDIOS register n is read by the MDIO master.

59.4.5 MDIOS clear read flag register (MDIOS_CRDFR)

Address offset: 0x10

Power-on reset value: 0x0000 0000

Bits 31:0 CRDF[31:0] : clear the read flag

Writing 1 to CRDFn clears the RDFn bit in the MDIOS_RDF register.

59.4.6 MDIOS status register (MDIOS_SR)

Address offset: 0x14

Power-on reset value: 0x0000 0000

Writes to this register have no effect.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 TERF : turnaround error flag

0: No turnaround error has occurred.

1: A turnaround error has occurred.

Note: Writing 1 to CTERF (MDIOS_CLRFR) clears this bit.

Bit 1 SERF : start error flag

0: No start error has occurred.

1: A start error has occurred.

Note: Writing 1 to CSERF (MDIOS_CLRFR) clears this bit.

Bit 0 PERF : preamble error flag
0: No preamble error has occurred.
1: A preamble error has occurred.

Note: Writing 1 to CPERF (MDIOS_CLRFR) clears this bit.
This bit is not set if DPC (disable preamble check, MDIOS_CR[7]) is set.

59.4.7 MDIOS clear flag register (MDIOS_CLRFR)

Address offset: 0x18
Power-on reset value: 0x0000 0000
Reads on this register returns all zeros.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CTERF : clear the turnaround error flag
Writing 1 to this bit clears the TERF flag (in MDIOS_SR ).
When DPC = 1 ( MDIOS_CR[7] ), the TERF flag must be cleared only when there is not a frame already in progress.

Bit 1 CSERF : clear the start error flag
Writing 1 to this bit clears the SERF flag (in MDIOS_SR ).
When DPC = 1 ( MDIOS_CR[7] ), the SERF flag must be cleared only when there is not a frame already in progress.

Bit 0 CPERF : clear the preamble error flag
Writing 1 to this bit clears the PERF flag (in MDIOS_SR ).

59.4.8 MDIOS input data register x (MDIOS_DINRx)

Address offset: \( 0x100 + 0x04 \times x \) , (x = 0 to 31)
Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DINn[15:0] : input data received from MDIO master during write frames

This field is written by hardware with the 16-bit data received in a write frame which is addressed to MDIOS register n.

59.4.9 MDIOS output data register x (MDIOS_DOUTrx)

Address offset: 0x180 + 0x04 * x, (x = 0 to 31)

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DOUTn[15:0] : output data sent to MDIO Master during read frames

This field is written by software. These 16 bits are serially output on the MDIO bus during read frames which address the MDIOS register n.

59.4.10 MDIOS register map

Table 471. MDIOS register map and reset values

Table 471. MDIOS register map and reset values (continued)

Refer to Section 2.3 on page 131 for the register boundary addresses.