20. Extended interrupt and event controller (EXTI)

The Extended Interrupt and event controller (EXTI) manages wakeup through configurable and direct event inputs. It provides wakeup requests to the Power Control, and generates interrupt requests to the CPU NVIC and to the D3 domain DMAMUX2, and events to the CPU event input.

The EXTI wakeup requests allow the system to be woken up from Stop mode, and the CPU to be woken up from CStop mode.

Both the interrupt request and event request generation can also be used in Run modes.

20.1 EXTI main features

The EXTI main features are the following:

• • All Event inputs allow the CPU to wakeup and to generate a CPU interrupt and/or CPU event
• • Some Event inputs allow the user to wakeup the D3 domain for autonomous Run mode and generate an interrupt to the D3 domain, i.e. the DMAMUX2

The asynchronous event inputs are classified in 2 groups:

• • Configurable events (signals from I/Os or peripherals able to generate a pulse), they have the following features:
  • – Selectable active trigger edge
  • – Interrupt pending status register bit
  • – Individual Interrupt and Event generation mask
  • – SW trigger possibility
  • – Configurable System D3 domain wakeup events have a D3 Pending mask and status register and may have a D3 interrupt signal.
• • Direct events (interrupt and wakeup sources from other peripherals, requiring to be cleared in the peripheral), they feature
  • – Fixed rising edge active trigger
  • – No interrupt pending status register bit in the EXTI (the interrupt pending status is provided by the peripheral generating the event)
  • – Individual Interrupt and Event generation mask
  • – No SW trigger possibility
  • – Direct system D3 domain wakeup events have a D3 Pending mask and status register and may have a D3 interrupt signal

20.2 EXTI block diagram

As shown in Figure 91 , the EXTI consists of a Register block accessed via an APB interface, an Event input Trigger block, and a Masking block.

The Register block contains all EXTI registers.

The Event input trigger block provides Event input edge triggering logic.

The Masking block provides the Event input distribution to the different wakeup, interrupt and event outputs, and their masking.

Figure 91. EXTI block diagram

20.2.1 EXTI connections between peripherals, CPU, and D3 domain

The peripherals able to generate wakeup events when the system is in Stop mode or the CPU is in CStop mode are connected to an EXTI Configurable event input or Direct Event input:

• • Peripheral signals that generate a pulse are connected to an EXTI Configurable Event input. For these events the EXTI provides a CPU status pending bit that has to be cleared.
• • Peripheral Interrupt and Wakeup sources that have to be cleared in the peripheral are connected to an EXTI Direct Event input. There is no CPU status pending bit within the EXTI. The Interrupt or Wakeup is cleared by the CPU in the peripheral.

The Event inputs able to wakeup D3 for autonomous Run mode are provided with a D3 domain pending request function, that has to be cleared. This clearing request is taken care of by the signal selected by the Pending clear selection.

The CPU interrupts are connected to their respective CPU NVIC, and, similarly, the CPU event is connected to the CPU rxev input.

The EXTI Wakeup signals are connected to the PWR block, and are used to wakeup the D3 domain and/or the CPU.

The D3 domain interrupts allow the system to trigger events for D3 domain autonomous Run mode operation.

20.3 EXTI functional description

Depending on the EXTI Event input type and wakeup target(s), different logic implementations are used. The applicable features are controlled from register bits:

• • Active trigger edge enable, by EXTI rising trigger selection register (EXTI_RTSR1) , EXTI rising trigger selection register (EXTI_RTSR2) , EXTI rising trigger selection register (EXTI_RTSR3) , and EXTI falling trigger selection register (EXTI_FTSR1) , EXTI falling trigger selection register (EXTI_FTSR2) , EXTI falling trigger selection register (EXTI_FTSR3)
• • Software trigger, by EXTI software interrupt event register (EXTI_SWIER1) , EXTI software interrupt event register (EXTI_SWIER2) , EXTI software interrupt event register (EXTI_SWIER3)
• • CPU Interrupt enable, by EXTI interrupt mask register (EXTI_CPUIMR1) , EXTI interrupt mask register (EXTI_CPUIMR2) , EXTI interrupt mask register (EXTI_CPUIMR3)
• • CPU Event enable, by EXTI event mask register (EXTI_CPEUMR1) , EXTI event mask register (EXTI_CPEUMR2) , EXTI event mask register (EXTI_CPEUMR3)
• • D3 domain wakeup pending, by EXTI D3 pending mask register (EXTI_D3PMR1) , EXTI D3 pending mask register (EXTI_D3PMR2) , EXTI D3 pending mask register (EXTI_D3PMR3)

Table 141. EXTI Event input configurations and register control ⁽¹⁾

1. X indicates that functionality is available.

2. Waking-up D3 domain for autonomous Run mode, and/or CPU.

20.3.1 EXTI configurable event input - CPU wakeup

Figure 93 is a detailed representation of the logic associated with Configurable Event inputs which will always wake up the CPU.

Figure 92. Configurable event triggering logic CPU wakeup

The Software interrupt event register allows the system to trigger Configurable events by software, writing the EXTI software interrupt event register (EXTI_SWIER1) , the EXTI software interrupt event register (EXTI_SWIER2) , or the EXTI software interrupt event register (EXTI_SWIER3) register bit.

The rising edge EXTI rising trigger selection register (EXTI_RTSR1) , EXTI rising trigger selection register (EXTI_RTSR2) , EXTI rising trigger selection register (EXTI_RTSR3) , and falling edge EXTI falling trigger selection register (EXTI_FTSR1) , EXTI falling trigger selection register (EXTI_FTSR2) , EXTI falling trigger selection register (EXTI_FTSR3) selection registers allow the system to enable and select the Configurable event active trigger edge or both edges.

The devices feature dedicated interrupt mask registers, namely EXTI interrupt mask register (EXTI_CPUIMR1) and EXTI interrupt mask register (EXTI_CPUIMR2) , EXTI interrupt mask register (EXTI_CPUIMR3) , and EXTI pending register (EXTI_CPUPR1) , EXTI pending register (EXTI_CPUPR2) , EXTI pending register (EXTI_CPUPR3) for Configurable events pending request registers. The CPU pending register will only be set for an unmasks CPU interrupt. Each event provides a individual CPU interrupt to the CPU NVIC. The Configurable events interrupts need to be acknowledged by software in the EXTI_CPUPR register.

The devices feature dedicated event mask registers, i.e. EXTI event mask register (EXTI_CPUEMR1) , EXTI event mask register (EXTI_CPUEMR2) , and EXTI event mask register (EXTI_CPUEMR3) . The enabled event then generates an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The CPU Pending register (EXTI_CPUPR) will not be set for an unmasked CPU event.

When a CPU interrupt or CPU event is enabled, the Asynchronous edge detection circuit is reset by the clocked Delay and Rising edge detect pulse generator. This guarantees that the CPU clock is woken up before the Asynchronous edge detection circuit is reset.

Note: A detected Configurable event, enabled by the CPU, is only cleared when the CPU wakes up.

20.3.2 EXTI configurable event input - any wakeup

Figure 93 is a detailed representation of the logic associated with Configurable Event inputs that can wakeup D3 domain for autonomous Run mode and/or CPU (“Any” target). It provides the same functionality as the Configurable event input CPU wakeup, with additional functionality to wake up the D3 domain independently.

When all CPU interrupts and CPU events are disabled, the Asynchronous edge detection circuit is reset by the D3 domain clocked Delay and Rising edge detect pulse generator. This guarantees that the D3 domain clock is woken up before the Asynchronous edge detection circuit is reset.

Table 142. Configurable event input asynchronous edge detector reset

Figure 93. Configurable event triggering logic - any wakeup

The event triggering logic for “Any” target has additional D3 Pending mask register EXTI D3 pending mask register (EXTI_D3PMR1) , EXTI D3 pending mask register (EXTI_D3PMR2) , EXTI D3 pending mask register (EXTI_D3PMR3) and D3 Pending request logic. The D3 Pending request logic will only be set for unmasked D3 Pending events. The D3 Pending request logic keeps the D3 domain in Run mode until the D3 Pending request logic is cleared by the selected D3 domain pendclear source.

20.3.3 EXTI direct event input - CPU wakeup

Figure 94 is a detailed representation of the logic associated with Direct Event inputs waking up the CPU.

Direct events only provide CPU interrupt enable and CPU event enable functionality.

Figure 94. Direct event triggering logic CPU wakeup

1. 1. The CPU interrupt for asynchronous Direct Event inputs (peripheral Wakeup signals) is synchronized with the CPU clock. The synchronous Direct Event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt without resynchronization.

20.3.4 EXTI direct event input - any wakeup

Figure 95 is a detailed representation of the logic associated with Direct Event inputs waking up D3 domain for autonomous Run mode and/or CPU, (“Any” target). It provides the same functionality as the Direct event input CPU wakeup, plus additional functionality to wakeup the D3 domain independently.

Figure 95. Direct event triggering logic - any wakeup

1. 1. The CPU interrupt and D3 domain interrupt for asynchronous Direct Event inputs (peripheral Wakeup signals) are synchronized, respectively, with the CPU clock and the D3 domain clock. The synchronous Direct Event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt and the D3 domain interrupt without resynchronization in the EXTI.

20.3.5 EXTI D3 pending request clear selection

Event inputs able to wake up D3 domain for autonomous Run mode have D3 Pending request logic that can be cleared by the selected D3 pendclear source. For each D3 Pending request a D3 domain pendclear source can be selected from four different inputs.

Figure 96 is a detailed representation of the logic selecting the D3 pendclear source.

The D3 Pending request clear selection registers EXTI D3 pending clear selection register low (EXTI_D3PCR1L) , EXTI D3 pending clear selection register high (EXTI_D3PCR1H) , EXTI D3 pending clear selection register low (EXTI_D3PCR2L) , EXTI D3 pending clear selection register high (EXTI_D3PCR2H) , EXTI D3 pending clear selection register low (EXTI_D3PCR2L) and EXTI D3 pending clear selection register high (EXTI_D3PCR3H) allow the system to select the source to reset the D3 Pending request.

20.4 EXTI event input mapping

For the sixteen GPIO Event inputs the associated IOPORT pin has to be selected in the SYSCFG register SYSCFG_EXTICRn. The same pin from each IOPORT maps to the corresponding EXTI Event input.

The wakeup capabilities of each Event input are detailed in Table 143 . An Event input can either wake up the CPU, and in the case of “Any” can also wake up D3 domain for autonomous Run mode.

The EXTI Event inputs with a connection to the CPU NVIC are indicated in the Connection to NVIC column. For the EXTI events not having a connection to the NVIC, the peripheral interrupt is directly connected to the NVIC in parallel with the connection to the EXTI.

All EXTI Event inputs are OR-ed together and connected to the CPU event input (rxev).

Table 143. EXTI Event input mapping

Table 143. EXTI Event input mapping (continued)

Table 143. EXTI Event input mapping (continued)

1. 1. PVD and AVD signals are OR-ed together on the same EXTI event input.
2. 2. RTC Tamper, RTC timestamp and RCC LSECSS signals are OR-ed together on the same EXTI event input.
3. 3. Not available on CPU NVIC, to be used for system wakeup only or CPU event input (rxev).
4. 4. Available on CPU NVIC directly from the peripheral

20.5 EXTI functional behavior

The Direct event inputs are enabled in the respective peripheral generating the event. The Configurable events are enabled by enabling at least one of the trigger edges.

When in Stop mode an event will always wake up the D3 domain. In system Run and Stop modes an event will always generate an associated D3 domain interrupt. An event will only wake up the CPU when the event associated CPU interrupt is unmasked and/or the CPU event is unmasked.

Table 144. Masking functionality

1. 1. Only for Event inputs that allow the system to wakeup D3 domain for autonomous Run mode (Any target).
2. 2. For Event inputs that will always wake up CPU.

For Configurable event inputs, when the enabled edge(s) occur on the event input, an event request is generated. When the associated CPU interrupt is unmasked, the corresponding pending PRx bit in EXTI_CPUPR is set and the CPU interrupt signal is activated. EXTI_CPUPR PRx pending bit shall be cleared by software writing it to '1'. This will clear the CPU interrupt.

For Direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit. When the associated CPU interrupt is unmasked the corresponding CPU interrupt signal is activated.

The CPU event has to be unmasked to generate an event. When the enabled edge(s) occur on the Event input a CPU event pulse is generated. There is no CPU event pending bit.

Both a CPU interrupt and a CPU event may be enabled on the same Event input. They will both trigger the same Event input condition(s).

For the Configurable Event inputs an event input request can be generated by software when writing a '1' in the software interrupt/event register EXTI_SWIER.

Whenever an Event input is enabled and a CPU interrupt and/or CPU event is unmasked, the Event input will also generate a D3 domain wakeup next to the CPU wakeup.

Some Event inputs are able to wakeup the D3 domain autonomous Run mode, in this case the CPU interrupt and CPU event are masked, preventing the CPU to be woken up. Two D3 domain autonomous Run mode wakeup mechanisms are supported:

• • D3 domain wakeup without pending (EXTI_D3PMR = 0)
  • – On a Configurable Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal automatically after the Delay + Rising Edge detect Pulse generator.
  • – On a Direct Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal after the Direct Event input signal is cleared.
• • D3 domain wakeup with pending (EXTI_D3PMR = 1)
  • – On a Configurable Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal after the Delay + Rising Edge detect Pulse generator and when the D3 Pending request is cleared.
  • – On a Direct Event input this mechanism will wake up D3 domain and clear the D3 domain wakeup signal after the Direct Event input signal is cleared and when the D3 Pending request is cleared.

20.5.1 EXTI CPU interrupt procedure

• • Unmask the Event input interrupt by setting the corresponding mask bits in the EXTI_CPUIMR register.
• • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• • Enable the associated interrupt source in the CPU NVIC or use the SEVONPEND, so that an interrupt coming from the CPU interrupt signal is detectable by the CPU after a WFI/WFE instruction.
  • – For Configurable event inputs the associated EXTI pending bit needs to be cleared.

20.5.2 EXTI CPU event procedure

• • Unmask the Event input by setting the corresponding mask bits of the EXTI_CPUEMR register.
• • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• • The CPU event signal is detected by the CPU after a WFE instruction.
  • – For Configurable event inputs there is no EXTI pending bit to clear.

20.5.3 EXTI CPU wakeup procedure

• • Unmask the Event input by setting at least one of the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers. The CPU wakeup is generated at the same time as the unmasked CPU interrupt and/or CPU event.
• • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• • Direct Events will automatically generate a CPU wakeup.

20.5.4 EXTI D3 domain wakeup for autonomous Run mode procedure

• • Mask the Event input for waking up the CPU, by clearing both the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers.
• • For Configurable Event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
• • Direct Events will automatically generate a D3 domain wakeup.
• • Select the D3 domain wakeup mechanism in EXTI_D3PMR.
  • – When D3 domain wakeup without pending (EXTI_PMR = 0) is selected, the Wakeup will be cleared automatically following the clearing of the Event input.
  • – When D3 domain wakeup with pending (EXTI_PMR = 1) is selected the Wakeup needs to be cleared by a selected D3 domain pendclear source.
    A pending D3 domain wakeup signal can also be cleared by FW clearing the associated EXTI_D3PMR register bit.
• • After the D3 domain wakeup a D3 domain interrupt is generated.
  • – Configurable Event inputs will generate a pulse on D3 domain interrupt.
  • – Direct Event inputs will activate the D3 domain interrupt until the event input is cleared in the peripheral.

20.5.5 EXTI software interrupt/event trigger procedure

Any of the Configurable Event inputs can be triggered from the software interrupt/event register (the associated CPU interrupt and/or CPU event shall be enabled by their respective procedure).

• • Enable the Event input by setting at least one of the corresponding edge trigger bits in the EXTI_RTSR and/or EXTI_FTSR registers.
• • Unmask the software interrupt/event trigger by setting at least one of the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers.
• • Trigger the software interrupt/event by writing “1” to the corresponding bit in the EXTI_SWIER register.
• • The Event input may be disabled by clearing the EXTI_RTSR and EXTI_FTSR register bits.

Note: An edge on the Configurable event input will also trigger an interrupt/event.

A software trigger can be used to set the D3 Pending request logic, keeping the D3 domain in Run until the D3 Pending request logic is cleared.

20.6 EXTI registers

Every register can only be accessed with 32-bit (word). A byte or half-word cannot be read or written.

20.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 TR[21:0] : Rising trigger event configuration bit of Configurable Event input x. ⁽¹⁾

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

1. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set.
   Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger.

20.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 TR[21:0] : Falling trigger event configuration bit of Configurable Event input x. ⁽¹⁾

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

1. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set.
   Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger.

20.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 SWIER[21:0] : Software interrupt on line x

This bitfield always returns 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.

20.6.4 EXTI D3 pending mask register (EXTI_D3PMR1)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 MR25 : D3 Pending Mask on Event input x

0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

Bits 24:22 Reserved, must be kept at reset value.

Bits 21:19 MR[21:19] : D3 Pending Mask on Event input x

0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

Bits 18:16 Reserved, must be kept at reset value.

Bits 15:0 MR[15:0] : D3 Pending Mask on Event input x

0: D3 Pending request from Line x is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

20.6.5 EXTI D3 pending clear selection register low (EXTI_D3PCR1L)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:0 PCS[15:0][1:0] : D3 Pending request clear input signal selection on Event input x = truncate (n/2)

00: DMA ch6 event selected as D3 domain pendclear source

01: DMA ch7 event selected as D3 domain pendclear source

10: LPTIM4 out selected as D3 domain pendclear source

11: LPTIM5 out selected as D3 domain pendclear source

20.6.6 EXTI D3 pending clear selection register high (EXTI_D3PCR1H)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 PCS25[1:0] : D3 Pending request clear input signal selection on Event input 25 = truncate \( ((n+32)/2) \)

• 00: DMA ch6 event selected as D3 domain pendclear source
• 01: DMA ch7 event selected as D3 domain pendclear source
• 10: LPTIM4 out selected as D3 domain pendclear source
• 11: LPTIM5 out selected as D3 domain pendclear source

Bits 17:12 Reserved, must be kept at reset value.

Bits 11:6 PCS[21:19][1:0] : D3 Pending request clear input signal selection on Event input x = truncate \( ((n+32)/2) \) (x = 21 to 19)

• 00: DMA ch6 event selected as D3 domain pendclear source
• 01: DMA ch7 event selected as D3 domain pendclear source
• 10: LPTIM4 out selected as D3 domain pendclear source
• 11: LPTIM5 out selected as D3 domain pendclear source

Bits 5:0 Reserved, must be kept at reset value.

20.6.7 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TR51 : Rising trigger event configuration bit of Configurable Event input x+32. ⁽¹⁾

• 0: Rising trigger disabled (for Event and Interrupt) for input line
• 1: Rising trigger enabled (for Event and Interrupt) for input line

Bit 18 Reserved, must be kept at reset value.

Bit 17 TR49 : Rising trigger event configuration bit of Configurable Event input x+32. ⁽¹⁾

• 0: Rising trigger disabled (for Event and Interrupt) for input line
• 1: Rising trigger enabled (for Event and Interrupt) for input line

Bits 16:0 Reserved, must be kept at reset value.

1. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set.
   Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger.

20.6.8 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TR51 : Falling trigger event configuration bit of Configurable Event input x+32. ⁽¹⁾

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line

Bit 18 Reserved, must be kept at reset value.

Bit 17 TR49 : Falling trigger event configuration bit of Configurable Event input x+32. ⁽¹⁾

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line

Bits 16:0 Reserved, must be kept at reset value.

1. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set.
   Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger.

20.6.9 EXTI software interrupt event register (EXTI_SWIER2)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 SWIER51 : Software interrupt on line x+32

Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.

Bit 18 Reserved, must be kept at reset value.

Bit 17 SWIER49 : Software interrupt on line x+32

Will always return 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.

Bits 16:0 Reserved, must be kept at reset value.

20.6.10 EXTI D3 pending mask register (EXTI_D3PMR2)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:16 MR[53:48] : D3 Pending Mask on Event input x+32

0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MR41 : D3 Pending Mask on Event input x+32

0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

Bits 8:4 Reserved, must be kept at reset value.

Bits 3:2 MR[35:34] : D3 Pending Mask on Event input x+32

0: D3 Pending request from Line x+32 is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x+32 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

Bits 1:0 Reserved, must be kept at reset value.

20.6.11 EXTI D3 pending clear selection register low (EXTI_D3PCR2L)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 PCS41[1:0] : D3 Pending request clear input signal selection on Event input x = truncate \( ((n+64)/2) \)

• 00: DMA ch6 event selected as D3 domain pendclear source
• 01: DMA ch7 event selected as D3 domain pendclear source
• 10: LPTIM4 out selected as D3 domain pendclear source
• 11: LPTIM5 out selected as D3 domain pendclear source

Bits 17:8 Reserved, must be kept at reset value.

Bits 7:4 PCS[35:34][1:0] : D3 Pending request clear input signal selection on Event input x= truncate \( ((n+64)/2) \)

• 00: DMA ch6 event selected as D3 domain pendclear source
• 01: DMA ch7 event selected as D3 domain pendclear source
• 10: LPTIM4 out selected as D3 domain pendclear source
• 11: LPTIM5 out selected as D3 domain pendclear source

Bits 3:0 Reserved, must be kept at reset value.

20.6.12 EXTI D3 pending clear selection register high (EXTI_D3PCR2H)

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 PCS[53:48][1:0] : D3 Pending request clear input signal selection on Event input x= truncate \( ((n+96)/2) \)

00: DMA ch6 event selected as D3 domain pendclear source

01: DMA ch7 event selected as D3 domain pendclear source

10: LPTIM4 out selected as D3 domain pendclear source

11: LPTIM5 out selected as D3 domain pendclear source

20.6.13 EXTI rising trigger selection register (EXTI_RTSR3)

Address offset: 0x40

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 TR[86:85] : Rising trigger event configuration bit of Configurable Event input x+64. ⁽¹⁾

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

Bits 20:0 Reserved, must be kept at reset value.

1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a rising edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set.
   Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger.

20.6.14 EXTI falling trigger selection register (EXTI_FTSR3)

Address offset: 0x44

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 TR[86:85] : Falling trigger event configuration bit of Configurable Event input x+64. ⁽¹⁾

0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line

Bits 20:0 Reserved, must be kept at reset value.

1. 1. The Configurable event inputs are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the Configurable event input occurs during writing of the register, the associated pending bit will not be set.
   Rising and falling edge triggers can be set for the same Configurable Event input. In this case, both edges generate a trigger.

20.6.15 EXTI software interrupt event register (EXTI_SWIER3)

Address offset: 0x48

Reset value: 0x0000 0000

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 SWIER[86:85] : Software interrupt on line x+64

Will alway return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit will trigger an event on line x. This bit is auto cleared by HW.

Bits 20:0 Reserved, must be kept at reset value.

20.6.16 EXTI D3 pending mask register (EXTI_D3PMR3)

Address offset: 0x4C

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 MR88 : D3 Pending Mask on Event input x+64

0: D3 Pending request from Line x+64 is masked. Writing this bit to 0 will also clear the D3 Pending request.

1: D3 Pending request from Line x+64 is unmasked. The D3 domain pending signal when triggered will keep D3 domain wakeup active until cleared.

Bits 23:0 Reserved, must be kept at reset value.

20.6.17 EXTI D3 pending clear selection register high (EXTI_D3PCR3H)

Address offset: 0x54

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:16 PCS88[1:0] : D3 Pending request clear input signal selection on Event input x= truncate \( \text{((n+160)/2)} \)

00: DMA ch6 event selected as D3 domain pendclear source

01: DMA ch7 event selected as D3 domain pendclear source

10: LPTIM4 out selected as D3 domain pendclear source

11: LPTIM5 out selected as D3 domain pendclear source

Bits 15:0 Reserved, must be kept at reset value.

20.6.18 EXTI interrupt mask register (EXTI_CPUIMR1)

Address offset: 0x80

Reset value: 0xFFC0 0000

Bits 31:22 MR[31:22] : CPU interrupt Mask on Direct Event input x ⁽¹⁾

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Bits 21:0 MR[21:0] : CPU interrupt Mask on Configurable Event input x ⁽²⁾

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

1. 1. The reset value for Direct Event inputs is set to '1' in order to enable the interrupt by default.
2. 2. The reset value for Configurable Event inputs is set to '0' in order to disable the interrupt by default.

20.6.19 EXTI event mask register (EXTI_CPUEMR1)

Address offset: 0x84

Reset value: 0x0000 0000

Bits 31:0 MR[31:0] : CPU Event mask on Event input x

0: Event request from Line x is masked

1: Event request from Line x is unmasked

20.6.20 EXTI pending register (EXTI_CPUPR1)

Address offset: 0x88

Reset value: undefined

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 PR[21:0] : Configurable event inputs x Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.

20.6.21 EXTI interrupt mask register (EXTI_CPUIMR2)

Address offset: 0x90

Reset value: 0xFFF5 FFFF

Bits 31:28 MR[63:60] : CPU Interrupt Mask on Direct Event input x+32 ⁽¹⁾ (x = 63 to 60)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Bit 27 Reserved, must be kept at reset value ⁽¹⁾ .

Bit 26 MR58 : CPU Interrupt Mask on Direct Event input 58+32 ⁽¹⁾

0: Interrupt request from Line 58 is masked

1: Interrupt request from Line 58 is unmasked

Bit 25 Reserved, must be kept at reset value ⁽¹⁾ .

Bits 24:20 MR[56:52] : CPU Interrupt Mask on Direct Event input x+32 ⁽¹⁾ (x = 56 to 52)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Bit 19 MR51 : CPU interrupt Mask on Configurable Event input 51+32 ⁽²⁾

0: Interrupt request from Line 51 is masked

1: Interrupt request from Line 51 is unmasked

Bit 18 MR50 : CPU Interrupt Mask on Direct Event input 50+32 ⁽¹⁾

0: Interrupt request from Line 50 is masked

1: Interrupt request from Line 50 is unmasked

Bit 17 MR49 : CPU interrupt Mask on Configurable Event input 49+32 ⁽²⁾

0: Interrupt request from Line 49 is masked

1: Interrupt request from Line 49 is unmasked

Bits 16:15 MR[48:47] : CPU Interrupt Mask on Direct Event input x+32 ⁽¹⁾ (x = 48 to 47)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Bits 14:12 Reserved, must be kept at reset value ⁽¹⁾ .

Bits 11:0 MR[43:32] : CPU Interrupt Mask on Direct Event input x+32 ⁽¹⁾ (x = 43 to 32)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

1. 1. The reset value for Direct Event inputs is set to '1' in order to enable the interrupt by default.
2. 2. The reset value for Configurable Event inputs is set to '0' in order to disable the interrupt by default.

20.6.22 EXTI event mask register (EXTI_CPUEMR2)

Address offset: 0x94

Reset value: 0x0000 0000

Bits 31:28 MR[63:60] : CPU Event mask on Event input x+32 (x = 63 to 60)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

Bit 27 Reserved, must be kept at reset value.

Bit 26 MR[58] : CPU Event mask on Event input 58+32

0: Event request from Line 58 is masked

1: Event request from Line 58 is unmasked

Bit 25 Reserved, must be kept at reset value.

Bits 24:14 MR[56:47] : CPU Event mask on Event input x+32 (x = 56 to 47)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

Bits 14:12 Reserved, must be kept at reset value.

Bits 11:0 MR[43:0] : CPU Event mask on Event input x+32 (x = 43 to 0)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

20.6.23 EXTI pending register (EXTI_CPUPR2)

Address offset: 0x98

Reset value: undefined

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 PR51 : Configurable event inputs 51+32 Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.

Bit 18 Reserved, must be kept at reset value.

Bit 17 PR49 : Configurable event inputs 49+32 Pending bit

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.

Bits 16:0 Reserved, must be kept at reset value.

20.6.24 EXTI interrupt mask register (EXTI_CPUIMR3)

Address offset: 0xA0

Reset value: 0x0F8B FFFF

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:23 MR[91:87] : CPU Interrupt Mask on Direct Event input x+64 ⁽¹⁾ (x = 91 to 87)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Bits 22:21 MR[86:85] : CPU interrupt Mask on Configurable Event input x+64 ⁽²⁾ (x = 86 to 85)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Bits 20:17 Reserved, must be kept at reset value.

Bit 16 MR16 : CPU Interrupt Mask on Direct Event input 80+64 ⁽¹⁾

0: Interrupt request from Line 80 is masked

1: Interrupt request from Line 80 is unmasked

Bit 15 Reserved, must be kept at reset value.

Bits 14:0 MR[78: 64] : CPU Interrupt Mask on Direct Event input x+64 ⁽¹⁾ (x = 78 to 64)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

1. 1. The reset value for Direct Event inputs is set to '1' in order to enable the interrupt by default.
2. 2. The reset value for Configurable Event inputs is set to '0' in order to disable the interrupt by default.

20.6.25 EXTI event mask register (EXTI_CPUEMR3)

Address offset: 0xA4

Reset value: 0x0000 0000

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:21 MR[91:21] : CPU Event mask on Event input x+64 (x = 91 to 21)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

Bits 20:17 Reserved, must be kept at reset value.

Bit 16 MR80 : CPU Event mask on Event input 80+64

0: Event request from Line 80 is masked

1: Event request from Line 80 is unmasked

Bit 15 Reserved, must be kept at reset value.

Bits 14:0 MR[78:64] : CPU Event mask on Event input x+64 (x = 78 to 64)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

20.6.26 EXTI pending register (EXTI_CPUPR3)

Address offset: 0xA8

Reset value: undefined

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 PR[86:84] : Configurable event inputs x+64 Pending bit (x = 86 to 84)

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.

20.6.27 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 145. Asynchronous interrupt/event controller register map and reset values

Table 145. Asynchronous interrupt/event controller register map and reset values (continued)

Table 145. Asynchronous interrupt/event controller register map and reset values (continued)

Refer to Section 2.3 on page 131 for the register boundary addresses.