17. DMA request multiplexer (DMAMUX)

17.1 Introduction

A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is deasserted.

In this document, the set of control signals required for the DMA request/acknowledge protocol is not explicitly shown or described, and it is referred to as DMA request line.

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controllers of the product. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. The DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

The number of DMAMUX instances and their main characteristics are specified in Section 17.3.1 .

The assignment of DMAMUX request multiplexer inputs to the DMA request lines from peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX synchronizations and trigger inputs to internal and external signals depend on the product implementation, and are detailed in Section 17.3.2 .

17.2 DMAMUX main features

• Up to 16-channel programmable DMA request line multiplexer output
• Up to 8-channel DMA request generator
• Up to 32 trigger inputs to DMA request generator
• Up to 16 synchronization inputs
• Per DMA request generator channel:
- – DMA request trigger input selector
- – DMA request counter
- – Event overrun flag for selected DMA request trigger input
• Per DMA request line multiplexer channel output:
- – Up to 129 input DMA request lines from peripherals
- – One DMA request line output
- – Synchronization input selector
- – DMA request counter
- – Event overrun flag for selected synchronization input
- – One event output, for DMA request chaining

17.3 DMAMUX implementation

17.3.1 DMAMUX1 and DMAMUX2 instantiation

The product integrates two instances of DMA request multiplexer:

• DMAMUX1 for DMA1 and DMA2 (D2 domain)
• DMAMUX2 for BDMA (D3 domain)

DMAMUX1 and DMAMUX2 are instantiated with the hardware configuration parameters listed in the following table.

Table 117. DMAMUX1 and DMAMUX2 instantiation

Feature	DMAMUX1	DMAMUX2
Number of DMAMUX output request channels	16	8
Number of DMAMUX request generator channels	8	8
Number of DMAMUX request trigger inputs	8	32
Number of DMAMUX synchronization inputs	8	16
Number of DMAMUX peripheral request inputs	129	12

17.3.2 DMAMUX1 mapping

The mapping of resources to DMAMUX1 is hardwired.

DMAMUX1 is used with DMA1 and DMA2 in D2 domain

• DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7
• DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7

Table 118. DMAMUX1: assignment of multiplexer inputs to resources

DMA request MUX input	Resource	DMA request MUX input	Resource	DMA request MUX input	Resource
1	dmamux1_req_gen0	47	TIM8_CH1	93	spdifrx_dat_dma
2	dmamux1_req_gen1	48	TIM8_CH2	94	spdifrx_ctrl_dma
3	dmamux1_req_gen2	49	TIM8_CH3	95	Reserved
4	dmamux1_req_gen3	50	TIM8_CH4	96	Reserved
5	dmamux1_req_gen4	51	TIM8_UP	97	Reserved
6	dmamux1_req_gen5	52	TIM8_TRIG	98	Reserved
7	dmamux1_req_gen6	53	TIM8_COM	99	Reserved
8	dmamux1_req_gen7	54	Reserved	100	Reserved
9	adc1_dma	55	TIM5_CH1	101	dfsdm1_dma0
10	adc2_dma	56	TIM5_CH2	102	dfsdm1_dma1
11	TIM1_CH1	57	TIM5_CH3	103	dfsdm1_dma2
12	TIM1_CH2	58	TIM5_CH4	104	dfsdm1_dma3
13	TIM1_CH3	59	TIM5_UP	105	TIM15_CH1
14	TIM1_CH4	60	TIM5_TRIG	106	TIM15_UP
15	TIM1_UP	61	spi3_rx_dma	107	TIM15_TRIG
16	TIM1_TRIG	62	spi3_tx_dma	108	TIM15_COM
17	TIM1_COM	63	uart4_rx_dma	109	TIM16_CH1
18	TIM2_CH1	64	uart4_tx_dma	110	TIM16_UP
19	TIM2_CH2	65	uart5_rx_dma	111	TIM17_CH1
20	TIM2_CH3	66	uart5_tx_dma	112	TIM17_UP
21	TIM2_CH4	67	dac_ch1_dma	113	Reserved
22	TIM2_UP	68	dac_ch2_dma	114	Reserved
23	TIM3_CH1	69	TIM6_UP	115	adc3_dma
24	TIM3_CH2	70	TIM7_UP	116	uart9_rx_dma
25	TIM3_CH3	71	usart6_rx_dma	117	uart9_tx_dma
26	TIM3_CH4	72	usart6_tx_dma	118	uart10_rx_dma
27	TIM3_UP	73	i2c3_rx_dma	119	uart10_tx_dma
28	TIM3_TRIG	74	i2c3_tx_dma	120	FMAC_RD
29	TIM4_CH1	75	dcmi_dma	121	FMAC_WR
30	TIM4_CH2	76	cryp_in_dma	122	CORDIC_RD
31	TIM4_CH3	77	cryp_out_dma	123	CORDIC_WR
32	TIM4_UP	78	hash_in_dma	124	i2c5_rx_dma
33	i2c1_rx_dma	79	uart7_rx_dma	125	i2c5_tx_dma
34	i2c1_tx_dma	80	uart7_tx_dma	126	TIM23_CH1
35	i2c2_rx_dma	81	uart8_rx_dma	127	TIM23_CH2
36	i2c2_tx_dma	82	uart8_tx_dma	128	TIM23_CH3

Table 118. DMAMUX1: assignment of multiplexer inputs to resources (continued)

DMA request MUX input	Resource	DMA request MUX input	Resource	DMA request MUX input	Resource
37	spi1_rx_dma	83	spi4_rx_dma	129	TIM23_CH4
38	spi1_tx_dma	84	spi4_tx_dma	130	TIM23_UP
39	spi2_rx_dma	85	spi5_rx_dma	131	TIM23_TRIG
40	spi2_tx_dma	86	spi5_tx_dma	132	TIM24_CH1
41	usart1_rx_dma	87	sai1a_dma	133	TIM24_CH2
42	usart1_tx_dma	88	sai1b_dma	134	TIM24_CH3
43	usart2_rx_dma	89	Reserved	135	TIM24_CH4
44	usart2_tx_dma	90	Reserved	136	TIM24_UP
45	usart3_rx_dma	91	swpmi_rx_dma	137	TIM24_TRIG
46	usart3_tx_dma	92	swpmi_tx_dma	-	-

Table 119. DMAMUX1: assignment of trigger inputs to resources

Trigger input	Resource	Trigger input	Resource
0	dmamux1_evt0	4	lptim2_out
1	dmamux1_evt1	5	lptim3_out
2	dmamux1_evt2	6	extit0
3	lptim1_out	7	TIM12_TRGO

Table 120. DMAMUX1: assignment of synchronization inputs to resources

Sync. input	Resource	Sync. input	Resource
0	dmamux1_evt0	4	lptim2_out
1	dmamux1_evt1	5	lptim3_out
2	dmamux1_evt2	6	extit0
3	lptim1_out	7	TIM12_TRGO

17.3.3 DMAMUX2 mapping

DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7.

Table 121. DMAMUX2: assignment of multiplexer inputs to resources

DMA request MUX input	Resource	DMA request MUX input	Resource
1	dmamux2_req_gen0	17	adc3_dma
2	dmamux2_req_gen1	18	Reserved
3	dmamux2_req_gen2	19	Reserved
4	dmamux2_req_gen3	20	Reserved
5	dmamux2_req_gen4	21	Reserved

Table 121. DMAMUX2: assignment of multiplexer inputs to resources (continued)

DMA request MUX input	Resource	DMA request MUX input	Resource
6	dmamux2_req_gen5	22	Reserved
7	dmamux2_req_gen6	23	Reserved
8	dmamux2_req_gen7	24	Reserved
9	lpuart1_rx_dma	25	Reserved
10	lpuart1_tx_dma	26	Reserved
11	spi6_rx_dma	27	Reserved
12	spi6_tx_dma	28	Reserved
13	i2c4_rx_dma	29	Reserved
14	i2c4_tx_dma	30	Reserved
15	sai4_a_dma	31	Reserved
16	sai4_b_dma	32	Reserved

Table 122. DMAMUX2: assignment of trigger inputs to resources

Trigger input	Resource	Trigger input	Resource
0	dmamux2_evt0	16	spi6_wkup
1	dmamux2_evt1	17	Comp1_out
2	dmamux2_evt2	18	Comp2_out
3	dmamux2_evt3	19	RTC_wkup
4	dmamux2_evt4	20	Syscfg_exti0_mux
5	dmamux2_evt5	21	Syscfg_exti2_mux
6	dmamux2_evt6	22	i2c4_event_it
7	lpuart_rx_wkup	23	spi6_it
8	lpuart_tx_wkup	24	Lpuart1_it_T
9	lptim2_wkup	25	Lpuart1_it_R
10	lptim2_out	26	adc3_it
11	lptim3_wkup	27	adc3_awd1
12	lptim3_out	28	bdma_ch0_it
13	Lptim4_ait	29	bdma_ch1_it
14	Lptim5_ait	30	Reserved
15	i2c4_wkup	31	Reserved

Table 123. DMAMUX2: assignment of synchronization inputs to resources

Sync input	Resource	Sync input	Resource
0	dmamux2_evt0	16	Reserved
1	dmamux2_evt1	17	Reserved
2	dmamux2_evt2	18	Reserved

Table 123. DMAMUX2: assignment of synchronization inputs to resources

Sync input	Resource	Sync input	Resource
3	dmamux2_evt3	19	Reserved
4	dmamux2_evt4	20	Reserved
5	dmamux2_evt5	21	Reserved
6	lpuart1_rx_wkup	22	Reserved
7	lpuart1_tx_wkup	23	Reserved
8	Lptim2_out	24	Reserved
9	Lptim3_out	25	Reserved
10	I2c4_wkup	26	Reserved
11	spi6_wkup	27	Reserved
12	Comp1_out	28	Reserved
13	RTC_wkup	29	Reserved
14	Syscfg_exti0_mux	30	Reserved
15	Syscfg_exti2_mux	31	Reserved

17.4 DMAMUX functional description

17.4.1 DMAMUX block diagram

Figure 85 shows the DMAMUX block diagram.

Figure 85. DMAMUX block diagram

Figure 85. DMAMUX block diagram. The diagram shows the internal architecture of the DMAMUX block. At the top, a 32-bit AHB bus connects to an 'AHB slave interface' block, which is also connected to the 'dmamux_hclk' signal. The main 'DMAMUX' block contains several sub-components: 'Request generator', 'Request multiplexer', 'Interrupt interface', and 'Sync'. The 'Request generator' has multiple channels (Channel 0 to Channel n) with control registers (DMAMUX_RGC0CR to DMAMUX_RGCnCR). It receives 'Trigger inputs: dmamux_trgx' (labeled t, 1, 0) and outputs 'dmamux_req_genx' signals. The 'Request multiplexer' has multiple channels (Channel 0 to Channel m) with control registers (DMAMUX_C0CR to DMAMUX_CmCR). It receives 'DMA requests from peripherals: dmamux_req_inx' (labeled p, 1, 0) and 'dmamux_reqx' signals. It outputs 'DMA requests to DMA controllers: dmamux_req_outx' (labeled m, 1, 0) and 'DMA channels events: dmamux_evttx' (labeled m, 1, 0). The 'Sync' block receives 'Channel select' and 'Ctrl' signals and outputs 's, 1, 0' signals. The 'Interrupt interface' block receives 'dmamux_reqx' and 's, 1, 0' signals and outputs an 'Interrupt: dmamux_ovr_it' signal. It also receives 'Synchronization inputs: dmamux_syncx' (labeled s, 1, 0). A 'Control registers' block is shown at the bottom left.

DMAMUX features two main sub-blocks: the request line multiplexer and the request line generator.

The implementation assigns:

• DMAMUX request multiplexer sub-block inputs ( dmamux_reqx) from peripherals ( dmamux_req_inx) and from channels of the DMAMUX request generator sub-block ( dmamux_req_genx)
• DMAMUX request outputs to channels of DMA controllers ( dmamux_req_outx)
• Internal or external signals to DMA request trigger inputs ( dmamux_trgx)
• Internal or external signals to synchronization inputs ( dmamux_syncx)

17.4.2 DMAMUX signals

Table 124 lists the DMAMUX signals.

Table 124. DMAMUX signals

Signal name	Description
dmamux_hclk	DMAMUX AHB clock
dmamux_req_inx	DMAMUX DMA request line inputs from peripherals
dmamux_trgx	DMAMUX DMA request triggers inputs (to request generator sub-block)
dmamux_req_genx	DMAMUX request generator sub-block channels outputs
dmamux_reqx	DMAMUX request multiplexer sub-block inputs (from peripheral requests and request generator channels)
dmamux_syncx	DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx	DMAMUX requests outputs (to DMA controllers)
dmamux_evttx	DMAMUX events outputs
dmamux_ovr_it	DMAMUX overrun interrupts

17.4.3 DMAMUX channels

A DMAMUX channel is a DMAMUX request multiplexer channel that may include, depending on the selected input of the request multiplexer, an additional DMAMUX request generator channel.

A DMAMUX request multiplexer channel is connected and dedicated to one single channel of DMA controller(s).

Channel configuration procedure

Follow the sequence below to configure both a DMAMUX x channel and the related DMA channel y:

1. Set and configure completely the DMA channel y, except enabling the channel y.
2. Set and configure completely the related DMAMUX y channel.
3. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.

17.4.4 DMAMUX request line multiplexer

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of DMA request/acknowledge control signals, named DMA request lines.

Each DMA request line is connected in parallel to all the channels of the DMAMUX request line multiplexer.

A DMA request is sourced either from the peripherals or from the DMAMUX request generator.

The DMAMUX request line multiplexer channel x selects the DMA request line number as configured by the DMAREQ_ID field in the DMAMUX_CxCR register.

Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected.

Caution: A same non-null DMAREQ_ID must not be programmed to different x and y DMAMUX request multiplexer channels (via DMAMUX_CxCR and DMAMUX_CyCR), except if application guarantees that the two connected DMA channels are not simultaneously active.

On top of the DMA request selection, the synchronization mode and/or the event generation may be configured and enabled, if required.

Synchronization mode and channel event generation

Each DMAMUX request line multiplexer channel x can be individually synchronized by setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.

DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in parallel to all the channels of the request multiplexer.

The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register of a given channel x.

When a channel is in this synchronization mode, the selected input DMA request line is propagated to the multiplexer channel output, once is detected a programmable rising/falling edge on the selected input synchronization signal, via the SPOL[1:0] field of the DMAMUX_CxCR register.

Additionally, there is a programmable DMA request counter, internally to the DMAMUX request multiplexer, which may be used for the channel request output generation and also possibly for an event generation. An event generation on the channel x output is enabled through the EGE bit (event generation enable) of the DMAMUX_CxCR register.

As shown in Figure 87 , upon the detected edge of the synchronization input, the pending selected input DMA request line is connected to the DMAMUX multiplexer channel x output.

Note: If a synchronization event occurs while there is no pending selected input DMA request line, it is discarded. The following asserted input request lines is not connected to the DMAMUX multiplexer channel output until a synchronization event occurs again.

From this point on, each time the connected DMAMUX request is served by the DMA controller (a served request is deasserted), the DMAMUX request counter is decremented. At its underrun, the DMA request counter is automatically loaded with the value in NBREQ field of the DMAMUX_CxCR register and the input DMA request line is disconnected from the multiplexer channel x output.

Thus, the number of DMA requests transferred to the multiplexer channel x output following a detected synchronization event, is equal to the value in NBREQ field, plus one.

Note: The NBREQ field value shall only be written by software when both synchronization enable bit SE and event generation enable EGE bit of the corresponding multiplexer channel x are disabled.

Figure 86. Synchronization mode of the DMAMUX request line multiplexer channel

Timing diagram for Figure 86 showing synchronization mode. It includes signals: Selected dmamux_reqx, dmamux_syncx, dmamux_req_outx, DMA request counter, and dmamux_evtx. The diagram shows the counter counting down from 4 to 0 and then auto-reloading to 4. Events are generated when the counter reaches zero. The example configuration is NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge).

Selected DMA request line transferred to the output

DMA requests served

DMA request pending

Not pending

Selected dmamux_reqx

dmamux_syncx

dmamux_req_outx

DMA request counter

dmamux_evtx

Synchronization event
Input DMA request line connected to output

DMA request counter underrun
DMA request counter auto-reload to NBREQ
Input DMA request line disconnected from output

Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)

MSv41974V1

Timing diagram for Figure 86 showing synchronization mode. It includes signals: Selected dmamux_reqx, dmamux_syncx, dmamux_req_outx, DMA request counter, and dmamux_evtx. The diagram shows the counter counting down from 4 to 0 and then auto-reloading to 4. Events are generated when the counter reaches zero. The example configuration is NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge).

Figure 87. Event generation of the DMA request line multiplexer channel

Timing diagram for Figure 87 showing event generation. It includes signals: Selected dmamux_reqx, dmamux_req_outx, DMA request counter, SE, EGE, and dmamux_evtx. The counter counts down from 3 to 0 and then auto-reloads to 3. Events are generated when the counter reaches zero. The example configuration is NBREQ=3, SE=0, EGE=1.

Selected DMA request line transferred to the output

DMA request pending

Not pending

Selected dmamux_reqx

dmamux_req_outx

DMA request counter

EGE

dmamux_evtx

DMA request counter reaches zero
Event is generated on the output
DMA request counter auto-reloads with NBREQ value

Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1

MSv41975V1

Timing diagram for Figure 87 showing event generation. It includes signals: Selected dmamux_reqx, dmamux_req_outx, DMA request counter, SE, EGE, and dmamux_evtx. The counter counts down from 3 to 0 and then auto-reloads to 3. Events are generated when the counter reaches zero. The example configuration is NBREQ=3, SE=0, EGE=1.

If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one AHB clock cycle, when its DMA request counter is automatically reloaded with the value of the programmed NBREQ field, as shown in Figure 86 and Figure 87.

Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.

Note: A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.

Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles.

Synchronization overrun and interrupt

If a new synchronization event occurs before the request counter underrun (the internal request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register.

Note: The request multiplexer channel x synchronization must be disabled (DMAMUX_CxCR.SE = 0) at the completion of the use of the related channel of the DMA controller. Else, upon a new detected synchronization event, there is a synchronization overrun due to the absence of a DMA acknowledge (that is, no served request) received from the DMA controller.

The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag bit CSOFx in the DMAMUX_CFR register.

Setting the synchronization overrun flag generates an interrupt if the synchronization overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.

17.4.5 DMAMUX request generator

The DMAMUX request generator produces DMA requests following trigger events on its DMA request trigger inputs.

The DMAMUX request generator has multiple channels. DMA request trigger inputs are connected in parallel to all channels.

The outputs of DMAMUX request generator channels are inputs to the DMAMUX request line multiplexer.

Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the corresponding DMAMUX_RGxCR register.

The DMA request trigger input for the DMAMUX request generator channel x is selected through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.

Trigger events on a DMA request trigger input can be rising edge, falling edge or either edge. The active edge is selected through the GPOL (generator polarity) field in the corresponding DMAMUX_RGxCR register.

Upon the trigger event, the corresponding generator channel starts generating DMA requests on its output. Each time the DMAMUX generated request is served by the connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX request generator) DMA request counter is decremented. At its underrun, the request generator channel stops generating DMA requests and the DMA request counter is automatically reloaded to its programmed value upon the next trigger event.

Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.

Note: The GNBREQ field value must be written by software only when the enable GE bit of the corresponding generator channel x is disabled.

There is no hardware write protection.

A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.

Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three AHB clock cycles.

Trigger overrun and interrupt

If a new DMA request trigger event occurs before the DMAMUX request generator counter underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR register), and if the request generator channel x was enabled via GE, then the request trigger event overrun flag bit OFx is asserted by the hardware in the status DMAMUX_RGSR register.

Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the completion of the usage of the related channel of the DMA controller. Else, upon a new detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that is, no served request) received from the DMA.

The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the DMAMUX_RGCFR register.

Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.

17.5 DMAMUX interrupts

An interrupt can be generated upon:

• a synchronization event overrun in each DMA request line multiplexer channel
• a trigger event overrun in each DMA request generator channel

For each case, per-channel individual interrupt enable, status and clear flag register bits are available.

Table 125. DMAMUX interrupts

Interrupt signal	Interrupt event	Event flag	Clear bit	Enable bit
dmamuxovr_it	Synchronization event overrun on channel x of the DMAMUX request line multiplexer	SOFx	CSOFx	SOIE
dmamuxovr_it	Trigger event overrun on channel x of the DMAMUX request generator	OFx	COFx	OIE

17.6 DMAMUX registers

Refer to the table containing register boundary addresses for the DMAMUX1 and DMAMUX2 base address.

DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word. The address must be aligned with the data size.

17.6.1 DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR)

Address offset: 0x000 + 0x04 * x (x = 0 to 15)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	SYNC_ID[2:0]				NBREQ[4:0]				SPOL[1:0]		SE
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	EGE	SOIE	Res.	DMAREQ_ID[6:0]
						rw	rw		rw	rw	rw	rw	rw	rw	rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 SYNC_ID[2:0] : Synchronization identification

Selects the synchronization input (see Table 120: DMAMUX1: assignment of synchronization inputs to resources ).

Bits 23:19 NBREQ[4:0] : Number of DMA requests minus 1 to forward

Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated.

This field shall only be written when both SE and EGE bits are low.

Bits 18:17 SPOL[1:0] : Synchronization polarity

Defines the edge polarity of the selected synchronization input:

00: No event, i.e. no synchronization nor detection.

01: Rising edge

10: Falling edge

11: Rising and falling edges

Bit 16 SE : Synchronization enable

0: Synchronization disabled

1: Synchronization enabled

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 EGE : Event generation enable

0: Event generation disabled

1: Event generation enabled

Bit 8 SOIE : Synchronization overrun interrupt enable

0: Interrupt disabled

1: Interrupt enabled

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 DMAREQ_ID[6:0] : DMA request identification

Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources.

17.6.2 DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR)

Address offset: 0x000 + 0x04 * x, where x = 0 to 7

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	SYNC_ID[4:0]					NBREQ[4:0]					SPOL[1:0]		SE
			rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw		rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	EGE	SOIE	Res.	Res.	Res.	DMAREQ_ID[4:0]
						rw	rw				rw	rw	rw	rw	rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SYNC_ID[4:0] : Synchronization identification

Selects the synchronization input (see Table 123: DMAMUX2: assignment of synchronization inputs to resources )

Bits 23:19 NBREQ[4:0] : Number of DMA requests minus 1 to forward

Defines the number of DMA requests to forward to the DMA controller after a synchronization event, and/or the number of DMA requests before an output event is generated.

This field shall only be written when both SE and EGE bits are low.

Bits 18:17 SPOL[1:0] : Synchronization polarity

Defines the edge polarity of the selected synchronization input:

00: no event, i.e. no synchronization nor detection.

01: rising edge

10: falling edge

11: rising and falling edges

Bit 16 SE : Synchronization enable

0: synchronization disabled

1: synchronization enabled

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 EGE : Event generation enable

0: event generation disabled

1: event generation enabled

Bit 8 SOIE : Synchronization overrun interrupt enable

0: interrupt disabled

1: interrupt enabled

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 DMAREQ_ID[4:0] : DMA request identification

Selects the input DMA request. (see the DMAMUX table about assignments of multiplexer inputs to resources).

17.6.3 DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR)

Address offset: 0x080

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOF15	SOF14	SOF13	SOF12	SOF11	SOF10	SOF9	SOF8	SOF7	SOF6	SOF5	SOF4	SOF3	SOF2	SOF1	SOF0
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SOF[15:0] : Synchronization overrun event flag

The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ.

The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.

For DMAMUX2 bits 15:8 are reserved, keep them at reset value.

17.6.4 DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR)

Address offset: 0x080

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SOF7	SOF6	SOF5	SOF4	SOF3	SOF2	SOF1	SOF0
								r	r	r	r	r	r	r	r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 SOF[7:0] : Synchronization overrun event flag

The flag is set when a new synchronization event occurs on a DMA request line multiplexer channel x before the request counter underrun (the internal request counter programmed via the NBREQ field of the DMAMUX_CxCR register).

The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX2_CFR register.

17.6.5 DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR)

Address offset: 0x084

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CSOF 15	CSOF 14	CSOF 13	CSOF 12	CSOF 11	CSOF 10	CSOF 9	CSOF 8	CSOF 7	CSOF 6	CSOF 5	CSOF 4	CSOF 3	CSOF 2	CSOF 1	CSOF 0
w	w	w	w	w	w	w	w	w	w	w	w	w	w	w	w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CSOF[15:0] : Clear synchronization overrun event flag

Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR register.

17.6.6 DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR)

Address offset: 0x084

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CSOF6	CSOF6	CSOF5	CSOF4	CSOF3	CSOF2	CSOF1	CSOF0
								w	w	w	w	w	w	w	w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 CSOF[7:0] : Clear synchronization overrun event flag

Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX2_CSR register.

17.6.7 DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR)

Address offset: 0x100 + 0x04 * x (x = 0 to 7)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	GNBREQ[4:0]					GPOL[1:0]		GE
								rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	OIE	Res.	Res.	Res.	Res.	Res.	SIG_ID[2:0]
							rw						rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0] : Number of DMA requests to be generated (minus 1)

Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ +1.

Note: This field must be written only when GE bit is disabled.

Bits 18:17 GPOL[1:0] : DMA request generator trigger polarity

Defines the edge polarity of the selected trigger input

00: No event, i.e. no trigger detection nor generation.

01: Rising edge

10: Falling edge

11: Rising and falling edges

Bit 16 GE : DMA request generator channel x enable

0: DMA request generator channel x disabled

1: DMA request generator channel x enabled

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 OIE : Trigger overrun interrupt enable

0: Interrupt on a trigger overrun event occurrence is disabled

1: Interrupt on a trigger overrun event occurrence is enabled

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 SIG_ID[2:0] : Signal identification

Selects the DMA request trigger input used for the channel x of the DMA request generator

17.6.8 DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR)

Address offset: 0x100 + 0x04 * x (x = 0 to 7)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	GNBREQ[4:0]					GPOL[1:0]		GE
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	OIE	Res.	Res.	Res.	SIG_ID[4:0]
							rw				rw	rw	rw	rw	rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0] : Number of DMA requests to be generated (minus 1)

Defines the number of DMA requests to be generated after a trigger event. The actual number of generated DMA requests is GNBREQ+1.

Note: This field shall only be written when GE bit is disabled.

Bits 18:17 GPOL[1:0] : DMA request generator trigger polarity

Defines the edge polarity of the selected trigger input

00: no event. I.e. none trigger detection nor generation.

01: rising edge

10: falling edge

11: rising and falling edge

Bit 16 GE : DMA request generator channel x enable

0: DMA request generator channel x disabled

1: DMA request generator channel x enabled

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 OIE : Trigger overrun interrupt enable

0: interrupt on a trigger overrun event occurrence is disabled

1: interrupt on a trigger overrun event occurrence is enabled

Bits 7:5 Reserved, must be kept at reset value.

Bits 4:0 SIG_ID[4:0] : Signal identification

Selects the DMA request trigger input used for the channel x of the DMA request generator

17.6.9 DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR)

Address offset: 0x140

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OF7	OF6	OF5	OF4	OF3	OF2	OF1	OF0
								r	r	r	r	r	r	r	r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 OF[7:0] : Trigger overrun event flag

The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register).

The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register.

17.6.10 DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR)

Address offset: 0x140

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OF7	OF6	OF5	OF4	OF3	OF2	OF1	OF0
								r	r	r	r	r	r	r	r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 OF[7:0] : Trigger overrun event flag

The flag is set when a new trigger event occurs on DMA request generator channel x.

The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX2_RGCFR register.

17.6.11 DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR)

Address offset: 0x144

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COF7	COF6	COF5	COF4	COF3	COF2	COF1	COF0
								w	w	w	w	w	w	w	w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 COF[7:0] : Clear trigger overrun event flag

Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR register.

17.6.12 DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR)

Address offset: 0x144

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COF7	COF6	COF5	COF4	COF3	COF2	COF1	COF0
								r	r	r	r	r	r	r	r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 COF[7:0] : Clear trigger overrun event flag

Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX2_RGSR register.

17.6.13 DMAMUX register map

The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address.

Table 126. DMAMUX register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	DMAMUX_C0CR ⁽¹⁾⁽²⁾	Res.	Res.	Res.	Res.	Res.	SYNC_ID [2:0]			NBREQ[4:0]					SPOL [1:0]		SE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	EGE	SOIE	Res.	DMAREQ_ID[6:0]
0x000	Reset value						0	0	0	0	0	0	0	0	0	0	0								0	0		0	0	0	0	0	0	0
0x004	DMAMUX_C1CR ⁽¹⁾	Res.	Res.	Res.	Res.	Res.	SYNC_ID [2:0]			NBREQ[4:0]					SPOL [1:0]		SE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	EGE	SOIE	Res.	DMAREQ_ID[6:0]
0x004	Reset value						0	0	0	0	0	0	0	0	0	0	0								0	0		0	0	0	0	0	0	0
0x008	DMAMUX_C2CR ⁽¹⁾	... (Same as DMAMUX_C1CR) ...
0x008	Reset value	... (Same as DMAMUX_C1CR) ...
0x00C	DMAMUX_C3CR ⁽¹⁾	... (Same as DMAMUX_C1CR) ...
0x00C	Reset value	... (Same as DMAMUX_C1CR) ...
0x010	DMAMUX_C4CR ⁽¹⁾	... (Same as DMAMUX_C1CR) ...
0x010	Reset value	... (Same as DMAMUX_C1CR) ...
0x014	DMAMUX_C5CR ⁽¹⁾	... (Same as DMAMUX_C1CR) ...
0x014	Reset value	... (Same as DMAMUX_C1CR) ...
0x018	DMAMUX_C6CR ⁽¹⁾	... (Same as DMAMUX_C1CR) ...
0x018	Reset value	... (Same as DMAMUX_C1CR) ...
0x01C	DMAMUX_C7CR ⁽¹⁾	... (Same as DMAMUX_C1CR) ...
0x01C	Reset value	... (Same as DMAMUX_C1CR) ...
0x020	DMAMUX_C8CR ⁽³⁾	... (Same as DMAMUX_C1CR) ...
0x020	Reset value	... (Same as DMAMUX_C1CR) ...
0x024	DMAMUX_C9CR ⁽⁴⁾	... (Same as DMAMUX_C1CR) ...
0x024	Reset value	... (Same as DMAMUX_C1CR) ...
0x028	DMAMUX_C10CR	... (Same as DMAMUX_C1CR) ...
0x028	Reset value	... (Same as DMAMUX_C1CR) ...
0x02C	DMAMUX_C11CR	... (Same as DMAMUX_C1CR) ...
0x02C	Reset value	... (Same as DMAMUX_C1CR) ...
0x030	DMAMUX_C12CR	... (Same as DMAMUX_C1CR) ...
0x030	Reset value	... (Same as DMAMUX_C1CR) ...
0x034	DMAMUX_C13CR	... (Same as DMAMUX_C1CR) ...
0x034	Reset value	... (Same as DMAMUX_C1CR) ...
0x038	DMAMUX_C14CR	... (Same as DMAMUX_C1CR) ...
0x038	Reset value	... (Same as DMAMUX_C1CR) ...
0x03C	DMAMUX_C15CR	... (Same as DMAMUX_C1CR) ...
0x03C	Reset value	... (Same as DMAMUX_C1CR) ...
0x040 - 0x07C	Reserved	Res.

Table 126. DMAMUX register map and reset values (continued)

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x080	DMAMUX_CSR ⁽⁴⁾	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x080	Reset value
0x084	DMAMUX_CFR ⁽⁴⁾	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x084	Reset value
0x088 - 0x0FC	Reserved	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res
0x100	DMAMUX_RG0CR ⁽⁵⁾	Res	Res	Res	Res	Res	Res	Res	Res	GNBREQ[4:0]					GPOL [1:0]	GE	Res	Res	Res	Res	Res	Res	Res	Res	OIE	Res	Res	Res	Res	Res	Res	SIG_ID [2:0]	Res
0x100	Reset value									0	0	0	0	0	0	0									0							0	0
0x104	DMAMUX_RG1CR	Res	Res	Res	Res	Res	Res	Res	Res	GNBREQ[4:0]					GPOL [1:0]	GE	Res	Res	Res	Res	Res	Res	Res	Res	OIE	Res	Res	Res	Res	Res	Res	SIG_ID [2:0]	Res
0x104	Reset value									0	0	0	0	0	0	0									0							0	0
0x108	DMAMUX_RG2CR	Res	Res	Res	Res	Res	Res	Res	Res	GNBREQ[4:0]					GPOL [1:0]	GE	Res	Res	Res	Res	Res	Res	Res	Res	OIE	Res	Res	Res	Res	Res	Res	SIG_ID [2:0]	Res
0x108	Reset value									0	0	0	0	0	0	0									0							0	0
0x10C	DMAMUX_RG3CR	Res	Res	Res	Res	Res	Res	Res	Res	GNBREQ[4:0]					GPOL [1:0]	GE	Res	Res	Res	Res	Res	Res	Res	Res	OIE	Res	Res	Res	Res	Res	Res	SIG_ID [2:0]	Res
0x10C	Reset value									0	0	0	0	0	0	0									0							0	0
0x140	DMAMUX_RGSR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x140	Reset value
0x144	DMAMUX_RGCFR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x144	Reset value
0x140	DMAMUX_RGSR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x140	Reset value
0x144	DMAMUX_RGCFR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x144	Reset value
0x148 - 0x3FC	Reserved	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res

1. For DMAMUX2 bits 6:5 are reserved.
2. For DMAMUX2 bits 28:24 correspond to SYNC_ID[4:0].
3. Only applies to DMAMUX1. For DMAMUX2 the word is reserved.
4. For DMAMUX2 bits 15:8 are reserved.
5. Valid for DMAMUX1. For DMAMUX2 bits 4:0 are for SIG_ID[4:0].

Refer to Section 2.3 on page 131 for the register boundary addresses.