12. System configuration controller (SYSCFG)

12.1 Introduction

The devices feature a set of configuration registers. The objectives of this section is to describe in details the system configuration controller.

12.2 SYSCFG main features

The system configuration controller main functions are the following:

• • Analog switch configuration management
• • I2C Fm+ configuration
• • Selection of the Ethernet PHY interface.
• • Management of the external interrupt line connection to the GPIOs
• • Management of the I/O compensation cell
• • Getting readout protection
• • Management of boot sequences and boot addresses
• • Management BOR reset level
• • Management of Flash memory secured and protected sector status
• • Management Flash memory write protections status
• • Management of DTCM secured section status
• • Management of independent watchdog behavior (hardware or software / freeze)
• • Reset generation in Stop and Standby mode
• • Secure mode enabling/disabling status
• • Management timer break input lock.

12.3 Management of timer break input lock

This feature allows, in addition to HSE break detection, to disable the timer output when an internal SRAM or Flash memory ECC double error, or when a PVD or core lockup occurs. This is particularly useful when timers are used to drive motors. The type of lockup can be selected through the SYSCFG_CFGR register in addition to the HSE break detection.

12.4 SYSCFG registers

12.4.1 SYSCFG peripheral mode configuration register (SYSCFG_PMCR)

Address offset: 0x04

Reset value: 0x0X00 0000

Note: 'X' correspond to PC3, PC2, PA1 and PA0 switch open bit reset value (PXnSO). PXnSO reset value is 0 when the corresponding PXn_C pin is available on the package but PXn is not, otherwise it is 1.

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 PC3SO : PC3 switch open

This bit controls the analog switch between PC3 and PC3_C (dual pad)

0: Analog switch closed (pads are connected through the analog switch)

1: Analog switch open (2 separated pads)

Bit 26 PC2SO : PC2 switch open

This bit controls the analog switch between PC2 and PC2_C (dual pad)

0: Analog switch closed (pads are connected through the analog switch)

1: Analog switch open (2 separated pads)

Bit 25 PA1SO : PA1 switch open

This bit controls the analog switch between PA1 and PA1_C (dual pad)

0: Analog switch closed (pads are connected through the analog switch)

1: Analog switch open (2 separated pads)

Bit 24 PA0SO : PA0 switch open

This bit controls the analog switch between PA0 and PA0_C (dual pad)

0: Analog switch closed (pads are connected through the analog switch)

1: Analog switch open (2 separated pads)

Bits 23:21 EPIS[2:0] : Ethernet PHY interface selection

These bits select the Ethernet PHY interface.

000: MII

100: RMII

Others: Reserved, must not be used

Bits 20:11 Reserved, must be kept at reset value.

Bit 10 I2C5FMP : I2C5 Fm+

This bit enables Fm+ on I2C5.

0: Fm+ disabled

1: Fm+ enabled

Bit 9 BOOSTVDDSEL : Analog switch supply voltage selection ( \( V_{DD}/V_{DDA}/\text{booster} \) )

To avoid current consumption due to booster activation when \( V_{DDA} < 2.7\text{ V} \) and \( V_{DD} > 2.7\text{ V} \) , \( V_{DD} \) can be selected as supply voltage for analog switches. In this case, the BOOSTE bit should be cleared to avoid unwanted power consumption.

When both \( V_{DD} < 2.7\text{ V} \) and \( V_{DDA} < 2.7\text{ V} \) , the booster is required to obtain full AC performance from I/O analog switches.

0: \( V_{DDA} \) selected as analog switch supply voltage (when BOOSTE bit is cleared)

1: \( V_{DD} \) selected as analog switch supply voltage

Bit 8 BOOSTE : Booster enable

This bit enables the booster to reduce the total harmonic distortion of the analog switch when the supply voltage is lower than 2.7 V.

Activating the booster allows to guaranty the analog switch AC performance when the supply voltage is below 2.7 V: in this case, the analog switch performance is the same on the full voltage range.

0: Booster disabled

1: Booster enabled

Bit 7 PB9FMP : PB(9) Fm+

This bit enables I2C Fm+ on PB(9).

0: Fm+ disabled

1: Fm+ enabled

Bit 6 PB8FMP : PB(8) Fm+

This bit enables I2C Fm+ on PB(8).

0: Fm+ disabled

1: Fm+ enabled

Bit 5 PB7FMP : PB(7) Fm+

this bit enables I2C Fm+ on PB(7).

0: Fm+ disabled

1: Fm+ enabled

Bit 4 PB6FMP : PB(6) Fm+

This bit enables I2C Fm+ on PB(6).

0: Fm+ disabled

1: Fm+ enabled

Bit 3 I2C4FMP : I2C4 Fm+

This bit enables Fm+ on I2C4.

0: Fm+ disabled

1: Fm+ enabled

Bit 2 I2C3FMP : I2C3 Fm+

This bit enables Fm+ on I2C3.

0: Fm+ disabled

1: Fm+ enabled

Bit 1 I2C2FMP : I2C2 Fm+

This bit enables Fm+ on I2C2.

0: Fm+ disabled

1: Fm+ enabled

Bit 0 I2C1FMP : I2C1 Fm+

This bit enables Fm+ on I2C1.

0: Fm+ disabled

1: Fm+ enabled

12.4.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

These bits are written by software to select the source input for the EXTI input for external interrupt / event detection.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0111: PH[x] pin

1001: PJ[x] pin

1010: PK[x] pin

Others: Reserved, must not be used

12.4.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTI[7:4][3:0] : EXTI x configuration (x = 4 to 7)

These bits are written by software to select the source input for the EXTI input for external interrupt / event detection.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0111: PH[x] pin

1001: PJ[x] pin

1010: PK[x] pin

Others: Reserved, must not be used

Note: PJ[7:4] and PK[7:4] are not used.

12.4.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTI[11:8][3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTI input for external interrupt / event detection.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0111: PH[x] pin

1001: PJ[x] pin

1010: PK[x] pin

Others: Reserved, must not be used

Note: PK[11:8] are not used.

12.4.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTI[5:12][3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTI input for external interrupt / event detection.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

0111: PH[x] pin

1001: PJ[x] pin

1010: PK[x] pin

Others: Reserved, must not be used

Note: PJ[15:12] and PK[15:12] are not used.

12.4.6 SYSCFG timer break lockup register (SYSCFG_CFGR)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 AXIRAML : D1 AXI-SRAM ECC double error lock bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D1 AXI-SRAM ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D1 AXI-SRAM ECC double error signal disconnected

1: D1 AXI-SRAM ECC double error signal connected

Bit 14 ITCML : D1 ITCM-RAM ECC double error lock bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D1 ITCM-RAM ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D1 ITCM-RAM ECC double error signal disconnected

1: D1 ITCM-RAM ECC double error signal connected

Bit 13 DTCML : D1 DTCM ECC double error lock bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D1 DTCM ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D1 DTCM ECC double error signal disconnected

1: D1 DTCM ECC double error signal connected

Bit 12 SRAM1L : D2 SRAM1 ECC double error lockup bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D2 SRAM1 ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D2 SRAM1 ECC double error signal disconnected

1: D2 SRAM1 ECC double error signal connected

Bit 11 SRAM2L : D2 SRAM2 ECC double error lockup bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D2 SRAM2 ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D2 SRAM2 ECC double error signal disconnected

1: D2 SRAM2 ECC double error signal connected

Bit 10 Reserved, must be kept at reset value.

Bit 9 SRAM4L : D3 SRAM4 ECC double error Lockup bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D3 SRAM4 ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D3 SRAM4 ECC double error signal disconnected

1: D3 SRAM4 ECC double error signal connected

Bit 8 Reserved, must be kept at reset value.

Bit 7 BKRAML : D3 backup SRAM ECC double error lockup bit

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the D3 backup SRAM ECC double error connection to TIM1/8/15/16 /17 Break inputs

0: D3 backup SRAM ECC double error signal disconnected

1: D3 backup SRAM ECC double error signal connected

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the CPU lockup connection to TIM1/8/15/16 /17

Break inputs

0: CPU lockup signal disconnected

1: CPU lockup signal connected

Bits 5:4 Reserved, must be kept at reset value.

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the FLASH double ECC error connection to

TIM1/8/15/16 /17 Break inputs

0: FLASH double ECC error signal disconnected

1: FLASH double ECC error signal connected

This bit is set by software and cleared by reset system only.

This bit is used to enable and lock the PVD connection to TIM1/8/15/16 /17 Break

inputs

0: PVD signal disconnected

1: PVD signal connected

Bits 1:0 Reserved, must be kept at reset value.

12.4.7 SYSCFG compensation cell control/status register (SYSCFG_CCCSR)

Address offset: 0x20

Reset value: 0x0000 0000

Refer to Section 11.3.11: I/O compensation cell for a detailed description of I/O compensation mechanism.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 HSLV : High-speed at low-voltage

• This bit is written by software to optimize the I/O speed when the product voltage is low.
• This bit is active only if IO_HSLV user option bit is set. It must be used only if the product supply voltage is below 2.5 V. Setting this bit when \( V_{DD} \) is higher than 2.5 V might be destructive.
• 0: No I/O speed optimization
• 1: I/O speed optimization

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 READY : Compensation cell ready flag

• This bit provides the status of the compensation cell.
• 0: I/O compensation cell not ready
• 1: I/O compensation cell ready

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 CS : Code selection

• This bit selects the code to be applied for the I/O compensation cell.
• 0: Code from the cell (available in the SYSCFG_CCVR)
• 1: Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)

Bit 0 EN : I/O compensation cell enable

• This bit enables the I/O compensation cell.
• 0: I/O compensation cell disabled
• 1: I/O compensation cell enabled

12.4.8 SYSCFG compensation cell value register (SYSCFG_CCVR)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 PCV[3:0] : PMOS compensation value

This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for PMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CCCSR is reset.

Bits 3:0 NCV[3:0] : NMOS compensation value

This value is provided by the cell and can be used by the CPU to compute an I/O compensation cell code for NMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CCCSR is reset.

12.4.9 SYSCFG compensation cell code register (SYSCFG_CCCR)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 PCC[3:0] : PMOS compensation code

These bits are written by software to define an I/O compensation cell code for PMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CCCSR is set.

Bits 3:0 NCC[3:0] : NMOS compensation code

These bits are written by software to define an I/O compensation cell code for NMOS transistors. This code is applied to the I/O compensation cell when the CS bit of the SYSCFG_CCCSR is set.

12.4.10 SYSCFG ADC2 internal input alternate connection register (SYSCFG_ADC2ALT)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

12.4.11 SYSCFG package register (SYSCFG_PKGR)

Address offset: 0x124

Reset value: 0x000X 000X

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 PKG[3:0] : Package

These bits indicate the device package.

0000: VFQFPN68 Industrial

0001: LQFP100 Legacy / TFBGA100 Legacy

0010: LQFP100 Industrial

0011: TFBGA100 Industrial

0100: WLCSP115 Industrial

0101: LQFP144 Legacy

0110: UFBGA144 Legacy

0111: LQFP144 Industrial

1000: UFBGA169 Industrial

1001: UFBGA176+25 Industrial

1010: LQFP176 Industrial

Other configurations: all pads enabled

12.4.12 SYSCFG user register 0 (SYSCFG_UR0)

Address offset: 0x300

Reset value: 0x00XX 0000

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 RDP[7:0] : Readout protection

These bits indicate the readout protection level.

0xAA: Level 0 (no protection)

0xCC: Level 2 (Flash memory readout protected, full debug features, boot from SRAM and boundary scan disabled)

Other configurations: Level 1 (Flash memory readout protected, limited debug features and boundary scan enabled)

Bits 15:0 Reserved, must be kept at reset value.

12.4.13 SYSCFG user register 2 (SYSCFG_UR2)

Address offset: 0x308

Reset value: 0xXXXX 000X

Bits 31:16 BOOT_ADD0[15:0] : Cortex-M7 boot address 0

These bits define the MSB of the Cortex-M7 core boot address when BOOT pin is low.

Bits 15:2 Reserved, must be kept at reset value.

Bits 1:0 BORH[1:0] : BOR_LEV Brownout reset threshold level

These bits indicate the Brownout reset high level.

00: BOR OFF

01: BOR Level 1

10: BOR Level 2

11: BOR Level 3

12.4.14 SYSCFG user register 3 (SYSCFG_UR3)

Address offset: 0x30C

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BOOT_ADD1[15:0] : Cortex-M7 boot address 1

These bits define the MSB of the core boot address when BOOT pin is high.

12.4.15 SYSCFG user register 4 (SYSCFG_UR4)

Address offset: 0x310

Reset value: 0x000X 0000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 MEPAD_1 : PCROP protected erase enable option configuration bit

If MEPAD_1 is set to 1, the PCROP protected area is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs.

Bits 15:0 Reserved, must be kept at reset value.

12.4.16 SYSCFG user register 5 (SYSCFG_UR5)

Address offset: 0x314

Reset value: 0x00XX 000X

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRPN_1[7:0] : Sector 7 to 0 write protection option status bit

Setting WRPN_1[n] bit to 0 write protects the corresponding bank sector (0: sector is write protected; 1: sector is not write protected).

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 MESAD_1 : Secure access protected erase enable option configuration bit

If MESAD_1 is set to 1, the secure access only area is erased when a protection level regression (change from level 1 to 0) or a bank erase with protection removal occurs.

12.4.17 SYSCFG user register 6 (SYSCFG_UR6)

Address offset: 0x318

Reset value: 0x0XXX 0XXX

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 PA_END_1[11:0] : PCROP area end configuration bits

These bits contain the last 256-byte block of the PCROP area.

If this address is equal to PA_BEG_1, the whole bank is PCROP protected.

If this address is lower than PA_BEG_1, no protection is set.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 PA_BEG_1[11:0] : PCROP area start configuration bits

These bits contain the first 256-byte block of the PCROP area.

If this address is equal to PA_END_1, the whole bank is PCROP protected.

If this address is higher than PA_END_1, no protection is set.

12.4.18 SYSCFG user register 7 (SYSCFG_UR7)

Address offset: 0x31C

Reset value: 0x0XXX 0XXX

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 SA_END_1[11:0] : Secure-only area end configuration bits

These bits contain the last block of 256 bytes of the secure-only area.

If this address is equal to SA_START_1, the whole bank is secure access only.

If this address is lower than SA_START_1, no protection is set.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 SA_BEG_1[11:0] : Secure-only area start configuration bits

These bits contain the first block of 256 bytes of the secure-only area.

If this address is equal to SA_END_1, the whole bank is secure access only.

If this address is higher than SA_END_1, no protection is set.

12.4.19 SYSCFG user register 11 (SYSCFG_UR11)

Address offset: 0x32C

Reset value: 0x000X 0000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 IWDG1M : Independent Watchdog 1 mode

This bit indicates the control mode of the Independent Watchdog 1 (IWDG1).

• 0: IWDG1 controlled by hardware
• 1: IWDG1 controlled by software

Bits 15:0 Reserved, must be kept at reset value.

12.4.20 SYSCFG user register 12 (SYSCFG_UR12)

Address offset: 0x330

Reset value: 0x000X 000X

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 SECURE : Secure mode (SECURITY)

This bit indicates the Secure mode status.

0: Secure mode disabled

1: Secure mode enabled

Bits 15:0 Reserved, must be kept at reset value.

12.4.21 SYSCFG user register 13 (SYSCFG_UR13)

Address offset: 0x334

Reset value: 0x000X 000X

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 D1SBRST : D1 Standby reset

This bit indicates if a reset is generated when D1 domain enters DStandby mode.

0: A reset is generated by entering D1 Standby mode

1: D1 Standby mode is entered without reset generation

Bits 15:2 Reserved, must be kept at reset value.

Bits 1:0 SDRS[1:0] : Secured DTCM-RAM size

These bits indicates the size of the secured DTCM-RAM.

00: 2 Kbytes

01: 4 Kbytes

10: 8 Kbytes

11: 16 Kbytes

12.4.22 SYSCFG user register 14 (SYSCFG_UR14)

Address offset: 0x338

Reset value: 0x000X 000X

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 D1STPRST : D1 Stop Reset

This bit indicates if a reset is generated when D1 domain enters in DStop mode.

0: A reset is generated entering D1 Stop mode

1: D1 Stop mode is entered without reset generation

12.4.23 SYSCFG user register 15 (SYSCFG_UR15)

Address offset: 0x33C

Reset value: 0x000X 000X

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 FZIWDGSTB : Freeze independent watchdog in Standby mode

This bit indicates if the independent watchdog is frozen in Standby mode.

0: Independent Watchdog frozen in Standby mode

1: Independent Watchdog running in Standby mode

Bits 15:0 Reserved, must be kept at reset value.

12.4.24 SYSCFG user register 16 (SYSCFG_UR16)

Address offset: 0x340

Reset value: 0x000X 000X

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 PKP : Private key programmed

• This bit indicates if the device private key is programmed.
• 0: Private key not programmed
• 1: Private key programmed

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 FZIWDGSTP : Freeze independent watchdog in Stop mode

• This bit indicates if the independent watchdog is frozen in Stop mode.
• 0: Independent Watchdog frozen in Stop mode
• 1: Independent Watchdog running in Stop mode

12.4.25 SYSCFG user register 17 (SYSCFG_UR17)

Address offset: 0x344

Reset value: 0x0000 000X

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:16 TCM_AXI_SHARED_CFG[1:0] : ITCM-RAM / AXI-SRAM size

• 00: 64-Kbyte ITCM-RAM / 320-Kbyte AXI-SRAM
• 01: 128-Kbyte ITCM-RAM / 256-Kbyte AXI-SRAM
• 10: 192-Kbyte ITCM-RAM / 192-Kbyte AXI-SRAM
• 11: 256-Kbyte ITCM-RAM / 128-Kbyte AXI-SRAM

Bit 0 IO_HSLV : I/O high speed / low voltage

This bit indicates that the IO_HSLV option bit is set.

• 0: Product is working on the full voltage range
• 1: Product is working below 2.5 V

12.4.26 SYSCFG user register 18 (SYSCFG_UR18)

Address offset: 0x348

Reset value: 0x0000 000X

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 CPU_FREQ_BOOST : CPU maximum frequency boost enable

When this bit is set, the CPU maximum frequency is boosted and the ECC on ITCM-RAM and DTCM-RAM are no more used.

• 0: CPU maximum frequency feature disabled.
• 1: CPU operates at a boosted maximum frequency (no more ECC on I/DTCM)

12.4.27 SYSCFG register maps

The following table gives the SYSCFG register map and the reset values.

Table 91. SYSCFG register map and reset values

Table 91. SYSCFG register map and reset values (continued)

Table 91. SYSCFG register map and reset values (continued)

Refer to Section 2.3 on page 131 for the register boundary addresses.