RM0468-STM32H723-733-725-735-730

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32H723/733, STM32H725/735 and STM32H730 memory and peripherals.

The STM32H723/733, STM32H725/735 and STM32H730 are lines of microcontrollers with different memory sizes, packages and peripherals. They are referred to as STM32H72x and STM32H73x hereafter.

The devices include ST state-of-the-art patented technology.

For ordering information, mechanical, and electrical device characteristics refer to the corresponding datasheets.

For information on the Arm® Cortex®-M7 with FPU core, refer to the corresponding Arm Technical Reference Manuals .

Contents

3.3.1RAMECC block diagram .....144
3.3.2RAMECC internal signals .....146
3.3.3RAMECC monitor mapping .....146
3.4RAMECC registers .....147
3.4.1RAMECC interrupt enable register (RAMECC_IER) .....147
3.4.2RAMECC monitor x configuration register (RAMECC_MxCR) .....148
3.4.3RAMECC monitor x status register (RAMECC_MxSR) .....148
3.4.4RAMECC monitor x failing address register (RAMECC_MxFAR) .....149
3.4.5RAMECC monitor x failing data low register (RAMECC_MxFDRL) .....149
3.4.6RAMECC monitor x failing data high register (RAMECC_MxFDRH) .....150
3.4.7RAMECC monitor x failing ECC error code register
RAMECC_MxFECR) .....		150
3.4.8RAMECC register map .....151
4Embedded Flash memory (FLASH) .....152
4.1Introduction .....152
4.2FLASH main features .....152
4.3FLASH functional description .....153
4.3.1FLASH block diagram .....153
4.3.2FLASH internal signals .....153
4.3.3FLASH architecture and integration in the system .....154
4.3.4Flash memory architecture and usage .....155
4.3.5FLASH system performance enhancements .....158
4.3.6FLASH data protection schemes .....158
4.3.7Overview of FLASH operations .....158
4.3.8FLASH read operations .....159
4.3.9FLASH program operations .....162
4.3.10FLASH erase operations .....165
4.3.11Flash memory error protections .....167
4.3.12FLASH reset and clocks .....169
4.4FLASH option bytes .....169
4.4.1About option bytes .....169
4.4.2Option byte loading .....170
4.4.3Option byte modification .....170
4.4.4Option bytes overview .....173
4.4.5Description of user and system option bytes .....174
4.4.6Description of data protection option bytes .....176
4.4.7Description of boot address option bytes . . . . .176
4.5FLASH protection mechanisms . . . . .177
4.5.1FLASH configuration protection . . . . .177
4.5.2Write protection . . . . .178
4.5.3Readout protection (RDP) . . . . .179
4.5.4Proprietary code readout protection (PCROP) . . . . .183
4.5.5Secure access mode . . . . .184
4.6FLASH low-power modes . . . . .186
4.6.1Introduction . . . . .186
4.6.2Managing the FLASH domain switching to DStop or DStandby . . . . .186
4.7FLASH error management . . . . .187
4.7.1Introduction . . . . .187
4.7.2Write protection error (WRPERR) . . . . .187
4.7.3Programming sequence error (PGSERR) . . . . .188
4.7.4Strobe error (STRBERR) . . . . .189
4.7.5Inconsistency error (INCERR) . . . . .189
4.7.6Operation error (OPERR) . . . . .189
4.7.7Error correction code error (SNECCERR/DBECCERR) . . . . .190
4.7.8Read protection error (RDPERR) . . . . .190
4.7.9Read secure error (RDSERR) . . . . .191
4.7.10CRC read error (CRCRDERR) . . . . .191
4.7.11Option byte change error (OPTCHANGEERR) . . . . .191
4.7.12Miscellaneous HardFault errors . . . . .191
4.8FLASH interrupts . . . . .192
4.9FLASH registers . . . . .194
4.9.1FLASH access control register (FLASH_ACR) . . . . .194
4.9.2FLASH key register (FLASH_KEYR) . . . . .194
4.9.3FLASH option key register (FLASH_OPTKEYR) . . . . .195
4.9.4FLASH control register (FLASH_CR) . . . . .195
4.9.5FLASH status register (FLASH_SR) . . . . .200
4.9.6FLASH clear control register (FLASH_CCR) . . . . .203
4.9.7FLASH option control register (FLASH_OPTCR) . . . . .204
4.9.8FLASH option status register (FLASH_OPTSR_CUR) . . . . .205
4.9.9FLASH option status register (FLASH_OPTSR_PRG) . . . . .207
4.9.10FLASH option clear control register (FLASH_OPTCCR) . . . . .209
4.9.11FLASH protection address (FLASH_PRAR_CUR) . . . . .210
4.9.12FLASH protection address (FLASH_PRAR_PRG) . . . . .210
4.9.13FLASH secure address (FLASH_SCAR_CUR) . . . . .211
4.9.14FLASH secure address (FLASH_SCAR_PRG) . . . . .212
4.9.15FLASH write sector protection (FLASH_WPSN_CUR) . . . . .212
4.9.16FLASH write sector protection (FLASH_WPSN_PRG) . . . . .213
4.9.17FLASH register boot address for Arm® Cortex®-M7 core
(FLASH_BOOT_CUR) . . . . .		213
4.9.18FLASH register boot address for Arm® Cortex®-M7 core
(FLASH_BOOT_PRG) . . . . .		214
4.9.19FLASH CRC control register (FLASH_CRCCR) . . . . .214
4.9.20FLASH CRC start address register (FLASH_CRCSADDR) . . . . .216
4.9.21FLASH CRC end address register (FLASH_CRCEADDR) . . . . .216
4.9.22FLASH CRC data register (FLASH_CRCDATAR) . . . . .217
4.9.23FLASH ECC fail address (FLASH_ECC_FAR) . . . . .217
4.9.24FLASH option status register 2 (FLASH_OPTSR2_CUR) . . . . .218
4.9.25FLASH option status register 2 (FLASH_OPTSR2_PRG) . . . . .218
4.10FLASH register map and reset values . . . . .220
5Secure memory management (SMM) . . . . .224
5.1Introduction . . . . .224
5.2Glossary . . . . .224
5.3Secure access mode . . . . .225
5.3.1Associated features . . . . .225
5.3.2Boot state machine . . . . .226
5.3.3Secure access mode configuration . . . . .227
5.4Root secure services (RSS) . . . . .227
5.4.1Secure area setting service . . . . .227
5.4.2Secure area exiting service . . . . .227
5.4.3OTFDEC encryption service . . . . .228
5.5Secure user software . . . . .228
5.5.1Access rules . . . . .228
5.5.2Setting secure user memory area . . . . .228
5.6Summary of Flash protection mechanisms . . . . .229
6Power control (PWR) . . . . .230
6.1Introduction . . . . .230
6.2PWR main features . . . . .230
6.3PWR block diagram . . . . .231
6.3.1PWR pins and internal signals . . . . .232
6.4Power supplies . . . . .233
6.4.1System supply startup . . . . .238
6.4.2Core domain . . . . .242
6.4.3PWR external supply . . . . .245
6.4.4Backup domain . . . . .245
6.4.5VBAT battery charging . . . . .247
6.4.6Analog supply . . . . .247
6.4.7USB regulator . . . . .248
6.5Power supply supervision . . . . .249
6.5.1Power-on reset (POR)/power-down reset (PDR) . . . . .249
6.5.2Brownout reset (BOR) . . . . .250
6.5.3Programmable voltage detector (PVD) . . . . .251
6.5.4Analog voltage detector (AVD) . . . . .252
6.5.5Battery voltage thresholds . . . . .253
6.5.6Temperature thresholds . . . . .254
6.5.7VCORE maximum voltage level detector . . . . .254
6.6Power management . . . . .255
6.6.1Operating modes . . . . .257
6.6.2Voltage scaling . . . . .260
6.6.3Power control modes . . . . .261
6.6.4Power management examples . . . . .265
6.7Low-power modes . . . . .271
6.7.1Slowing down system clocks . . . . .271
6.7.2Controlling peripheral clocks . . . . .271
6.7.3Entering low-power modes . . . . .271
6.7.4Exiting from low-power modes . . . . .272
6.7.5CSleep mode . . . . .273
6.7.6CStop mode . . . . .273
6.7.7DStop mode . . . . .274
6.7.8Stop mode . . . . .276
6.7.9DStandby mode . . . . .278
6.7.10Standby mode . . . . .280
6.7.11Monitoring low-power modes . . . . .282
6.8PWR registers . . . . .283
6.8.1PWR control register 1 (PWR_CR1) . . . . .283
6.8.2PWR control status register 1 (PWR_CSR1) . . . . .285
6.8.3PWR control register 2 (PWR_CR2) . . . . .286
6.8.4PWR control register 3 (PWR_CR3) . . . . .287
6.8.5PWR CPU control register (PWR_CPUCR) . . . . .289
6.8.6PWR D3 domain control register (PWR_D3CR) . . . . .291
6.8.7PWR wakeup clear register (PWR_WKUPCR) . . . . .292
6.8.8PWR wakeup flag register (PWR_WKUPFR) . . . . .292
6.8.9PWR wakeup enable and polarity register (PWR_WKUPEPR) . . . . .293
6.8.10PWR register map . . . . .294
7Low-power D3 domain application example . . . . .295
7.1Introduction . . . . .295
7.2EXTI, RCC and PWR interconnections . . . . .295
7.2.1Interrupts and wakeup . . . . .297
7.2.2Block interactions . . . . .297
7.2.3Role of DMAMUX2 in D3 domain . . . . .298
7.3Low-power application example based on
LPUART1 transmission . . . . .		299
7.3.1Memory retention . . . . .299
7.3.2Memory-to-peripheral transfer using LPUART1 interface . . . . .299
7.3.3Overall description of the low-power application example based on
LPUART1 transmission . . . . .		304
7.3.4Alternate implementations . . . . .305
7.4Other low-power applications . . . . .306
8Reset and clock control (RCC) . . . . .307
8.1RCC main features . . . . .307
8.2RCC block diagram . . . . .308
8.3RCC pins and internal signals . . . . .308
8.4RCC reset block functional description . . . . .310
8.4.1Power-on/off reset . . . . .310
8.4.2System reset . . . . .311
8.4.3Local resets . . . . .312
8.4.4Reset source identification . . . . .314
8.4.5Low-power mode security reset (lpwr_rst) . . . . .315
8.4.6Backup domain reset . . . . .315
8.4.7Power-on and wakeup sequences . . . . .315
8.5RCC clock block functional description . . . . .318
8.5.1Clock naming convention . . . . .320
8.5.2Description of the oscillators . . . . .320
8.5.3Clock Security System (CSS) . . . . .325
8.5.4Clock output generation (MCO1/MCO2) . . . . .326
8.5.5PLL description . . . . .326
8.5.6System clock (sys_ck) . . . . .331
8.5.7Handling clock generators in Stop and Standby mode . . . . .333
8.5.8Kernel clock selection . . . . .335
8.5.9General clock concept overview . . . . .348
8.5.10Peripheral allocation . . . . .352
8.5.11Peripheral clock gating control . . . . .354
8.5.12CPU and bus matrix clock gating control . . . . .359
8.6RCC Interrupts . . . . .361
8.7RCC registers . . . . .362
8.7.1Register mapping overview . . . . .362
8.7.2RCC source control register (RCC_CR) . . . . .363
8.7.3RCC HSI configuration register (RCC_HSICFGR) . . . . .367
8.7.4RCC clock recovery RC register (RCC_CRRRCR) . . . . .368
8.7.5RCC CSI configuration register (RCC_CSICFGR) . . . . .369
8.7.6RCC clock configuration register (RCC_CFGR) . . . . .370
8.7.7RCC domain 1 clock configuration register (RCC_D1CFGR) . . . . .373
8.7.8RCC domain 2 clock configuration register (RCC_D2CFGR) . . . . .375
8.7.9RCC Domain 3 Clock Configuration Register (RCC_D3CFGR) . . . . .376
8.7.10RCC PLLs clock source selection register (RCC_PLLCKSELR) . . . . .377
8.7.11RCC PLLs Configuration Register (RCC_PLLCFGR) . . . . .379
8.7.12RCC PLL1 dividers configuration register (RCC_PLL1DIVR) . . . . .382
8.7.13RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .384
8.7.14RCC PLL2 dividers configuration register (RCC_PLL2DIVR) . . . . .385
8.7.15RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . .387
8.7.16RCC PLL3 dividers configuration register (RCC_PLL3DIVR) . . . . .388
8.7.17RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . .390
8.7.18RCC domain 1 kernel clock configuration register
(RCC_D1CCIPR) . . . . .		391
8.7.19RCC domain 2 kernel clock configuration register
(RCC_D2CCIP1R) . . . . .		393
8.7.20RCC domain 2 kernel clock configuration register (RCC_D2CCIP2R) . . . . .395
8.7.21RCC domain 3 kernel clock configuration register (RCC_D3CCIPR) . . . . .397
8.7.22RCC clock source interrupt enable register (RCC_CIER) . . . . .400
8.7.23RCC clock source interrupt flag register (RCC_CIFR) . . . . .402
8.7.24RCC clock source interrupt clear register (RCC_CICR) . . . . .404
8.7.25RCC backup domain control register (RCC_BDCR) . . . . .406
8.7.26RCC Clock Control and Status Register (RCC_CSR) . . . . .408
8.7.27RCC AHB3 reset register (RCC_AHB3RSTR) . . . . .409
8.7.28RCC AHB1 peripheral reset register(RCC_AHB1RSTR) . . . . .411
8.7.29RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .412
8.7.30RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .414
8.7.31RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .416
8.7.32RCC APB1 peripheral reset register (RCC_APB1LRSTR) . . . . .417
8.7.33RCC APB1 peripheral reset register (RCC_APB1HRSTR) . . . . .420
8.7.34RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .422
8.7.35RCC APB4 peripheral reset register (RCC_APB4RSTR) . . . . .424
8.7.36RCC global control register (RCC_GCR) . . . . .426
8.7.37RCC D3 Autonomous mode register (RCC_D3AMR) . . . . .427
8.7.38RCC reset status register (RCC_RSR) . . . . .430
8.7.39RCC AHB3 clock register (RCC_AHB3ENR) . . . . .432
8.7.40RCC AHB1 clock register (RCC_AHB1ENR) . . . . .434
8.7.41RCC AHB2 clock register (RCC_AHB2ENR) . . . . .436
8.7.42RCC AHB4 clock register (RCC_AHB4ENR) . . . . .438
8.7.43RCC APB3 clock register (RCC_APB3ENR) . . . . .440
8.7.44RCC APB1 clock register (RCC_APB1LENR) . . . . .441
8.7.45RCC APB1 clock register (RCC_APB1HENR) . . . . .445
8.7.46RCC APB2 clock register (RCC_APB2ENR) . . . . .447
8.7.47RCC APB4 clock register (RCC_APB4ENR) . . . . .450
8.7.48RCC AHB3 Sleep clock register (RCC_AHB3LPENR) . . . . .453
8.7.49RCC AHB1 Sleep clock register (RCC_AHB1LPENR) . . . . .455
8.7.50RCC AHB2 Sleep clock register (RCC_AHB2LPENR) . . . . .457
8.7.51RCC AHB4 Sleep clock register (RCC_AHB4LPENR) . . . . .459
8.7.52RCC APB3 Sleep Clock Register (RCC_APB3LPENR) . . . . .461
8.7.53RCC APB1 Low Sleep clock register (RCC_APB1LLPENR) . . . . .462
8.7.54RCC APB1 High Sleep clock register (RCC_APB1HLPENR) . . . . .466
8.7.55RCC APB2 Sleep clock register (RCC_APB2LPENR) . . . . .468
10.4.1HSEM register semaphore x (HSEM_Rx) . . . . .501
10.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .502
10.4.3HSEM interrupt enable register (HSEM_IER) . . . . .503
10.4.4HSEM interrupt clear register (HSEM_ICR) . . . . .504
10.4.5HSEM interrupt status register (HSEM_ISR) . . . . .504
10.4.6HSEM interrupt status register (HSEM_MISR) . . . . .504
10.4.7HSEM clear register (HSEM_CR) . . . . .505
10.4.8HSEM interrupt clear register (HSEM_KEYR) . . . . .505
10.4.9HSEM register map . . . . .507
11General-purpose I/Os (GPIO) . . . . .508
11.1Introduction . . . . .508
11.2GPIO main features . . . . .508
11.3GPIO functional description . . . . .508
11.3.1General-purpose I/O (GPIO) . . . . .511
11.3.2I/O pin alternate function multiplexer and mapping . . . . .511
11.3.3I/O port control registers . . . . .512
11.3.4I/O port data registers . . . . .512
11.3.5I/O data bitwise handling . . . . .512
11.3.6GPIO locking mechanism . . . . .513
11.3.7I/O alternate function input/output . . . . .513
11.3.8External interrupt/wakeup lines . . . . .513
11.3.9Input configuration . . . . .514
11.3.10Output configuration . . . . .514
11.3.11I/O compensation cell . . . . .515
11.3.12Alternate function configuration . . . . .515
11.3.13Analog configuration . . . . .516
11.3.14Using the HSE or LSE oscillator pins as GPIOs . . . . .517
11.3.15Using the GPIO pins in the backup supply domain . . . . .517
11.4GPIO registers . . . . .518
11.4.1GPIO port mode register (GPIOx_MODER)
(x = A to H, J, K) . . . . .		518
11.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to H, J, K) . . . . .		518
11.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to H, J, K) . . . . .		519
11.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to H, J, K) . . . . .		519
11.4.5GPIO port input data register (GPIOx_IDR)
(x = A to H, J, K) . . . . .		520
11.4.6GPIO port output data register (GPIOx_ODR)
(x = A to H, J, K) . . . . .		520
11.4.7GPIO port bit set/reset register (GPIOx_BRR)
(x = A to H, J, K) . . . . .		521
11.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to H, J, K) . . . . .		521
11.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to H, J, K) . . . . .		522
11.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to H, J, K) . . . . .		523
11.4.11GPIO register map . . . . .525
12System configuration controller (SYSCFG) . . . . .527
12.1Introduction . . . . .527
12.2SYSCFG main features . . . . .527
12.3Management of timer break input lock . . . . .527
12.4SYSCFG registers . . . . .528
12.4.1SYSCFG peripheral mode configuration register (SYSCFG_PMCR) . . . . .528
12.4.2SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		530
12.4.3SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		530
12.4.4SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		532
12.4.5SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		533
12.4.6SYSCFG timer break lockup register (SYSCFG_CFGR) . . . . .533
12.4.7SYSCFG compensation cell control/status register
(SYSCFG_CCCSR) . . . . .		536
12.4.8SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . .537
12.4.9SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . .537
12.4.10SYSCFG ADC2 internal input alternate connection register
(SYSCFG_ADC2ALT) . . . . .		538
12.4.11SYSCFG package register (SYSCFG_PKGR) . . . . .538
12.4.12SYSCFG user register 0 (SYSCFG_UR0) . . . . .540
12.4.13SYSCFG user register 2 (SYSCFG_UR2) . . . . .540
12.4.14SYSCFG user register 3 (SYSCFG_UR3) . . . . .541
12.4.15SYSCFG user register 4 (SYSCFG_UR4) . . . . .541
12.4.16SYSCFG user register 5 (SYSCFG_UR5) . . . . .541
12.4.17SYSCFG user register 6 (SYSCFG_UR6) . . . . .542
12.4.18SYSCFG user register 7 (SYSCFG_UR7) . . . . .542
12.4.19SYSCFG user register 11 (SYSCFG_UR11) . . . . .543
12.4.20SYSCFG user register 12 (SYSCFG_UR12) . . . . .543
12.4.21SYSCFG user register 13 (SYSCFG_UR13) . . . . .544
12.4.22SYSCFG user register 14 (SYSCFG_UR14) . . . . .545
12.4.23SYSCFG user register 15 (SYSCFG_UR15) . . . . .546
12.4.24SYSCFG user register 16 (SYSCFG_UR16) . . . . .547
12.4.25SYSCFG user register 17 (SYSCFG_UR17) . . . . .547
12.4.26SYSCFG user register 18 (SYSCFG_UR18) . . . . .548
12.4.27SYSCFG register maps . . . . .549
13Block interconnect . . . . .552
13.1Peripheral interconnect . . . . .552
13.1.1Introduction . . . . .552
13.1.2Connection overview . . . . .552
13.2Wakeup from low power modes . . . . .571
13.3DMA . . . . .576
13.3.1MDMA (D1 domain) . . . . .577
13.3.2DMAMUX1, DMA1 and DMA2 (D2 domain) . . . . .579
13.3.3DMAMUX2, BDMA (D3 domain) . . . . .585
14MDMA controller (MDMA) . . . . .588
14.1MDMA introduction . . . . .588
14.2MDMA main features . . . . .588
14.3MDMA functional description . . . . .590
14.3.1MDMA block diagram . . . . .590
14.3.2MDMA internal signals . . . . .590
14.3.3MDMA overview . . . . .590
14.3.4MDMA channel . . . . .592
14.3.5Source, destination and transfer modes . . . . .592
14.3.6Pointer update . . . . .592
14.3.7MDMA buffer transfer . . . . .593
14.3.8Request arbitration . . . . .594
14.3.9FIFO . . . . .594
14.3.10Block transfer . . . . .594
14.3.11Block repeat mode . . . . .595
14.3.12Linked-list mode . . . . .595
14.3.13MDMA transfer completion . . . . .595
14.3.14MDMA transfer suspension . . . . .595
14.3.15Error management . . . . .596
14.4MDMA interrupts . . . . .596
14.5MDMA registers . . . . .597
14.5.1MDMA global interrupt/status register (MDMA_GISR0) . . . . .597
14.5.2MDMA channel x interrupt/status register (MDMA_CxISR) . . . . .597
14.5.3MDMA channel x interrupt flag clear register (MDMA_CxIFCR) . . . . .599
14.5.4MDMA channel x error status register (MDMA_CxESR) . . . . .599
14.5.5MDMA channel x control register (MDMA_CxCR) . . . . .600
14.5.6MDMA channel x transfer configuration register (MDMA_CxTCR) . . . . .602
14.5.7MDMA channel x block number of data register (MDMA_CxBNDTR) . . . . .606
14.5.8MDMA channel x source address register (MDMA_CxSAR) . . . . .607
14.5.9MDMA channel x destination address register (MDMA_CxDAR) . . . . .608
14.5.10MDMA channel x block repeat address update register
(MDMA_CxBRUR) . . . . .		608
14.5.11MDMA channel x link address register (MDMA_CxLAR) . . . . .609
14.5.12MDMA channel x trigger and bus selection register
(MDMA_CxTBR) . . . . .		610
14.5.13MDMA channel x mask address register (MDMA_CxMAR) . . . . .611
14.5.14MDMA channel x mask data register (MDMA_CxMDR) . . . . .611
14.5.15MDMA register map . . . . .612
15Direct memory access controller (DMA) . . . . .613
15.1DMA introduction . . . . .613
15.2DMA main features . . . . .613
15.3DMA functional description . . . . .615
15.3.1DMA block diagram . . . . .615
15.3.2DMA internal signals . . . . .615
15.3.3DMA overview . . . . .615
15.3.4DMA transactions . . . . .616
15.3.5DMA request mapping . . . . .616
15.3.6Arbiter . . . . .617
15.3.7DMA streams . . . . .617
15.3.8Source, destination and transfer modes . . . . .617
15.3.9Pointer incrementation . . . . .621
15.3.10Circular mode . . . . .622
15.3.11Double-buffer mode . . . . .622
15.3.12Programmable data width, packing/unpacking, endianness . . . . .623
15.3.13Single and burst transfers . . . . .624
15.3.14FIFO . . . . .625
15.3.15DMA transfer completion . . . . .628
15.3.16DMA transfer suspension . . . . .629
15.3.17Flow controller . . . . .630
15.3.18Summary of the possible DMA configurations . . . . .631
15.3.19Stream configuration procedure . . . . .631
15.3.20Error management . . . . .632
15.4DMA interrupts . . . . .633
15.5DMA registers . . . . .634
15.5.1DMA low interrupt status register (DMA_LISR) . . . . .634
15.5.2DMA high interrupt status register (DMA_HISR) . . . . .635
15.5.3DMA low interrupt flag clear register (DMA_LIFCR) . . . . .636
15.5.4DMA high interrupt flag clear register (DMA_HIFCR) . . . . .636
15.5.5DMA stream x configuration register (DMA_SxCR) . . . . .637
15.5.6DMA stream x number of data register (DMA_SxNDTR) . . . . .640
15.5.7DMA stream x peripheral address register (DMA_SxPAR) . . . . .641
15.5.8DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . .		641
15.5.9DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . .		641
15.5.10DMA stream x FIFO control register (DMA_SxFCR) . . . . .642
15.5.11DMA register map . . . . .644
16Basic direct memory access controller (BDMA) . . . . .648
16.1Introduction . . . . .648
16.2BDMA main features . . . . .648
16.3BDMA implementation . . . . .649
16.3.1BDMA . . . . .649
16.3.2BDMA request mapping . . . . .649
16.4BDMA functional description . . . . .649
16.4.1BDMA block diagram . . . . .649
16.4.2BDMA pins and internal signals . . . . .650
16.4.3BDMA transfers . . . . .650
16.4.4BDMA arbitration . . . . .651
16.4.5BDMA channels . . . . .651
16.4.6BDMA data width, alignment and endianness . . . . .656
16.4.7BDMA error management . . . . .657
16.5BDMA interrupts . . . . .658
16.6BDMA registers . . . . .658
16.6.1BDMA interrupt status register (BDMA_ISR) . . . . .658
16.6.2BDMA interrupt flag clear register (BDMA_IFCR) . . . . .661
16.6.3BDMA channel x configuration register (BDMA_CCRx) . . . . .662
16.6.4BDMA channel x number of data to transfer register
(BDMA_CNDTRx) . . . . .		666
16.6.5BDMA channel x peripheral address register (BDMA_CPARx) . . . . .666
16.6.6BDMA channel x memory 0 address register (BDMA_CM0ARx) . . . . .667
16.6.7BDMA channel x memory 1 address register (BDMA_CM1ARx) . . . . .668
16.6.8BDMA register map . . . . .668
17DMA request multiplexer (DMAMUX) . . . . .671
17.1Introduction . . . . .671
17.2DMAMUX main features . . . . .672
17.3DMAMUX implementation . . . . .672
17.3.1DMAMUX1 and DMAMUX2 instantiation . . . . .672
17.3.2DMAMUX1 mapping . . . . .672
17.3.3DMAMUX2 mapping . . . . .674
17.4DMAMUX functional description . . . . .677
17.4.1DMAMUX block diagram . . . . .677
17.4.2DMAMUX signals . . . . .678
17.4.3DMAMUX channels . . . . .678
17.4.4DMAMUX request line multiplexer . . . . .678
17.4.5DMAMUX request generator . . . . .681
17.5DMAMUX interrupts . . . . .682
17.6DMAMUX registers . . . . .683
17.6.1DMAMUX1 request line multiplexer channel x configuration register
(DMAMUX1_CxCR) . . . . .		683
17.6.2DMAMUX2 request line multiplexer channel x configuration register
(DMAMUX2_CxCR) . . . . .		684
17.6.3DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR) . . . . .685
17.6.4DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR) . . . . .685
17.6.5DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR) . . . . .686
17.6.6DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) . . . . .686
17.6.7DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) . . . . .687
17.6.8DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR) . . . . .687
17.6.9DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR) . . . . .688
17.6.10DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR) . . . . .689
17.6.11DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR) . . . . .689
17.6.12DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR) . . . . .690
17.6.13DMAMUX register map . . . . .691
18Chrom-Art Accelerator controller (DMA2D) . . . . .693
18.1DMA2D introduction . . . . .693
18.2DMA2D main features . . . . .693
18.3DMA2D functional description . . . . .694
18.3.1General description . . . . .694
18.3.2DMA2D internal signals . . . . .695
18.3.3DMA2D control . . . . .696
18.3.4DMA2D foreground and background FIFOs . . . . .696
18.3.5DMA2D foreground and background pixel format converter (PFC) . . . . .696
18.3.6DMA2D foreground and background CLUT interface . . . . .699
18.3.7DMA2D blender . . . . .700
18.3.8DMA2D output PFC . . . . .700
18.3.9DMA2D output FIFO . . . . .701
18.3.10DMA2D output FIFO byte reordering . . . . .701
18.3.11DMA2D AXI master port timer . . . . .703
18.3.12DMA2D transactions . . . . .703
18.3.13DMA2D configuration . . . . .704
18.3.14YCbCr support . . . . .708
20Extended interrupt and event controller (EXTI) . . . . .740
20.1EXTI main features . . . . .740
20.2EXTI block diagram . . . . .740
20.2.1EXTI connections between peripherals, CPU, and D3 domain . . . . .741
20.3EXTI functional description . . . . .742
20.3.1EXTI configurable event input - CPU wakeup . . . . .743
20.3.2EXTI configurable event input - any wakeup . . . . .744
20.3.3EXTI direct event input - CPU wakeup . . . . .746
20.3.4EXTI direct event input - any wakeup . . . . .747
20.3.5EXTI D3 pending request clear selection . . . . .748
20.4EXTI event input mapping . . . . .748
20.5EXTI functional behavior . . . . .751
20.5.1EXTI CPU interrupt procedure . . . . .752
20.5.2EXTI CPU event procedure . . . . .753
20.5.3EXTI CPU wakeup procedure . . . . .753
20.5.4EXTI D3 domain wakeup for autonomous Run mode procedure . . . . .753
20.5.5EXTI software interrupt/event trigger procedure . . . . .754
20.6EXTI registers . . . . .755
20.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .755
20.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .755
20.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .756
20.6.4EXTI D3 pending mask register (EXTI_D3PMR1) . . . . .756
20.6.5EXTI D3 pending clear selection register low (EXTI_D3PCR1L) . . . . .757
20.6.6EXTI D3 pending clear selection register high (EXTI_D3PCR1H) . . . . .757
20.6.7EXTI rising trigger selection register (EXTI_RTSR2) . . . . .758
20.6.8EXTI falling trigger selection register (EXTI_FTSR2) . . . . .759
20.6.9EXTI software interrupt event register (EXTI_SWIER2) . . . . .759
20.6.10EXTI D3 pending mask register (EXTI_D3PMR2) . . . . .760
20.6.11EXTI D3 pending clear selection register low (EXTI_D3PCR2L) . . . . .761
20.6.12EXTI D3 pending clear selection register high (EXTI_D3PCR2H) . . . . .761
20.6.13EXTI rising trigger selection register (EXTI_RTSR3) . . . . .762
20.6.14EXTI falling trigger selection register (EXTI_FTSR3) . . . . .762
20.6.15EXTI software interrupt event register (EXTI_SWIER3) . . . . .763
20.6.16EXTI D3 pending mask register (EXTI_D3PMR3) . . . . .763
20.6.17EXTI D3 pending clear selection register high (EXTI_D3PCR3H) . . . . .764
20.6.18EXTI interrupt mask register (EXTI_CPUIMR1) . . . . .764
20.6.19EXTI event mask register (EXTI_CPUEMR1) . . . . .765
20.6.20EXTI pending register (EXTI_CPUPR1) . . . . .765
20.6.21EXTI interrupt mask register (EXTI_CPUIMR2) . . . . .766
20.6.22EXTI event mask register (EXTI_CPUEMR2) . . . . .767
20.6.23EXTI pending register (EXTI_CPUPR2) . . . . .767
20.6.24EXTI interrupt mask register (EXTI_CPUIMR3) . . . . .768
20.6.25EXTI event mask register (EXTI_CPUEMR3) . . . . .769
20.6.26EXTI pending register (EXTI_CPUPR3) . . . . .769
20.6.27EXTI register map . . . . .770
21Cyclic redundancy check calculation unit (CRC) . . . . .773
21.1Introduction . . . . .773
21.2CRC main features . . . . .773
21.3CRC functional description . . . . .774
21.3.1CRC block diagram . . . . .774
21.3.2CRC internal signals . . . . .774
21.3.3CRC operation . . . . .774
21.4CRC registers . . . . .776
21.4.1CRC data register (CRC_DR) . . . . .776
21.4.2CRC independent data register (CRC_IDR) . . . . .776
21.4.3CRC control register (CRC_CR) . . . . .777
21.4.4CRC initial value (CRC_INIT) . . . . .778
21.4.5CRC polynomial (CRC_POL) . . . . .778
21.4.6CRC register map . . . . .779
22CORDIC co-processor (CORDIC) . . . . .780
22.1CORDIC introduction . . . . .780
22.2CORDIC main features . . . . .780
22.3CORDIC functional description . . . . .780
22.3.1General description . . . . .780
22.3.2CORDIC functions . . . . .780
22.3.3Fixed point representation . . . . .787
22.3.4Scaling factor . . . . .787
22.3.5Precision . . . . .788
22.3.6Zero-overhead mode . . . . .791
22.3.7Polling mode . . . . .792
22.3.8Interrupt mode . . . . .793
22.3.9DMA mode . . . . .793
22.4CORDIC registers . . . . .794
22.4.1CORDIC control/status register (CORDIC_CSR) . . . . .794
22.4.2CORDIC argument register (CORDIC_WDATA) . . . . .796
22.4.3CORDIC result register (CORDIC_RDATA) . . . . .797
22.4.4CORDIC register map . . . . .797
23Filter math accelerator (FMAC) . . . . .798
23.1FMAC introduction . . . . .798
23.2FMAC main features . . . . .798
23.3FMAC functional description . . . . .799
23.3.1General description . . . . .799
23.3.2Local memory and buffers . . . . .800
23.3.3Input buffers . . . . .800
23.3.4Output buffer . . . . .803
23.3.5Initialization functions . . . . .805
23.3.6Filter functions . . . . .806
23.3.7Fixed point representation . . . . .810
23.3.8Implementing FIR filters with the FMAC . . . . .810
23.3.9Implementing IIR filters with the FMAC . . . . .812
23.3.10Examples of filter initialization . . . . .814
23.3.11Examples of filter operation . . . . .815
23.3.12Filter design tips . . . . .817
23.4FMAC registers . . . . .818
23.4.1FMAC X1 buffer configuration register (FMAC_X1BUFCFG) . . . . .818
23.4.2FMAC X2 buffer configuration register (FMAC_X2BUFCFG) . . . . .818
23.4.3FMAC Y buffer configuration register (FMAC_YBUFCFG) . . . . .819
23.4.4FMAC parameter register (FMAC_PARAM) . . . . .820
23.4.5FMAC control register (FMAC_CR) . . . . .821
23.4.6FMAC status register (FMAC_SR) . . . . .822
23.4.7FMAC write data register (FMAC_WDATA) . . . . .823
23.4.8FMAC read data register (FMAC_RDATA) . . . . .824
23.4.9FMAC register map . . . . .824
24Flexible memory controller (FMC) . . . . .826
24.1FMC main features . . . . .826
25.3OCTOSPI implementation . . . . .909
25.4OCTOSPI functional description . . . . .910
25.4.1OCTOSPI block diagram . . . . .910
25.4.2OCTOSPI interface to memory modes . . . . .911
25.4.3OCTOSPI Regular-command protocol . . . . .911
25.4.4OCTOSPI Regular-command protocol signal interface . . . . .915
25.4.5HyperBus protocol . . . . .918
25.4.6Specific features . . . . .922
25.4.7OCTOSPI operating modes introduction . . . . .924
25.4.8OCTOSPI Indirect mode . . . . .924
25.4.9OCTOSPI Automatic status-polling mode . . . . .926
25.4.10OCTOSPI Memory-mapped mode . . . . .926
25.4.11OCTOSPI configuration introduction . . . . .927
25.4.12OCTOSPI system configuration . . . . .927
25.4.13OCTOSPI device configuration . . . . .928
25.4.14OCTOSPI Regular-command mode configuration . . . . .929
25.4.15OCTOSPI HyperBus protocol configuration . . . . .931
25.4.16OCTOSPI error management . . . . .933
25.4.17OCTOSPI BUSY and ABORT . . . . .933
25.4.18OCTOSPI reconfiguration or deactivation . . . . .934
25.4.19NCS behavior . . . . .934
25.5Address alignment and data number . . . . .935
25.6OCTOSPI interrupts . . . . .936
25.7OCTOSPI registers . . . . .937
25.7.1OCTOSPI control register (OCTOSPI_CR) . . . . .937
25.7.2OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . .939
25.7.3OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . .941
25.7.4OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . .942
25.7.5OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . .943
25.7.6OCTOSPI status register (OCTOSPI_SR) . . . . .943
25.7.7OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .944
25.7.8OCTOSPI data length register (OCTOSPI_DLR) . . . . .945
25.7.9OCTOSPI address register (OCTOSPI_AR) . . . . .945
25.7.10OCTOSPI data register (OCTOSPI_DR) . . . . .946
25.7.11OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .946
25.7.12OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .947
25.7.13OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .947
25.7.14OCTOSPI communication configuration register (OCTOSPI_CCR) . . .948
25.7.15OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .950
25.7.16OCTOSPI instruction register (OCTOSPI_IR) . . . . .951
25.7.17OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .951
25.7.18OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .952
25.7.19OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . .		952
25.7.20OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . .954
25.7.21OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .955
25.7.22OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .955
25.7.23OCTOSPI write communication configuration register
(OCTOSPI_WCCR) . . . . .		956
25.7.24OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . .958
25.7.25OCTOSPI write instruction register (OCTOSPI_WIR) . . . . .958
25.7.26OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . .959
25.7.27OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . .		959
25.7.28OCTOSPI register map . . . . .960
26OCTOSPI I/O manager (OCTOSPIM) . . . . .963
26.1Introduction . . . . .963
26.2OCTOSPIM main features . . . . .963
26.3OCTOSPIM implementation . . . . .963
26.4OCTOSPIM functional description . . . . .963
26.4.1OCTOSPIM block diagram . . . . .963
26.4.2OCTOSPIM matrix . . . . .964
26.4.3OCTOSPIM multiplexed mode . . . . .965
26.5OCTOSPIM registers . . . . .966
26.5.1OCTOSPIM control register (OCTOSPIM_CR) . . . . .966
26.5.2OCTOSPIM Port n configuration register
(OCTOSPIM_PnCR) . . . . .		966
26.5.3OCTOSPIM register map . . . . .968
27Delay block (DLYB) . . . . .969
27.1Introduction . . . . .969
27.2DLYB main features . . . . .969
27.3DLYB functional description . . . . .969
27.3.1DLYB diagram . . . . .969
27.3.2DLYB pins and internal signals . . . . .970
27.3.3General description . . . . .970
27.3.4Delay line length configuration procedure . . . . .971
27.3.5Output clock phase configuration procedure . . . . .971
27.4DLYB registers . . . . .972
27.4.1DLYB control register (DLYB_CR) . . . . .972
27.4.2DLYB configuration register (DLYB_CFGR) . . . . .973
27.4.3DLYB register map . . . . .974
28Analog-to-digital converters (ADC1/ADC2) . . . . .975
28.1Introduction . . . . .975
28.2ADC main features . . . . .976
28.3ADC implementation . . . . .977
28.4ADC functional description . . . . .978
28.4.1ADC block diagram . . . . .978
28.4.2ADC pins and internal signals . . . . .979
28.4.3ADC clocks . . . . .980
28.4.4ADC1/2 connectivity . . . . .982
28.4.5Slave AHB interface . . . . .984
28.4.6ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .984
28.4.7Single-ended and differential input channels . . . . .985
28.4.8Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) . . . . .985
28.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .991
28.4.10Constraints when writing the ADC control bits . . . . .992
28.4.11Channel selection (SQRx, JSQRx) . . . . .992
28.4.12Channel preselection register (ADC_PCSEL) . . . . .993
28.4.13Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .994
28.4.14Single conversion mode (CONT=0) . . . . .994
28.4.15Continuous conversion mode (CONT=1) . . . . .995
28.4.16Starting conversions (ADSTART, JADSTART) . . . . .996
28.4.17Timing . . . . .997
28.4.18Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .997
28.4.19Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .999
28.4.20Injected channel management . . . . .1002
28.4.21Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .1004
28.4.22Queue of context for injected conversions . . . . .1005
28.4.23Programmable resolution (RES) - fast conversion mode . . . . .1014
28.4.24End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .1014
28.4.25End of conversion sequence (EOS, JEOS) . . . . .1014
28.4.26Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . .		1015
28.4.27Data management . . . . .1016
28.4.28Managing conversions using the DFSDM . . . . .1024
28.4.29Dynamic low-power features . . . . .1024
28.4.30Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AW Dy) . . . . .		1029
28.4.31Oversampler . . . . .1032
28.4.32Dual ADC modes . . . . .1038
28.4.33VBAT supply monitoring . . . . .1053
28.4.34Monitoring the internal voltage reference . . . . .1054
28.4.35Monitoring internal DAC output . . . . .1055
28.5ADC interrupts . . . . .1056
28.6ADC registers (for each ADC) . . . . .1057
28.6.1ADC interrupt and status register (ADC_ISR) . . . . .1057
28.6.2ADC interrupt enable register (ADC_IER) . . . . .1060
28.6.3ADC control register (ADC_CR) . . . . .1062
28.6.4ADC configuration register (ADC_CFGR) . . . . .1067
28.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .1071
28.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .1073
28.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .1074
28.6.8ADC channel preselection register (ADC_PCSEL) . . . . .1075
28.6.9ADC watchdog threshold register 1 (ADC_LTR1) . . . . .1075
28.6.10ADC watchdog threshold register 1 (ADC_HTR1) . . . . .1076
28.6.11ADC regular sequence register 1 (ADC_SQR1) . . . . .1077
28.6.12ADC regular sequence register 2 (ADC_SQR2) . . . . .1078
28.6.13ADC regular sequence register 3 (ADC_SQR3) . . . . .1079
28.6.14ADC regular sequence register 4 (ADC_SQR4) . . . . .1080
28.6.15ADC regular Data Register (ADC_DR) . . . . .1081
28.6.16ADC injected sequence register (ADC_JSQR) . . . . .1082
28.6.17ADC injected channel y offset register (ADC_OFRy) . . . . .1084
28.6.18ADC injected channel y data register (ADC_JDRy) . . . . .1085
28.6.19ADC analog watchdog 2 configuration register
(ADC_AWD2CR) . . . . .		1085
28.6.20ADC analog watchdog 3 configuration register
(ADC_AWD3CR) . . . . .		1086
28.6.21ADC watchdog lower threshold register 2 (ADC_LTR2) . . . . .1086
28.6.22ADC watchdog higher threshold register 2 (ADC_HTR2) . . . . .1087
28.6.23ADC watchdog lower threshold register 3 (ADC_LTR3) . . . . .1087
28.6.24ADC watchdog higher threshold register 3 (ADC_HTR3) . . . . .1088
28.6.25ADC differential mode selection register (ADC_DIFSEL) . . . . .1088
28.6.26ADC calibration factors register (ADC_CALFACT) . . . . .1089
28.6.27ADC calibration factor register 2 (ADC_CALFACT2) . . . . .1089
28.7ADC common registers . . . . .1090
28.7.1ADC common status register (ADCx_CSR) (x=1/2) . . . . .1090
28.7.2ADC common control register (ADCx_CCR) (x=1/2) . . . . .1092
28.7.3ADC common regular data register for dual mode
(ADCx_CDR) (x=1/2) . . . . .		1095
28.7.4ADC common regular data register for 32-bit dual mode
(ADCx_CDR2) (x=1/2) . . . . .		1095
28.8ADC register map . . . . .1096
29Analog-to-digital converters (ADC3) . . . . .1100
29.1Introduction . . . . .1100
29.2ADC main features . . . . .1100
29.3ADC implementation . . . . .1101
29.4ADC functional description . . . . .1103
29.4.1ADC block diagram . . . . .1103
29.4.2ADC pins and internal signals . . . . .1104
29.4.3ADC clocks . . . . .1107
29.4.4ADC connectivity . . . . .1109
29.4.5Slave AHB interface . . . . .1110
29.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . .		1110
29.4.7Single-ended and differential input channels . . . . .1111
29.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .1111
29.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .1114
29.4.10Constraints when writing the ADC control bits . . . . .1115
29.4.11Channel selection (SQRx, JSQRx) . . . . .1116
29.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . .1117
29.4.13Single conversion mode (CONT = 0) . . . . .1118
29.4.14Continuous conversion mode (CONT = 1) . . . . .1119
29.4.15Starting conversions (ADSTART, JADSTART) . . . . .1120
29.4.16ADC timing . . . . .1121
29.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .1121
29.4.18Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .		1123
29.4.19Injected channel management . . . . .1124
29.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .1125
29.4.21Queue of context for injected conversions . . . . .1127
29.4.22Programmable resolution (RES) - fast conversion mode . . . . .1134
29.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .1135
29.4.24End of conversion sequence (EOS, JEOS) . . . . .1135
29.4.25Timing diagrams example (Single/Continuous modes,
hardware/software triggers) . . . . .		1136
29.4.26Data management . . . . .1138
29.4.27Managing conversions using the DFSDM . . . . .1144
29.4.28Dynamic low-power features . . . . .1145
29.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .		1150
29.4.30Oversampler . . . . .1154
29.4.31Temperature sensor . . . . .1160
29.4.32VBAT supply monitoring . . . . .1162
29.4.33Monitoring the internal voltage reference . . . . .1162
29.5ADC interrupts . . . . .1164
29.6ADC registers . . . . .1166
29.6.1ADC interrupt and status register (ADC_ISR) . . . . .1166
29.6.2ADC interrupt enable register (ADC_IER) . . . . .1168
29.6.3ADC control register (ADC_CR) . . . . .1170
29.6.4ADC configuration register (ADC_CFGR) . . . . .1174
29.6.5ADC configuration register 2 (ADC_CFGR2) . . . . .1178
29.6.6ADC sample time register 1 (ADC_SMPR1) . . . . .1181
29.6.7ADC sample time register 2 (ADC_SMPR2) . . . . .1181
29.6.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .1182
29.6.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .1183
29.6.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .1184
29.6.11ADC regular sequence register 1 (ADC_SQR1) . . . . .1184
29.6.12ADC regular sequence register 2 (ADC_SQR2) . . . . .1185
29.6.13ADC regular sequence register 3 (ADC_SQR3) . . . . .1186
29.6.14ADC regular sequence register 4 (ADC_SQR4) . . . . .1187
29.6.15ADC regular data register (ADC_DR) . . . . .1188
29.6.16ADC injected sequence register (ADC_JSQR) . . . . .1188
29.6.17ADC offset y register (ADC_OFRy) . . . . .1191
29.6.18ADC injected channel y data register (ADC_JDRy) . . . . .1192
29.6.19ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR) . . . . .1193
29.6.20ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR) . . . . .1193
29.6.21ADC Differential mode Selection Register (ADC_DIFSEL) . . . . .1194
29.6.22ADC Calibration Factors (ADC_CALFACT) . . . . .1195
29.7ADC common registers . . . . .1195
29.7.1ADC common control register (ADC_CCR) . . . . .1195
29.8ADC register map . . . . .1197
30Digital temperature sensor (DTS) . . . . .1200
30.1Introduction . . . . .1200
30.2DTS main features . . . . .1200
30.3DTS functional description . . . . .1201
30.3.1DTS block diagram . . . . .1201
30.3.2DTS internal signals . . . . .1201
30.3.3DTS block operation . . . . .1202
30.3.4Operating modes . . . . .1202
30.3.5Calibration . . . . .1202
30.3.6Prescaler . . . . .1202
30.3.7Temperature measurement principles . . . . .1203
30.3.8Sampling time . . . . .1204
30.3.9Quick measurement mode . . . . .1204
30.3.10Trigger input . . . . .1205
30.3.11On-off control and ready flag . . . . .1205
30.3.12Temperature measurement sequence . . . . .1206
30.4DTS low-power modes . . . . .1207
30.5DTS interrupts . . . . .1207
30.5.1Temperature window comparator . . . . .1207
30.5.2Synchronous interrupt . . . . .1207
30.5.3Asynchronous wakeup . . . . .1207
30.6DTS registers . . . . .1209
30.6.1Temperature sensor configuration register 1 (DTS_CFGR1) . . . . .1209
30.6.2Temperature sensor T0 value register 1 (DTS_T0VALR1) . . . . .1210
30.6.3Temperature sensor ramp value register (DTS_RAMPVALR) . . . . .1210
30.6.4Temperature sensor interrupt threshold register 1 (DTS_ITR1) . . . . .1211
30.6.5Temperature sensor data register (DTS_DR) . . . . .1211
30.6.6Temperature sensor status register (DTS_SR) . . . . .1212
30.6.7Temperature sensor interrupt enable register (DTS_ITENR) . . . . .1213
30.6.8Temperature sensor clear interrupt flag register (DTS_ICIFR) . . . . .1214
30.6.9Temperature sensor option register (DTS_OR) . . . . .1215
30.6.10DTS register map . . . . .1216
31Digital-to-analog converter (DAC) . . . . .1217
31.1Introduction . . . . .1217
31.2DAC main features . . . . .1217
31.3DAC implementation . . . . .1218
31.4DAC functional description . . . . .1219
31.4.1DAC block diagram . . . . .1219
31.4.2DAC pins and internal signals . . . . .1220
31.4.3DAC channel enable . . . . .1221
31.4.4DAC data format . . . . .1221
31.4.5DAC conversion . . . . .1223
31.4.6DAC output voltage . . . . .1223
31.4.7DAC trigger selection . . . . .1223
31.4.8DMA requests . . . . .1224
31.4.9Noise generation . . . . .1224
31.4.10Triangle-wave generation . . . . .1226
31.4.11DAC channel modes . . . . .1227
31.4.12DAC channel buffer calibration . . . . .1230
31.4.13Dual DAC channel conversion modes (if dual channels are available) . . . . .1231
31.5DAC in low-power modes . . . . .1235
31.6DAC interrupts . . . . .1236
31.7DAC registers . . . . .1237
31.7.1DAC control register (DAC_CR) . . . . .1237
31.7.2DAC software trigger register (DAC_SWTRGR) . . . . .1240
31.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) .....1241
31.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) .....1241
31.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) .....1242
31.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) .....1242
31.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) .....1243
31.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) .....1243
31.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) .....1244
31.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) .....1244
31.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) .....1245
31.7.12DAC channel1 data output register (DAC_DOR1) .....1245
31.7.13DAC channel2 data output register (DAC_DOR2) .....1246
31.7.14DAC status register (DAC_SR) .....1246
31.7.15DAC calibration control register (DAC_CCR) .....1248
31.7.16DAC mode control register (DAC_MCR) .....1248
31.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) .....1250
31.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) .....1250
31.7.19DAC sample and hold time register (DAC_SHHR) .....1251
31.7.20DAC sample and hold refresh time register (DAC_SHRR) .....1251
31.7.21DAC register map .....1253
32Voltage reference buffer (VREFBUF) .....1255
32.1Introduction .....1255
32.2VREFBUF functional description .....1255
32.3VREFBUF registers .....1256
32.3.1VREFBUF control and status register (VREFBUF_CSR) .....1256
32.3.2VREFBUF calibration control register (VREFBUF_CCR) .....1257
32.3.3VREFBUF register map .....1257
33Comparator (COMP) .....1258
33.1Introduction . . . . .1258
33.2COMP main features . . . . .1258
33.3COMP functional description . . . . .1259
33.3.1COMP block diagram . . . . .1259
33.3.2COMP pins and internal signals . . . . .1259
33.3.3COMP reset and clocks . . . . .1261
33.3.4Comparator LOCK mechanism . . . . .1261
33.3.5Window comparator . . . . .1261
33.3.6Hysteresis . . . . .1261
33.3.7Comparator output blanking function . . . . .1262
33.3.8Comparator output on GPIOs . . . . .1263
33.3.9Comparator output redirection . . . . .1264
33.3.10COMP power and speed modes . . . . .1264
33.4COMP low-power modes . . . . .1265
33.5COMP interrupts . . . . .1265
33.5.1Interrupt through EXTI block . . . . .1265
33.5.2Interrupt through NVIC of the CPU . . . . .1266
33.6SCALER function . . . . .1266
33.7COMP registers . . . . .1267
33.7.1Comparator status register (COMP_SR) . . . . .1267
33.7.2Comparator interrupt clear flag register (COMP_ICFR) . . . . .1267
33.7.3Comparator option register (COMP_OR) . . . . .1268
33.7.4Comparator configuration register 1 (COMP_CFGR1) . . . . .1268
33.7.5Comparator configuration register 2 (COMP_CFGR2) . . . . .1270
33.7.6COMP register map . . . . .1273
34Operational amplifiers (OPAMP) . . . . .1274
34.1Introduction . . . . .1274
34.2OPAMP main features . . . . .1274
34.3OPAMP functional description . . . . .1274
34.3.1OPAMP reset and clocks . . . . .1274
34.3.2Initial configuration . . . . .1275
34.3.3Signal routing . . . . .1275
34.3.4OPAMP modes . . . . .1276
34.3.5Calibration . . . . .1283
34.4OPAMP low-power modes . . . . .1285
34.5OPAMP PGA gain . . . . .1285
34.6OPAMP registers . . . . .1285
34.6.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .1285
34.6.2OPAMP1 trimming register in normal mode (OPAMP1_OTR) . . . . .1287
34.6.3OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR) . . . . .1288
34.6.4OPAMP option register (OPAMP_OR) . . . . .1288
34.6.5OPAMP2 control/status register (OPAMP2_CSR) . . . . .1288
34.6.6OPAMP2 trimming register in normal mode (OPAMP2_OTR) . . . . .1290
34.6.7OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR) . . . . .1291
34.6.8OPAMP register map . . . . .1292
35Digital filter for sigma delta modulators (DFSDM) . . . . .1293
35.1Introduction . . . . .1293
35.2DFSDM main features . . . . .1294
35.3DFSDM implementation . . . . .1295
35.4DFSDM functional description . . . . .1296
35.4.1DFSDM block diagram . . . . .1296
35.4.2DFSDM pins and internal signals . . . . .1297
35.4.3DFSDM reset and clocks . . . . .1298
35.4.4Serial channel transceivers . . . . .1299
35.4.5Configuring the input serial interface . . . . .1309
35.4.6Parallel data inputs . . . . .1309
35.4.7Channel selection . . . . .1312
35.4.8Digital filter configuration . . . . .1312
35.4.9Integrator unit . . . . .1313
35.4.10Analog watchdog . . . . .1314
35.4.11Short-circuit detector . . . . .1316
35.4.12Extreme detector . . . . .1317
35.4.13Data unit block . . . . .1317
35.4.14Signed data format . . . . .1318
35.4.15Launching conversions . . . . .1319
35.4.16Continuous and fast continuous modes . . . . .1319
35.4.17Request precedence . . . . .1320
35.4.18Power optimization in run mode . . . . .1321
35.5DFSDM interrupts . . . . .1321
35.6DFSDM DMA transfer . . . . .1323
35.7DFSDM channel y registers (y=0..7) . . . . .1323
35.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . .1323
35.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . .1325
35.7.3DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . .		1326
35.7.4DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . .		1327
35.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .1327
35.7.6DFSDM channel y delay register (DFSDM_CHyDLYR) . . . . .1328
35.8DFSDM filter x module registers (x=0..3) . . . . .1329
35.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .1329
35.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .1332
35.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .1333
35.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .1335
35.8.5DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . .		1336
35.8.6DFSDM filter x control register (DFSDM_FLTxFR) . . . . .1336
35.8.7DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . .		1337
35.8.8DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . .		1338
35.8.9DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . .		1339
35.8.10DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . .		1339
35.8.11DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . .		1340
35.8.12DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . .		1341
35.8.13DFSDM filter x extremes detector maximum register
(DFSDM_FLTxFMAX) . . . . .		1341
35.8.14DFSDM filter x extremes detector minimum register
(DFSDM_FLTxFMIN) . . . . .		1342
35.8.15DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . .1342
35.8.16DFSDM register map . . . . .1343
36Digital camera interface (DCMI) . . . . .1353
36.1Introduction . . . . .1353
36.2DCMI main features . . . . .1353
36.3DCMI functional description . . . . .1353
36.3.1DCMI block diagram . . . . .1354
36.3.2DCMI pins and internal signals . . . . .1354
36.3.3DCMI clocks . . . . .1355
36.3.4DCMI DMA interface . . . . .1355
36.3.5DCMI physical interface . . . . .1355
36.3.6DCMI synchronization . . . . .1357
36.3.7DCMI capture modes . . . . .1359
36.3.8DCMI crop feature . . . . .1360
36.3.9DCMI JPEG format . . . . .1361
36.3.10DCMI FIFO . . . . .1361
36.3.11DCMI data format description . . . . .1362
36.4DCMI interrupts . . . . .1364
36.5DCMI registers . . . . .1365
36.5.1DCMI control register (DCMI_CR) . . . . .1365
36.5.2DCMI status register (DCMI_SR) . . . . .1367
36.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .1368
36.5.4DCMI interrupt enable register (DCMI_IER) . . . . .1369
36.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .1370
36.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .1371
36.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .1371
36.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .1372
36.5.9DCMI crop window start (DCMI_CWSTR) . . . . .1373
36.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .1373
36.5.11DCMI data register (DCMI_DR) . . . . .1374
36.5.12DCMI register map . . . . .1374
37Parallel synchronous slave interface (PSSI) . . . . .1376
37.1Introduction . . . . .1376
37.2PSSI main features . . . . .1376
37.3PSSI functional description . . . . .1376
37.3.1PSSI block diagram . . . . .1377
37.3.2PSSI pins and internal signals . . . . .1377
37.3.3PSSI clock . . . . .1378
37.3.4PSSI data management . . . . .1378
37.3.5PSSI optional control signals . . . . .1380
37.4PSSI interrupts . . . . .1383
37.5PSSI registers . . . . .1384
37.5.1PSSI control register (PSSI_CR) . . . . .1384
37.5.2PSSI status register (PSSI_SR) . . . . .1386
37.5.3PSSI raw interrupt status register (PSSI_RIS) . . . . .1386
37.5.4PSSI interrupt enable register (PSSI_IER) . . . . .1387
37.5.5PSSI masked interrupt status register (PSSI_MIS) . . . . .1387
37.5.6PSSI interrupt clear register (PSSI_ICR) . . . . .1388
37.5.7PSSI data register (PSSI_DR) . . . . .1389
37.5.8PSSI register map . . . . .1389
38LCD-TFT display controller (LTDC) . . . . .1391
38.1Introduction . . . . .1391
38.2LTDC main features . . . . .1391
38.3LTDC functional description . . . . .1392
38.3.1LTDC block diagram . . . . .1392
38.3.2LTDC pins and internal signals . . . . .1392
38.3.3LTDC reset and clocks . . . . .1393
38.4LTDC programmable parameters . . . . .1395
38.4.1LTDC global configuration parameters . . . . .1395
38.4.2Layer programmable parameters . . . . .1397
38.5LTDC interrupts . . . . .1402
38.6LTDC programming procedure . . . . .1403
38.7LTDC registers . . . . .1404
38.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .1404
38.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .1405
38.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .1406
38.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .1407
38.7.5LTDC global control register (LTDC_GCR) . . . . .1407
38.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .1409
38.7.7LTDC background color configuration register (LTDC_BCCR) . . . . .1409
38.7.8LTDC interrupt enable register (LTDC_IER) . . . . .1410
38.7.9LTDC interrupt status register (LTDC_ISR) . . . . .1411
38.7.10LTDC interrupt clear register (LTDC_ICR) . . . . .1411
38.7.11LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . .1412
38.7.12LTDC current position status register (LTDC_CPSR) . . . . .1412
38.7.13LTDC current display status register (LTDC_CDSR) . . . . .1413
38.7.14LTDC layer x control register (LTDC_LxCR) . . . . .1414
38.7.15LTDC layer x window horizontal position configuration register
(LTDC_LxWHPER) . . . . .		1414
38.7.16LTDC layer x window vertical position configuration register
(LTDC_LxWVPER) . . . . .		1416
38.7.17LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . .		1417
38.7.18LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . .		1417
38.7.19LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . .		1418
38.7.20LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . .		1419
38.7.21LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . .		1419
38.7.22LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . .		1421
38.7.23LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . .		1421
38.7.24LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . .		1422
38.7.25LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . .1422
38.7.26LTDC register map . . . . .1423
39True random number generator (RNG) . . . . .1426
39.1Introduction . . . . .1426
39.2RNG main features . . . . .1426
39.3RNG functional description . . . . .1427
39.3.1RNG block diagram . . . . .1427
39.3.2RNG internal signals . . . . .1427
39.3.3Random number generation . . . . .1428
39.3.4RNG initialization . . . . .1431
39.3.5RNG operation . . . . .1432
39.3.6RNG clocking . . . . .1433
39.3.7Error management . . . . .1433
39.3.8RNG low-power usage . . . . .1434
39.4RNG interrupts . . . . .1434
39.5RNG processing time . . . . .1435
39.6RNG entropy source validation . . . . .1435
40.6CRYP processing time . . . . .1492
40.7CRYP registers . . . . .1493
40.7.1CRYP control register (CRYP_CR) . . . . .1493
40.7.2CRYP status register (CRYP_SR) . . . . .1495
40.7.3CRYP data input register (CRYP_DIN) . . . . .1496
40.7.4CRYP data output register (CRYP_DOUT) . . . . .1497
40.7.5CRYP DMA control register (CRYP_DMACR) . . . . .1497
40.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .1498
40.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .1498
40.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .1499
40.7.9CRYP key register 0L (CRYP_K0LR) . . . . .1500
40.7.10CRYP key register 0R (CRYP_K0RR) . . . . .1500
40.7.11CRYP key register 1L (CRYP_K1LR) . . . . .1501
40.7.12CRYP key register 1R (CRYP_K1RR) . . . . .1501
40.7.13CRYP key register 2L (CRYP_K2LR) . . . . .1502
40.7.14CRYP key register 2R (CRYP_K2RR) . . . . .1502
40.7.15CRYP key register 3L (CRYP_K3LR) . . . . .1503
40.7.16CRYP key register 3R (CRYP_K3RR) . . . . .1503
40.7.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .1503
40.7.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .1504
40.7.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .1504
40.7.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .1505
40.7.21CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) . . . . .1505
40.7.22CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . .1506
40.7.23CRYP register map . . . . .1507
41Hash processor (HASH) . . . . .1510
41.1Introduction . . . . .1510
41.2HASH main features . . . . .1510
41.3HASH implementation . . . . .1511
41.4HASH functional description . . . . .1511
41.4.1HASH block diagram . . . . .1511
41.4.2HASH internal signals . . . . .1512
41.4.3About secure hash algorithms . . . . .1512
41.4.4Message data feeding . . . . .1512
41.4.5Message digest computing . . . . .1514
41.4.6Message padding . . . . .1515
41.4.7HMAC operation . . . . .1517
41.4.8HASH suspend/resume operations . . . . .1519
41.4.9HASH DMA interface . . . . .1521
41.4.10HASH error management . . . . .1521
41.5HASH interrupts . . . . .1521
41.6HASH processing time . . . . .1522
41.7HASH registers . . . . .1523
41.7.1HASH control register (HASH_CR) . . . . .1523
41.7.2HASH data input register (HASH_DIN) . . . . .1525
41.7.3HASH start register (HASH_STR) . . . . .1526
41.7.4HASH digest registers . . . . .1527
41.7.5HASH interrupt enable register (HASH_IMR) . . . . .1528
41.7.6HASH status register (HASH_SR) . . . . .1529
41.7.7HASH context swap registers . . . . .1529
41.7.8HASH register map . . . . .1531
42On-The-Fly decryption engine - AXI (OTFDEC) . . . . .1533
42.1Introduction . . . . .1533
42.2OTFDEC main features . . . . .1533
42.3OTFDEC functional description . . . . .1534
42.3.1OTFDEC block diagram . . . . .1534
42.3.2OTFDEC internal signals . . . . .1535
42.3.3OTFDEC on-the-fly decryption . . . . .1535
42.3.4AES in counter mode decryption . . . . .1536
42.3.5Flow control management . . . . .1538
42.3.6OTFDEC error management . . . . .1540
42.4OTFDEC interrupts . . . . .1540
42.5OTFDEC application information . . . . .1541
42.5.1OTFDEC initialization process . . . . .1541
42.5.2OTFDEC and power management . . . . .1542
42.5.3Encrypting for OTFDEC . . . . .1542
42.5.4OTFDEC Key CRC source code . . . . .1543
42.6OTFDEC registers . . . . .1544
42.6.1OTFDEC region x configuration register (OTFDEC_RxCFGGR) . . . . .1544
42.6.2OTFDEC region x start address register (OTFDEC2_RxSTARTADDR) . . . . .1545
42.6.3OTFDEC region x end address register (OTFDEC_RxENDADDR) . . . . .1545
42.6.4OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . .1546
42.6.5OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . .1546
42.6.6OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . .1547
42.6.7OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . .1547
42.6.8OTFDEC region x key register 2 (OTFDEC_RxKEYR2) . . . . .1547
42.6.9OTFDEC region x key register 3 (OTFDEC_RxKEYR3) . . . . .1548
42.6.10OTFDEC interrupt status register (OTFDEC_ISR) . . . . .1548
42.6.11OTFDEC interrupt clear register (OTFDEC_ICR) . . . . .1549
42.6.12OTFDEC interrupt enable register (OTFDEC_IER) . . . . .1550
42.6.13OTFDEC register map . . . . .1551
43Advanced-control timers (TIM1/TIM8) . . . . .1555
43.1TIM1/TIM8 introduction . . . . .1555
43.2TIM1/TIM8 main features . . . . .1555
43.3TIM1/TIM8 functional description . . . . .1557
43.3.1Time-base unit . . . . .1557
43.3.2Counter modes . . . . .1559
43.3.3Repetition counter . . . . .1570
43.3.4External trigger input . . . . .1572
43.3.5Clock selection . . . . .1573
43.3.6Capture/compare channels . . . . .1577
43.3.7Input capture mode . . . . .1579
43.3.8PWM input mode . . . . .1580
43.3.9Forced output mode . . . . .1581
43.3.10Output compare mode . . . . .1582
43.3.11PWM mode . . . . .1583
43.3.12Asymmetric PWM mode . . . . .1586
43.3.13Combined PWM mode . . . . .1587
43.3.14Combined 3-phase PWM mode . . . . .1588
43.3.15Complementary outputs and dead-time insertion . . . . .1589
43.3.16Using the break function . . . . .1591
43.3.17Bidirectional break inputs . . . . .1597
43.3.18Clearing the OCxREF signal on an external event . . . . .1598
43.3.196-step PWM generation . . . . .1600
43.3.20One-pulse mode . . . . .1601
43.3.21Retriggerable one pulse mode . . . . .1602
43.3.22Encoder interface mode . . . . .1603
43.3.23UIF bit remapping . . . . .1605
43.3.24Timer input XOR function . . . . .1606
43.3.25Interfacing with Hall sensors . . . . .1606
43.3.26Timer synchronization . . . . .1609
43.3.27ADC synchronization . . . . .1613
43.3.28DMA burst mode . . . . .1613
43.3.29Debug mode . . . . .1614
43.4TIM1/TIM8 registers . . . . .1615
43.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1615
43.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .1616
43.4.3TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . .1619
43.4.4TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . .1621
43.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .1623
43.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .1625
43.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1626
43.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1627
43.4.9TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1630
43.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1631
43.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		1633
43.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1636
43.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1636
43.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .1636
43.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1637
43.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . .1637
43.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . .1638
43.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . .1638
43.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . .1639
43.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		1639
43.4.21TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . .1643
43.4.22TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . .1644
43.4.23TIMx capture/compare mode register 3 (TIMx_CCMR3)(x = 1, 8) . . . . .1645
43.4.24TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . .1646
43.4.25TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . .1647
43.4.26TIM1 alternate function option register 1 (TIM1_AF1) . . . . .1647
43.4.27TIM1 Alternate function register 2 (TIM1_AF2) . . . . .1649
43.4.28TIM8 Alternate function option register 1 (TIM8_AF1) . . . . .1650
43.4.29TIM8 Alternate function option register 2 (TIM8_AF2) . . . . .1652
43.4.30TIM1 timer input selection register (TIM1_TISEL) . . . . .1654
43.4.31TIM8 timer input selection register (TIM8_TISEL) . . . . .1654
43.4.32TIM1 register map . . . . .1656
43.4.33TIM8 register map . . . . .1658
44General-purpose timers (TIM2/TIM3/TIM4/TIM5/TIM23/TIM24) . . . . .1661
44.1TIM2/TIM3/TIM4/TIM5/TIM23/TIM24 introduction . . . . .1661
44.2TIM2/TIM3/TIM4/TIM5/TIM23/TIM24 main features . . . . .1661
44.3TIM2/TIM3/TIM4/TIM5/TIM23/TIM24 functional description . . . . .1663
44.3.1Time-base unit . . . . .1663
44.3.2Counter modes . . . . .1665
44.3.3Clock selection . . . . .1675
44.3.4Capture/Compare channels . . . . .1679
44.3.5Input capture mode . . . . .1680
44.3.6PWM input mode . . . . .1681
44.3.7Forced output mode . . . . .1682
44.3.8Output compare mode . . . . .1683
44.3.9PWM mode . . . . .1684
44.3.10Asymmetric PWM mode . . . . .1687
44.3.11Combined PWM mode . . . . .1688
44.3.12Clearing the OCxREF signal on an external event . . . . .1689
44.3.13One-pulse mode . . . . .1691
44.3.14Retriggerable one pulse mode . . . . .1692
44.3.15Encoder interface mode . . . . .1693
44.3.16UIF bit remapping . . . . .1695
44.3.17Timer input XOR function . . . . .1695
44.3.18Timers and external trigger synchronization . . . . .1696
44.3.19Timer synchronization . . . . .1699
44.3.20DMA burst mode . . . . .1704
44.3.21Debug mode . . . . .1705
44.4TIM2/TIM3/TIM4/TIM5/TIM23/TIM24 registers . . . . .1706
44.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5, 23, 24) . . . . .1706
44.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5, 23, 24) . . . . .1707
44.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5, 23, 24) . . . . .1709
44.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5, 23, 24) . . . . .1713
44.4.5TIMx status register (TIMx_SR)(x = 2 to 5, 23, 24) . . . . .1714
44.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5, 23, 24) . . . . .1715
44.4.7TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5, 23, 24) . . . . .		1716
44.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5, 23, 24) . . . . .		1718
44.4.9TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5, 23, 24) . . . . .		1720
44.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5, 23, 24) . . . . .		1721
44.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5, 23, 24) . . . . .		1722
44.4.12TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5, 23, 24) . . . . .1723
44.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5, 23, 24) . . . . .1724
44.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5, 23, 24) . . . . .1724
44.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5, 23, 24) . . . . .1725
44.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5, 23, 24) . . . . .1725
44.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5, 23, 24) . . . . .1726
44.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5, 23, 24) . . . . .1726
44.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5, 23, 24) . . . . .1727
44.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5, 23, 24) . . . . .1728
44.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5, 23, 24) . . . . .1728
44.4.22TIM2 alternate function option register 1 (TIM2_AF1) . . . . .1729
44.4.23TIM3 alternate function option register 1 (TIM3_AF1) . . . . .1729
44.4.24TIM4 alternate function option register 1 (TIM4_AF1) . . . . .1730
44.4.25TIM5 alternate function option register 1 (TIM5_AF1) . . . . .1730
44.4.26TIM23 alternate function option register 1 (TIM23_AF1) . . . . .1730
44.4.27TIM24 alternate function option register 1 (TIM24_AF1) . . . . .1731
44.4.28TIM2 timer input selection register (TIM2_TISEL) . . . . .1731
44.4.29TIM3 timer input selection register (TIM3_TISEL) . . . . .1732
44.4.30TIM4 timer input selection register (TIM4_TISEL) . . . . .1733
44.4.31TIM5 timer input selection register (TIM5_TISEL) . . . . .1734
44.4.32TIM23 timer input selection register (TIM23_TISEL) . . . . .1735
44.4.33TIM24 timer input selection register (TIM24_TISEL) . . . . .1735
44.4.34TIMx register map . . . . .1737
45General-purpose timers (TIM12/TIM13/TIM14) . . . . .1740
45.1TIM12/TIM13/TIM14 introduction . . . . .1740
45.2TIM12/TIM13/TIM14 main features . . . . .1740
45.2.1TIM12 main features . . . . .1740
45.2.2TIM13/TIM14 main features . . . . .1741
45.3TIM12/TIM13/TIM14 functional description . . . . .1743
45.3.1Time-base unit . . . . .1743
45.3.2Counter modes . . . . .1745
45.3.3Clock selection . . . . .1748
45.3.4Capture/compare channels . . . . .1750
45.3.5Input capture mode . . . . .1752
45.3.6PWM input mode (only for TIM12) . . . . .1753
45.3.7Forced output mode . . . . .1754
45.3.8Output compare mode . . . . .1755
45.3.9PWM mode . . . . .1756
45.3.10Combined PWM mode (TIM12 only) . . . . .1757
45.3.11One-pulse mode . . . . .1758
45.3.12Retriggerable one pulse mode (TIM12 only) . . . . .1760
45.3.13UIF bit remapping . . . . .1761
45.3.14Timer input XOR function . . . . .1761
45.3.15TIM12 external trigger synchronization . . . . .1761
45.3.16Slave mode – combined reset + trigger mode . . . . .1764
45.3.17Timer synchronization (TIM12) . . . . .1765
45.3.18Using timer output as trigger for other timers (TIM13/TIM14) . . . . .1765
45.3.19Debug mode . . . . .1765
45.4TIM12 registers . . . . .1765
45.4.1TIM12 control register 1 (TIM12_CR1) . . . . .1765
45.4.2TIM12 control register 2 (TIM12_CR2) . . . . .1766
45.4.3TIM12 slave mode control register (TIM12_SMCR) . . . . .1767
45.4.4TIM12 Interrupt enable register (TIM12_DIER) . . . . .1769
45.4.5TIM12 status register (TIM12_SR) . . . . .1769
45.4.6TIM12 event generation register (TIM12_EGR) . . . . .1770
45.4.7TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1771
45.4.8TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1772
45.4.9TIM12 capture/compare enable register (TIM12_CCER) . . . . .1775
45.4.10TIM12 counter (TIM12_CNT) . . . . .1776
45.4.11TIM12 prescaler (TIM12_PSC) . . . . .1777
45.4.12TIM12 auto-reload register (TIM12_ARR) . . . . .1777
45.4.13TIM12 capture/compare register 1 (TIM12_CCR1) . . . . .1777
45.4.14TIM12 capture/compare register 2 (TIM12_CCR2) . . . . .1778
45.4.15TIM12 timer input selection register (TIM12_TISEL) . . . . .1778
45.4.16TIM12 register map . . . . .1779
45.5TIM13/TIM14 registers . . . . .1781
45.5.1TIMx control register 1 (TIMx_CR1)(x = 13 to 14) . . . . .1781
45.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 13 to 14) . . . . .1782
45.5.3TIMx status register (TIMx_SR)(x = 13 to 14) . . . . .1782
45.5.4TIMx event generation register (TIMx_EGR)(x = 13 to 14) . . . . .1783
45.5.5TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13 to 14) . . . . .		1784
45.5.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13 to 14) . . . . .		1785
45.5.7TIMx capture/compare enable register
(TIMx_CCER)(x = 13 to 14) . . . . .		1787
45.5.8TIMx counter (TIMx_CNT)(x = 13 to 14) . . . . .1788
45.5.9TIMx prescaler (TIMx_PSC)(x = 13 to 14) . . . . .1789
45.5.10TIMx auto-reload register (TIMx_ARR)(x = 13 to 14) . . . . .1789
45.5.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 13 to 14) . . . . .1789
45.5.12TIM13 timer input selection register (TIM13_TISEL) . . . . .1790
45.5.13TIM14 timer input selection register (TIM14_TISEL) . . . . .1790
45.5.14TIM13/TIM14 register map . . . . .1791
46General-purpose timers (TIM15/TIM16/TIM17) . . . . .1793
46.1TIM15/TIM16/TIM17 introduction . . . . .1793
46.2TIM15 main features . . . . .1793
46.3TIM16/TIM17 main features . . . . .1794
46.4TIM15/TIM16/TIM17 functional description . . . . .1797
46.4.1Time-base unit . . . . .1797
46.4.2Counter modes . . . . .1799
46.4.3Repetition counter . . . . .1803
46.4.4Clock selection . . . . .1804
46.4.5Capture/compare channels . . . . .1806
46.4.6Input capture mode . . . . .1808
46.4.7PWM input mode (only for TIM15) . . . . .1809
46.4.8Forced output mode . . . . .1810
46.4.9Output compare mode . . . . .1811
46.4.10PWM mode . . . . .1812
46.4.11Combined PWM mode (TIM15 only) . . . . .1813
46.4.12Complementary outputs and dead-time insertion . . . . .1814
46.4.13Using the break function . . . . .1816
46.4.14Bidirectional break inputs . . . . .1821
46.4.156-step PWM generation . . . . .1822
46.4.16One-pulse mode . . . . .1824
46.4.17Retriggerable one pulse mode (TIM15 only) . . . . .1826
46.4.18UIF bit remapping . . . . .1826
46.4.19Timer input XOR function (TIM15 only) . . . . .1828
46.4.20External trigger synchronization (TIM15 only) . . . . .1829
46.4.21Slave mode – combined reset + trigger mode . . . . .1831
46.4.22DMA burst mode . . . . .1831
46.4.23Timer synchronization (TIM15) . . . . .1833
46.4.24Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1833
46.4.25Debug mode . . . . .1833
46.5TIM15 registers . . . . .1834
46.5.1TIM15 control register 1 (TIM15_CR1) . . . . .1834
46.5.2TIM15 control register 2 (TIM15_CR2) . . . . .1835
46.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1837
46.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1838
46.5.5TIM15 status register (TIM15_SR) . . . . .1839
46.5.6TIM15 event generation register (TIM15_EGR) . . . . .1841
46.5.7TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1842
46.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1843
46.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1846
46.5.10TIM15 counter (TIM15_CNT) . . . . .1849
46.5.11TIM15 prescaler (TIM15_PSC) .....1849
46.5.12TIM15 auto-reload register (TIM15_ARR) .....1849
46.5.13TIM15 repetition counter register (TIM15_RCR) .....1850
46.5.14TIM15 capture/compare register 1 (TIM15_CCR1) .....1850
46.5.15TIM15 capture/compare register 2 (TIM15_CCR2) .....1851
46.5.16TIM15 break and dead-time register (TIM15_BDTR) .....1851
46.5.17TIM15 DMA control register (TIM15_DCR) .....1854
46.5.18TIM15 DMA address for full transfer (TIM15_DMAR) .....1854
46.5.19TIM15 alternate register 1 (TIM15_AF1) .....1855
46.5.20TIM15 input selection register (TIM15_TISEL) .....1856
46.5.21TIM15 register map .....1857
46.6TIM16/TIM17 registers .....1860
46.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....1860
46.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .....1861
46.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .....1862
46.6.4TIMx status register (TIMx_SR)(x = 16 to 17) .....1863
46.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) .....1864
46.6.6TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) .....		1865
46.6.7TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) .....		1866
46.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) .....1868
46.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) .....1870
46.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) .....1871
46.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) .....1871
46.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) .....1872
46.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) .....1872
46.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .....1873
46.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) .....1876
46.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) .....1876
46.6.17TIM16 alternate function register 1 (TIM16_AF1) .....1877
46.6.18TIM16 input selection register (TIM16_TISEL) .....1878
46.6.19TIM17 alternate function register 1 (TIM17_AF1) .....1879
46.6.20TIM17 input selection register (TIM17_TISEL) .....1880
46.6.21TIM16/TIM17 register map .....1881
47Basic timers (TIM6/TIM7) .....1883
47.1TIM6/TIM7 introduction . . . . .1883
47.2TIM6/TIM7 main features . . . . .1883
47.3TIM6/TIM7 functional description . . . . .1884
47.3.1Time-base unit . . . . .1884
47.3.2Counting mode . . . . .1886
47.3.3UIF bit remapping . . . . .1889
47.3.4Clock source . . . . .1889
47.3.5Debug mode . . . . .1890
47.4TIM6/TIM7 registers . . . . .1890
47.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1890
47.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1892
47.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1892
47.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1893
47.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1893
47.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1893
47.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1894
47.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .1894
47.4.9TIMx register map . . . . .1895
48Low-power timer (LPTIM) . . . . .1896
48.1Introduction . . . . .1896
48.2LPTIM main features . . . . .1896
48.3LPTIM implementation . . . . .1897
48.4LPTIM functional description . . . . .1897
48.4.1LPTIM block diagram . . . . .1897
48.4.2LPTIM pins and internal signals . . . . .1899
48.4.3LPTIM input and trigger mapping . . . . .1899
48.4.4LPTIM reset and clocks . . . . .1902
48.4.5Glitch filter . . . . .1902
48.4.6Prescaler . . . . .1903
48.4.7Trigger multiplexer . . . . .1904
48.4.8Operating mode . . . . .1904
48.4.9Timeout function . . . . .1906
48.4.10Waveform generation . . . . .1906
48.4.11Register update . . . . .1907
48.4.12Counter mode . . . . .1908

50Independent watchdog (IWDG) . . . . .1932
50.1Introduction . . . . .1932
50.2IWDG main features . . . . .1932
50.3IWDG functional description . . . . .1932
50.3.1IWDG block diagram . . . . .1932
50.3.2IWDG internal signals . . . . .1933
50.3.3Window option . . . . .1933
50.3.4Hardware watchdog . . . . .1934
50.3.5Low-power freeze . . . . .1934
50.3.6Register access protection . . . . .1934
50.3.7Debug mode . . . . .1935
50.4IWDG registers . . . . .1936
50.4.1IWDG key register (IWDG_KR) . . . . .1936
50.4.2IWDG prescaler register (IWDG_PR) . . . . .1937
50.4.3IWDG reload register (IWDG_RLR) . . . . .1938
50.4.4IWDG status register (IWDG_SR) . . . . .1939
50.4.5IWDG window register (IWDG_WINR) . . . . .1940
50.4.6IWDG register map . . . . .1941
51Real-time clock (RTC) . . . . .1942
51.1Introduction . . . . .1942
51.2RTC main features . . . . .1943
51.3RTC implementation . . . . .1943
51.4RTC functional description . . . . .1944
51.4.1RTC block diagram . . . . .1944
51.4.2RTC pins and internal signals . . . . .1946
51.4.3GPIOs controlled by the RTC . . . . .1947
51.4.4Clock and prescalers . . . . .1949
51.4.5Real-time clock and calendar . . . . .1949
51.4.6Programmable alarms . . . . .1950
51.4.7Periodic auto-wakeup . . . . .1950
51.4.8RTC initialization and configuration . . . . .1951
51.4.9Reading the calendar . . . . .1952
51.4.10Resetting the RTC . . . . .1953
51.4.11RTC synchronization . . . . .1954
51.4.12RTC reference clock detection . . . . .1954
51.4.13RTC smooth digital calibration . . . . .1955
51.4.14Time-stamp function . . . . .1957
51.4.15Tamper detection . . . . .1958
51.4.16Calibration clock output . . . . .1959
51.4.17Alarm output . . . . .1960
51.5RTC low-power modes . . . . .1960
51.6RTC interrupts . . . . .1960
51.7RTC registers . . . . .1961
51.7.1RTC time register (RTC_TR) . . . . .1961
51.7.2RTC date register (RTC_DR) . . . . .1962
51.7.3RTC control register (RTC_CR) . . . . .1964
51.7.4RTC initialization and status register (RTC_ISR) . . . . .1967
51.7.5RTC prescaler register (RTC_PRER) . . . . .1970
51.7.6RTC wakeup timer register (RTC_WUTR) . . . . .1971
51.7.7RTC alarm A register (RTC_ALRMAR) . . . . .1972
51.7.8RTC alarm B register (RTC_ALRMBR) . . . . .1973
51.7.9RTC write protection register (RTC_WPR) . . . . .1974
51.7.10RTC sub second register (RTC_SSR) . . . . .1974
51.7.11RTC shift control register (RTC_SHIFTR) . . . . .1975
51.7.12RTC timestamp time register (RTC_TSTR) . . . . .1976
51.7.13RTC timestamp date register (RTC_TSDR) . . . . .1977
51.7.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .1978
51.7.15RTC calibration register (RTC_CALR) . . . . .1979
51.7.16RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . .		1980
51.7.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1983
51.7.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1984
51.7.19RTC option register (RTC_OR) . . . . .1985
51.7.20RTC backup registers (RTC_BKPxR) . . . . .1985
51.7.21RTC register map . . . . .1986
52Inter-integrated circuit (I2C) interface . . . . .1988
52.1Introduction . . . . .1988
52.2I2C main features . . . . .1988
52.3I2C implementation . . . . .1989
52.4I2C functional description . . . . .1989
52.4.1I2C block diagram . . . . .1990
52.4.2I2C pins and internal signals . . . . .1991
52.4.3I2C clock requirements . . . . .1991
52.4.4Mode selection . . . . .1991
52.4.5I2C initialization . . . . .1992
52.4.6Software reset . . . . .1997
52.4.7Data transfer . . . . .1998
52.4.8I2C slave mode . . . . .2000
52.4.9I2C master mode . . . . .2009
52.4.10I2C_TIMINGR register configuration examples . . . . .2021
52.4.11SMBus specific features . . . . .2022
52.4.12SMBus initialization . . . . .2025
52.4.13SMBus: I2C_TIMEOUTR register configuration examples . . . . .2027
52.4.14SMBus slave mode . . . . .2027
52.4.15Wakeup from Stop mode on address match . . . . .2035
52.4.16Error conditions . . . . .2035
52.4.17DMA requests . . . . .2037
52.4.18Debug mode . . . . .2038
52.5I2C low-power modes . . . . .2038
52.6I2C interrupts . . . . .2039
52.7I2C registers . . . . .2040
52.7.1I2C control register 1 (I2C_CR1) . . . . .2040
52.7.2I2C control register 2 (I2C_CR2) . . . . .2043
52.7.3I2C own address 1 register (I2C_OAR1) . . . . .2045
52.7.4I2C own address 2 register (I2C_OAR2) . . . . .2046
52.7.5I2C timing register (I2C_TIMINGR) . . . . .2047
52.7.6I2C timeout register (I2C_TIMEOUTR) . . . . .2048
52.7.7I2C interrupt and status register (I2C_ISR) . . . . .2049
52.7.8I2C interrupt clear register (I2C_ICR) . . . . .2051
52.7.9I2C PEC register (I2C_PECR) . . . . .2052
52.7.10I2C receive data register (I2C_RXDR) . . . . .2053
52.7.11I2C transmit data register (I2C_TXDR) . . . . .2053
52.7.12I2C register map . . . . .2054
53Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .2056
53.1USART introduction . . . . .2056
53.2USART main features . . . . .2057
53.3USART extended features . . . . .2058
53.4USART implementation . . . . .2058
53.5USART functional description . . . . .2059
53.5.1USART block diagram . . . . .2059
53.5.2USART signals . . . . .2060
53.5.3USART character description . . . . .2061
53.5.4USART FIFOs and thresholds . . . . .2063
53.5.5USART transmitter . . . . .2063
53.5.6USART receiver . . . . .2067
53.5.7USART baud rate generation . . . . .2074
53.5.8Tolerance of the USART receiver to clock deviation . . . . .2075
53.5.9USART Auto baud rate detection . . . . .2077
53.5.10USART multiprocessor communication . . . . .2079
53.5.11USART Modbus communication . . . . .2081
53.5.12USART parity control . . . . .2082
53.5.13USART LIN (local interconnection network) mode . . . . .2083
53.5.14USART synchronous mode . . . . .2085
53.5.15USART single-wire Half-duplex communication . . . . .2089
53.5.16USART receiver timeout . . . . .2089
53.5.17USART Smartcard mode . . . . .2090
53.5.18USART IrDA SIR ENDEC block . . . . .2094
53.5.19Continuous communication using USART and DMA . . . . .2097
53.5.20RS232 Hardware flow control and RS485 Driver Enable . . . . .2099
53.5.21USART low-power management . . . . .2102
53.6USART in low-power modes . . . . .2105
53.7USART interrupts . . . . .2106
53.8USART registers . . . . .2107
53.8.1USART control register 1 [alternate] (USART_CR1) . . . . .2107
53.8.2USART control register 1 [alternate] (USART_CR1) . . . . .2111
53.8.3USART control register 2 (USART_CR2) . . . . .2114
53.8.4USART control register 3 (USART_CR3) . . . . .2118
53.8.5USART baud rate register (USART_BRR) . . . . .2123
53.8.6USART guard time and prescaler register (USART_GTPR) . . . . .2123
53.8.7USART receiver timeout register (USART_RTOR) . . . . .2124
53.8.8USART request register (USART_RQR) . . . . .2125
53.8.9USART interrupt and status register [alternate] (USART_ISR) . . . . .2126
53.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .2132
53.8.11USART interrupt flag clear register (USART_ICR) . . . . .2137
53.8.12USART receive data register (USART_RDR) . . . . .2139
53.8.13USART transmit data register (USART_TDR) . . . . .2139
53.8.14USART prescaler register (USART_PRESC) . . . . .2140
53.8.15USART register map . . . . .2141
54Low-power universal asynchronous receiver transmitter (LPUART) . . . . .2143
54.1LPUART introduction . . . . .2143
54.2LPUART main features . . . . .2144
54.3LPUART implementation . . . . .2145
54.4LPUART functional description . . . . .2146
54.4.1LPUART block diagram . . . . .2146
54.4.2LPUART signals . . . . .2147
54.4.3LPUART character description . . . . .2147
54.4.4LPUART FIFOs and thresholds . . . . .2148
54.4.5LPUART transmitter . . . . .2149
54.4.6LPUART receiver . . . . .2152
54.4.7LPUART baud rate generation . . . . .2156
54.4.8Tolerance of the LPUART receiver to clock deviation . . . . .2157
54.4.9LPUART multiprocessor communication . . . . .2158
54.4.10LPUART parity control . . . . .2160
54.4.11LPUART single-wire Half-duplex communication . . . . .2161
54.4.12Continuous communication using DMA and LPUART . . . . .2161
54.4.13RS232 Hardware flow control and RS485 Driver Enable . . . . .2164
54.4.14LPUART low-power management . . . . .2166
54.5LPUART in low-power modes . . . . .2169
54.6LPUART interrupts . . . . .2170
54.7LPUART registers . . . . .2171
54.7.1LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2171
54.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2174
54.7.3LPUART control register 2 (LPUART_CR2) . . . . .2177
54.7.4LPUART control register 3 (LPUART_CR3) . . . . .2179
54.7.5LPUART baud rate register (LPUART_BRR) . . . . .2182
54.7.6LPUART request register (LPUART_RQR) . . . . .2183

55 Serial peripheral interface (SPI) . . . . . 2196

55.9.2Pin sharing with SPI function . . . . .2231
55.9.3Bits and fields usable in I2S/PCM mode . . . . .2232
55.9.4Slave and master modes . . . . .2233
55.9.5Supported audio protocols . . . . .2233
55.9.6Additional Serial Interface Flexibility . . . . .2239
55.9.7Start-up sequence . . . . .2241
55.9.8Stop sequence . . . . .2242
55.9.9Clock generator . . . . .2243
55.9.10Internal FIFOs . . . . .2245
55.9.11FIFOs status flags . . . . .2246
55.9.12Handling of underrun situation . . . . .2247
55.9.13Handling of overrun situation . . . . .2248
55.9.14Frame error detection . . . . .2248
55.9.15DMA Interface . . . . .2250
55.9.16Programing examples . . . . .2251
55.9.17Slave I2S Philips standard, receive . . . . .2253
55.10I2S wakeup and interrupts . . . . .2254
55.11SPI/I2S registers . . . . .2255
55.11.1SPI/I2S control register 1 (SPI_CR1) . . . . .2255
55.11.2SPI control register 2 (SPI_CR2) . . . . .2257
55.11.3SPI configuration register 1 (SPI_CFG1) . . . . .2257
55.11.4SPI configuration register 2 (SPI_CFG2) . . . . .2260
55.11.5SPI/I2S interrupt enable register (SPI_IER) . . . . .2262
55.11.6SPI/I2S status register (SPI_SR) . . . . .2263
55.11.7SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . .2266
55.11.8SPI/I2S transmit data register (SPI_TXDR) . . . . .2267
55.11.9SPI/I2S receive data register (SPI_RXDR) . . . . .2267
55.11.10SPI polynomial register (SPI_CRCPOLY) . . . . .2268
55.11.11SPI transmitter CRC register (SPI_TXCRC) . . . . .2268
55.11.12SPI receiver CRC register (SPI_RXCRC) . . . . .2269
55.11.13SPI underrun data register (SPI_UDRDR) . . . . .2270
55.11.14SPI/I2S configuration register (SPI_I2SCFGR) . . . . .2270
55.12SPI register map and reset values . . . . .2273
56Serial audio interface (SAI) . . . . .2275
56.1Introduction . . . . .2275
56.2SAI main features . . . . .2275
56.6.18SAI PDM control register (SAI_PDMCR) . . . . .2338
56.6.19SAI PDM delay register (SAI_PDMPLY) . . . . .2339
56.6.20SAI register map . . . . .2342
57SPDIF receiver interface (SPDIFRX) . . . . .2344
57.1SPDIFRX interface introduction . . . . .2344
57.2SPDIFRX main features . . . . .2344
57.3SPDIFRX functional description . . . . .2344
57.3.1SPDIFRX pins and internal signals . . . . .2345
57.3.2S/PDIF protocol (IEC-60958) . . . . .2346
57.3.3SPDIFRX decoder (SPDIFRX_DC) . . . . .2348
57.3.4SPDIFRX tolerance to clock deviation . . . . .2352
57.3.5SPDIFRX synchronization . . . . .2352
57.3.6SPDIFRX handling . . . . .2354
57.3.7Data reception management . . . . .2356
57.3.8Dedicated control flow . . . . .2358
57.3.9Reception errors . . . . .2359
57.3.10Clocking strategy . . . . .2361
57.3.11Symbol clock generation . . . . .2361
57.3.12DMA interface . . . . .2363
57.3.13Interrupt generation . . . . .2364
57.3.14Register protection . . . . .2365
57.4Programming procedures . . . . .2365
57.4.1Initialization phase . . . . .2366
57.4.2Handling of interrupts coming from SPDIFRX . . . . .2367
57.4.3Handling of interrupts coming from DMA . . . . .2367
57.5SPDIFRX interface registers . . . . .2368
57.5.1Control register (SPDIFRX_CR) . . . . .2368
57.5.2Interrupt mask register (SPDIFRX_IMR) . . . . .2370
57.5.3Status register (SPDIFRX_SR) . . . . .2371
57.5.4Interrupt flag clear register (SPDIFRX_IFCR) . . . . .2373
57.5.5Data input register (SPDIFRX_FMT0_DR) . . . . .2374
57.5.6Data input register (SPDIFRX_FMT1_DR) . . . . .2374
57.5.7Data input register (SPDIFRX_FMT2_DR) . . . . .2375
57.5.8Channel status register (SPDIFRX_CSR) . . . . .2376
57.5.9Debug information register (SPDIFRX_DIR) . . . . .2376
57.5.10SPDIFRX interface register map . . . . .2377
58Single wire protocol master interface (SWPMI) . . . . .2379
58.1Introduction . . . . .2379
58.2SWPMI main features . . . . .2380
58.3SWPMI functional description . . . . .2381
58.3.1SWPMI block diagram . . . . .2381
58.3.2SWPMI pins and internal signals . . . . .2381
58.3.3SWP initialization and activation . . . . .2382
58.3.4SWP bus states . . . . .2383
58.3.5SWPMI_IO (internal transceiver) bypass . . . . .2384
58.3.6SWPMI bit rate . . . . .2384
58.3.7SWPMI frame handling . . . . .2385
58.3.8Transmission procedure . . . . .2385
58.3.9Reception procedure . . . . .2390
58.3.10Error management . . . . .2394
58.3.11Loopback mode . . . . .2396
58.4SWPMI low-power modes . . . . .2396
58.5SWPMI interrupts . . . . .2397
58.6SWPMI registers . . . . .2398
58.6.1SWPMI configuration/control register (SWPMI_CR) . . . . .2398
58.6.2SWPMI Bitrate register (SWPMI_BRR) . . . . .2399
58.6.3SWPMI Interrupt and Status register (SWPMI_ISR) . . . . .2400
58.6.4SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . .2401
58.6.5SWPMI Interrupt Enable register (SWPMI_IER) . . . . .2402
58.6.6SWPMI Receive Frame Length register (SWPMI_RFL) . . . . .2404
58.6.7SWPMI Transmit data register (SWPMI_TDR) . . . . .2404
58.6.8SWPMI Receive data register (SWPMI_RDR) . . . . .2404
58.6.9SWPMI Option register (SWPMI_OR) . . . . .2405
58.6.10SWPMI register map and reset value table . . . . .2406
59Management data input/output (MDIOS) . . . . .2407
59.1MDIOS introduction . . . . .2407
59.2MDIOS main features . . . . .2407
59.3MDIOS functional description . . . . .2408
59.3.1MDIOS block diagram . . . . .2408
59.3.2MDIOS pins and internal signals . . . . .2408
59.3.3MDIOS protocol . . . . .2409
59.3.4MDIOS enabling and disabling .....2410
59.3.5MDIOS data .....2410
59.3.6MDIOS APB frequency .....2412
59.3.7Write/read flags and interrupts .....2412
59.3.8MDIOS error management .....2412
59.3.9MDIOS in Stop mode .....2413
59.3.10MDIOS interrupts .....2413
59.4MDIOS registers .....2414
59.4.1MDIOS configuration register (MDIOS_CR) .....2414
59.4.2MDIOS write flag register (MDIOS_WRFR) .....2415
59.4.3MDIOS clear write flag register (MDIOS_CWRFR) .....2415
59.4.4MDIOS read flag register (MDIOS_RDFR) .....2415
59.4.5MDIOS clear read flag register (MDIOS_CRDFR) .....2416
59.4.6MDIOS status register (MDIOS_SR) .....2416
59.4.7MDIOS clear flag register (MDIOS_CLRFR) .....2417
59.4.8MDIOS input data register x (MDIOS_DINRx) .....2417
59.4.9MDIOS output data register x (MDIOS_DOUTRx) .....2418
59.4.10MDIOS register map .....2418
60Secure digital input/output MultiMediaCard interface (SDMMC) ..2420
60.1SDMMC main features .....2420
60.2SDMMC implementation .....2420
60.3SDMMC bus topology .....2421
60.4SDMMC operation modes .....2423
60.5SDMMC functional description .....2424
60.5.1SDMMC block diagram .....2424
60.5.2SDMMC pins and internal signals .....2424
60.5.3General description .....2425
60.5.4SDMMC adapter .....2427
60.5.5SDMMC AHB slave interface .....2449
60.5.6SDMMC AHB master interface .....2449
60.5.7MDMA request generation .....2451
60.5.8AHB and SDMMC_CK clock relation .....2452
60.6Card functional description .....2453
60.6.1SD I/O mode .....2453
60.6.2CMD12 send timing .....2461
60.6.3Sleep (CMD5) .....2464
60.6.4Interrupt mode (Wait-IRQ) .....2465
60.6.5Boot operation .....2466
60.6.6Response R1b handling .....2469
60.6.7Reset and card cycle power .....2470
60.7Hardware flow control .....2471
60.8Ultra-high-speed phase I (UHS-I) voltage switch .....2472
60.9SDMMC interrupts .....2475
60.10SDMMC registers .....2477
60.10.1SDMMC power control register (SDMMC_POWER) .....2477
60.10.2SDMMC clock control register (SDMMC_CLKCR) .....2478
60.10.3SDMMC argument register (SDMMC_ARGR) .....2480
60.10.4SDMMC command register (SDMMC_CMDR) .....2480
60.10.5SDMMC command response register (SDMMC_RESPCMDR) .....2482
60.10.6SDMMC response x register (SDMMC_RESPxR) .....2483
60.10.7SDMMC data timer register (SDMMC_DTIMER) .....2483
60.10.8SDMMC data length register (SDMMC_DLENR) .....2484
60.10.9SDMMC data control register (SDMMC_DCTRL) .....2485
60.10.10SDMMC data counter register (SDMMC_DCNTR) .....2486
60.10.11SDMMC status register (SDMMC_STAR) .....2487
60.10.12SDMMC interrupt clear register (SDMMC_ICR) .....2490
60.10.13SDMMC mask register (SDMMC_MASKR) .....2492
60.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) .....2495
60.10.15SDMMC data FIFO registers x (SDMMC_FIFORx) .....2495
60.10.16SDMMC DMA control register (SDMMC_IDMACTRLR) .....2496
60.10.17SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) .....2497
60.10.18SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) .....		2497
60.10.19SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) .....		2498
60.10.20SDMMC register map .....2499
61Controller area network with flexible data rate (FDCAN) .....2502
61.1Introduction .....2502
61.2FDCAN main features .....2505
61.3FDCAN implementation .....2505
61.4FDCAN functional description .....2506
61.4.1Operating modes .....2507
61.4.2Message RAM .....2516
61.4.3FIFO acknowledge handling .....2527
61.4.4Bit timing .....2528
61.4.5Clock calibration on CAN .....2529
61.4.6Application .....2533
61.4.7TT CAN operations (FDCAN1 only) .....2534
61.4.8TT CAN configuration .....2535
61.4.9Message scheduling .....2537
61.4.10TT CAN gap control .....2544
61.4.11Stop watch .....2545
61.4.12Local time, cycle time, global time,
and external clock synchronization .....		2545
61.4.13TT CAN error level .....2548
61.4.14TT CAN message handling .....2549
61.4.15TT CAN interrupt and error handling .....2552
61.4.16Level 0 .....2553
61.4.17Synchronization to external time schedule .....2555
61.4.18FDCAN Rx buffer and FIFO element .....2556
61.4.19FDCAN Tx buffer element .....2558
61.4.20FDCAN Tx event FIFO element .....2560
61.4.21FDCAN standard message ID filter element .....2561
61.4.22FDCAN extended message ID filter element .....2563
61.4.23FDCAN trigger memory element .....2564
61.5FDCAN registers .....2566
61.5.1FDCAN core release register (FDCAN_CREL) .....2566
61.5.2FDCAN Endian register (FDCAN_ENDN) .....2566
61.5.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) .....2566
61.5.4FDCAN test register (FDCAN_TEST) .....2567
61.5.5FDCAN RAM watchdog register (FDCAN_RWD) .....2568
61.5.6FDCAN CC control register (FDCAN_CCCR) .....2569
61.5.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) .....2571
61.5.8FDCAN timestamp counter configuration register (FDCAN_TSCC) .....2572
61.5.9FDCAN timestamp counter value register (FDCAN_TSCV) .....2572
61.5.10FDCAN timeout counter configuration register (FDCAN_TOCC) .....2573
61.5.11FDCAN timeout counter value register (FDCAN_TOCV) .....2574
61.5.12FDCAN error counter register (FDCAN_ECR) .....2574
61.5.13FDCAN protocol status register (FDCAN_PSR) . . . . .2575
61.5.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . .2577
61.5.15FDCAN interrupt register (FDCAN_IR) . . . . .2578
61.5.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2581
61.5.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2583
61.5.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2584
61.5.19FDCAN global filter configuration register (FDCAN_GFC) . . . . .2585
61.5.20FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . .2586
61.5.21FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . .2586
61.5.22FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2587
61.5.23FDCAN high priority message status register (FDCAN_HPMS) . . . .2588
61.5.24FDCAN new data 1 register (FDCAN_NDAT1) . . . . .2588
61.5.25FDCAN new data 2 register (FDCAN_NDAT2) . . . . .2589
61.5.26FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . .2589
61.5.27FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2590
61.5.28FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2591
61.5.29FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . .2591
61.5.30FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . .2592
61.5.31FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2592
61.5.32FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2593
61.5.33FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . .		2594
61.5.34FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2595
61.5.35FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2596
61.5.36FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . .		2597
61.5.37FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2597
61.5.38FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2598
61.5.39FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . .2599
61.5.40FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) .2599
61.5.41FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . .2600
61.5.42FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		2600
61.5.43FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		2600
61.5.44FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . .2601
61.5.45FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .2602
61.5.46FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .2602
61.5.47FDCAN register map and reset values . . . . .2604
61.6TTCAN registers . . . . .2606
61.6.1FDCAN TT trigger memory configuration register (FDCAN_TTTMC) 2606
61.6.2FDCAN TT reference message configuration register
(FDCAN_TTRMC) . . . . .		2606
61.6.3FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . .2607
61.6.4FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . .2609
61.6.5FDCAN TUR configuration register (FDCAN_TURCF) . . . . .2610
61.6.6FDCAN TT operation control register (FDCAN_TTOCN) . . . . .2611
61.6.7FDCAN TT global time preset register (FDCAN_TTGTP) . . . . .2613
61.6.8FDCAN TT time mark register (FDCAN_TTTMK) . . . . .2613
61.6.9FDCAN TT interrupt register (FDCAN_TTIR) . . . . .2614
61.6.10FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . .2616
61.6.11FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . .2618
61.6.12FDCAN TT operation status register (FDCAN_TTOST) . . . . .2620
61.6.13FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . .2622
61.6.14FDCAN TT local and global time register (FDCAN_TTLGT) . . . . .2622
61.6.15FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . .2623
61.6.16FDCAN TT capture time register (FDCAN_TTCPT) . . . . .2623
61.6.17FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . .2624
61.6.18FDCAN TT trigger select register (FDCAN_TTTS) . . . . .2624
61.6.19FDCAN TT register map and reset values . . . . .2626
61.7CCU registers . . . . .2628
61.7.1Clock calibration unit core release register (FDCAN_CCU_CREL) . . . . .2628
61.7.2Calibration configuration register (FDCAN_CCU_CCFG) . . . . .2628
61.7.3Calibration status register (FDCAN_CCU_CSTAT) . . . . .2630
61.7.4Calibration watchdog register (FDCAN_CCU_CWD) . . . . .2630
61.7.5Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . .2631
61.7.6Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . . . . .2632
61.7.7CCU register map and reset value table . . . . .2633
62USB on-the-go high-speed (OTG_HS) . . . . .2634
62.1Introduction . . . . .2634
62.2OTG_HS main features . . . . .2635
62.2.1General features . . . . .2635
62.2.2Host-mode features . . . . .2636
62.2.3Peripheral-mode features . . . . .2636
62.3OTG_HS implementation . . . . .2637
62.4OTG_HS functional description . . . . .2637
62.4.1OTG_HS block diagram . . . . .2637
62.4.2OTG_HS pin and internal signals . . . . .2638
62.4.3OTG_HS core . . . . .2638
62.4.4Embedded full-speed OTG PHY connected to OTG_HS . . . . .2639
62.4.5OTG detections . . . . .2639
62.4.6High-speed OTG PHY connected to OTG_HS . . . . .2639
62.5OTG_HS dual role device (DRD) . . . . .2640
62.5.1ID line detection . . . . .2640
62.5.2HNP dual role device . . . . .2640
62.5.3SRP dual role device . . . . .2641
62.6OTG_HS as a USB peripheral . . . . .2641
62.6.1SRP-capable peripheral . . . . .2642
62.6.2Peripheral states . . . . .2642
62.6.3Peripheral endpoints . . . . .2643
62.7OTG_HS as a USB host . . . . .2645
62.7.1SRP-capable host . . . . .2646
62.7.2USB host states . . . . .2646
62.7.3Host channels . . . . .2648
62.7.4Host scheduler . . . . .2649
62.8OTG_HS SOF trigger . . . . .2650
62.8.1Host SOFs . . . . .2650
62.8.2Peripheral SOFs . . . . .2650
62.9OTG_HS low-power modes . . . . .2651
62.10OTG_HS Dynamic update of the OTG_HFIR register . . . . .2652
62.11OTG_HS data FIFOs . . . . .2652
62.11.1Peripheral FIFO architecture . . . . .2653
62.11.2Host FIFO architecture . . . . .2654
62.11.3FIFO RAM allocation . . . . .2655
62.12OTG_HS interrupts . . . . .2657
62.13OTG_HS control and status registers . . . . .2659
62.13.1CSR memory map . . . . .2659
62.14OTG_HS registers . . . . .2664
62.14.1OTG control and status register (OTG_GOTGCTL) . . . . .2664
62.14.2OTG interrupt register (OTG_GOTGINT) . . . . .2667
62.14.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .2669
62.14.4OTG USB configuration register (OTG_GUSBCFG) . . . . .2670
62.14.5OTG reset register (OTG_GRSTCTL) . . . . .2673
62.14.6OTG core interrupt register (OTG_GINTSTS) . . . . .2676
62.14.7OTG interrupt mask register (OTG_GINTMSK) . . . . .2680
62.14.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .2684
62.14.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .2685
62.14.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .2686
62.14.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .2687
62.14.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .2688
62.14.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		2688
62.14.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		2689
62.14.15OTG general core configuration register (OTG_GCCFG) . . . . .2690
62.14.16OTG core ID register (OTG_CID) . . . . .2692
62.14.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .2692
62.14.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		2696
62.14.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		2696
62.14.20Host-mode registers . . . . .2697
62.14.21OTG host configuration register (OTG_HCFG) . . . . .2697
62.14.22OTG host frame interval register (OTG_HFIR) . . . . .2698
62.14.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		2699
62.14.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		2700
62.14.25OTG host all channels interrupt register (OTG_HAINT) . . . . .2701
62.14.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		2701
62.14.27OTG host frame list base address register
(OTG_HFLBADDR) . . . . .		2702
62.14.28OTG host port control and status register (OTG_HPRT) . . . . .2702
62.14.29OTG host channel x characteristics register (OTG_HCCHARx) . . . . .2705
62.14.30OTG host channel x split control register (OTG_HCSPLTx) . . . . .2706
62.14.31OTG host channel x interrupt register (OTG_HCINTx) . . . . .2707
62.14.32OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .2708
62.14.33OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .2710
62.14.34OTG host channel x transfer size register (OTG_HCTSIZSGx) . . . .2711
62.14.35OTG host channel x DMA address register in buffer DMA [alternate]
(OTG_HCDMAX) . . . . .		2713
62.14.36OTG host channel x DMA address register in scatter/gather DMA
[alternate] (OTG_HCDMASGx) . . . . .		2713
62.14.37OTG host channel-n DMA address buffer register
(OTG_HCDMABx) . . . . .		2714
62.14.38Device-mode registers . . . . .2715
62.14.39OTG device configuration register (OTG_DCFG) . . . . .2715
62.14.40OTG device control register (OTG_DCTL) . . . . .2717
62.14.41OTG device status register (OTG_DSTS) . . . . .2719
62.14.42OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		2720
62.14.43OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		2721
62.14.44OTG device all endpoints interrupt register (OTG_DAIN) . . . . .2722
62.14.45OTG all endpoints interrupt mask register
(OTG_DAINMSK) . . . . .		2723
62.14.46OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		2724
62.14.47OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		2724
62.14.48OTG device threshold control register (OTG_DTHRCTL) . . . . .2725
62.14.49OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		2726
62.14.50OTG device each endpoint interrupt register (OTG_DEACHINT) . . . .2726
62.14.51OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) . . . . .		2727
62.14.52OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) . . . . .		2727
62.14.53OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) . . . . .		2728
62.14.54OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .2730
62.14.55OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .2732
62.14.56OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . .		2734
62.14.57OTG device IN endpoint x DMA address register
(OTG_DIEPDMAX) . . . . .		2734
62.14.58OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . .		2735
62.14.59OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . .2735
62.14.60OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) . . . . .2736
62.14.61OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .2738
62.14.62OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . .2740
62.14.63OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) . . . . .2741
62.14.64OTG device OUT endpoint x control register (OTG_DOEPCTLx) . . . . .2741
62.14.65OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) . . . . .2744
62.14.66OTG power and clock gating control register (OTG_PCGCCTL) . . . . .2745
62.14.67OTG_HS register map . . . . .2746
62.15OTG_HS programming model . . . . .2758
62.15.1Core initialization . . . . .2758
62.15.2Host initialization . . . . .2759
62.15.3Device initialization . . . . .2760
62.15.4DMA mode . . . . .2760
62.15.5Host programming model . . . . .2761
62.15.6Device programming model . . . . .2793
62.15.7Worst case response time . . . . .2813
62.15.8OTG programming model . . . . .2815
63Ethernet (ETH): media access control (MAC) with DMA controller . . . . .2821
63.1Ethernet introduction . . . . .2821
63.2Ethernet main features . . . . .2821
63.2.1MAC core features . . . . .2821
63.2.2DMA features . . . . .2823
63.2.3Bus interface features . . . . .2824
63.3Ethernet pins and internal signals . . . . .2824
63.4Ethernet architecture . . . . .2826
63.4.1DMA controller . . . . .2827
63.4.2MTL . . . . .2833
63.4.3MAC . . . . .2834
63.5Ethernet functional description: MAC . . . . .2839
63.5.1Double VLAN processing . . . . .2839
63.5.2Source Address and VLAN insertion, replacement, or deletion . . . . .2840
63.5.3Packet filtering . . . . .2842
63.5.4IEEE 1588 timestamp support . . . . .2848
63.5.5Checksum offload engine . . . . .2873
63.5.6TCP segmentation offload . . . . .2879
63.5.7IPv4 ARP offload . . . . .2885
63.5.8Loopback . . . . .2886
63.5.9Flow control . . . . .2887
63.5.10MAC management counters . . . . .2890
63.5.11Interrupts generated by the MAC . . . . .2892
63.5.12MAC and MMC register descriptions . . . . .2892
63.6Ethernet functional description: PHY interfaces . . . . .2893
63.6.1Station management agent (SMA) . . . . .2893
63.6.2Media independent interface (MII) . . . . .2900
63.6.3Reduced media independent interface (RMII) . . . . .2901
63.7Ethernet low-power modes . . . . .2905
63.7.1Low-power management . . . . .2905
63.7.2Energy Efficient Ethernet (EEE) . . . . .2911
63.8Ethernet interrupts . . . . .2917
63.8.1DMA interrupts . . . . .2917
63.8.2MTL interrupts . . . . .2919
63.8.3MAC Interrupts . . . . .2919
63.9Ethernet programming model . . . . .2920
63.9.1DMA initialization . . . . .2920
63.9.2MTL initialization . . . . .2921
63.9.3MAC initialization . . . . .2921
63.9.4Performing normal receive and transmit operation . . . . .2922
63.9.5Stopping and starting transmission . . . . .2923
63.9.6Programming guidelines for switching to new descriptor list
in RxDMA . . . . .		2923
63.9.7Programming guidelines for switching the AHB clock frequency . . . . .2923
63.9.8Programming guidelines for MII link state transitions . . . . .2924
63.9.9Programming guidelines for IEEE 1588 timestamping . . . . .2925
63.9.10Programming guidelines for PTP offload feature . . . . .2926
63.9.11Programming guidelines for Energy Efficient Ethernet (EEE) . . . . .2930
63.9.12Programming guidelines for flexible pulse-per-second (PPS) output . . . . .2932
63.9.13Programming guidelines for TSO . . . . .2934
63.9.14Programming guidelines to perform VLAN filtering on the receive . . . . .2935
63.10Descriptors . . . . .2935
63.10.1Descriptor overview . . . . .2935
63.10.2Descriptor structure . . . . .2936
63.10.3Transmit descriptor . . . . .2938
63.10.4Receive descriptor . . . . .2950
63.11Ethernet registers . . . . .2962
63.11.1Ethernet registers maps . . . . .2962
63.11.2Ethernet DMA registers . . . . .2962
63.11.3Ethernet MTL registers . . . . .2988
63.11.4Ethernet MAC and MMC registers . . . . .3000
64HDMI-CEC controller (CEC) . . . . .3098
64.1Introduction . . . . .3098
64.2HDMI-CEC controller main features . . . . .3098
64.3HDMI-CEC functional description . . . . .3099
64.3.1HDMI-CEC pin and internal signals . . . . .3099
64.3.2HDMI-CEC block diagram . . . . .3100
64.3.3Message description . . . . .3100
64.3.4Bit timing . . . . .3101
64.4Arbitration . . . . .3101
64.4.1SFT option bit . . . . .3103
64.5Error handling . . . . .3103
64.5.1Bit error . . . . .3103
64.5.2Message error . . . . .3104
64.5.3Bit rising error (BRE) . . . . .3104
64.5.4Short bit period error (SBPE) . . . . .3104
64.5.5Long bit period error (LBPE) . . . . .3104
64.5.6Transmission error detection (TXERR) . . . . .3106
64.6HDMI-CEC interrupts . . . . .3107
64.7HDMI-CEC registers . . . . .3108
64.7.1CEC control register (CEC_CR) . . . . .3108
64.7.2CEC configuration register (CEC_CFGR) . . . . .3109
64.7.3CEC Tx data register (CEC_TXDR) . . . . .3111
64.7.4CEC Rx data register (CEC_RXDR) . . . . .3111
64.7.5CEC interrupt and status register (CEC_ISR) . . . . .3111
64.7.6CEC interrupt enable register (CEC_IER) . . . . .3113

64.7.7 HDMI-CEC register map ..... 3115

65 Debug infrastructure ..... 3116

65.1 Introduction .....3116

65.2 Debug infrastructure features .....3117

65.3 Debug infrastructure functional description .....3117

65.3.1 Debug infrastructure block diagram ..... 3117

65.3.2 Debug infrastructure powering, clocking and reset ..... 3118

65.4 Debug access port functional description ..... 3120

65.4.1 Serial-wire and JTAG debug port (SWJ-DP) ..... 3120

65.4.2 Access ports ..... 3134

65.5 Trace and debug subsystem functional description ..... 3140

65.5.1 System ROM tables ..... 3140

65.5.2 Cross trigger interfaces (CTI) and matrix (CTM) ..... 3149

65.5.3 Trace funnel (CSTF) ..... 3167

65.5.4 Embedded trace FIFO (ETF) ..... 3177

65.5.5 Trace port interface unit (TPIU) ..... 3199

65.5.6 Serial wire output (SWO) ..... 3217

65.5.7 Microcontroller debug unit (DBGMCU) ..... 3228

65.6 Cortex-M7 debug functional description ..... 3241

65.6.1 Cortex-M7 ROM tables ..... 3241

65.6.2 Cortex-M7 data watchpoint and trace unit (DWT) ..... 3253

65.6.3 Cortex-M7 instrumentation trace macrocell (ITM) ..... 3266

65.6.4 Cortex-M7 breakpoint unit (FPB) ..... 3275

65.6.5 Cortex-M7 embedded trace macrocell (ETM) ..... 3282

65.6.6 Cortex-M7 cross trigger interface (CTI) ..... 3313

65.7 References for debug infrastructure ..... 3314

66 Device electronic signature ..... 3315

66.1 Unique device ID register (96 bits) ..... 3315

66.2 Flash size ..... 3316

66.3 Line identifier ..... 3316

66.4 Package data register ..... 3317

67 Revision history ..... 3318

List of tables

Table 1.Availability of security features . . . . .105
Table 2.Bus-master-to-bus-slave interconnect . . . . .106
Table 3.ASIB configuration . . . . .112
Table 4.AMIB configuration . . . . .113
Table 5.AXI interconnect register map and reset values . . . . .123
Table 6.Memory map and default device memory area attributes . . . . .132
Table 7.Register boundary addresses . . . . .134
Table 8.ITCM/DTCM/AXI configuration . . . . .141
Table 9.Boot modes . . . . .142
Table 10.RAMECC internal input/output signals . . . . .146
Table 11.ECC controller mapping . . . . .146
Table 12.RAMECC register map and reset values . . . . .151
Table 13.FLASH internal input/output signals . . . . .153
Table 14.Flash memory organization (STM32H730 devices) . . . . .156
Table 15.Flash memory organization (STM32H723/733 and STM32H725/735 devices) . . . . .156
Table 16.FLASH recommended number of wait states and programming delay . . . . .161
Table 17.FLASH parallelism parameter . . . . .165
Table 18.Option byte organization . . . . .173
Table 19.Flash interface register protection summary . . . . .178
Table 20.RDP value vs readout protection level . . . . .179
Table 21.Protection vs RDP Level . . . . .180
Table 22.RDP transition and effects . . . . .182
Table 23.Effect of low-power modes on the embedded Flash memory . . . . .186
Table 24.Flash interrupt request . . . . .192
Table 25.Register map and reset value table . . . . .220
Table 26.List of preferred terms . . . . .224
Table 27.Summary of Flash protected areas access rights . . . . .229
Table 28.PWR input/output signals connected to package pins or balls . . . . .232
Table 29.PWR internal input/output signals . . . . .232
Table 30.Supply configuration control . . . . .237
Table 31.Summary of the operating mode . . . . .259
Table 32.PDDS_Dn low-power mode control . . . . .262
Table 33.Low-power exit mode flags . . . . .264
Table 34.CSleep mode . . . . .273
Table 35.CStop mode . . . . .274
Table 36.DStop mode overview . . . . .275
Table 37.DStop mode . . . . .275
Table 38.Stop mode operation . . . . .277
Table 39.Stop mode . . . . .278
Table 40.DStandby mode . . . . .279
Table 41.Standby and Stop flags . . . . .281
Table 42.Standby mode . . . . .281
Table 43.Low-power modes monitoring pin overview . . . . .282
Table 44.GPIO state according to CPU and domain state . . . . .282
Table 45.Power control register map and reset values . . . . .294
Table 46.BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) . . . . .302
Table 47.LPUART1 Initial programming (LPUART1_INIT) . . . . .304
Table 48.LPUART1 start programming (LPUART1_Start) . . . . .304
Table 49.RCC input/output signals connected to package pins or balls . . . . .308
Table 50.RCC internal input/output signals . . . . .309
Table 51.Reset distribution summary . . . . .312
Table 52.Reset source identification (RCC_RSR) . . . . .314
Table 53.Ratio between clock timer and pclk . . . . .332
Table 54.STOPWUCK and STOPKERWUCK description . . . . .333
Table 55.HSIKERON and CSIKERON behavior . . . . .334
Table 56.Kernel clock distribution overview . . . . .336
Table 57.System states overview . . . . .351
Table 58.Peripheral clock enabling for D1 and D2 peripherals . . . . .356
Table 59.Peripheral clock enabling for D3 peripherals . . . . .357
Table 60.Interrupt sources and control . . . . .361
Table 61.RCC_RSR address offset and reset value . . . . .430
Table 62.RCC_AHB3ENR address offset and reset value . . . . .432
Table 63.RCC_AHB1ENR address offset and reset value . . . . .434
Table 64.RCC_AHB2ENR address offset and reset value . . . . .436
Table 65.RCC_AHB4ENR address offset and reset value . . . . .438
Table 66.RCC_APB3ENR address offset and reset value . . . . .440
Table 67.RCC_APB1ENR address offset and reset value . . . . .441
Table 68.RCC_APB1ENR address offset and reset value . . . . .445
Table 69.RCC_APB2ENR address offset and reset value . . . . .447
Table 70.RCC_APB4ENR address offset and reset value . . . . .450
Table 71.RCC_AHB3LPENR address offset and reset value . . . . .453
Table 72.RCC_AHB1LPENR address offset and reset value . . . . .455
Table 73.RCC_AHB2LPENR address offset and reset value . . . . .457
Table 74.RCC_AHB4LPENR address offset and reset value . . . . .459
Table 75.RCC_APB3LPENR address offset and reset value . . . . .461
Table 76.RCC_APB1LLPENR address offset and reset value . . . . .462
Table 77.RCC_APB1HLPENR address offset and reset value . . . . .466
Table 78.RCC_APB2LPENR address offset and reset value . . . . .468
Table 79.RCC_APB4LPENR address offset and reset value . . . . .471
Table 80.RCC register map and reset values . . . . .473
Table 81.CRS features . . . . .483
Table 82.CRS internal input/output signals . . . . .484
Table 83.Effect of low-power modes on CRS . . . . .488
Table 84.Interrupt control bits . . . . .488
Table 85.CRS register map and reset values . . . . .493
Table 86.HSEM internal input/output signals . . . . .496
Table 87.Authorized AHB bus master ID . . . . .501
Table 88.HSEM register map and reset values . . . . .507
Table 89.Port bit configuration table . . . . .510
Table 90.GPIO register map and reset values . . . . .525
Table 91.SYSCFG register map and reset values . . . . .549
Table 92.Peripherals interconnect matrix (D2 domain) . . . . .553
Table 93.Peripherals interconnect matrix (D3 domain) . . . . .554
Table 94.Peripherals interconnect matrix details . . . . .555
Table 95.EXTI wakeup inputs . . . . .572
Table 96.EXTI pending requests clear inputs . . . . .575
Table 97.MDMA . . . . .577
Table 98.DMAMUX1, DMA1 and DMA2 connections . . . . .579
Table 99.DMAMUX2 and BDMA connections . . . . .585
Table 100.MDMA internal input/output signals . . . . .590
Table 101.MDMA interrupt requests . . . . .596
Table 102.MDMA register map and reset values . . . . .612
Table 103.DMA internal input/output signals . . . . .615
Table 104.Source and destination address . . . . .617
Table 105.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .623
Table 106.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .624
Table 107.Restriction on NDT versus PSIZE and MSIZE . . . . .624
Table 108.FIFO threshold configurations . . . . .627
Table 109.Possible DMA configurations . . . . .631
Table 110.DMA interrupt requests . . . . .633
Table 111.DMA register map and reset values . . . . .644
Table 112.BDMA implementation . . . . .649
Table 113.BDMA internal input/output signals . . . . .650
Table 114.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .656
Table 115.BDMA interrupt requests . . . . .658
Table 116.BDMA register map and reset values . . . . .668
Table 117.DMAMUX1 and DMAMUX2 instantiation . . . . .672
Table 118.DMAMUX1: assignment of multiplexer inputs to resources . . . . .673
Table 119.DMAMUX1: assignment of trigger inputs to resources . . . . .674
Table 120.DMAMUX1: assignment of synchronization inputs to resources . . . . .674
Table 121.DMAMUX2: assignment of multiplexer inputs to resources . . . . .674
Table 122.DMAMUX2: assignment of trigger inputs to resources . . . . .675
Table 123.DMAMUX2: assignment of synchronization inputs to resources . . . . .675
Table 124.DMAMUX signals . . . . .678
Table 125.DMAMUX interrupts . . . . .682
Table 126.DMAMUX register map and reset values . . . . .691
Table 127.DMA2D internal input/output signals . . . . .695
Table 128.Supported color mode in input . . . . .696
Table 129.Data order in memory . . . . .698
Table 130.Alpha mode configuration . . . . .698
Table 131.Supported CLUT color mode . . . . .699
Table 132.CLUT data order in memory . . . . .699
Table 133.Supported color mode in output . . . . .700
Table 134.Data order in memory . . . . .701
Table 135.Standard data order in memory . . . . .702
Table 136.Output FIFO byte reordering steps . . . . .703
Table 137.MCU order in memory . . . . .708
Table 138.DMA2D interrupt requests . . . . .709
Table 139.DMA2D register map and reset values . . . . .729
Table 140.NVIC . . . . .732
Table 141.EXTI Event input configurations and register control . . . . .742
Table 142.Configurable event input asynchronous edge detector reset . . . . .744
Table 143.EXTI Event input mapping . . . . .749
Table 144.Masking functionality . . . . .751
Table 145.Asynchronous interrupt/event controller register map and reset values . . . . .770
Table 146.CRC internal input/output signals . . . . .774
Table 147.CRC register map and reset values . . . . .779
Table 148.CORDIC functions . . . . .781
Table 149.Cosine parameters . . . . .781
Table 150.Sine parameters . . . . .782
Table 151.Phase parameters . . . . .782
Table 152.Modulus parameters . . . . .783
Table 153.Arctangent parameters . . . . .784
Table 154.Hyperbolic cosine parameters . . . . .784
Table 155.Hyperbolic sine parameters . . . . .785
Table 156.Hyperbolic arctangent parameters . . . . .785
Table 157.Natural logarithm parameters . . . . .786
Table 158.Natural log scaling factors and corresponding ranges . . . . .786
Table 159.Square root parameters . . . . .787
Table 160.Square root scaling factors and corresponding ranges . . . . .787
Table 161.Precision vs. number of iterations. . . . .790
Table 162.CORDIC register map and reset value . . . . .797
Table 163.Valid combinations for read and write methods . . . . .811
Table 164.FMAC register map and reset values . . . . .824
Table 165.FMC pins . . . . .829
Table 166.FMC bank mapping options . . . . .832
Table 167.NOR/PSRAM bank selection . . . . .832
Table 168.NOR/PSRAM External memory address . . . . .832
Table 169.NAND memory mapping and timing registers. . . . .833
Table 170.NAND bank selection . . . . .833
Table 171.SDRAM bank selection. . . . .833
Table 172.SDRAM address mapping . . . . .834
Table 173.SDRAM address mapping with 8-bit data bus width. . . . .834
Table 174.SDRAM address mapping with 16-bit data bus width. . . . .835
Table 175.SDRAM address mapping with 32-bit data bus width. . . . .836
Table 176.Programmable NOR/PSRAM access parameters . . . . .838
Table 177.Non-multiplexed I/O NOR Flash memory . . . . .838
Table 178.16-bit multiplexed I/O NOR Flash memory . . . . .839
Table 179.Non-multiplexed I/Os PSRAM/SRAM . . . . .839
Table 180.16-Bit multiplexed I/O PSRAM . . . . .839
Table 181.NOR Flash/PSRAM: Example of supported memories
and transactions . . . . .		840
Table 182.FMC_BCRx bitfields (mode 1) . . . . .843
Table 183.FMC_BTRx bitfields (mode 1) . . . . .844
Table 184.FMC_BCRx bitfields (mode A) . . . . .846
Table 185.FMC_BTRx bitfields (mode A) . . . . .847
Table 186.FMC_BWTRx bitfields (mode A). . . . .847
Table 187.FMC_BCRx bitfields (mode 2/B). . . . .849
Table 188.FMC_BTRx bitfields (mode 2/B). . . . .850
Table 189.FMC_BWTRx bitfields (mode 2/B) . . . . .850
Table 190.FMC_BCRx bitfields (mode C) . . . . .852
Table 191.FMC_BTRx bitfields (mode C) . . . . .853
Table 192.FMC_BWTRx bitfields (mode C). . . . .853
Table 193.FMC_BCRx bitfields (mode D) . . . . .855
Table 194.FMC_BTRx bitfields (mode D) . . . . .855
Table 195.FMC_BWTRx bitfields (mode D). . . . .856
Table 196.FMC_BCRx bitfields (Muxed mode) . . . . .858
Table 197.FMC_BTRx bitfields (Muxed mode) . . . . .858
Table 198.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .864
Table 199.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .864
Table 200.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .865
Table 201.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .866
Table 202.Programmable NAND Flash access parameters . . . . .876
Table 203.8-bit NAND Flash memory . . . . .876
Table 204.16-bit NAND Flash memory . . . . .877
Table 205.Supported memories and transactions . . . . .877
Table 206.ECC result relevant bits . . . . .887
Table 207.SDRAM signals . . . . .888
Table 208.FMC register map . . . . .905
Table 209.OCTOSPI implementation . . . . .909
Table 210.Command/address phase description . . . . .919
Table 211.Address alignment cases . . . . .935
Table 212.OCTOSPI interrupt requests . . . . .937
Table 213.OCTOSPI register map and reset values . . . . .960
Table 214.OCTOSPIM implementation . . . . .963
Table 215.OCTOSPIM register map and reset values . . . . .968
Table 216.DLYB internal input/output signals . . . . .970
Table 217.DLYB interconnection . . . . .970
Table 218.Delay block control . . . . .970
Table 219.DLYB register map and reset values . . . . .974
Table 220.ADC features . . . . .977
Table 221.ADC input/output pins . . . . .979
Table 222.ADC internal input/output signals . . . . .979
Table 223.ADC interconnection . . . . .980
Table 224.Configuring the trigger polarity for regular external triggers . . . . .999
Table 225.Configuring the trigger polarity for injected external triggers . . . . .999
Table 226.ADC1 and ADC2- External triggers for regular channels . . . . .1000
Table 227.ADC1 and ADC2 - External triggers for injected channels . . . . .1001
Table 228.TSAR timings depending on resolution . . . . .1014
Table 229.Offset computation versus data resolution . . . . .1017
Table 230.16-bit data formats . . . . .1020
Table 231.Numerical examples for 16-bit format (bold indicates saturation) . . . . .1020
Table 232.Analog watchdog channel selection . . . . .1029
Table 233.Analog watchdog 1,2,3 comparison . . . . .1030
Table 234.Oversampler operating modes summary . . . . .1038
Table 235.ADC interrupts per each ADC . . . . .1056
Table 236.DELAY bits versus ADC resolution . . . . .1094
Table 237.ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) . . . . .		1096
Table 238.ADC register map and reset values (master and slave ADC
common registers) offset =0x300) . . . . .		1098
Table 239.ADC features . . . . .1101
Table 240.ADC input/output pins . . . . .1104
Table 241.ADC internal input/output signals . . . . .1104
Table 242.ADC interconnection . . . . .1104
Table 243.Configuring the trigger polarity for regular external triggers . . . . .1123
Table 244.Configuring the trigger polarity for injected external triggers . . . . .1123
Table 245.TSAR timings depending on resolution . . . . .1135
Table 246.Offset computation versus data resolution . . . . .1138
Table 247.Analog watchdog channel selection . . . . .1150
Table 248.Analog watchdog 1 comparison . . . . .1151
Table 249.Analog watchdog 2 and 3 comparison . . . . .1152
Table 250.Maximum output results versus N and M (gray cells indicate truncation) . . . . .1155
Table 251.ADC interrupts . . . . .1165
Table 252.ADC global register map . . . . .1197
Table 253.ADC register map and reset values . . . . .1197
Table 254.ADC register map and reset values (master and slave ADC common registers) . . . . .1199
Table 255.DTS internal input/output signals . . . . .1201
Table 256.Sampling time configuration . . . . .1204
Table 257.Trigger configuration . . . . .1205
Table 258.Temperature sensor behavior in low-power modes . . . . .1207
Table 259.Interrupt control bits . . . . .1208
Table 260.DTS register map and reset values . . . . .1216
Table 261.DAC features . . . . .1218
Table 262.DAC input/output pins . . . . .1220
Table 263.DAC internal input/output signals . . . . .1220
Table 264.DAC trigger selection . . . . .1221
Table 265.Sample and refresh timings . . . . .1228
Table 266.Channel output modes summary . . . . .1229
Table 267.Effect of low-power modes on DAC . . . . .1235
Table 268.DAC interrupts . . . . .1236
Table 269.DAC register map and reset values . . . . .1253
Table 270.VREF buffer modes . . . . .1255
Table 271.VREFBUF register map and reset values . . . . .1257
Table 272.COMP input/output internal signals . . . . .1260
Table 273.COMP input/output pins . . . . .1260
Table 274.COMP1_OUT assignment to GPIOs . . . . .1263
Table 275.COMP2_OUT assignment to GPIOs . . . . .1263
Table 276.Comparator behavior in the low-power modes . . . . .1265
Table 277.Interrupt control bits . . . . .1265
Table 278.Interrupt control bits . . . . .1266
Table 279.COMP register map and reset values . . . . .1273
Table 280.Operational amplifier possible connections . . . . .1275
Table 281.Operating modes and calibration . . . . .1283
Table 282.Effect of low-power modes on the OPAMP . . . . .1285
Table 283.OPAMP register map and reset values . . . . .1292
Table 284.DFSDM1 implementation . . . . .1295
Table 285.DFSDM external pins . . . . .1297
Table 286.DFSDM internal signals . . . . .1297
Table 287.DFSDM triggers connection . . . . .1297
Table 288.DFSDM break connection . . . . .1298
Table 289.Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .1313
Table 290.Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .1314
Table 291.DFSDM interrupt requests . . . . .1322
Table 292.DFSDM register map and reset values . . . . .1343
Table 293.DCMI input/output pins . . . . .1354
Table 294.DCMI internal input/output signals . . . . .1354
Table 295.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1356
Table 296.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .1356
Table 297.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .1356
Table 298.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .1357
Table 299.Data storage in monochrome progressive video format . . . . .1362
Table 300.Data storage in RGB progressive video format . . . . .1363
Table 301.Data storage in YCbCr progressive video format . . . . .1363
Table 302.Data storage in YCbCr progressive video format - Y extraction mode . . . . .1364
Table 303.DCMI interrupts. . . . .1364
Table 304.DCMI register map and reset values . . . . .1374
Table 305.PSSI input/output pins . . . . .1378
Table 306.PSSI internal input/output signals. . . . .1378
Table 307.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1379
Table 308.Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .1380
Table 309.PSSI interrupt requests. . . . .1383
Table 310.PSSI register map and reset values . . . . .1389
Table 311.LTDC external pins . . . . .1392
Table 312.LTDC internal signals . . . . .1393
Table 313.Clock domain for each register . . . . .1393
Table 314.LTDC register access and update durations . . . . .1394
Table 315.Pixel data mapping versus color format . . . . .1398
Table 316.LTDC interrupt requests . . . . .1402
Table 317.LTDC register map and reset values . . . . .1423
Table 318.RNG internal input/output signals . . . . .1427
Table 319.RNG interrupt requests. . . . .1435
Table 320.RNG configurations . . . . .1436
Table 321.RNG register map and reset map. . . . .1441
Table 322.CRYP internal input/output signals. . . . .1445
Table 323.Counter mode initialization vector. . . . .1469
Table 324.GCM last block definition . . . . .1472
Table 325.GCM mode IV registers initialization. . . . .1472
Table 326.CCM mode IV registers initialization. . . . .1479
Table 327.DES/TDES data swapping example. . . . .1483
Table 328.AES data swapping example . . . . .1484
Table 329.Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .1486
Table 330.Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .1487
Table 331.Initialization vector endianness in CRYP_IVxR registers (AES). . . . .1487
Table 332.Initialization vector endianness in CRYP_IVxR registers (DES/TDES) . . . . .1487
Table 333.Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .1488
Table 334.Cryptographic processor configuration for peripheral-to-memory DMA transfers . . . . .1489
Table 335.CRYP interrupt requests. . . . .1491
Table 336.Processing latency for ECB, CBC and CTR. . . . .1492
Table 337.Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .1492
Table 338.CRYP register map and reset values . . . . .1507
Table 339.HASH internal input/output signals. . . . .1512
Table 340.Hash processor outputs . . . . .1515
Table 341.HASH interrupt requests. . . . .1522
Table 342.Processing time (in clock cycle) . . . . .1522
Table 343.HASH register map and reset values . . . . .1531
Table 344.OTFDEC internal input/output signals . . . . .1535
Table 345.OTFDEC interrupt requests . . . . .1540
Table 346.OTFDEC register map and reset values. . . . .1551
Table 347.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .1596
Table 348.Break protection disarming conditions . . . . .1598
Table 349.Counting direction versus encoder signals. . . . .1604
Table 350.TIMx internal trigger connection . . . . .1621
Table 351.Output control bits for complementary OCx and OCxN channels with break feature. . . . .1635
Table 352.TIM1 register map and reset values . . . . .1656
Table 353.TIM8 register map and reset values . . . . .1658
Table 354.Counting direction versus encoder signals . . . . .1694
Table 355.TIMx internal trigger connection . . . . .1712
Table 356.Output control bit for standard OCx channels . . . . .1723
Table 357.TIM2/TIM3/TIM4/TIM5/TIM23/TIM24 register map and reset values . . . . .1737
Table 358.TIMx internal trigger connection . . . . .1768
Table 359.Output control bit for standard OCx channels . . . . .1776
Table 360.TIM12 register map and reset values . . . . .1779
Table 361.Output control bit for standard OCx channels . . . . .1788
Table 362.TIM13/TIM14 register map and reset values . . . . .1791
Table 363.Break protection disarming conditions . . . . .1821
Table 364.TIMx Internal trigger connection . . . . .1838
Table 365.Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .1848
Table 366.TIM15 register map and reset values . . . . .1857
Table 367.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .1870
Table 368.TIM16/TIM17 register map and reset values . . . . .1881
Table 369.TIMx register map and reset values . . . . .1895
Table 370.STM32H72x and STM32H73x LPTIM features . . . . .1897
Table 371.LPTIM input/output pins . . . . .1899
Table 372.LPTIM internal signals . . . . .1899
Table 373.LPTIM1 external trigger connection . . . . .1899
Table 374.LPTIM2 external trigger connection . . . . .1900
Table 375.LPTIM3 external trigger connection . . . . .1900
Table 376.LPTIM4 external trigger connection . . . . .1900
Table 377.LPTIM5 external trigger connection . . . . .1901
Table 378.LPTIM1 input 1 connection . . . . .1901
Table 379.LPTIM1 input 2 connection . . . . .1901
Table 380.LPTIM2 input 1 connection . . . . .1901
Table 381.LPTIM2 input 2 connection . . . . .1902
Table 382.LPTIM3 input 1 connection . . . . .1902
Table 383.Prescaler division ratios . . . . .1903
Table 384.Encoder counting scenarios . . . . .1910
Table 385.Effect of low-power modes on the LPTIM . . . . .1911
Table 386.Interrupt events . . . . .1912
Table 387.LPTIM register map and reset values . . . . .1923
Table 388.STM32H72x and STM32H73x WWDG features . . . . .1925
Table 389.WWDG internal input/output signals . . . . .1926
Table 390.WWDG register map and reset values . . . . .1931
Table 391.IWDG internal input/output signals . . . . .1933
Table 392.IWDG register map and reset values . . . . .1941
Table 393.RTC pins and internal signals . . . . .1946
Table 394.RTC pin PC13 configuration . . . . .1947
Table 395.RTC_OUT mapping . . . . .1948
Table 396.RTC functions over modes . . . . .1948
Table 397.Effect of low-power modes on RTC . . . . .1960
Table 398.Interrupt control bits . . . . .1961
Table 399.RTC register map and reset values . . . . .1986
Table 400.STM32H72x and STM32H73x I2C implementation . . . . .1989
Table 401.I2C input/output pins . . . . .1991
Table 402.I2C internal input/output signals . . . . .1991
Table 403.Comparison of analog vs. digital filters . . . . .1993
Table 404.I2C-SMBus specification data setup and hold times . . . . .1996
Table 405.I2C configuration. . . . .2000
Table 406.I2C-SMBus specification clock timings . . . . .2011
Table 407.Examples of timing settings for fI2CCLK = 8 MHz . . . . .2021
Table 408.Examples of timings settings for fI2CCLK = 16 MHz . . . . .2021
Table 409.Examples of timings settings for fI2CCLK = 48 MHz . . . . .2022
Table 410.SMBus timeout specifications . . . . .2024
Table 411.SMBus with PEC configuration . . . . .2026
Table 412.Examples of TIMEOUTA settings for various i2c_ker_ck frequencies
(max t TIMEOUT = 25 ms) . . . . .		2027
Table 413.Examples of TIMEOUTB settings for various i2c_ker_ck frequencies . . . . .2027
Table 414.Examples of TIMEOUTA settings for various i2c_ker_ck frequencies
(max t IDLE = 50 µs) . . . . .		2027
Table 415.Effect of low-power modes on the I2C . . . . .2038
Table 416.I2C Interrupt requests . . . . .2039
Table 417.I2C register map and reset values . . . . .2054
Table 418.USART / LPUART features . . . . .2058
Table 419.Noise detection from sampled data . . . . .2073
Table 420.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .2076
Table 421.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .2077
Table 422.USART frame formats . . . . .2082
Table 423.Effect of low-power modes on the USART . . . . .2105
Table 424.USART interrupt requests. . . . .2106
Table 425.USART register map and reset values . . . . .2141
Table 426.USART / LPUART features . . . . .2145
Table 427.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .2156
Table 428.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .2157
Table 429.Tolerance of the LPUART receiver. . . . .2158
Table 431.Effect of low-power modes on the LPUART . . . . .2169
Table 432.LPUART interrupt requests. . . . .2170
Table 433.LPUART register map and reset values . . . . .2194
Table 434.STM32H72x/3x SPI features . . . . .2197
Table 435.SPI wakeup and interrupt requests. . . . .2229
Table 436.Bit fields usable in PCM/I2S mode . . . . .2232
Table 437.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .2240
Table 438.Serial data line swapping . . . . .2240
Table 439.CLKGEN programming examples for usual I2S frequencies . . . . .2245
Table 440.I2S interrupt requests . . . . .2254
Table 441.SPI register map and reset values . . . . .2273
Table 442.STM32H72x/73x SAI features . . . . .2276
Table 443.SAI internal input/output signals . . . . .2278
Table 444.SAI input/output pins. . . . .2278
Table 445.External synchronization selection . . . . .2280
Table 446.MCLK_x activation conditions. . . . .2286
Table 447.Clock generator programming examples . . . . .2289
Table 448.TDM settings. . . . .2296
Table 449.TDM frame configuration examples . . . . .2298
Table 450.SOPD pattern . . . . .2302
Table 451.Parity bit calculation . . . . .2302
Table 452.Audio sampling frequency versus symbol rates . . . . .2303
Table 453.SAI interrupt sources . . . . .2312
Table 454.SAI register map and reset values . . . . .2342
Table 455.SPDIFRX internal input/output signals . . . . .2345
Table 456.SPDIFRX pins. . . . .2346
Table 457.Transition sequence for preamble . . . . .2351
Table 458.Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . .2361
Table 459.Conditions of spdifrx_symb_ck generation. . . . .2362
Table 460.Bit field property versus SPDIFRX state. . . . .2365
Table 461.SPDIFRX interface register map and reset values . . . . .2377
Table 462.SWPMI input/output signals connected to package pins or balls . . . . .2381
Table 463.SWPMI internal input/output signals. . . . .2382
Table 464.Effect of low-power modes on SWPMI . . . . .2396
Table 465.Interrupt control bits . . . . .2397
Table 466.Buffer modes selection for transmission/reception . . . . .2399
Table 467.SWPMI register map and reset values . . . . .2406
Table 468.MDIOS input/output signals connected to package pins or balls . . . . .2408
Table 469.MDIOS internal input/output signals . . . . .2408
Table 470.Interrupt control bits . . . . .2413
Table 471.MDIOS register map and reset values . . . . .2418
Table 472.SDMMC features . . . . .2420
Table 473.SDMMC operation modes SD & SDIO . . . . .2423
Table 474.SDMMC operation modes e•MMC . . . . .2423
Table 475.SDMMC internal input/output signals . . . . .2424
Table 476.SDMMC pins. . . . .2425
Table 477.SDMMC Command and data phase selection . . . . .2426
Table 478.Command token format . . . . .2432
Table 479.Short response with CRC token format . . . . .2433
Table 480.Short response without CRC token format . . . . .2433
Table 481.Long response with CRC token format. . . . .2433
Table 482.Specific Commands overview. . . . .2434
Table 483.Command path status flags . . . . .2435
Table 484.Command path error handling . . . . .2435
Table 485.Data token format . . . . .2443
Table 486.Data path status flags and clear bits. . . . .2443
Table 487.Data path error handling. . . . .2445
Table 488.Data FIFO access. . . . .2446
Table 489.Transmit FIFO status flags . . . . .2447
Table 490.Receive FIFO status flags . . . . .2448
Table 491.SDMMC connections to MDMA . . . . .2452
Table 492.AHB and SDMMC_CK clock frequency relation . . . . .2452
Table 493.SDIO special operation control. . . . .2453
Table 494.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .2457
Table 495.CMD12 use cases . . . . .2461
Table 496.SDMMC interrupts . . . . .2475
Table 497.Response type and SDMMC_RESPxR registers . . . . .2483
Table 498.SDMMC register map . . . . .2499
Table 499.CAN subsystem I/O signals . . . . .2502
Table 500.CAN triggers . . . . .2503
Table 501.CAN subsystem I/O pins. . . . .2503
Table 502.Main features . . . . .2505
Table 503.DLC coding in FDCAN . . . . .2510
Table 504.Example of filter configuration for Rx buffers . . . . .2522
Table 505.Example of filter configuration for Debug messages . . . . .2523
Table 506.Possible configurations for frame transmission . . . . .2523
Table 507.Tx buffer/FIFO - queue element size . . . . .2524
Table 508.First byte of level 1 reference message . . . . .2534
Table 509.First four bytes of level 2 reference message . . . . .2535
Table 510.First four bytes of level 0 reference message . . . . .2535
Table 511.TUR configuration example . . . . .2536
Table 512.System matrix, Node A . . . . .2541
Table 513.Trigger list, Node A . . . . .2542
Table 514.Number of data bytes transmitted with a reference message . . . . .2549
Table 515.Rx buffer and FIFO element . . . . .2556
Table 516.Rx buffer and FIFO element description . . . . .2556
Table 517.Tx buffer and FIFO element . . . . .2558
Table 518.Tx buffer element description . . . . .2558
Table 519.Tx Event FIFO element . . . . .2560
Table 520.Tx Event FIFO element description . . . . .2560
Table 521.Standard message ID filter element . . . . .2561
Table 522.Standard message ID filter element field description . . . . .2562
Table 523.Extended message ID filter element . . . . .2563
Table 524.Extended message ID filter element field description . . . . .2563
Table 525.Trigger memory element . . . . .2564
Table 526.Trigger memory element description . . . . .2564
Table 527.FDCAN register map and reset values . . . . .2604
Table 528.FDCAN TT register map and reset values . . . . .2626
Table 529.CCU register map and reset values . . . . .2633
Table 530.OTG_HS speeds supported . . . . .2635
Table 531.OTG_HS implementation . . . . .2637
Table 532.OTG_HS input/output pins . . . . .2638
Table 533.OTG_HS input/output signals . . . . .2638
Table 534.Compatibility of STM32 low power modes with the OTG . . . . .2651
Table 535.Core global control and status registers (CSRs) . . . . .2659
Table 536.Host-mode control and status registers (CSRs) . . . . .2660
Table 537.Device-mode control and status registers . . . . .2662
Table 538.Data FIFO (DFIFO) access register map . . . . .2664
Table 539.Power and clock gating control and status registers . . . . .2664
Table 540.TRDT values . . . . .2673
Table 541.Minimum duration for soft disconnect . . . . .2718
Table 542.OTG_HS register map and reset values . . . . .2746
Table 543.Ethernet peripheral pins . . . . .2824
Table 544.Ethernet internal input/output signals . . . . .2825
Table 545.Double VLAN processing features in Tx path . . . . .2839
Table 546.Double VLAN processing in Rx path . . . . .2840
Table 547.VLAN insertion or replacement based on VLTi bit . . . . .2841
Table 548.Destination address filtering . . . . .2844
Table 549.Source address filtering . . . . .2845
Table 550.VLAN match status . . . . .2846
Table 551.Ordinary clock: PTP messages for snapshot . . . . .2849
Table 552.End-to-end transparent clock: PTP messages for snapshot . . . . .2850
Table 553.Peer-to-peer transparent clock: PTP messages for snapshot . . . . .2851
Table 554.Egress and ingress latency for PHY interfaces . . . . .2854
Table 555.Minimum PTP clock frequency example . . . . .2855
Table 556.Message format defined in IEEE 1588-2008 . . . . .2856
Table 557.Message format defined in IEEE 1588-2008 . . . . .2856
Table 558.IPv6-UDP PTP packet fields required for control and status . . . . .2857
Table 559.Ethernet PTP packet fields required for control and status . . . . .2858
Table 560.Timestamp Snapshot Dependency on ETH_MACTSCR Bits . . . . .2860
Table 561.PTP message generation criteria . . . . .2866
Table 562.Common PTP message header fields . . . . .2868
Table 563.MAC Transmit PTP mode and one-step timestamping operation . . . . .2871
Table 564.Transmit checksum offload engine functions for different packet types . . . . .2876
Table 565.Receive checksum offload engine functions for different packet types . . . . .2878
Table 566.TSO: TCP and IP header fields . . . . .2882
Table 567.Pause packet fields . . . . .2887
Table 568.Tx MAC flow control . . . . .2888
Table 569.Rx MAC flow control . . . . .2888
Table 570.Size of the maximum receive packet . . . . .2891
Table 571.MCD clock selection . . . . .2894
Table 572.MDIO Clause 45 frame structure . . . . .2895
Table 573.MDIO Clause 22 frame structure . . . . .2896
Table 574.Remote wakeup packet filter register . . . . .2907
Table 575.Description of the remote wakeup filter fields . . . . .2908
Table 576.Remote wakeup packet and PMT interrupt generation . . . . .2909
Table 577.Transfer complete interrupt behavior . . . . .2918
Table 578.TDES0 normal descriptor (read format) . . . . .2938
Table 579.TDES1 normal descriptor (read format) . . . . .2939
Table 580.TDES2 normal descriptor (read format) . . . . .2939
Table 581.TDES3 normal descriptor (read format) . . . . .2940
Table 582.TDES0 normal descriptor (write-back format) . . . . .2943
Table 583.TDES1 normal descriptor (write-back format) . . . . .2943
Table 584.TDES2 normal descriptor (write-back format) . . . . .2944
Table 585.TDES3 normal descriptor (write-back format) . . . . .2944
Table 586.TDES0 context descriptor . . . . .2947
Table 587.TDES1 context descriptor . . . . .2947
Table 588.TDES2 context descriptor . . . . .2948
Table 589.TDES3 context descriptor . . . . .2948
Table 590.RDES0 normal descriptor (read format) . . . . .2951
Table 591.RDES1 normal descriptor (read format) . . . . .2951
Table 592.RDES2 normal descriptor (read format) . . . . .2951
Table 593.RDES3 normal descriptor (read format) . . . . .2952
Table 594.RDES0 normal descriptor (write-back format) . . . . .2953
Table 595.RDES1 normal descriptor (write-back format) . . . . .2954
Table 596.RDES2 normal descriptor (write-back format) . . . . .2956
Table 597.RDES3 normal descriptor (write-back format) . . . . .2957
Table 598.RDES0 context descriptor . . . . .2960
Table 599.RDES1 context descriptor . . . . .2961
Table 600.RDES2 context descriptor . . . . .2961
Table 601.RDES3 context descriptor . . . . .2961
Table 602.ETH_DMA common register map and reset values . . . . .2985
Table 603.ETH_DMA_CH register map and reset values . . . . .2985
Table 604.ETH_MTL register map and reset values . . . . .2998
Table 605.Giant Packet Status based on S2KP and JE Bits . . . . .3004
Table 606.Packet Length based on the CST and ACS bits . . . . .3004
Table 607.Ethernet MAC register map and reset values . . . . .3087
Table 608.HDMI pin . . . . .3099
Table 609.HDMI-CEC internal input/output signals . . . . .3099
Table 610. Error handling timing parameters . . . . .3105
Table 611. TXERR timing parameters . . . . .3106
Table 612. HDMI-CEC interrupts . . . . .3107
Table 613. HDMI-CEC register map and reset values . . . . .3115
Table 614. Packet request . . . . .3121
Table 615. ACK response . . . . .3121
Table 616. Data transfer . . . . .3121
Table 617. JTAG-DP data registers . . . . .3124
Table 618. Debug port registers . . . . .3126
Table 619. MEM-AP registers . . . . .3136
Table 620. System ROM table 1 . . . . .3141
Table 621. System ROM table 2 . . . . .3141
Table 622. System ROM table 1 register map and reset values . . . . .3147
Table 623. System ROM table 2 register map and reset values . . . . .3148
Table 624. System CTI inputs . . . . .3150
Table 625. System CTI outputs . . . . .3150
Table 626. Cortex-M7 CTI inputs . . . . .3150
Table 627. Cortex-M7 CTI outputs . . . . .3151
Table 628. CTI register map and reset values . . . . .3165
Table 629. CSTF register map and reset values . . . . .3175
Table 630. ETF register map and reset values . . . . .3197
Table 631. TPIU register map and reset values . . . . .3214
Table 632. SWO register map and reset values . . . . .3226
Table 633. DBGMCU register map and reset values . . . . .3239
Table 634. Cortex-M7 CPU ROM table . . . . .3241
Table 635. Cortex-M7 PPB ROM table . . . . .3242
Table 636. Cortex-M7 CPU ROM table register map and reset values . . . . .3247
Table 637. Cortex-M7 PPB ROM table register map and reset values . . . . .3252
Table 638. Cortex-M7 DWT register map and reset values . . . . .3264
Table 639. Cortex-M7 ITM register map and reset values . . . . .3273
Table 640. Cortex-M7 FPB register map and reset values . . . . .3281
Table 641. Cortex-M7 ETM register map and reset values . . . . .3309
Table 642. Document revision history . . . . .3318

List of figures

Figure 1.System architecture . . . . .107
Figure 2.AXI interconnect . . . . .112
Figure 3.RAM ECC controller implementation schematic. . . . .145
Figure 4.Connection between RAM ECC controller and RAMECC monitoring unit . . . . .145
Figure 5.FLASH block diagram . . . . .153
Figure 6.Detailed FLASH architecture . . . . .154
Figure 7.Embedded Flash memory organization . . . . .155
Figure 8.Embedded Flash memory usage . . . . .157
Figure 9.FLASH protection mechanisms . . . . .158
Figure 10.FLASH read pipeline architecture . . . . .160
Figure 11.FLASH write pipeline architecture . . . . .163
Figure 12.RDP protection transition scheme . . . . .181
Figure 13.Example of protected region overlapping . . . . .183
Figure 14.Flash memory areas and services in Standard and Secure access modes . . . . .225
Figure 15.Bootloader state machine in Secure access mode. . . . .226
Figure 16.Core access to Flash memory areas . . . . .229
Figure 17.Power control block diagram . . . . .231
Figure 18.Power supply overview . . . . .235
Figure 19.System supply configurations . . . . .236
Figure 20.Device startup with V CORE supplied from voltage regulator . . . . .239
Figure 21.Device startup with V CORE supplied directly from
SMPS step-down converter . . . . .		240
Figure 22.Device startup with V CORE supplied in Bypass mode
from external regulator . . . . .		241
Figure 23.Backup domain . . . . .247
Figure 24.USB supply configurations . . . . .248
Figure 25.Power-on reset/power-down reset waveform . . . . .249
Figure 26.BOR thresholds . . . . .250
Figure 27.PVD thresholds . . . . .251
Figure 28.AVD thresholds . . . . .252
Figure 29.VBAT thresholds . . . . .253
Figure 30.Temperature thresholds . . . . .254
Figure 31.V CORE overvoltage protection. . . . .255
Figure 32.V CORE voltage scaling versus system power modes . . . . .261
Figure 33.Power control modes detailed state diagram . . . . .263
Figure 34.Dynamic voltage scaling in Run mode . . . . .266
Figure 35.Dynamic voltage scaling behavior with D1,
D2 and system in Stop mode . . . . .		267
Figure 36.Dynamic Voltage Scaling D1, D2, system Standby mode . . . . .268
Figure 37.Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and
D3 in Autonomous mode . . . . .		270
Figure 38.EXTI, RCC and PWR interconnections . . . . .296
Figure 39.Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain
in Autonomous mode . . . . .		300
Figure 40.BDMA and DMAMUX2 interconnection . . . . .302
Figure 41.Timing diagram of LPUART1 transmission with D3 domain
in Autonomous mode . . . . .		305
Figure 42.RCC Block diagram . . . . .308
Figure 43.System reset circuit . . . . .311
Figure 44.Boot sequences versus system states . . . . .317
Figure 45.Top-level clock tree. . . . .319
Figure 46.HSE/LSE clock source . . . . .320
Figure 47.PLL block diagram . . . . .327
Figure 48.PLLs Initialization Flowchart . . . . .330
Figure 49.Core and bus clock generation . . . . .332
Figure 50.Kernel clock distribution for SAIs and SPDIFRX . . . . .339
Figure 51.Kernel clock distribution for DFSDM. . . . .339
Figure 52.Kernel clock distribution for SPIs and SPI/I2S . . . . .340
Figure 53.Kernel clock distribution for I2Cs . . . . .341
Figure 54.Kernel clock distribution for UARTs, USARTs and LPUART1 . . . . .342
Figure 55.Kernel clock distribution for LTDC . . . . .343
Figure 56.Kernel clock distribution for SDMMC, OCTOSPI and FMC . . . . .343
Figure 57.Kernel clock distribution for USB (2) . . . . .344
Figure 58.Kernel clock distribution for Ethernet . . . . .344
Figure 59.Kernel clock distribution for ADCs, SWPMI, RNG and FDCAN (2) . . . . .345
Figure 60.Kernel clock distribution for LPTIMs and HDMI-CEC (2) . . . . .346
Figure 61.Peripheral allocation example. . . . .349
Figure 62.Kernel Clock switching . . . . .352
Figure 63.Peripheral kernel clock enable logic details . . . . .355
Figure 64.Bus clock enable logic . . . . .360
Figure 65.RCC mapping overview . . . . .362
Figure 66.CRS block diagram. . . . .484
Figure 67.CRS counter behavior . . . . .486
Figure 68.HSEM block diagram . . . . .496
Figure 69.Procedure state diagram . . . . .497
Figure 70.Interrupt state diagram . . . . .500
Figure 71.Basic structure of an I/O port bit . . . . .509
Figure 72.Basic structure of a 5-Volt tolerant I/O port bit . . . . .509
Figure 73.Input floating / pull up / pull down configurations . . . . .514
Figure 74.Output configuration . . . . .515
Figure 75.Alternate function configuration . . . . .516
Figure 76.High impedance-analog configuration . . . . .516
Figure 77.Analog inputs connected to ADC inputs . . . . .517
Figure 78.MDMA block diagram . . . . .590
Figure 79.DMA block diagram . . . . .615
Figure 80.Peripheral-to-memory mode . . . . .619
Figure 81.Memory-to-peripheral mode . . . . .620
Figure 82.Memory-to-memory mode . . . . .621
Figure 83.FIFO structure. . . . .626
Figure 84.BDMA block diagram . . . . .649
Figure 85.DMAMUX block diagram . . . . .677
Figure 86.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .680
Figure 87.Event generation of the DMA request line multiplexer channel . . . . .680
Figure 88.DMA2D block diagram . . . . .695
Figure 89.Intel 8080 16-bit mode (RGB565) . . . . .702
Figure 90.Intel 8080 18/24-bit mode (RGB888) . . . . .702
Figure 91.EXTI block diagram . . . . .741
Figure 92.Configurable event triggering logic CPU wakeup . . . . .743
Figure 93.Configurable event triggering logic - any wakeup . . . . .745
Figure 94.Direct event triggering logic CPU wakeup . . . . .746
Figure 95.Direct event triggering logic - any wakeup . . . . .747
Figure 96.D3 domain pending request clear logic . . . . .748
Figure 97.CRC calculation unit block diagram . . . . .774
Figure 98.CORDIC convergence for trigonometric functions . . . . .788
Figure 99.CORDIC convergence for hyperbolic functions . . . . .789
Figure 100.CORDIC convergence for square root . . . . .790
Figure 101.Block diagram . . . . .799
Figure 102.Input buffer areas . . . . .801
Figure 103.Circular input buffer . . . . .802
Figure 104.Circular input buffer operation . . . . .803
Figure 105.Circular output buffer . . . . .804
Figure 106.Circular output buffer operation . . . . .805
Figure 107.FIR filter structure . . . . .807
Figure 108.IIR filter structure (direct form 1) . . . . .809
Figure 109.X1 buffer initialization . . . . .814
Figure 110.Filtering example 1 . . . . .815
Figure 111.Filtering example 2 . . . . .816
Figure 112.FMC block diagram . . . . .828
Figure 113.FMC memory banks (default mapping) . . . . .831
Figure 114.Mode 1 read access waveforms . . . . .842
Figure 115.Mode 1 write access waveforms . . . . .843
Figure 116.Mode A read access waveforms . . . . .845
Figure 117.Mode A write access waveforms . . . . .846
Figure 118.Mode 2 and mode B read access waveforms . . . . .848
Figure 119.Mode 2 write access waveforms . . . . .848
Figure 120.Mode B write access waveforms . . . . .849
Figure 121.Mode C read access waveforms . . . . .851
Figure 122.Mode C write access waveforms . . . . .851
Figure 123.Mode D read access waveforms . . . . .854
Figure 124.Mode D write access waveforms . . . . .854
Figure 125.Muxed read access waveforms . . . . .857
Figure 126.Muxed write access waveforms . . . . .857
Figure 127.Asynchronous wait during a read access waveforms . . . . .860
Figure 128.Asynchronous wait during a write access waveforms . . . . .860
Figure 129.Wait configuration waveforms . . . . .863
Figure 130.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .863
Figure 131.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .865
Figure 132.NAND Flash controller waveforms for common memory access . . . . .879
Figure 133.Access to non 'CE don't care' NAND-Flash . . . . .880
Figure 134.Burst write SDRAM access waveforms . . . . .890
Figure 135.Burst read SDRAM access . . . . .891
Figure 136.Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . .892
Figure 137.Read access crossing row boundary . . . . .894
Figure 138.Write access crossing row boundary . . . . .894
Figure 139.Self-refresh mode . . . . .897
Figure 140.Power-down mode . . . . .898
Figure 141.OCTOSPI block diagram in octal configuration . . . . .910
Figure 142.OCTOSPI block diagram in quad configuration . . . . .910
Figure 143.OCTOSPI block diagram in dual-quad configuration . . . . .911
Figure 144.SDR read command in octal configuration . . . . .912
Figure 145.DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .915
Figure 146.SDR write command in octo-SPI mode example . . . . .917
Figure 147. DTR write in octal-SPI mode (Macronix mode) example . . . . .917
Figure 148. Example of HyperBus read operation. . . . .919
Figure 149. HyperBus write operation with initial latency . . . . .920
Figure 150. HyperBus read operation with additional latency . . . . .921
Figure 151. HyperBus write operation with additional latency . . . . .921
Figure 152. HyperBus write operation with no latency. . . . .922
Figure 153. HyperBus read operation page crossing with latency. . . . .922
Figure 154. NCS when CKMODE = 0 (T = CLK period) . . . . .934
Figure 155. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .934
Figure 156. NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .935
Figure 157. NCS when CKMODE = 1 with an abort (T = CLK period). . . . .935
Figure 158. OCTOSPIM block diagram . . . . .964
Figure 159. DLYB block diagram. . . . .969
Figure 160. ADC block diagram. . . . .978
Figure 161. ADC Clock scheme. . . . .981
Figure 162. ADC1 connectivity . . . . .982
Figure 163. ADC2 connectivity . . . . .983
Figure 164. ADC calibration . . . . .987
Figure 165. Updating the ADC offset calibration factor . . . . .987
Figure 166. Mixing single-ended and differential channels . . . . .988
Figure 167. Enabling / Disabling the ADC . . . . .991
Figure 168. Analog to digital conversion time . . . . .997
Figure 169. Stopping ongoing regular conversions . . . . .998
Figure 170. Stopping ongoing regular and injected conversions. . . . .998
Figure 171. Triggers are shared between ADC master and ADC slave . . . . .1000
Figure 172. Injected conversion latency . . . . .1004
Figure 173. Example of JSQR queue of context (sequence change) . . . . .1007
Figure 174. Example of JSQR queue of context (trigger change) . . . . .1007
Figure 175. Example of JSQR queue of context with overflow before conversion . . . . .1008
Figure 176. Example of JSQR queue of context with overflow during conversion . . . . .1008
Figure 177. Example of JSQR queue of context with empty queue (case JQM=0). . . . .1009
Figure 178. Example of JSQR queue of context with empty queue (case JQM=1). . . . .1010
Figure 179. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . .		1010
Figure 180. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		1011
Figure 181. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . .		1011
Figure 182. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .1012
Figure 183. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .1012
Figure 184. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .1013
Figure 185. Single conversions of a sequence, software trigger . . . . .1015
Figure 186. Continuous conversion of a sequence, software trigger. . . . .1015
Figure 187. Single conversions of a sequence, hardware trigger . . . . .1016
Figure 188. Continuous conversions of a sequence, hardware trigger . . . . .1016
Figure 189. Right alignment (offset disabled, unsigned value) . . . . .1018
Figure 190. Right alignment (offset enabled, signed value) . . . . .1018
Figure 191. Left alignment (offset disabled, unsigned value) . . . . .1019
Figure 192. Left alignment (offset enabled, signed value) . . . . .1019
Figure 193. Example of overrun (OVRMOD = 0). . . . .1022
Figure 194. Example of overrun (OVRMOD = 1). . . . .1022
Figure 195. AUTDLY=1, regular conversion in continuous mode, software trigger . . . . .1026
Figure 196. AUTDLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . .		1026
Figure 197. AUTDLY=1, regular HW conversions interrupted by injected conversions.
(DISCEN=1, JDISCEN=1) . . . . .		1027
Figure 198. AUTDLY=1, regular continuous conversions interrupted by injected conversions . . . . .1028
Figure 199. AUTDLY=1 in auto- injected mode (JAUTO=1) . . . . .1028
Figure 200. Analog watchdog guarded area . . . . .1029
Figure 201. ADC y _AWD x _OUT signal generation (on all regular channels). . . . .1031
Figure 202. ADC y _AWD x _OUT signal generation (AWD x flag not cleared by SW) . . . . .1031
Figure 203. ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .1032
Figure 204. ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .1032
Figure 205. 16-bit result oversampling with 10-bits right shift and rounding . . . . .1033
Figure 206. Triggered regular oversampling mode (TROVS bit = 1) . . . . .1035
Figure 207. Regular oversampling modes (4x ratio) . . . . .1036
Figure 208. Regular and injected oversampling modes used simultaneously . . . . .1036
Figure 209. Triggered regular oversampling with injection . . . . .1037
Figure 210. Oversampling in auto-injected mode . . . . .1037
Figure 211. Dual ADC block diagram (1) . . . . .1040
Figure 212. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .1041
Figure 213. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .1043
Figure 214. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .1044
Figure 215. Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . .1045
Figure 216. Interleaved conversion with injection . . . . .1045
Figure 217. Alternate trigger: injected group of each ADC . . . . .1046
Figure 218. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .1047
Figure 219. Alternate + regular simultaneous . . . . .1048
Figure 220. Case of trigger occurring during injected conversion . . . . .1048
Figure 221. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .1049
Figure 222. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		1049
Figure 223. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		1049
Figure 224. DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . .1050
Figure 225. DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . .1051
Figure 226. DMA requests in interleaved mode when DAMDF=0b10 . . . . .1051
Figure 227. VBAT channel block diagram . . . . .1054
Figure 228. VREFINT channel block diagram . . . . .1054
Figure 229. ADC block diagram . . . . .1103
Figure 230. ADC clock scheme . . . . .1108
Figure 231. ADC3 connectivity . . . . .1109
Figure 232. ADC calibration . . . . .1112
Figure 233. Updating the ADC calibration factor . . . . .1113
Figure 234. Mixing single-ended and differential channels . . . . .1114
Figure 235. Enabling / disabling the ADC . . . . .1115
Figure 236. Bulb mode timing diagram . . . . .1118
Figure 237. Analog to digital conversion time . . . . .1121
Figure 238. Stopping ongoing regular conversions . . . . .1122
Figure 239. Stopping ongoing regular and injected conversions . . . . .1122
Figure 240. Trigger selection . . . . .1124
Figure 241. Injected conversion latency . . . . .1125
Figure 242. Example of JSQR queue of context (sequence change) . . . . .1128
Figure 243. Example of JSQR queue of context (trigger change) . . . . .1128
Figure 244. Example of JSQR queue of context with overflow before conversion . . . . .1129
Figure 245. Example of JSQR queue of context with overflow during conversion . . . . .1129
Figure 246. Example of JSQR queue of context with empty queue (case JQM = 0) . . . . .1130
Figure 247. Example of JSQR queue of context with empty queue (JQM = 1) . . . . .1131
Figure 248. Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion. . . . .		1131
Figure 249. Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs during an ongoing conversion and a new
trigger occurs . . . . .		1132
Figure 250. Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0) -
JADSTP occurs outside an ongoing conversion. . . . .		1132
Figure 251. Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .1133
Figure 252. Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 0) . . . . .1133
Figure 253. Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 1) . . . . .1134
Figure 254. Single conversions of a sequence, software trigger . . . . .1136
Figure 255. Continuous conversion of a sequence, software trigger. . . . .1136
Figure 256. Single conversions of a sequence, hardware trigger . . . . .1137
Figure 257. Continuous conversions of a sequence, hardware trigger . . . . .1137
Figure 258. Right alignment (offset disabled, unsigned value) . . . . .1139
Figure 259. Right alignment (offset enabled, signed value). . . . .1140
Figure 260. Left alignment (offset disabled, unsigned value) . . . . .1140
Figure 261. Left alignment (offset enabled, signed value). . . . .1141
Figure 262. Example of overrun (OVRMOD = 0). . . . .1142
Figure 263. Example of overrun (OVRMOD = 1). . . . .1143
Figure 264. AUTODLY = 1, regular conversion in Continuous mode, software trigger . . . . .1146
Figure 265. AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		1147
Figure 266. AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 1, JDISCEN = 1) . . . . .		1148
Figure 267. AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .1149
Figure 268. AUTODLY = 1 in auto- injected mode (JAUTO = 1) . . . . .1149
Figure 269. Analog watchdog guarded area . . . . .1150
Figure 270. ADC y _AWD x _OUT signal generation (on all regular channels). . . . .1152
Figure 271. ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .1153
Figure 272. ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .1153
Figure 273. ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .1153
Figure 274. 20-bit to 16-bit result truncation . . . . .1155
Figure 275. Numerical example with 5-bit shift and rounding . . . . .1155
Figure 276. Triggered regular oversampling mode (TROVS bit = 1). . . . .1157
Figure 277. Regular oversampling modes (4x ratio) . . . . .1158
Figure 278. Regular and injected oversampling modes used simultaneously . . . . .1159
Figure 279. Triggered regular oversampling with injection . . . . .1159
Figure 280. Oversampling in auto-injected mode . . . . .1160
Figure 281. Temperature sensor channel block diagram . . . . .1161
Figure 282. VBAT channel block diagram . . . . .1162
Figure 283. VREFINT channel block diagram . . . . .1163
Figure 284. Temperature sensor functional block diagram . . . . .1201
Figure 285. Method for low REF_CLK frequencies . . . . .1203
Figure 286. Method for high REF_CLK frequencies . . . . .1203
Figure 287. Temperature sensor sequence . . . . .1206
Figure 288. Dual-channel DAC block diagram . . . . .1219
Figure 289. Data registers in single DAC channel mode . . . . .1222
Figure 290. Data registers in dual DAC channel mode . . . . .1222
Figure 291. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .1223
Figure 292. DAC LFSR register calculation algorithm . . . . .1225
Figure 293. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .1225
Figure 294. DAC triangle wave generation . . . . .1226
Figure 295. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .1226
Figure 296. DAC Sample and hold mode phase diagram . . . . .1229
Figure 297. Comparator functional block diagram . . . . .1259
Figure 298. Comparator hysteresis . . . . .1262
Figure 299. Comparator output blanking . . . . .1262
Figure 300. Output redirection . . . . .1264
Figure 301. Scaler block diagram . . . . .1266
Figure 302. Standalone mode: external gain setting mode . . . . .1277
Figure 303. Follower configuration. . . . .1278
Figure 304. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .1279
Figure 305. PGA mode, internal gain setting (x2/x4/x8/x16),
inverting input used for filtering. . . . .		1280
Figure 306. PGA mode, non-inverting gain setting (x2/x4/x8/x16)
or inverting gain setting (x-1/x-3/x-7/x-15) . . . . .		1281
Figure 307. Example configuration . . . . .1281
Figure 308. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain
setting (x-1/x-3/x-7/x-15) with filtering. . . . .		1282
Figure 309. Example configuration . . . . .1282
Figure 310. Single DFSDM block diagram. . . . .1296
Figure 311. Input channel pins redirection. . . . .1300
Figure 312. Channel transceiver timing diagrams . . . . .1303
Figure 313. Clock absence timing diagram for SPI . . . . .1304
Figure 314. Clock absence timing diagram for Manchester coding . . . . .1305
Figure 315. First conversion for Manchester coding (Manchester synchronization) . . . . .1307
Figure 316. DFSDM_CHyDATINR registers operation modes and assignment . . . . .1311
Figure 317. Example: Sinc3 filter response . . . . .1313
Figure 318. DCMI block diagram . . . . .1354
Figure 319. DCMI signal waveforms . . . . .1355
Figure 320. Timing diagram . . . . .1357
Figure 321. Frame capture waveforms in snapshot mode. . . . .1359
Figure 322. Frame capture waveforms in continuous grab mode . . . . .1360
Figure 323. Coordinates and size of the window after cropping . . . . .1360
Figure 324. Data capture waveforms. . . . .1361
Figure 325. Pixel raster scan order . . . . .1362
Figure 326. PSSI block diagram . . . . .1377
Figure 327. Top-level block diagram . . . . .1377
Figure 328. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .1381
Figure 329. Data enable waveform diagram in transmit mode (CKPOL=0). . . . .1381
Figure 330. Ready in receive mode waveform diagram (CKPOL=0). . . . .1382
Figure 331. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . .1383
Figure 332. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . .1383
Figure 333. LTDC block diagram . . . . .1392
Figure 334. LTDC synchronous timings. . . . .1395
Figure 335. Layer window programmable parameters . . . . .1398
Figure 336. Blending two layers with background . . . . .1401
Figure 337. Interrupt events. . . . .1402
Figure 338. RNG block diagram . . . . .1427
Figure 339. NIST SP800-90B entropy source model. . . . .1428
Figure 340. RNG initialization overview. . . . .1431
Figure 341. CRYPT block diagram . . . . .1444
Figure 342. AES-ECB mode overview. . . . .1447
Figure 343. AES-CBC mode overview. . . . .1448
Figure 344. AES-CTR mode overview. . . . .1449
Figure 345. AES-GCM mode overview . . . . .1450
Figure 346. AES-GMAC mode overview . . . . .1450
Figure 347. AES-CCM mode overview . . . . .1451
Figure 348. Example of suspend mode management. . . . .1456
Figure 349. DES/TDES-ECB mode encryption . . . . .1457
Figure 350. DES/TDES-ECB mode decryption . . . . .1458
Figure 351. DES/TDES-CBC mode encryption . . . . .1459
Figure 352. DES/TDES-CBC mode decryption . . . . .1460
Figure 353. AES-ECB mode encryption . . . . .1462
Figure 354. AES-ECB mode decryption . . . . .1463
Figure 355. AES-CBC mode encryption . . . . .1464
Figure 356. AES-CBC mode decryption . . . . .1465
Figure 357. Message construction for the Counter mode . . . . .1467
Figure 358. AES-CTR mode encryption . . . . .1468
Figure 359. AES-CTR mode decryption . . . . .1469
Figure 360. Message construction for the Galois/counter mode . . . . .1471
Figure 361. Message construction for the Galois Message Authentication Code mode . . . . .1476
Figure 362. Message construction for the Counter with CBC-MAC mode. . . . .1477
Figure 363. 64-bit block construction according to the data type (IN FIFO). . . . .1484
Figure 364. 128-bit block construction according to the data type. . . . .1486
Figure 365. HASH block diagram . . . . .1511
Figure 366. Message data swapping feature. . . . .1513
Figure 367. HASH suspend/resume mechanism. . . . .1519
Figure 368. OTFDEC block diagram . . . . .1534
Figure 369. Typical OTFDEC usage in the device. . . . .1535
Figure 370. AES CTR decryption flow . . . . .1537
Figure 371. OTFDEC flow control overview (dual burst read request) . . . . .1538
Figure 372. OTFDEC flow control overview (burst then single read request) . . . . .1539
Figure 373. Advanced-control timer block diagram . . . . .1556
Figure 374. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1558
Figure 375. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1558
Figure 376. Counter timing diagram, internal clock divided by 1 . . . . .1560
Figure 377. Counter timing diagram, internal clock divided by 2 . . . . .1560
Figure 378. Counter timing diagram, internal clock divided by 4 . . . . .1561
Figure 379. Counter timing diagram, internal clock divided by N. . . . .1561
Figure 380. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1562
Figure 381. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1562
Figure 382. Counter timing diagram, internal clock divided by 1 . . . . .1564
Figure 383. Counter timing diagram, internal clock divided by 2 . . . . .1564
Figure 384. Counter timing diagram, internal clock divided by 4 . . . . .1565
Figure 385. Counter timing diagram, internal clock divided by N. . . . .1565
Figure 386. Counter timing diagram, update event when repetition counter is not used. . . . .1566
Figure 387. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1567
Figure 388. Counter timing diagram, internal clock divided by 2 . . . . .1568
Figure 389. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1568
Figure 390. Counter timing diagram, internal clock divided by N . . . . .1569
Figure 391. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .1569
Figure 392. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1570
Figure 393. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1571
Figure 394. External trigger input block . . . . .1572
Figure 395. TIM1/TIM8 ETR input circuitry . . . . .1572
Figure 396. Control circuit in normal mode, internal clock divided by 1 . . . . .1573
Figure 397. TI2 external clock connection example. . . . .1574
Figure 398. Control circuit in external clock mode 1 . . . . .1575
Figure 399. External trigger input block . . . . .1575
Figure 400. Control circuit in external clock mode 2 . . . . .1576
Figure 401. Capture/compare channel (example: channel 1 input stage) . . . . .1577
Figure 402. Capture/compare channel 1 main circuit . . . . .1577
Figure 403. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .1578
Figure 404. Output stage of capture/compare channel (channel 4). . . . .1578
Figure 405. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1579
Figure 406. PWM input mode timing . . . . .1581
Figure 407. Output compare mode, toggle on OC1 . . . . .1583
Figure 408. Edge-aligned PWM waveforms (ARR=8) . . . . .1584
Figure 409. Center-aligned PWM waveforms (ARR=8). . . . .1585
Figure 410. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1587
Figure 411. Combined PWM mode on channel 1 and 3 . . . . .1588
Figure 412. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1589
Figure 413. Complementary output with dead-time insertion . . . . .1590
Figure 414. Dead-time waveforms with delay greater than the negative pulse . . . . .1590
Figure 415. Dead-time waveforms with delay greater than the positive pulse. . . . .1591
Figure 416. Break and Break2 circuitry overview . . . . .1593
Figure 417. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .1595
Figure 418. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .1596
Figure 419. PWM output state following BRK assertion (OSSI=0) . . . . .1597
Figure 420. Output redirection (BRK2 request not represented) . . . . .1598
Figure 421. Clearing TIMx_OCxREF . . . . .1599
Figure 422. 6-step generation, COM example (OSSR=1) . . . . .1600
Figure 423. Example of one pulse mode. . . . .1601
Figure 424. Retriggerable one pulse mode . . . . .1603
Figure 425. Example of counter operation in encoder interface mode. . . . .1604
Figure 426. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .1605
Figure 427. Measuring time interval between edges on 3 signals . . . . .1606
Figure 428. Example of Hall sensor interface . . . . .1608
Figure 429. Control circuit in reset mode . . . . .1609
Figure 430. Control circuit in Gated mode . . . . .1610
Figure 431. Control circuit in trigger mode . . . . .1611
Figure 432. Control circuit in external clock mode 2 + trigger mode . . . . .1612
Figure 433. General-purpose timer block diagram . . . . .1662
Figure 434. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1664
Figure 435. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1664
Figure 436. Counter timing diagram, internal clock divided by 1 . . . . .1665
Figure 437. Counter timing diagram, internal clock divided by 2 . . . . .1666
Figure 438. Counter timing diagram, internal clock divided by 4 . . . . .1666
Figure 439. Counter timing diagram, internal clock divided by N. . . . .1667
Figure 440. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1667
Figure 441. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1668
Figure 442. Counter timing diagram, internal clock divided by 1 . . . . .1669
Figure 443. Counter timing diagram, internal clock divided by 2 . . . . .1669
Figure 444. Counter timing diagram, internal clock divided by 4 . . . . .1670
Figure 445. Counter timing diagram, internal clock divided by N . . . . .1670
Figure 446. Counter timing diagram, Update event when repetition counter is not used . . . . .1671
Figure 447. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1672
Figure 448. Counter timing diagram, internal clock divided by 2 . . . . .1673
Figure 449. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1673
Figure 450. Counter timing diagram, internal clock divided by N . . . . .1674
Figure 451. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .1674
Figure 452. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1675
Figure 453. Control circuit in normal mode, internal clock divided by 1 . . . . .1676
Figure 454. TI2 external clock connection example . . . . .1676
Figure 455. Control circuit in external clock mode 1 . . . . .1677
Figure 456. External trigger input block . . . . .1678
Figure 457. Control circuit in external clock mode 2 . . . . .1679
Figure 458. Capture/Compare channel (example: channel 1 input stage) . . . . .1679
Figure 459. Capture/Compare channel 1 main circuit . . . . .1680
Figure 460. Output stage of Capture/Compare channel (channel 1) . . . . .1680
Figure 461. PWM input mode timing . . . . .1682
Figure 462. Output compare mode, toggle on OC1 . . . . .1684
Figure 463. Edge-aligned PWM waveforms (ARR=8) . . . . .1685
Figure 464. Center-aligned PWM waveforms (ARR=8) . . . . .1686
Figure 465. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1687
Figure 466. Combined PWM mode on channels 1 and 3 . . . . .1689
Figure 467. Clearing TIMx_OCxREF . . . . .1690
Figure 468. Example of one-pulse mode . . . . .1691
Figure 469. Retriggerable one-pulse mode . . . . .1693
Figure 470. Example of counter operation in encoder interface mode . . . . .1694
Figure 471. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1695
Figure 472. Control circuit in reset mode . . . . .1696
Figure 473. Control circuit in gated mode . . . . .1697
Figure 474. Control circuit in trigger mode . . . . .1698
Figure 475. Control circuit in external clock mode 2 + trigger mode . . . . .1699
Figure 476. Master/Slave timer example . . . . .1699
Figure 477. Master/slave connection example with 1 channel only timers . . . . .1700
Figure 478. Gating TIM2 with OC1REF of TIM3 . . . . .1701
Figure 479. Gating TIM2 with Enable of TIM3 . . . . .1702
Figure 480. Triggering TIM2 with update of TIM3 . . . . .1702
Figure 481. Triggering TIM2 with Enable of TIM3 . . . . .1703
Figure 482. Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .1704
Figure 483. General-purpose timer block diagram (TIM12) . . . . .1741
Figure 484. General-purpose timer block diagram (TIM13/TIM14) . . . . .1742
Figure 485. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1744
Figure 486. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1744
Figure 487. Counter timing diagram, internal clock divided by 1 . . . . .1745
Figure 488. Counter timing diagram, internal clock divided by 2 . . . . .1746
Figure 489. Counter timing diagram, internal clock divided by 4 . . . . .1746
Figure 490. Counter timing diagram, internal clock divided by N . . . . .1747
Figure 491. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .1747
Figure 492. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1748
Figure 493. Control circuit in normal mode, internal clock divided by 1 . . . . .1749
Figure 494. TI2 external clock connection example. . . . .1749
Figure 495. Control circuit in external clock mode 1 . . . . .1750
Figure 496. Capture/compare channel (example: channel 1 input stage) . . . . .1751
Figure 497. Capture/compare channel 1 main circuit . . . . .1751
Figure 498. Output stage of capture/compare channel (channel 1). . . . .1752
Figure 499. PWM input mode timing . . . . .1754
Figure 500. Output compare mode, toggle on OC1. . . . .1756
Figure 501. Edge-aligned PWM waveforms (ARR=8) . . . . .1757
Figure 502. Combined PWM mode on channel 1 and 2 . . . . .1758
Figure 503. Example of one pulse mode. . . . .1759
Figure 504. Retriggerable one pulse mode . . . . .1760
Figure 505. Measuring time interval between edges on 2 signals . . . . .1761
Figure 506. Control circuit in reset mode . . . . .1762
Figure 507. Control circuit in gated mode . . . . .1763
Figure 508. Control circuit in trigger mode . . . . .1764
Figure 509. TIM15 block diagram . . . . .1795
Figure 510. TIM16/TIM17 block diagram . . . . .1796
Figure 511. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1798
Figure 512. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1798
Figure 513. Counter timing diagram, internal clock divided by 1 . . . . .1800
Figure 514. Counter timing diagram, internal clock divided by 2 . . . . .1800
Figure 515. Counter timing diagram, internal clock divided by 4 . . . . .1801
Figure 516. Counter timing diagram, internal clock divided by N . . . . .1801
Figure 517. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1802
Figure 518. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1802
Figure 519. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1804
Figure 520. Control circuit in normal mode, internal clock divided by 1 . . . . .1805
Figure 521. TI2 external clock connection example. . . . .1805
Figure 522. Control circuit in external clock mode 1 . . . . .1806
Figure 523. Capture/compare channel (example: channel 1 input stage) . . . . .1807
Figure 524. Capture/compare channel 1 main circuit . . . . .1807
Figure 525. Output stage of capture/compare channel (channel 1). . . . .1808
Figure 526. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1808
Figure 527. PWM input mode timing . . . . .1810
Figure 528. Output compare mode, toggle on OC1. . . . .1812
Figure 529. Edge-aligned PWM waveforms (ARR=8) . . . . .1813
Figure 530. Combined PWM mode on channel 1 and 2 . . . . .1814
Figure 531. Complementary output with dead-time insertion. . . . .1815
Figure 532. Dead-time waveforms with delay greater than the negative pulse. . . . .1815
Figure 533. Dead-time waveforms with delay greater than the positive pulse. . . . .1816
Figure 534. Break circuitry overview . . . . .1818
Figure 535. Output behavior in response to a break . . . . .1820
Figure 536. Output redirection . . . . .1822
Figure 537. 6-step generation, COM example (OSSR=1) . . . . .1823
Figure 538. Example of one pulse mode . . . . .1825
Figure 539. Retriggerable one pulse mode . . . . .1826
Figure 540. Measuring time interval between edges on 2 signals . . . . .1828
Figure 541.Control circuit in reset mode . . . . .1829
Figure 542.Control circuit in gated mode . . . . .1830
Figure 543.Control circuit in trigger mode . . . . .1831
Figure 544.Basic timer block diagram . . . . .1883
Figure 545.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1885
Figure 546.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1885
Figure 547.Counter timing diagram, internal clock divided by 1 . . . . .1886
Figure 548.Counter timing diagram, internal clock divided by 2 . . . . .1887
Figure 549.Counter timing diagram, internal clock divided by 4 . . . . .1887
Figure 550.Counter timing diagram, internal clock divided by N . . . . .1888
Figure 551.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1888
Figure 552.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1889
Figure 553.Control circuit in normal mode, internal clock divided by 1 . . . . .1890
Figure 554.Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . .1897
Figure 555.Low-power timer block diagram (LPTIM3) . . . . .1898
Figure 556.Low-power timer block diagram (LPTIM4 and LPTIM5) . . . . .1898
Figure 557.Glitch filter timing diagram . . . . .1903
Figure 558.LPTIM output waveform, single counting mode configuration . . . . .1905
Figure 559.LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .1905
Figure 560.LPTIM output waveform, Continuous counting mode configuration . . . . .1906
Figure 561.Waveform generation . . . . .1907
Figure 562.Encoder mode counting sequence . . . . .1911
Figure 563.Watchdog block diagram . . . . .1926
Figure 564.Window watchdog timing diagram . . . . .1928
Figure 565.Independent watchdog block diagram . . . . .1933
Figure 566.RTC block overview . . . . .1944
Figure 567.Detailed RTC block diagram . . . . .1945
Figure 568.Tamper detection . . . . .1946
Figure 569.I2C block diagram . . . . .1990
Figure 570.I2C bus protocol . . . . .1992
Figure 571.Setup and hold timings . . . . .1994
Figure 572.I2C initialization flowchart . . . . .1997
Figure 573.Data reception . . . . .1998
Figure 574.Data transmission . . . . .1999
Figure 575.Slave initialization flowchart . . . . .2002
Figure 576.Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 0 . . . . .2004
Figure 577.Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 1 . . . . .2005
Figure 578.Transfer bus diagrams for I2C slave transmitter . . . . .2006
Figure 579.Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . .2007
Figure 580.Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . .2008
Figure 581.Transfer bus diagrams for I2C slave receiver . . . . .2008
Figure 582.Master clock generation . . . . .2010
Figure 583.Master initialization flowchart . . . . .2012
Figure 584.10-bit address read access with HEAD10R=0 . . . . .2012
Figure 585.10-bit address read access with HEAD10R=1 . . . . .2013
Figure 586.Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . .2014
Figure 587.Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . .2015
Figure 588. Transfer bus diagrams for I2C master transmitter . . . . .2016
Figure 589. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . .2018
Figure 590. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . .2019
Figure 591. Transfer bus diagrams for I2C master receiver . . . . .2020
Figure 592. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .2024
Figure 593. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . .2028
Figure 594. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .2029
Figure 595. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . .2030
Figure 596. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . .2031
Figure 597. Bus transfer diagrams for SMBus master transmitter . . . . .2032
Figure 598. Bus transfer diagrams for SMBus master receiver . . . . .2034
Figure 599. I2C interrupt mapping diagram . . . . .2040
Figure 600. USART block diagram . . . . .2059
Figure 601. Word length programming . . . . .2062
Figure 602. Configurable stop bits . . . . .2064
Figure 603. TC/TXE behavior when transmitting . . . . .2067
Figure 604. Start bit detection when oversampling by 16 or 8. . . . .2068
Figure 605. usart_ker_ck clock divider block diagram . . . . .2071
Figure 606. Data sampling when oversampling by 16 . . . . .2072
Figure 607. Data sampling when oversampling by 8 . . . . .2073
Figure 608. Mute mode using Idle line detection . . . . .2080
Figure 609. Mute mode using address mark detection . . . . .2081
Figure 610. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .2084
Figure 611. Break detection in LIN mode vs. Framing error detection. . . . .2085
Figure 612. USART example of synchronous master transmission. . . . .2086
Figure 613. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		2086
Figure 614. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		2087
Figure 615. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		2088
Figure 616. ISO 7816-3 asynchronous protocol . . . . .2090
Figure 617. Parity error detection using the 1.5 stop bits . . . . .2092
Figure 618. IrDA SIR ENDEC block diagram. . . . .2096
Figure 619. IrDA data modulation (3/16) - Normal mode. . . . .2096
Figure 620. Transmission using DMA . . . . .2098
Figure 621. Reception using DMA . . . . .2099
Figure 622. Hardware flow control between 2 USARTs . . . . .2099
Figure 623. RS232 RTS flow control . . . . .2100
Figure 624. RS232 CTS flow control . . . . .2101
Figure 625. Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . .2104
Figure 626. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . .		2104
Figure 627. LPUART block diagram . . . . .2146
Figure 628. LPUART word length programming . . . . .2148
Figure 629. Configurable stop bits . . . . .2150
Figure 630. TC/TXE behavior when transmitting . . . . .2152
Figure 631. lpuart_ker_ck clock divider block diagram . . . . .2155
Figure 632. Mute mode using Idle line detection . . . . .2159
Figure 633. Mute mode using address mark detection . . . . .2160
Figure 634. Transmission using DMA . . . . .2162
Figure 635. Reception using DMA . . . . .2163
Figure 636. Hardware flow control between 2 LPUARTs . . . . .2164
Figure 637. RS232 RTS flow control . . . . .2164
Figure 638. RS232 CTS flow control . . . . .2165
Figure 639. Wakeup event verified (wakeup event = address match,
FIFO disabled) . . . . .		2168
Figure 640. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . .		2168
Figure 641. SPI2S block diagram . . . . .2198
Figure 642. Full-duplex single master/ single slave application . . . . .2200
Figure 643. Half-duplex single master/ single slave application . . . . .2200
Figure 644. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		2201
Figure 645. Master and three independent slaves at star topology . . . . .2202
Figure 646. Master and three slaves at circular (daisy chain) topology . . . . .2204
Figure 647. Multi-master application . . . . .2205
Figure 648. Scheme of SS control logic . . . . .2207
Figure 649. Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . .2207
Figure 650. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). . . . .2208
Figure 651. Data clock timing diagram . . . . .2210
Figure 652. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . .2211
Figure 653. Packing data in FIFO for transmission and reception . . . . .2219
Figure 654. TI mode transfer . . . . .2221
Figure 655. Optional configurations of slave's behavior at detection of underrun condition . . . . .2223
Figure 656. Low-power mode application example . . . . .2227
Figure 657. Waveform examples . . . . .2234
Figure 658. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .2235
Figure 659. I2S Philips standard waveforms . . . . .2235
Figure 660. Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . .2236
Figure 661. Master MSB justified 16 or 24-bit data length . . . . .2236
Figure 662. Slave MSB justified . . . . .2237
Figure 663. LSB justified 16 or 24-bit data length . . . . .2237
Figure 664. Master PCM when the frame length is equal the data length . . . . .2238
Figure 665. Master PCM standard waveforms (16 or 24-bit data length) . . . . .2238
Figure 666. Slave PCM waveforms . . . . .2239
Figure 667. Start-up sequence, I2S Philips standard, master . . . . .2241
Figure 668. Start-up sequence, I2S Philips standard, slave . . . . .2242
Figure 669. Stop sequence, I2S Philips standard, master . . . . .2243
Figure 670. I 2 S clock generator architecture . . . . .2243
Figure 671. Data Format . . . . .2246
Figure 672. Handling of underrun situation . . . . .2247
Figure 673. Handling of overrun situation . . . . .2248
Figure 674. Frame error detection, with FIXCH=0 . . . . .2249
Figure 675. Frame error detection, with FIXCH=1 . . . . .2249
Figure 676. SAI functional block diagram . . . . .2277
Figure 677. Audio frame . . . . .2281
Figure 678. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2283
Figure 679. FS role is start of frame (FSDEF = 0) . . . . .2284
Figure 680. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2285
Figure 681. First bit offset . . . . .2285
Figure 682. Audio block clock generator overview . . . . .2287
Figure 683. PDM typical connection and timing . . . . .2291
Figure 684. Detailed PDM interface block diagram . . . . .2292
Figure 685. Start-up sequence . . . . .2293
Figure 686. SAI_ADR format in TDM, 32-bit slot width . . . . .2294
Figure 687. SAI_ADR format in TDM, 16-bit slot width . . . . .2295
Figure 688. SAI_ADR format in TDM, 8-bit slot width . . . . .2296
Figure 689. AC'97 audio frame . . . . .2299
Figure 690. Example of typical AC'97 configuration on devices featuring at least
2 embedded SAIs (three external AC'97 decoders) . . . . .		2300
Figure 691. SPDIF format . . . . .2301
Figure 692. SAI_xDR register ordering . . . . .2302
Figure 693. Data companding hardware in an audio block in the SAI . . . . .2306
Figure 694. Tristate strategy on SD output line on an inactive slot . . . . .2307
Figure 695. Tristate on output data line in a protocol like I2S . . . . .2308
Figure 696. Overrun detection error . . . . .2309
Figure 697. FIFO underrun event . . . . .2309
Figure 698. SPDIFRX block diagram . . . . .2345
Figure 699. S/PDIF sub-frame format . . . . .2346
Figure 700. S/PDIF block format . . . . .2347
Figure 701. S/PDIF Preambles . . . . .2347
Figure 702. Channel coding example . . . . .2348
Figure 703. SPDIFRX decoder . . . . .2349
Figure 704. Noise filtering and edge detection . . . . .2349
Figure 705. Thresholds . . . . .2351
Figure 706. Synchronization flowchart . . . . .2353
Figure 707. Synchronization process scheduling . . . . .2354
Figure 708. SPDIFRX States . . . . .2355
Figure 709. SPDIFRX_FMTx_DR register format . . . . .2357
Figure 710. Channel/user data format . . . . .2358
Figure 711. S/PDIF overrun error when RXSTEO = 0 . . . . .2360
Figure 712. S/PDIF overrun error when RXSTEO = 1 . . . . .2361
Figure 713. SPDIFRX interface interrupt mapping diagram . . . . .2364
Figure 714. S1 signal coding . . . . .2379
Figure 715. S2 signal coding . . . . .2379
Figure 716. SWPMI block diagram . . . . .2381
Figure 717. SWP bus states . . . . .2384
Figure 718. SWP frame structure . . . . .2385
Figure 719. SWPMI No software buffer mode transmission . . . . .2386
Figure 720. SWPMI No software buffer mode transmission, consecutive frames . . . . .2387
Figure 721. SWPMI Multi software buffer mode transmission . . . . .2389
Figure 722. SWPMI No software buffer mode reception . . . . .2391
Figure 723. SWPMI single software buffer mode reception . . . . .2392
Figure 724. SWPMI Multi software buffer mode reception . . . . .2394
Figure 725. SWPMI single buffer mode reception with CRC error . . . . .2395
Figure 726. MDIOS block diagram . . . . .2408
Figure 727. MDIO protocol write frame waveform . . . . .2409
Figure 728. MDIO protocol read frame waveform . . . . .2409
Figure 729. SDMMC “no response” and “no data” operations . . . . .2421
Figure 730. SDMMC (multiple) block read operation . . . . .2421
Figure 731. SDMMC (multiple) block write operation . . . . .2422
Figure 732. SDMMC (sequential) stream read operation . . . . .2422
Figure 733. SDMMC (sequential) stream write operation . . . . .2422
Figure 734. SDMMC block diagram . . . . .2424
Figure 735. SDMMC Command and data phase relation . . . . .2426
Figure 736. Control unit . . . . .2428
Figure 737. Command/response path . . . . .2429
Figure 738. Command path state machine (CPSM) . . . . .2430
Figure 739. Data path . . . . .2436
Figure 740. DDR mode data packet clocking . . . . .2437
Figure 741. DDR mode CRC status / boot acknowledgment clocking. . . . .2437
Figure 742. Data path state machine (DPSM) . . . . .2438
Figure 743. CLKMUX unit . . . . .2449
Figure 744. Asynchronous interrupt generation. . . . .2454
Figure 745. Synchronous interrupt period data read . . . . .2454
Figure 746. Synchronous interrupt period data write . . . . .2455
Figure 747. Asynchronous interrupt period data read . . . . .2456
Figure 748. Asynchronous interrupt period data write . . . . .2456
Figure 749. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .2459
Figure 750. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .2459
Figure 751. Read Wait with SDMMC_CK < 50 MHz . . . . .2460
Figure 752. Read Wait with SDMMC_CK > 50 MHz . . . . .2461
Figure 753. CMD12 stream timing . . . . .2463
Figure 754. CMD5 Sleep Awake procedure . . . . .2465
Figure 755. Normal boot mode operation . . . . .2467
Figure 756. Alternative boot mode operation . . . . .2468
Figure 757. Command response R1b busy signaling . . . . .2469
Figure 758. SDMMC state control . . . . .2470
Figure 759. Card cycle power / power up diagram . . . . .2471
Figure 760. CMD11 signal voltage switch sequence . . . . .2472
Figure 761. Voltage switch transceiver typical application. . . . .2474
Figure 762. CAN subsystem . . . . .2504
Figure 763. FDCAN block diagram . . . . .2506
Figure 764. Transceiver delay measurement . . . . .2511
Figure 765. Pin control in bus monitoring mode . . . . .2513
Figure 766. Pin control in loop back mode. . . . .2515
Figure 767. Message RAM configuration. . . . .2516
Figure 768. Standard message ID filter path . . . . .2519
Figure 769. Extended message ID filter path. . . . .2520
Figure 770. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . .2526
Figure 771. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . .2526
Figure 772. Bit timing . . . . .2528
Figure 773. Bypass operation . . . . .2530
Figure 774. FSM calibration. . . . .2531
Figure 775. Cycle time and global time synchronization . . . . .2546
Figure 776. TTCAN level 0 and level 2 drift compensation . . . . .2547
Figure 777. Level 0 schedule synchronization state machine . . . . .2554
Figure 778. Level 0 master to slave relation . . . . .2555
Figure 779. OTG_HS high-speed block diagram. . . . .2637
Figure 780. OTG_HS A-B device connection . . . . .2640
Figure 781. OTG_HS peripheral-only connection . . . . .2642
Figure 782. OTG_HS host-only connection . . . . .2646
Figure 783. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .2650
Figure 784. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .2652
Figure 785. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .2653
Figure 786. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .2654
Figure 787. Interrupt hierarchy. . . . .2658
Figure 788. Transmit FIFO write task . . . . .2763
Figure 789. Receive FIFO read task . . . . .2764
Figure 790. Normal bulk/control OUT/SETUP . . . . .2765
Figure 791. Bulk/control IN transactions . . . . .2769
Figure 792. Normal interrupt OUT . . . . .2772
Figure 793. Normal interrupt IN . . . . .2777
Figure 794. Isochronous OUT transactions . . . . .2779
Figure 795. Isochronous IN transactions . . . . .2782
Figure 796. Normal bulk/control OUT/SETUP transactions - DMA . . . . .2784
Figure 797. Normal bulk/control IN transaction - DMA . . . . .2786
Figure 798. Normal interrupt OUT transactions - DMA mode . . . . .2787
Figure 799. Normal interrupt IN transactions - DMA mode . . . . .2788
Figure 800. Normal isochronous OUT transaction - DMA mode . . . . .2789
Figure 801. Normal isochronous IN transactions - DMA mode . . . . .2790
Figure 802. Receive FIFO packet read . . . . .2796
Figure 803. Processing a SETUP packet . . . . .2798
Figure 804. Bulk OUT transaction . . . . .2805
Figure 805. TRDT max timing case . . . . .2814
Figure 806. A-device SRP . . . . .2815
Figure 807. B-device SRP . . . . .2816
Figure 808. A-device HNP . . . . .2817
Figure 809. B-device HNP . . . . .2819
Figure 810. Ethernet high-level block diagram . . . . .2826
Figure 811. DMA transmission flow (standard mode) . . . . .2829
Figure 812. DMA transmission flow (OSP mode) . . . . .2831
Figure 813. Receive DMA flow . . . . .2833
Figure 814. Overview of MAC transmission flow . . . . .2836
Figure 815. MAC reception flow . . . . .2838
Figure 816. Packet filtering sequence . . . . .2842
Figure 817. Networked time synchronization . . . . .2851
Figure 818. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . .		2852
Figure 819. System time update using fine correction method . . . . .2862
Figure 820. TCP segmentation offload overview . . . . .2879
Figure 821. TCP segmentation offload flow . . . . .2880
Figure 822. Header and payload fields of segmented packets . . . . .2883
Figure 823. Supported PHY interfaces . . . . .2893
Figure 824. SMA Interface block . . . . .2893
Figure 825. MDIO packet structure (Clause 45) . . . . .2894
Figure 826. MDIO packet structure (Clause 22) . . . . .2895
Figure 827. SMA write operation flow . . . . .2897
Figure 828. Write data packet . . . . .2898
Figure 829. Read data packet . . . . .2898
Figure 830. Media independent interface (MII) signals . . . . .2900
Figure 831. RMII block diagram . . . . .2902
Figure 832. Transmission bit order . . . . .2903
Figure 833. Receive bit order . . . . .2904
Figure 834. LPI transitions (Transmit, 100 Mbds) . . . . .2912
Figure 835. LPI Tx clock gating (when LPITCSE = 1) . . . . .2913
Figure 836. LPI transitions (receive, 100 Mbps) . . . . .2914
Figure 837. Descriptor ring structure . . . . .2936
Figure 838. DMA descriptor ring . . . . .2937
Figure 839. Transmit descriptor (read format) . . . . .2938
Figure 840. Transmit descriptor write-back format. . . . .2943
Figure 841. Transmit context descriptor format . . . . .2947
Figure 842. Receive normal descriptor (read format) . . . . .2950
Figure 843. Receive normal descriptor (write-back format) . . . . .2953
Figure 844. Receive context descriptor . . . . .2960
Figure 845. Generation of ETH_DMAISR flags . . . . .2978
Figure 846. HDMI-CEC block diagram . . . . .3100
Figure 847. Message structure . . . . .3100
Figure 848. Blocks . . . . .3101
Figure 849. Bit timings . . . . .3101
Figure 850. Signal free time . . . . .3102
Figure 851. Arbitration phase . . . . .3102
Figure 852. SFT of three nominal bit periods . . . . .3102
Figure 853. Error bit timing . . . . .3103
Figure 854. Error handling . . . . .3105
Figure 855. TXERR detection . . . . .3106
Figure 856. Block diagram of debug infrastructure . . . . .3117
Figure 857. Power domains of debug infrastructure . . . . .3118
Figure 858. Clock domains of debug infrastructure . . . . .3119
Figure 859. SWD successful data transfer . . . . .3122
Figure 860. JTAG TAP state machine . . . . .3123
Figure 861. Debug and access port connections . . . . .3134
Figure 862. APB-D CoreSight component topology . . . . .3142
Figure 863. Embedded cross trigger . . . . .3149
Figure 864. Mapping of trigger inputs to outputs . . . . .3151
Figure 865. ETF state transition diagram. . . . .3179
Figure 866. Cortex-M7 CoreSight Topology . . . . .3243

Chapters