39. Revision history

Table 270. Document revision history

Date	Revision	Changes
17-Dec-2019	1	Initial release.
9-Jul-2020	2	Updated: – New Section 4.10.28: Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPS2R) – Figure 21: Clock tree – Figure 22: HSE32 clock sources and Figure 23: HSE32 TCXO control – MSICLA[7:0] in Section 6.4.2: RCC internal clock sources calibration register (RCC_ICSCR) – Caution in Section 17.4.6: DMAMUX request line multiplexer – Section 16.9: Temperature sensor and internal reference voltage – TSEL1[3:0] in Section 17.7.1: DAC control register (DAC_CR) – TRIM[5:0] in Section 27.3.2: VREFBUF calibration control register (VREFBUF_CCR) – New Table 154: Point on elliptic curve Fp check average computation times – ADDRERRF and RAMERRF in Section 23.7.2: PKA status register (PKA_SR) – CKD[1:0] in Section 37.4.1: TIM1 control register 1 (TIM1_CR1) – DTG[7:0] in Section 37.4.20: TIM1 break and dead-time register (TIM1_BDTR) – BKCMP2P in Section 37.4.27: TIM1 alternate function option register 1 (TIM1_AF1) – Figure 408: Master/slave connection example with 1 channel only timers – OC1FE in Section 38.4.8: TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) – Table 307: Output control bit for standard OCx channels – New Section 40.3.17: Using timer output as trigger for other timers (TIM16/TIM17) – IC1M[3:0] in Section 40.4.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) – Table 315: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) – TI1SEL[3:0] in Section 40.4.19: TIM16 input selection register (TIM16_TISEL) and Section 40.4.22: TIM17 input selection register (TIM17_TISEL) – Note in Section 26.6: LPTIM interrupts – PSC[7:0] in Section 48.7.6: USART guard time and prescaler register (USART_GTPR) – SBKF in Section 48.7.9: USART interrupt and status register [alternate] (USART_ISR)
27-Oct-2020	3	Updated: – Section 5.2.1: Power-on reset (POR)/power-down reset (PDR) /Brownout reset (BOR) – Various updates on Section 7: Hardware semaphore (HSEM)

Table 270. Document revision history (continued)

Date	Revision	Changes
24-Jun-2021	4	Updated: – Patented technology and errata sheet in the Introduction – Section 3.3.2: Empty check – OPTVAL in Section 3.4.2: Option bytes programming – OPTNV description in Section 3.10.5: FLASH status register (FLASH_SR) – Section 4.1: Sub-GHz radio introduction – Section 4.2: Sub-GHz radio main features – Section 4.5.5: Generic framing – Section 4.1: Sub-GHz radio introduction – New functionality in Section 4.6: Sub-GHz radio data buffer – Section 4.13.172: Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR) – Section 4.7.2: Sleep mode – Note removed in Set_RfFrequency() command – Section 4.10: Sub-GHz radio application configuration – Danger note removed in Section 4.13: Sub-GHz radio registers – Figure 101: Brownout reset waveform – PVD naming in Section 17.6.2: PWR control register 2 (PWR_CR2) and Section 17.6.6: Power status register 2 (PWR_SR2) – First sentence in Section 40.1.2: System reset – External source (HSE32 TXCO) – First sentence of Section 30.4: HSEM registers – Caution in Section 12.4.4: DMAMUX request line multiplexer – Note in Section 12.4.5: DMAMUX request generator – New note in Polynomial programmability – Figure 30: ADC block diagram – Formula in Figure 17.5: RNG processing time – Table 119: Interrupt control bits – Table 82: CTR mode initialization vector definition – Table 85: Initialization of SAES_IVRx registers in CCM mode – Section 19.3.4: PKA public key acceleration – Table 97: Montgomery multiplication – Section 19.5: Example of configurations and processing times – Table 122: PKA interrupt requests – AFIO renamed in Section 21: General-purpose timer (TIM2) – New note in Section 50.4.7: Trigger multiplexer – Some bit descriptions in Section 26.7.2: LPTIM interrupt clear register (LPTIM_ICR) – Table 430: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz

Table 270. Document revision history (continued)

Date	Revision	Changes
19-Apr-2022	5	Updated: – Section 3.3.1: Flash memory organization – Section 4.1: Sub-GHz radio introduction – Section 4.2: Sub-GHz radio main features – Section 4.5.3: FSK modem – Figure 9: Generic packet frames format – Section 4.5.7: BPSK framing – Table 32: Recommended CAD configuration settings – LoRa Set_LoRaSymbTimeout() command – Get_RxBufferStatus() command – New registers in Section 4.13: Sub-GHz radio registers – SMPSEN desc in Section 5.5.8: PWR control register 5 (PWR_CR5) – Section 15.4.6: Calibration (ADCAL) – Section 15.4.10: Configuring the ADC – Notes in Section 15.15.4: ADC configuration register 1 (ADC_CFGR1) and Section 15.15.5: ADC configuration register 2 (ADC_CFGR2) – Health checks – Section 35.3.4: RNG initialization – Section 35.5: RNG processing time – Section 35.6.2: Validation conditions – RNDATA desc in Section 35.7.3: RNG data register (RNG_DR) – Section 21.4.16: AES DMA interface – Note in Section 24.3.16: Using the break function – Section 24.4.4: TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) – Note in Section 26.5.14: Bidirectional break inputs – Section 26.5.15: 6-step PWM generation – Note on Section 30.6.1: RTC time register (RTC_TR) – New Section 77: Important security notice
16-Nov-2022	6	Updated: – Table 19: Sub-GHz radio transmit high output power – Table 23: LoRa bandwidth setting – Table 27: PA optimal setting and operating modes – Register names from Section 4.10.18 to Section 4.10.25: Sub-GHz radio generic synchronization word control register 7 (SUBGHZ_GSYNCR7) – Address offset of Section 4.10.43: Sub-GHz radio AGC RSSI control register (SUBGHZ_AGCRSSICTL0R) – New Section 4.10.59: Sub-GHz radio regulator drive control register (SUBGHZ_REGDRVCR) – RFEOLF description in Section 5.5.6: Power status register 2 (PWR_SR2) – SVCall description in Table 78: Vector table – DAC_DHR8RD, DAC_DHR12RD, and DAC_DHR12LD registers removed in Section 19: Digital-to-analog converter (DAC)
03-Mar-2023	7	Updated Section 6.2: Clocks , Section 6.2.12: SPI2S2 clock , Section 36.9.2: ITM trace enable register (ITM_TER) , and Section 36.9.3: ITM trace privilege register (ITM_TPR) . Minor text edits across the whole document.

Table 270. Document revision history (continued)

Date	Revision	Changes
29-Aug-2023	8	Updated Table 4: Flash memory - Single bank organization , Table 98: ADC register map and reset values , Table 118: RNG interrupt requests , Table 119: RNG configurations , and Table 209: Interrupt requests . Updated Section 3.8.7: FLASH option register (FLASH_OPTR) , Section 16.12.13: ADC analog watchdog 2 configuration register (ADC_AWD2CR) , Section 24.3.15: Encoder interface mode , and Section 30.6.18: RTC status register (RTC_SR) . Updated Figure 248: Low-power timer block diagram , Figure 265: I2C initialization flow , and Figure 268: Target initialization flow . Minor text edits across the whole document.
05-Apr-2024	9	Updated Get_RssiInst() command , Temperature sensor , DAC output , V _REFINTand V _BATinternal channels , Section 20.5: RNG processing time , Section 28.3.3: Hardware watchdog , Section 28.4.4: IWDG status register (IWDG_SR) , Section 30.3.4: Clock and prescalers , Section 32.4.15: SMBus controller mode , Section 32.7: I2C DMA requests , Section 32.8: I2C debug modes , and note in Section 33.8.14: USART prescaler register (USART_PRESC) . Updated Figure 50: Analog-to-digital conversion time and Figure 319: LPUART block diagram . Updated Table 119: RNG configurations . Added Table 120: Configuration selection , Table 229: USART/UART input/output pins , Table 230: USART internal input/output signals , Table 239: LPUART input/output pins , and Table 240: LPUART internal input/output signals . Minor text edits across the whole document.
02-Dec-2024	10	Added Section 1.3: Register reset value . Updated Section 7.3.5: HSEM unlock procedures , Section 16.3.3: Calibration (ADCAL) , Section 16.3.5: ADC clock (CKMODE, PRESC[3:0]) , Section 16.12.5: ADC configuration register 2 (ADC_CFGR2) , Section 17.4.12: DAC channel buffer calibration , Noise source error detection , Section 30.3.4: Clock and prescalers , Section 30.6.18: RTC status register (RTC_SR) , Section 30.6.19: RTC masked interrupt status register (RTC_MISR) , Section 32.4: I2C functional description and its subsections . Master and slave terms in Section 32: Inter-integrated circuit interface (I2C) changed into controller and target. Updated Table 4: Flash memory - Single bank organization and Table 119: RNG configurations . Updated Figure 9: Generic packet frames format , Figure 45: ADC calibration , Figure 46: Calibration factor forcing , Figure 47: Enabling/disabling the ADC , Figure 48: ADC clock scheme , Figure 52: Stopping an ongoing conversion , Figure 65: ADC_AWDx_OUT signal generation (on a single channel) , Figure 76: DAC conversion (SW trigger enabled) with LFSR wave generation , Figure 248: Low-power timer block diagram , Figure 257: Independent watchdog block diagram , and Figure 268: Target initialization flow . Minor text edits across the whole document.

Date

Revision

Changes

29-Aug-2023

Updated Table 4: Flash memory - Single bank organization , Table 98: ADC register map and reset values , Table 118: RNG interrupt requests , Table 119: RNG configurations , and Table 209: Interrupt requests .

Updated Section 3.8.7: FLASH option register (FLASH_OPTR) , Section 16.12.13: ADC analog watchdog 2 configuration register (ADC_AWD2CR) , Section 24.3.15: Encoder interface mode , and Section 30.6.18: RTC status register (RTC_SR) .

Updated Figure 248: Low-power timer block diagram , Figure 265: I2C initialization flow , and Figure 268: Target initialization flow .

Minor text edits across the whole document.

05-Apr-2024

Updated Get_RssiInst() command , Temperature sensor , DAC output , V _REFINTand V _BATinternal channels , Section 20.5: RNG processing time , Section 28.3.3: Hardware watchdog , Section 28.4.4: IWDG status register (IWDG_SR) , Section 30.3.4: Clock and prescalers , Section 32.4.15: SMBus controller mode , Section 32.7: I2C DMA requests , Section 32.8: I2C debug modes , and note in Section 33.8.14: USART prescaler register (USART_PRESC) .

Updated Figure 50: Analog-to-digital conversion time and Figure 319: LPUART block diagram .

Updated Table 119: RNG configurations .

Added Table 120: Configuration selection , Table 229: USART/UART input/output pins , Table 230: USART internal input/output signals , Table 239: LPUART input/output pins , and Table 240: LPUART internal input/output signals .

Minor text edits across the whole document.

02-Dec-2024

Added Section 1.3: Register reset value .

Updated Section 7.3.5: HSEM unlock procedures , Section 16.3.3: Calibration (ADCAL) , Section 16.3.5: ADC clock (CKMODE, PRESC[3:0]) , Section 16.12.5: ADC configuration register 2 (ADC_CFGR2) , Section 17.4.12: DAC channel buffer calibration , Noise source error detection , Section 30.3.4: Clock and prescalers , Section 30.6.18: RTC status register (RTC_SR) , Section 30.6.19: RTC masked interrupt status register (RTC_MISR) , Section 32.4: I2C functional description and its subsections .

Master and slave terms in Section 32: Inter-integrated circuit interface (I2C) changed into controller and target.

Updated Table 4: Flash memory - Single bank organization and Table 119: RNG configurations .

Updated Figure 9: Generic packet frames format , Figure 45: ADC calibration , Figure 46: Calibration factor forcing , Figure 47: Enabling/disabling the ADC , Figure 48: ADC clock scheme , Figure 52: Stopping an ongoing conversion , Figure 65: ADC_AWDx_OUT signal generation (on a single channel) , Figure 76: DAC conversion (SW trigger enabled) with LFSR wave generation , Figure 248: Low-power timer block diagram , Figure 257: Independent watchdog block diagram , and Figure 268: Target initialization flow .

Minor text edits across the whole document.

Table 270. Document revision history (continued)

Date	Revision	Changes
23-Apr-2026	11	Updated: Set_RfFrequency() command in Section 4.8.4: Sub-GHz radio configuration commands. Section 7.3.1: HSEM block diagram, Section 16.3.4: ADC on-off control (ADEN, ADDIS, ADRDY), Section 17.4.11: DAC channel modes, Section 17.4.13: DAC channel conversion modes, Section 17.7.1: DAC control register (DAC_CR), Section 18.1: VREFBUF introduction, Section 26.4.15: Encoder mode Renamed Section 7.1: HSEM introduction, Section 7.2: HSEM main features, Section 15.1: CRC introduction, Section 17.1: DAC introduction, Section 20.1: RNG introduction, Section 26.1: LPTIM introduction, Section 29.1: WWDG introduction, Section 32.1: I2C introduction.

Date

Revision

Changes

23-Apr-2026

Updated:
Set_RfFrequency() command in Section 4.8.4: Sub-GHz radio configuration commands. Section 7.3.1: HSEM block diagram, Section 16.3.4: ADC on-off control (ADEN, ADDIS, ADRDY), Section 17.4.11: DAC channel modes, Section 17.4.13: DAC channel conversion modes, Section 17.7.1: DAC control register (DAC_CR), Section 18.1: VREFBUF introduction, Section 26.4.15: Encoder mode

Renamed Section 7.1: HSEM introduction, Section 7.2: HSEM main features, Section 15.1: CRC introduction, Section 17.1: DAC introduction, Section 20.1: RNG introduction, Section 26.1: LPTIM introduction, Section 29.1: WWDG introduction, Section 32.1: I2C introduction.