19. Comparator (COMP)

19.1 COMP introduction

The device embeds two ultra-low-power comparators (COMP1 and COMP2).

These comparators can be used for a variety of functions including the following:

• wake up from low-power mode triggered by an analog signal
• analog signal conditioning
• cycle-by-cycle current control loop when combined with a PWM output from a timer

19.2 COMP main features

• Configurable plus and minus inputs used for flexible voltage:
- – Multiplexed I/O pins
- – DAC channel1
- – Internal reference voltage and three sub multiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider)
• Programmable hysteresis
• Programmable speed / consumption
• Redirection of outputs to an I/O or to timer inputs for triggering:
- – break events for fast PWM shutdowns
• Blanking of comparator outputs
• Window comparator
• Interrupt generation capability with wake up from Sleep and Stop modes (through the EXTI controller)

19.3 COMP functional description

19.3.1 COMP block diagram

The block diagram of the comparators is shown in the figure below.

Figure 80. Comparator block diagram

Figure 80. Comparator block diagram. The diagram shows a comparator block labeled COMPx. The non-inverting input (+) is labeled COMPx_INP and is connected to a multiplexer. The inverting input (-) is labeled COMPx_INM and is connected to another multiplexer. The COMPx_INP multiplexer has inputs from COMPx_INP I/Os and COMPx_INPSEL. The COMPx_INM multiplexer has inputs from COMPx_INM I/Os, COMPx_INM I/Os, DAC_CH1, VREFINT, 3/4 VREFINT, 1/2 VREFINT, and 1/4 VREFINT. The output of the comparator is labeled COMPx_VALUE and is connected to a polarity selection block. The polarity selection block has inputs from COMPx_POL and an inverter. The output of the polarity selection block is connected to COMPx_OUT, which is labeled 'GPIO alternate function'. The COMPx_VALUE output is also connected to 'Wakeup EXTI line interrupt' and 'Timers'. The diagram is labeled MSv60765V1.

19.3.2 COMP pins and internal signals

The I/Os used as comparator inputs must be configured in analog mode in the GPIO registers.

The comparator outputs can be connected to the I/Os through their alternate functions (refer to the product datasheet).

The outputs can also be internally redirected to a variety of timer inputs for the following purposes:

• emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• cycle-by-cycle current control, using OCREF_CLR inputs
• input capture for timing measurements

The comparator output can be simultaneously redirected internally and externally.

Table 110. COMP1 input plus assignment

COMP1_INP	COMP1_INPSEL
PB4	00
PB2	01

Table 111. COMP1 input minus assignment

COMP1_INM	COMP1_INMSEL[2:0]	COMP1_INMESEL[1:0]
1/4 V _REFINT	000	Not affected
1/2 V _REFINT	001	Not affected
3/4 V _REFINT	010	Not affected
V _REFINT	011	Not affected
DAC channel1	100	Not affected
Reserved	101	Not affected
PB3	110	Not affected
PA10	111	00
PA11	111	01
PA15	111	10
Reserved	111	11

Table 112. COMP2 input plus assignment

COMP2_INP	COMP2_INPSEL
PB4	00
PB1	01
PA15	10

Table 113. COMP2 input minus assignment

COMP2_INM	COMP2_INMSEL[2:0]	COMP2_INMESEL[1:0]
1/4 V _REFINT	000	Not affected
1/2 V _REFINT	001	Not affected
3/4 V _REFINT	010	Not affected
V _REFINT	011	Not affected
DAC channel1	100	Not affected
Reserved	101	Not affected
PB3	110	Not affected
PB2	111	00
PA10	111	01
PA11	111	10
Reserved	111	11

19.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the APB2 clock.

There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG.

Note: Important: The polarity selection logic and the output redirection to the port works independently from the APB2 clock. This allows the comparator to work even in Stop mode.

19.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications with specific functional safety requirements, the comparator configuration can be protected against undesired alteration that may happen, for example, at program counter corruption.

For this purpose, the comparator configuration registers can be write-protected (read-only).

Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPx LOCK bit.

The write protection can only be removed through the MCU reset.

19.3.5 Window comparator

The purpose of the window comparator is to monitor the analog voltage and check that it is comprised within the specified voltage range defined by lower and upper thresholds.

COMP1 and COMP2 can be utilized to create window comparator. The monitored analog voltage is connected to the non-inverting (plus) inputs of comparators connected together, and the upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators. The two non-inverting inputs can be connected internally together by enabling the WINMODE bit to save one I/O for other purposes.

Figure 81. Window mode

The diagram illustrates the window mode configuration for two comparators, COMPx and COMPy. Each comparator has two multiplexers for input selection: INPSEL for the non-inverting input (INP) and INMSEL for the inverting input (INM). The INPSEL multiplexers select between external I/Os and internal sources. The INMSEL multiplexers select between external I/Os and internal sources. The WINMODE signal is connected to the non-inverting input of COMPy. The diagram is labeled MSv37667V1.

Schematic diagram of window mode for two comparators, COMPx and COMPy. Each comparator has multiple input sources (I/Os and internal sources) connected through multiplexers (INPSEL and INMSEL). The non-inverting input (INP) and inverting input (INM) are connected to the comparator. A WINMODE signal is connected to the non-inverting input of COMPy. The diagram is labeled MSv37667V1.

19.3.6 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.

Figure 82. Comparator hysteresis

The diagram shows the hysteresis effect in a comparator. The top graph plots the non-inverting input (INP) and the inverting input (INM) over time. The bottom graph plots the output (COMP_OUT) over time. The output transitions are shown with hysteresis, indicated by the difference between the rising and falling thresholds (INM and INM - V _hyst). The diagram is labeled MS19984V1.

Timing diagram showing the hysteresis effect. The top graph plots INP (non-inverting input) and INM (inverting input) over time. The bottom graph plots COMP_OUT (output) over time. The output transitions are shown with hysteresis, indicated by the difference between the rising and falling thresholds (INM and INM - V_hyst). The diagram is labeled MS19984V1.

19.3.7 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It uses a blanking window defined with a timer output compare signal. Refer to the register description for selectable blanking signals. The blanking signal gates the internal comparator output such as to clean the comp_outfrom spurious pulses due to current spikes, as depicted in the figure below.

Figure 83. Comparator output blanking

Timing diagram and logic schematic for comparator output blanking. The timing diagram shows four waveforms: PWM, Inverting input (current limit), Non-inverting input (current), and cmp_out (before blanking gate). A 'current spike' in the non-inverting input causes a 'spurious pulse' in the cmp_out signal. The cmp_blk signal (blanking window) is shown as a series of pulses. The final comp_out signal is the result of an AND gate (Blanking gate) with inputs cmp_out and cmp_blk (inverted). The output is labeled 'comp_out (to I/Os, TIM_BK ...)'.

The figure illustrates the comparator output blanking function. It includes a timing diagram and a logic schematic. The timing diagram shows the following signals over time:

PWM: A periodic square wave signal.
Inverting input (represents current limit): A constant reference voltage level.
Non-inverting input (represents current): A signal that ramps up and then drops sharply during a 'current spike'.
cmp_out (before blanking gate): The raw output of the comparator, which shows a 'spurious pulse' when the current spike occurs.
cmp_blk (blanking window): A signal that is high during the initial part of each PWM period to blank out spurious pulses.
comp_out (COMP output): The final output after blanking, which remains stable despite the current spike.

Below the timing diagram, a logic schematic shows a 2-input AND gate labeled 'Blanking gate'. The inputs are cmp_outand cmp_blk(with a bubble indicating inversion). The output is labeled comp_out (to I/Os, TIM_BK ...).

MS30964V2

Timing diagram and logic schematic for comparator output blanking. The timing diagram shows four waveforms: PWM, Inverting input (current limit), Non-inverting input (current), and cmp_out (before blanking gate). A 'current spike' in the non-inverting input causes a 'spurious pulse' in the cmp_out signal. The cmp_blk signal (blanking window) is shown as a series of pulses. The final comp_out signal is the result of an AND gate (Blanking gate) with inputs cmp_out and cmp_blk (inverted). The output is labeled 'comp_out (to I/Os, TIM_BK ...)'.

19.3.8 COMP power and speed modes

COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.

PWRMODE[1:0] bits in COMPx_CSR registers can be programmed as follows:

00: High speed/full power
01: Medium speed/medium power
10: Medium speed/medium power
11: Very-low speed/ultra-low-power

19.4 COMP low-power modes

Table 114. Comparator behavior in the low-power modes

Mode	Description
Sleep	No effect on the comparators Comparator interrupts cause the device to exit the Sleep mode.
LPRun	No effect
LPSleep	No effect on the comparators Comparator interrupts cause the device to exit the LPSleep mode.
Stop 0	No effect on the comparators Comparator interrupts cause the device to exit the Stop mode.
Stop 1
Stop 2
Standby	COMP registers are powered down and must be reinitialized after exiting Standby or Shutdown mode.
Shutdown

19.5 COMP interrupts

The comparator outputs are internally connected to the extended interrupts and events controller (EXTI). Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes.

Refer to the “Interrupt and events” section for more details.

The following sequence enables the COMPx interrupt through EXTI block:

1. Configure and enable the EXTI line corresponding to the COMPx output event in interrupt mode and select the rising, falling or both edges sensitivity.
2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines.
3. Enable the COMPx.

Table 115. Interrupt control bits

Interrupt event	Event flag	Enable control bit	Exit from Sleep mode	Exit from Stop modes	Exit from Standby mode
COMP1 output	VALUE in COMP1_CSR	Through EXTI	Yes	Yes	Not applicable
COMP2 output	VALUE in COMP2_CSR	Through EXTI	Yes	Yes	Not applicable

19.6 COMP registers

19.6.1 COMP1 control and status register (COMP1_CSR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	INMESEL[1:0]		Res.	SCALEN	BRGEN	Res.	BLANKING[2:0]		HYST[1:0]
rs	r				rw	rw		rw	rw		rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	Res.	Res.	Res.	Res.	Res.	Res.	INPSEL[1:0]		INMSEL[2:0]			PWRMODE[1:0]		Res.	EN
rw							rw	rw	rw	rw	rw	rw	rw		rw

Bit 31 LOCK : locks the whole content of the register, COMP1_CSR[31:0]

This bit is set by software and cleared by a hardware system reset.

0: COMP1_CSR[31:0] are read/write.

1: COMP1_CSR[31:0] are read-only.

Bit 30 VALUE : COMP1 output status bit

This bit is read-only. It reflects the current COMP1 output taking into account the effect of the POLARITY bit.

Bits 29:27 Reserved, must be kept at reset value.

Bits 26:25 INMESEL[1:0] : COMP1 input minus extended selection

These bits are set and cleared by software. They select which extended GPIO input is connected to the input minus of COMP1, if INMSEL[2:0] = 111.

00: PA10

01: PA11

10: PA15

11: reserved

Bit 24 Reserved, must be kept at reset value.

Bit 23 SCALEN : voltage scaler enable

This bit is set and cleared by software. It enables outputs of the V _REFINTdivider available on the minus input of COMP1.

0: Bandgap scaler disabled (if SCALEN bit of COMP2_CSR register is also reset)

1: Bandgap scaler enabled

Bit 22 BRGEN : scaler bridge enable

This bit is set and cleared by software. It enables the bridge of the scaler.

If SCALEN is set and BRGEN is reset, the BG voltage reference is available but not 1/4 BGAP, 1/2 BGAP or 3/4 BGAP. The BGAP value is sent instead of 1/4 BGAP, 1/2 BGAP, 3/4 BGAP. If SCALEN and BRGEN are both set, 1/4 BGAP 1/2 BGAP 3/4 BGAP and BGAP voltage references are available.

0: Scaler resistor bridge disabled (if BRGEN bit of COMP2_CSR register is also reset)

1: Scaler resistor bridge enabled

Bit 21 Reserved, must be kept at reset value.

Bits 20:18 BLANKING[2:0] : COMP1 blanking source selection

These bits select which timer output controls the COMP1 output blanking.

000: No blanking

001: TIM1 OC5 selected as blanking source

010: TIM2 OC3 selected as blanking source

Others: reserved

Bits 17:16 HYST[1:0] : COMP1 hysteresis selection

These bits are set and cleared by software. They select the COMP1 hysteresis voltage.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : COMP1 polarity selection

This bit is set and cleared by software. It inverts COMP1 polarity.

0: COMP1 output value not inverted

1: COMP1 output value inverted

Bits 14:9 Reserved, must be kept at reset value.

Bits 8:7 INPSEL[1:0] : COMP1 input plus selection

These bits are set and cleared by software.

00: PB4

01: PB2

10: reserved

11: reserved

Bits 6:4 INMSEL[2:0] : COMP1 input minus selection

These bits are set and cleared by software. They select which input is connected to the input minus of COMP1.

000: 1/4 V _REFINT

001: 1/2 V _REFINT

000: 3/4 V _REFINT

011: V _REFINT

100: DAC channel1

101: reserved

110: PB3

111: GPIOx selected by INMESEL[1:0] bits

Bits 3:2 PWRMODE[1:0] : COMP1 power mode

These bits are set and cleared by software. They control the power and speed of COMP1.

00: High speed

01: Medium speed

10: Medium speed

11: Ultra low-power

Bit 1 Reserved, must be kept at reset value.

Bit 0 EN : COMP1 enable

This bit is set and cleared by software. It switches COMP1 on.

0: COMP1 switched off

1: COMP1 switched on

19.6.2 COMP2 control and status register (COMP2_CSR)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	INMESEL[1:0]		Res.	SCALEN	BRGEN	Res.	BLANKING[2:0]		HYST[1:0]
rs	r				rw	rw		rw	rw		rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	Res.	Res.	Res.	Res.	Res.	WINMODE	INPSEL[1:0]		INMSEL[2:0]			PWRMODE[1:0]		Res.	EN
rw						rw	rw	rw	rw	rw	rw	rw	rw		rw

Bit 31 LOCK : locks the whole content of the register, COMP2_CSR[31:0]

This bit is set by software and cleared by a hardware system reset.

0: COMP2_CSR[31:0] are read/write.

1: COMP2_CSR[31:0] are read-only.

Bit 30 VALUE : COMP2 output status bit

This bit is read-only. It reflects the current COMP2 output taking into account the effect of the POLARITY bit.

Bits 29:27 Reserved, must be kept at reset value.

Bits 26:25 INMESEL[1:0] : COMP2 input minus extended selection

These bits are set and cleared by software. They select which extended GPIO input is connected to the input minus of COMP2, if INMSEL[2:0] = 111.

00: PB2

01: PA10

10: PA11

11: reserved

Bit 24 Reserved, must be kept at reset value.

Bit 23 SCALEN : voltage scaler enable

This bit is set and cleared by software. It enables outputs of the V _REFINTdivider available on the minus input of COMP2.

0: Bandgap scaler disabled (if SCALEN bit of COMP1_CSR register is also reset)

1: Bandgap scaler enabled

Bit 22 BRGEN : scaler bridge enable

This bit is set and cleared by software. It enables the bridge of the scaler.

0: Scaler resistor bridge disabled (if BRGEN bit of COMP1_CSR register is also reset)

1: Scaler resistor bridge enabled

Bit 21 Reserved, must be kept at reset value.

Bits 20:18 BLANKING[2:0] : COMP2 blanking source selection

These bits select which timer output controls the COMP2 output blanking.

000: No blanking

001: TIM1 OC5 selected as blanking source

010: TIM2 OC3 selected as blanking source

Others: reserved

Bits 17:16 HYST[1:0] : COMP2 hysteresis selection

These bits are set and cleared by software. They select the COMP2 hysteresis voltage.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : COMP2 polarity selection

This bit is set and cleared by software. It inverts COMP2 polarity.

0: COMP2 output value not inverted

1: COMP2 output value inverted

Bits 14:10 Reserved, must be kept at reset value.

Bit 9 WINMODE : window mode selection

This bit is set and cleared by software. It selects the window mode of the comparators. If set, both positive inputs of comparators are connected together.

0: COMP2 input plus is not connected to COMP1.

1: COMP2 input plus is connected to COMP1.

Bits 8:7 INPSEL[1:0] : COMP2 input plus selection

These bits are set and cleared by software.

00: PB4

01: PB1

10: PA15

11: reserved

Bits 6:4 INMSEL[2:0] : COMP2 input minus selection

These bits are set and cleared by software. They select which input is connected to the input minus of COMP2.

000: 1/4 V _REFINT

001: 1/2 V _REFINT

000: 3/4 V _REFINT

011: V _REFINT

100: DAC channel1

101: reserved

110: PB3

111: GPIOx selected by INMESEL[1:0] bits

Bits 3:2 PWRMODE[1:0] : COMP2 power mode

These bits are set and cleared by software. They control the power and speed of COMP2.

00: High speed

01: Medium speed

10: Medium speed

11: Ultra low-power

Bit 1 Reserved, must be kept at reset value.

Bit 0 EN : COMP2 enable

This bit is set and cleared by software. It switches COMP2 on.

0: COMP2 switched off

1: COMP2 switched on

19.6.3 COMP register map

Table 116. COMP register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	COMP1_CSR	LOCK	VALUE	Res.	Res.	Res.	INMESEL[1:0]	Res.	SCALEN	BRGEN	Res.	BLANKING[2:0]			HYST[1:0]	POLARITY	Res.	Res.	Res.	Res.	Res.	Res.		INPSEL[1:0]			INMSEL[2:0]			PWRMODE[1:0]	Res.	EN
0x00	Reset value	0	0				0	0		0	0	0	0	0	0	0	0							0	0	0	0	0	0	0	0	0
0x04	COMP2_CSR	LOCK	VALUE	Res.	Res.	Res.	INMESEL[1:0]	Res.	SCALEN	BRGEN	Res.	BLANKING[2:0]			HYST[1:0]	POLARITY	Res.	Res.	Res.	Res.	Res.	Res.	WINMODE	INPSEL[1:0]			INMSEL[2:0]			PWRMODE[1:0]	Res.	EN
0x04	Reset value	0	0				0	0		0	0	0	0	0	0	0	0						0	0	0	0	0	0	0	0	0	0

Refer to Section 2.4 for the register boundary addresses.