13. Nested vectored interrupt controller (NVIC)

13.1 NVIC main features

• 62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt lines)
• 16 programmable priority levels (four bits of interrupt priority used)
• Low-latency exception interrupt handling
• Power management control
• Implementation of system control registers

The NVIC and the processor core interfaces are closely coupled, resulting in low-latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC.

For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for Cortex ^®-M4 (PM0214).

13.2 Interrupt and exception vectors

The vector table is given in Table 78 (shaded cells indicate the processor exceptions).

Table 78. Vector table

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾	Address
-	-	-	-	Reserved	0x0000 0000
-	-3	Fixed	Reset	Reset	0x0000 0004
-	-2	Fixed	NMI	Non maskable interrupt HSE32 CSS, flash ECC and SRAM2 parity	0x0000 0008
-	-1	Fixed	HardFault	All classes of fault	0x0000 000C
-	0	Settable	MemManager	Memory manager	0x0000 0010
-	1	Settable	BusFault	Prefetch fault, memory access fault	0x0000 0014
-	2	Settable	UsageFault	Undefined instruction or illegal state	0x0000 0018
-	-	-	-	Reserved	0x0000 001C 0x0000 0028
-	3	Settable	SVCall	System service call via SWI instruction	0x0000 002C
-	4	Settable	Debug	Debug monitor	0x0000 0030
-	-	-	-	Reserved	0x0000 0034
-	5	Settable	PendSV	Pendable request for system service	0x0000 0038
-	6	Settable	SysTick	SysTick timer	0x0000 003C
0	7	Settable	WWDG	Window watchdog early wake-up	0x0000 0040

Table 78. Vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾	Address
1	8	Settable	PVD, PVM[3]	PVD through EXTI[16] PVM[3] through EXTI[34]	0x0000 0044
2	9	Settable	TAMP, RTC_STAMP, LSE_CSS, RTC_SSRU	TAMP tamper RTC timestamp LSECSS interrupt RTC SSR underflow interrupt	0x0000 0048
3	10	Settable	RTC_WKUP	RTC wake-up interrupt	0x0000 004C
4	11	Settable	FLASH	Flash memory global interrupt and flash memory ECC single error interrupt	0x0000 0050
5	12	Settable	RCC	RCC global interrupt	0x0000 0054
6	13	Settable	EXTI0	EXTI line 0 interrupt through EXTI[0]	0x0000 0058
7	14	Settable	EXTI1	EXTI line 1 interrupt through EXTI[1]	0x0000 005C
8	15	Settable	EXTI2	EXTI line 2 interrupt through EXTI[2]	0x0000 0060
9	16	Settable	EXTI3	EXTI line 3 interrupt through EXTI[3]	0x0000 0064
10	17	Settable	EXTI4	EXTI line 4 interrupt through EXTI[4]	0x0000 0068
11	18	Settable	DMA1_CH1	DMA1 channel 1 non-secure interrupt	0x0000 006C
12	19	Settable	DMA1_CH2	DMA1 channel 2 non-secure interrupt	0x0000 0070
13	20	Settable	DMA1_CH3	DMA1 channel 3 non-secure interrupt	0x0000 0074
14	21	Settable	DMA1_CH4	DMA1 channel 4 non-secure interrupt	0x0000 0078
15	22	Settable	DMA1_CH5	DMA1 channel 5 non-secure interrupt	0x0000 007C
16	23	Settable	DMA1_CH6	DMA1 channel 6 non-secure interrupt	0x0000 0080
17	24	Settable	DMA1_CH7	DMA1 channel 7 non-secure interrupt	0x0000 0084
18	25	Settable	ADC	ADC global interrupt	0x0000 0088
19	26	Settable	DAC	DAC global interrupt	0x0000 008C
20	27	Settable	Reserved	Reserved	0x0000 0090
21	28	Settable	COMP	COMP2 and COMP1 interrupt through EXTI[22:21]	0x0000 0094
22	29	Settable	EXTI[9:5]	EXTI line [9:5] interrupt through EXTI[9:5]	0x0000 0098
23	30	Settable	TIM1_BRK	Timer 1 break interrupt	0x0000 009C
24	31	Settable	TIM1_UP	Timer 1 Update	0x0000 00A0
25	32	Settable	TIM1_TRG_COM	Timer 1 trigger and communication	0x0000 00A4
26	33	Settable	TIM1_CC	Timer 1 capture compare interrupt	0x0000 00A8
27	34	Settable	TIM2	Timer 2 global interrupt	0x0000 00AC
28	35	Settable	TIM16	Timer 16 global interrupt	0x0000 00B0
29	36	Settable	TIM17	Timer 17 global interrupt	0x0000 00B4
30	37	Settable	I2C1_EV	I2C1 event interrupt	0x0000 00B8

Table 78. Vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾	Address
31	38	Settable	I2C1_ER	I2C1 error interrupt	0x0000 00BC
32	39	Settable	I2C2_EV	I2C2 event interrupt	0x0000 00C0
33	40	Settable	I2C2_ER	I2C2 error interrupt	0x0000 00C4
34	41	Settable	SPI1	SPI1 global interrupt	0x0000 00C8
35	42	Settable	SPI2S2	SPI2S2 global interrupt	0x0000 00CC
36	43	Settable	USART1	USART1 global interrupt	0x0000 00D0
37	44	Settable	USART2	USART2 global interrupt	0x0000 00D4
38	45	Settable	LPUART1	LPUART1 global interrupt	0x0000 00D8
39	46	Settable	LPTIM1	LP timer 1 global interrupt	0x0000 00DC
40	47	Settable	LPTIM2	LP timer 2 global interrupt	0x0000 00E0
41	48	Settable	EXTI[15:10]	EXTI line [15:10] interrupt through EXTI[15:10]	0x0000 00E4
42	49	Settable	RTC_ALARM	RTC alarms A and B interrupt	0x0000 00E8
43	50	Settable	LPTIM3	LP timer 3 global interrupt	0x0000 00EC
44	51	Settable	Reserved	Reserved	0x0000 00F0
45	52	Settable	Reserved	Reserved	0x0000 00F4
46	53	Settable	Reserved	Reserved	0x0000 00F8
47	54	Settable	HSEM	Semaphore interrupt 0 to CPU	0x0000 00FC
48	55	Settable	I2C3_EV	I2C3 event interrupt	0x0000 0100
49	56	Settable	I2C3_ER	I2C3 error interrupt	0x0000 0104
50	57	Settable	Radio IRQ, Busy	Radio IRQs RFBUSY interrupt through EXTI[45]	0x0000 0108
51	58	Settable	AES	AES global interrupt	0x0000 010C
52	59	Settable	True RNG	True random number generator interrupt	0x0000 0110
53	60	Settable	PKA	Private key accelerator interrupt	0x0000 0114
54	61	Settable	DMA2_CH1	DMA2 channel 1 non-secure interrupt	0x0000 0118
55	62	Settable	DMA2_CH2	DMA2 channel 2 non-secure interrupt	0x0000 011C
56	63	Settable	DMA2_CH3	DMA2 channel 3 non-secure interrupt	0x0000 0120
57	64	Settable	DMA2_CH4	DMA2 channel 4 non-secure interrupt	0x0000 0124
58	65	Settable	DMA2_CH5	DMA2 channel 5 non-secure interrupt	0x0000 0128
59	66	Settable	DMA2_CH6	DMA2 channel 6 non-secure interrupt	0x0000 012C
60	67	Settable	DMA2_CH7	DMA2 channel 7 non-secure interrupt	0x0000 0130
61	68	Settable	DMAMUX1_OVR	DMAMUX1 overrun interrupt	0x0000 0134

1. EXTI[n] refer to the input event number [n] of the EXTI.