10. Peripherals interconnect matrix

10.1 Introduction

Several peripherals have direct connections between them, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently power consumption. In addition, these hardware connections remove software latency and result in more predictable system design.

Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1 and Stop 2 modes.

10.2 Connection summary

Table 65. STM32WLEx peripherals interconnect matrix ^{(1) (2)}

1. Numbers in this table are links to corresponding subsections of Section 10.3: Interconnection details .

2. The “-” symbol in grayed cells means no interconnect.

10.3 Interconnection details

10.3.1 From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)

Purpose

Some timers are linked together internally for synchronization or chaining.

When one timer is configured in Master mode, it can reset, start, stop or clock the counter of another timer configured in Slave mode. A description of the feature is provided in Section 23.3.26: Timer synchronization .

The synchronization modes are detailed in the following sections:

• • Section 23.3.26: Timer synchronization for advanced-control timers (TIM1)
• • Section 24.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2)

Triggering signals

The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The input and output signals for TIM1 are shown in Figure 114: Advanced-control timer block diagram .

The possible master/slave connections are given in tables below:

• • Table 168: TIM1 internal trigger connection for TIM1
• • Table 172: TIM2 internal trigger connection for TIM2

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.2 From timer (LPTIM1/LPTIM2) to timer (LPTIM3)

Purpose

Some timers are linked together internally for synchronization or chaining.

When one timer is configured in Master mode, it can reset, start, stop or clock the counter of another timer configured in Slave mode. A description of the feature is provided in Section 23.3.26: Timer synchronization .

Triggering signals

The output is on signals LPTIMx_OUT following a configurable timer event. The input (to slave) is on signals LPTIM3_ETR.

The input and output signals for LPTIM are shown in Figure 248: Low-power timer block diagram .

The possible connections are given in Table 183: LPTIM3 external trigger connections .

Active power modes

Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1

10.3.3 From timer (TIM1/TIM2) and GPIO pin EXTI to ADC/DAC

Purpose

Advanced-control timer TIM1, general-purpose timer TIM2 and GPIO pin EXTI can be used to generate an ADC/DAC trigger event.

TIMx synchronization is described in Section 23.3.27: ADC synchronization .

GPIO pin EXTI mux is described in Section 9: System configuration controller (SYSCFG) .

ADC synchronization is described in Section 16.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .

DAC synchronization is described in Section 17.4.7: DAC trigger selection .

Triggering signals

The output from timer is on signals TIMx_TRGO, TIMx_TRGO2, TIMx_CCx, TIMx_CHn event. The output from GPIO pin is on EXTI mux signal from SYSCFG.

The input to ADC is on signals TRG[7:0].

The connection between timers, GPIO pin EXTI mux and ADC, is provided in Table 90: External triggers .

The input to DAC is on signals dac_ch1_trg[15:0].

The connection between timers, GPIO pin EXTI mux and DAC, is provided in Table 102: DAC interconnection .

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.4 From timer (LPTIM1/LPTIM2) to DAC

Purpose

Low-power timer LPTIM1/LPTIM2 can be used to generate an DAC trigger event.

DAC triggering is described in Section 17.4.7: DAC trigger selection .

Triggering signals

The output from low-power timer is on signals LPTIMx_OUT event.

The input to DAC is on signals dac_ch1_trg[15:0].

The connection between timers and DAC is provided in Table 102: DAC interconnection .

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.5 From ADC to timer (TIM1)

Purpose

ADC can provide trigger event through watchdog signals to advanced-control timers (TIM1).

A description of the ADC analog watchdog setting is provided in Section 16.8.2: Analog watchdog .

Trigger settings on the timer are provided in Section 23.3.4: External trigger input .

Triggering signals

The output (from ADC) is on signals ADC_AWDx_OUT, x = 1, 2, 3 (3 watchdogs on ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.6 From HSE32, LSE, LSI, MSI, MCO, RTC to timers (TIM2/TIM16/TIM17)

Purpose

External clocks (HSE32, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wake-up interrupt can be used as input to general-purpose timers (TIM16/17) channel 1.

This makes possible calibration of the HSI16/MSI system clocks (with TIM16 and LSE) or of the LSI (with TIM16 and HSE32). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency.

When the low-speed external (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 6.2.20: Internal/external clock measurement with TIM16/TIM17 .

External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin (see TIM2 option register 1 (TIM2_OR1) ).

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.7 From RTC, TAMP, COMP1, COMP2 to low-power timers (LPTIM1/LPTIM2)

Purpose

RTC alarm A/B, TAMP_IN1/2/3 input detection and COMP1/2_OUT can be used as trigger to start LPTIM1/LPTIM2 counters.

Triggering signals

This trigger feature is described in Section 26.4.7: Trigger multiplexer (and following sections).

The input selection is described in Table 181: LPTIM1 external trigger connections and Table 182: LPTIM2 external trigger connections .

Active power modes

Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only)

10.3.8 From timer (TIM1/TIM2) to comparators (COMP1/COMP2)

Purpose

Advanced-control timer (TIM1) and general-purpose timer (TIM2) can be used as blanking window input to COMP1/COMP2.

The blanking function is described in Section 19.3.7: Comparator output blanking function .

The blanking sources are given in the following registers:

• • COMP1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0]
• • COMP2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0]

Triggering signals

Timer output signals TIMx_OCx are the inputs to blanking source of COMP1/COMP2.

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.9 From internal analog to ADC

Purpose

Internal temperature sensor ( \( V_{TS} \) ), Internal reference voltage ( \( V_{REFINT} \) ) and \( V_{BAT} \) monitoring channel are connected to ADC input channel.

This is according to the following sections:

• • Section 16.2: ADC main features
• • Section 16.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• • Section 16.9: Temperature sensor and internal reference voltage
• • Section 16.10: Battery voltage monitoring

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.10 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM16/TIM17)

Purpose

Comparators (COMP1/COMP2) output values can be connected to timers TIM1/TIM2/TIM16/TIM17 input captures or TIMx_ETR signals.

Comparators (COMP1/COMP2) output values can also generate break input signals for timer TIM1 on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of I/Os.

The possible connections are given in the following sections:

• • Section 23.4.23: TIM1 option register 1 (TIM1_OR1)
• • Section 23.4.28: TIM1 Alternate function register 2 (TIM1_AF2)
• • Section 24.4.22: TIM2 option register 1 (TIM2_OR1)
• • Section 24.4.23: TIM2 alternate function option register 1 (TIM2_AF1)
• • Section 25.4.21: TIM17 alternate function register 1 (TIM17_AF1)

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.11 From system errors to timers (TIM1/TIM16/TIM17)

Purpose

CSS, CPU hard fault, RAM parity error, FLASH ECC double error detection and PVD can generate system errors in the form of timer break toward timers (TIM1/TIM16/TIM17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

List of possible source of break are described in the following sections:

• • Section 23.3.16: Using the break function (TIM1)
• • Section 25.3.11: Using the break function (TIM16/TIM17)

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.12 From timers (TIM16/TIM17) to IRTIM

Purpose

General-purpose timer (TIM16/TIM17) output channels TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 27: Infrared interface (IRTIM) .

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.13 From timer (LPTIM1/LPTIM2/LPTIM3/GPIO pin EXTI) to DMAMUX1 trigger

Purpose

Low-power timers LPTIM1/LPTIM2/LPTIM3 and GPIO pin EXTI mux in SYSCFG, can be used to generate a DMAMUX1 trigger event.

GPIO pin EXTI mux is described in Section 9: System configuration controller (SYSCFG) .

DMAMUX1 triggering is described in Section 12.3.2: DMAMUX1 mapping .

Triggering signals

The output from low-power timer is on signals LPTIMx_OUT event. The output from GPIO pin is on EXTI mux signal from SYSCFG.

The input to DMAMUX1 is on signals trigger input [20:0].

The connection between timers, GPIO pin EXTI mux and DMAMUX1, is provided in Table 72: DMAMUX1: assignment of multiplexer inputs to resources .

Active power modes

Run, Sleep, LPRun, LPSleep

10.3.14 From timer (LPTIM3) to sub-GHz radio SPI NSS

Purpose

Low-power timer LPTIM3 can be used to generate a sub-GHz radio SPI NSS event.

Triggering signals

The output from low-power timer is on signal LPTIM3_OUT event.

The connection between timers and sub-GHz radio SPI NSS is provided in PWR sub-GHz SPI control register (PWR_SUBGHZSPICR) .

Active power modes

Run, Sleep, LPRun, LPSleep