8. General-purpose I/Os (GPIO)

8.1 GPIO introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and one 32-bit set/reset register (GPIOx_BSRR).

All GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2 GPIO main features

• • Output states: push-pull or open drain + pull-up/down
• • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)
• • Speed selection for each I/O
• • Input states: floating, pull-up/down, analog
• • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• • Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
• • Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• • Analog function
• • Alternate function selection registers
• • Fast toggle capable of changing every two clock cycles
• • Highly flexible pin multiplexing allowing the use of I/O pins as GPIOs or as one of several peripheral functions

8.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of GPIO ports can be individually configured by software in several modes listed below:

• • Input floating
• • Input pull-up
• • Input pull-down
• • Analog
• • Output open-drain with pull-up or pull-down capability
• • Output push-pull with pull-up or pull-down capability
• • Alternate function push-pull with pull-up or pull-down capability
• • Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers must be accessed as 32-bit words, half-words or bytes.

GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

Figure 30 and Figure 31 show the basic structure of a standard and a 5V-tolerant I/O port bit.

Table 59 gives the possible port bit configurations.

Figure 30. Basic structure of a standard I/O port bit

Figure 31. Basic structure of a 5V-tolerant I/O port bit

Table 59. Port bit configurations

Table 59. Port bit configurations (continued)

1. GP = general purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open drain, AF = alternate function.

8.3.1 General purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode.

The debug pins listed below are in AF pull-up/pull-down after reset:

• • PA15: JTDI in input mode with pull-up
• • PA14: JTCK/SWCLK in input mode with pull-down
• • PA13: JTMS/SWDAT in input mode with pull-up
• • PB4: NJTRST in input mode with pull-up
• • PB3: JTDO in HI-Z mode no pulls.

PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading phase (see Section 8.3.15: Using PH3 as GPIO ).

When the I/O pin is configured as output, the value written to the output data register GPIOx_ODR is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z).

The input data register GPIOx_IDR captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

8.3.2 I/O pin alternate function multiplexer and mapping

The I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one AF peripheral connected to each I/O pin at a time. This avoids conflict between peripherals available on the same I/O pin.

Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15), that can be configured through the registers GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15):

After reset, the multiplexer selection is alternate function 0 (AF0). I/Os are configured in alternate function mode through GPIOx_MODER register.

Specific alternate function assignments for each pin are detailed in the product datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped on different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, the user must proceed as follows:

• • Debug function

After each device reset, these pins are assigned as alternate function pins immediately usable by the debugger host.

• • GPIO

Configure the desired I/O as output, input or analog in the GPIOx_MODER register.

• • Peripheral alternate function

• – Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register.
• – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively.
• – Configure the desired I/O as an alternate function in the GPIOx_MODER register.

• • Additional functions

• – For ADC, DAC and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC and COMP registers.
• – For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers.

Refer to the “Alternate function mapping” table in the product datasheet for the detailed mapping of the alternate function I/O pins.

8.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR) to configure up to sixteen I/Os.

GPIOx_MODER is used to select the I/O mode (input, output, AF or analog).

GPIOx_OTYPER and GPIOx_OSPEEDR are used to select the output type (push-pull or open-drain) and speed.

GPIOx_PUPDR is used to select the pull-up/pull-down whatever the I/O direction.

8.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped input and output data registers: GPIOx_IDR and GPIOx_ODR.

GPIOx_ODR stores the data to be output, it is read/write accessible.

Data input through the I/O are stored into GPIOx_IDR, it is a read-only register.

8.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register that allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). GPIOx_BSRR has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR correspond two control bits in GPIOx_BSRR, BS(i) and BR(i):

• • When written to 1, BS(i) sets the corresponding ODR(i) bit.
• • When written to 1, BR(i) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using GPIOx_BSRR to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. GPIOx_BSRR provides a way of performing atomic bitwise handling.

There is no software need to disable interrupts when programming GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

8.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. Frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write GPIOx_LCKR, a specific write/read sequence must be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the I/Os configuration (during the write sequence, LCKR[15:0] value must be the same).

When the LOCK sequence is applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset.

Each GPIOx_LCKR bit freezes the corresponding bit in the control registers GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

The LOCK sequence can only be performed using a word (32-bit long) access to GPIOx_LCKR due to the fact that GPIOx_LCKR bit 16 must be set at the same time as the [15:0] bits.

8.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for each I/O: GPIOx_AFRL and GPIOx_AFRH.

With these registers, the user can connect an alternate function to some other pin as required by the application. This means that a number of possible peripheral functions are multiplexed on each GPIO. The application can thus select any one of the possible functions for each I/O.

The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.

To know which functions are multiplexed on each GPIO pin, refer to the product datasheet.

8.3.8 External interrupt/wake-up lines

All ports have external interrupt capability.

To use external interrupt lines, the port must be configured in input mode.

Refer to Section 14.4.1: EXTI configurable event input wake-up .

8.3.9 Input configuration

When the I/O port is programmed as input, the following occurs:

• • The output buffer is disabled.
• • The Schmitt trigger input is activated.
• • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register.
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle.
• • A read access to the input data register provides the I/O state.

The figure below shows the input configuration of the I/O port bit.

Figure 32. Input floating/pull-up/pull-down configurations

8.3.10 Output configuration

When the I/O port is programmed as output, the following occurs:

• • The output buffer is enabled:
  • – Open drain mode: A 0 in the Output register activates the N-MOS whereas a 1 in the Output register leaves the port in Hi-Z (the P-MOS is never activated).
  • – Push-pull mode: A 0 in the Output register activates the N-MOS whereas a 1 in the Output register activates the P-MOS.
• • The Schmitt trigger input is activated.
• • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register.
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle.
• • A read access to the input data register gets the I/O state.
• • A read access to the output data register gets the last written value.

The figure below shows the output configuration of the I/O port bit.

Figure 33. Output configuration

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function, the following occurs:

• • The output buffer can be configured in open-drain or push-pull mode.
• • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data).
• • The Schmitt trigger input is activated.
• • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register.
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle.
• • A read access to the input data register gets the I/O state.

The figure below shows the alternate function configuration of the I/O port bit.

Figure 34. Alternate function configuration

8.3.12 Analog configuration

When the I/O port is programmed as analog configuration, the following occurs:

• • The output buffer is disabled.
• • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• • The weak pull-up and pull-down resistors are disabled by hardware.
• • Read access to the input data register gets the value 0.

The figure below shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 35. High impedance analog configuration

8.3.13 Using the LSE oscillator pins as GPIOs

When the LSE oscillator is switched off (default state after reset), the related oscillator pins can be used as normal GPIOs.

When the LSE oscillator is switched on (by setting the LSEON bit in the RCC_CSR register), the oscillator takes the control of its associated pins and the GPIO configuration of these pins has no effect.

When the oscillator is configured in a user external clock mode, only the OSC32_IN pin is reserved for clock input and the OSC32_OUT pin can still be used as normal GPIO.

Note: The HSE32 OSC_IN and OSC_OUT pins are dedicated oscillator pins and cannot be used as GPIO.

8.3.14 Using the GPIO pins in the RTC supply domain

GPIO functionality of PC13, PC14 and PC15 is lost when the core supply domain is powered off (device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode.

For details about I/O control by the RTC, refer to Section 30: Real-time clock (RTC) .

8.3.15 Using PH3 as GPIO

PH3 may be used as boot pin (BOOT0) or as GPIO.

PH3 switches from the input mode to the analog input mode depending on the nSWBOOT0 bit in the user option byte as follows:

• • After the option byte loading phase if nSWBOOT0 = 1.
• • After reset if nSWBOOT0 = 0.

8.4 GPIO registers

This section gives a detailed description of the GPIO registers for GPIOx port, with x = A to C and x = H.

For a summary of register bits, register address offsets and reset values, refer to Table 60 to Table 63 .

The peripheral registers can be written in word, half word or byte mode.

8.4.1 GPIOx mode register (GPIOx_MODER) (x = A to B)

Address offset: Block A: 0x0000

Address offset: Block B: 0x0400

Reset value: Block A: 0xABFF FFFF

Reset value: Block B: 0xFFFF FEBF

Bits 31:0 MODEy[1:0] : Port Pxy I/O type configuration (y = 15 to 0)

These bits are written by software to configure the I/O mode.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

8.4.2 GPIOx output type register (GPIOx_OTYPER) (x = A to B)

Address offset: Block A: 0x0004

Address offset: Block B: 0x0404

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OTy : Port Pxy output type configuration (y = 15 to 0)

These bits are written by software to configure the I/O output type.

0: Output push-pull (reset state)

1: Output open-drain

8.4.3 GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B)

Address offset: Block A: 0x0008

Address offset: Block B: 0x0408

Reset value: Block A: 0x0C00 0000

Reset value: Block B: 0x0000 00C0

Bits 31:0 OSPEEDy[1:0] : Port Pxy output speed configuration (y = 15 to 0)

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: Fast speed

11: High speed

Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.

8.4.4 GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B)

Address offset: Block A: 0x000C

Address offset: Block B: 0x040C

Reset value: Block A: 0x6400 0000

Reset value: Block B: 0x0000 0100

Bits 31:0 PUPDy[1:0] : Port Pxy pull configuration (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

8.4.5 GPIOx input data register (GPIOx_IDR) (x = A to B)

Address offset: Block A: 0x0010

Address offset: Block B: 0x0410

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDy : Port Pxy input data bit (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.

8.4.6 GPIOx output data register (GPIOx_ODR) (x = A to B)

Address offset: Block A: 0x0014

Address offset: Block B: 0x0414

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODy : Port Pxy output data (y = 15 to 0)

These bits can be read and written by software.

Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the GPIOx_BSRR and GPIOx_BRR registers.

8.4.7 GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B)

Address offset: Block A: 0x0018

Address offset: Block B: 0x0418

Reset value: 0x0000 0000

Bits 31:16 BRy : Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)

These bits are read clear-write 1. A read to these bits returns the value 0x0000.

0: No action on the corresponding GPIOx_ODR.OD[y] bit

1: Resets the corresponding GPIOx_ODR.OD[y] bit.

Note: If both BSy and BRy are set, BSy has priority.

Bits 15:0 BSy : Port Pxy set output data bit [15:0] in GPIOx_ODR (y = 15 to 0)

These bits are read clear-write 1. A read to these bits returns the value 0x0000.

0: No action on the corresponding GPIOx_ODR.OD[y] bit

1: Sets the corresponding GPIOx_ODR.OD[y] bit.

8.4.8 GPIOx configuration lock register (GPIOx_LCKR) (x = A to B)

Address offset: Block A: 0x001C

Address offset: Block B: 0x041C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to GPIOx_LCKR. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK : Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset.

LOCK key write sequence:

WR \( LCKR[16] = 1 + LCKR[15:0] \)

WR \( LCKR[16] = 0 + LCKR[15:0] \)

WR \( LCKR[16] = 1 + LCKR[15:0] \)

RD LCKR

RD \( LCKR[16] = 1 \) (This read operation is optional but it confirms that the lock is active.)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

Bits 15:0 LCKy : Port Px[15:0] lock configuration (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is 0.

0: Port Pxy configuration not locked

1: Port Pxy configuration locked

8.4.9 GPIOx alternate function low register (GPIOx_AFRL) (x = A to B)

Address offset: Block A: 0x0020

Address offset: Block B: 0x0420

Reset value: 0x0000 0000

Bits 31:0 AFSELY[3:0] : Port Pxy alternate function selection (y = 7 to 0)

These bits are written by software to configure alternate function I/Os

0x0: AF0 selected

0x1: AF1 selected

0x2: AF2 selected

...

0xE: AF14 selected

0xF: AF15 selected

8.4.10 GPIOx alternate function high register (GPIOx_AFRH) (x = A to B)

Address offset: Block A: 0x0024

Address offset: Block B: 0x0424

Reset value: 0x0000 0000

Bits 31:0 AFSELY[3:0] : Port Pxy alternate function selection (y = 15 to 8)

These bits are written by software to configure alternate function I/Os

0x0: AF0 selected

0x1: AF1 selected

0x2: AF2 selected

...

0xE: AF14 selected

0xF: AF15 selected

8.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B)

Address offset: Block A: 0x0028

Address offset: Block B: 0x0428

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BRy : Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)

These bits are read clear-write 1. A read to these bits returns the value 0x0000.

0: No action on the corresponding GPIOx_ODR.OD[y] bit

1: Resets the corresponding GPIOx_ODR.OD[y] bit.

8.4.12 GPIOC mode register (GPIOC_MODER)

Address offset: 0x0800

Reset value: 0xFC00 3FFF

Bits 31:30 MODE15[1:0] : Port PC15 IO type configuration

Bits 29:28 MODE14[1:0] : Port PC14 IO type configuration

Bits 27:26 MODE13[1:0] : Port PC13 IO type configuration

Bits 25:14 Reserved, must be kept at reset value.

Bits 13:12 MODE6[1:0] : Port PC6 IO type configuration

Bits 11:10 MODE5[1:0] : Port PC5 IO type configuration

Bits 9:8 MODE4[1:0] : Port PC4 IO type configuration

Bits 7:6 MODE3[1:0] : Port PC3 IO type configuration

Bits 5:4 MODE2[1:0] : Port PC2 IO type configuration

Bits 3:2 MODE1[1:0] : Port PC1 IO type configuration

Bits 1:0 MODE0[1:0] : Port PC0 IO type configuration

These bits are written by software to configure the I/O mode.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

8.4.13 GPIOC output type register (GPIOC_OTYPER)

Address offset: 0x0804

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 OTy : Port PCy output type configuration (y = 15 to 13)

These bits are written by software to configure the I/O output type.

0: Output push-pull (reset state)

1: Output open-drain

Bits 12:7 Reserved, must be kept at reset value.

Bits 6:0 OTy : Port PCy output type configuration (y = 6 to 0)

8.4.14 GPIOC output speed register (GPIOC_OSPEEDR)

Address offset: 0x0808

Reset value: 0x0000 0000

Bits 31:30 OSPEED15[1:0] : Port PC15 output speed configuration

Bits 29:28 OSPEED14[1:0] : Port PC14 output speed configuration

Bits 27:26 OSPEED13[1:0] : Port PC13 output speed configuration

Bits 25:14 Reserved, must be kept at reset value.

Bits 13:12 OSPEED6[1:0] : Port PC6 output speed configuration

Bits 11:10 OSPEED5[1:0] : Port PC5 output speed configuration

Bits 9:8 OSPEED4[1:0] : Port PC4 output speed configuration

Bits 7:6 OSPEED3[1:0] : Port PC3 output speed configuration

Bits 5:4 OSPEED2[1:0] : Port PC2 output speed configuration

Bits 3:2 OSPEED1[1:0] : Port PC1 output speed configuration

Bits 1:0 OSPEED0[1:0] : Port PC0 output speed configuration

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: Fast speed

11: High speed

Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.

8.4.15 GPIOC pull-up/pull-down register (GPIOC_PUPDR)

Address offset: 0x080C

Reset value: 0x0000 0000

Bits 31:30 PUPD15[1:0] : Port PC15 pull configuration

Bits 29:28 PUPD14[1:0] : Port PC14 pull configuration

Bits 27:26 PUPD13[1:0] : Port PC13 pull configuration

Bits 25:14 Reserved, must be kept at reset value.

Bits 13:12 PUPD6[1:0] : Port PC6 pull configuration

Bits 11:10 PUPD5[1:0] : Port PC5 pull configuration

Bits 9:8 PUPD4[1:0] : Port PC4 pull configuration

Bits 7:6 PUPD3[1:0] : Port PC3 pull configuration

Bits 5:4 PUPD2[1:0] : Port PC2 pull configuration

Bits 3:2 PUPD1[1:0] : Port PC1 pull configuration

Bits 1:0 PUPD0[1:0] : Port PC0 pull configuration

These bits are written by software to configure the I/O pull-up or pull-down.

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

8.4.16 GPIOC input data register (GPIOC_IDR)

Address offset: 0x0810

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 IDy : Port PCy input data bit (y = 15 to 13)

These bits are read-only. They contain the input value of the corresponding I/O port.

Bits 12:7 Reserved, must be kept at reset value.

Bits 6:0 IDy : Port PCy input data bit (y = 6 to 0)

8.4.17 GPIOC output data register (GPIOC_ODR)

Address offset: 0x0814

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 ODy : Port PCy output data bit (y = 15 to 13)

These bits can be read and written by software.

Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the GPIOC_BSRR and GPIOC_BRR registers.

Bits 12:7 Reserved, must be kept at reset value.

Bits 6:0 ODy : Port PCy output data bit (y = 6 to 0)

8.4.18 GPIOC bit set/reset register (GPIOC_BSRR)

Address offset: 0x0818

Reset value: 0x0000 0000

Bits 31:29 BRy : Port PCy reset output data bit [y] in GPIOC_ODR (y = 15 to 13)

These bits are read clear-write 1. A read to these bits returns the value 0.

0: No action on the corresponding GPIOC_ODR.OD0

1: Resets the corresponding GPIOC_ODR.OD0.

Note: If both BS0 and BR0 are set, BS0 has priority.

Bits 28:23 Reserved, must be kept at reset value.

Bits 22:16 BRy : Port PCy reset output data bit [y] in GPIOC_ODR (y = 6 to 0)

Bits 15:13 BSy : Port PCy set output data bit [y] in GPIOC_ODR (y = 15 to 13)

These bits are read clear-write 1. A read to these bits returns the value 0.

0: No action on the corresponding GPIOC_ODR.OD0

1: Resets the corresponding GPIOC_ODR.OD0.

Note: If both BS0 and BR0 are set, BS0 has priority.

Bits 12:7 Reserved, must be kept at reset value.

Bits 6:0 BSy : Port PCy set output data bit [y] in GPIOC_ODR (y = 6 to 0)

8.4.19 GPIOC configuration lock register (GPIOC_LCKR)

Address offset: 0x081C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to the GPIOC_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Bits 31:17 Reserved, must be kept at reset value.

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port PC configuration lock key not active

1: Port PC configuration lock key active. GPIOC_LCKR is locked until the next MCU reset or peripheral reset.

LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

RD LCKR

RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

This bit is read/write but can only be written when the LCKK bit is 0.

0: Port PCy configuration not locked

1: Port PCy configuration locked

Bits 12:7 Reserved, must be kept at reset value.

Bits 6:0 LCKy : Port PCy lock configuration (y = 6 to 0)

8.4.20 GPIOC alternate function low register (GPIOC_AFRL)

Address offset: 0x0820

Reset value: 0x0000 0000

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 AFSEL6[3:0] : Port PC6 alternate function selection

Bits 23:20 AFSEL5[3:0] : Port PC5 alternate function selection

Bits 19:16 AFSEL4[3:0] : Port PC4 alternate function selection

Bits 15:12 AFSEL3[3:0] : Port PC3 alternate function selection

Bits 11:8 AFSEL2[3:0] : Port PC2 alternate function selection

Bits 7:4 AFSEL1[3:0] : Port PC1 alternate function selection

Bits 3:0 AFSEL0[3:0] : Port PC0 alternate function selection

These bits are written by software to configure alternate function I/Os.

0x0: AF0 selected

0x1: AF1 selected

0x2: AF2 selected

...

0xE: AF14 selected

0xF: AF15 selected

8.4.21 GPIOC alternate function high register (GPIOC_AFRH)

Address offset: 0x0824

Reset value: 0x0000 0000

Bits 31:28 AFSEL15[3:0] : Port PC15 alternate function selection

Bits 27:24 AFSEL14[3:0] : Port PC14 alternate function selection

Bits 23:20 AFSEL13[3:0] : Port PC13 alternate function selection

These bits are written by software to configure alternate function I/Os.

0x0: AF0 selected

0x1: AF1 selected

0x2: AF2 selected

...

0xE: AF14 selected

0xF: AF15 selected

Bits 19:0 Reserved, must be kept at reset value.

8.4.22 GPIOC bit reset register (GPIOC_BRR)

Address offset: 0x0828

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 BRy : Port PCy reset output data bit [15] in GPIOC_ODR (y = 15 to 13)

These bits are read clear-write 1. A read to this bit returns the value 0.

0: No action on the corresponding GPIOC_ODR.OD0

1: Resets the corresponding GPIOC_ODR.OD0.

Bits 12:7 Reserved, must be kept at reset value.

Bits 6:0 BRy : Port PCy reset output data bit [6] in GPIOC_ODR (y = 6 to 0)

8.4.23 GPIOH mode register (GPIOH_MODER)

Address offset: 0x1C00

Reset value: 0x0000 00C0

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:6 MODE3[1:0] : Port PH3 IO type configuration

These bits are written by software to configure the I/O mode.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

Bits 5:0 Reserved, must be kept at reset value.

8.4.24 GPIO H output type register (GPIOH_OTYPER)

Address offset: 0x1C04

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 OT3 : Port PH3 output type configuration

These bits are written by software to configure the I/O output type.

0: Output push-pull (reset state)

1: Output open-drain

Bits 2:0 Reserved, must be kept at reset value.

8.4.25 GPIOH output speed register (GPIOH_OSPEEDR)

Address offset: 0x1C08

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:6 OSPEED3[1:0] : Port PH3 output speed configuration

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: Fast speed

11: High speed

Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed.

Bits 5:0 Reserved, must be kept at reset value.

8.4.26 GPIOH pull-up/pull-down register (GPIOH_PUPDR)

Address offset: 0x1C0C

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:6 PUPD3[1:0] : Port PH3 pull configuration

These bits are written by software to configure the I/O pull-up or pull-down.

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

Bits 5:0 Reserved, must be kept at reset value.

8.4.27 GPIOH input data register (GPIOH_IDR)

Address offset: 0x1C10

Reset value: 0x0000 000X

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ID3 : Port PH3 input data bit

This bit is read-only. It contains the input value of the corresponding I/O port.

Bits 2:0 Reserved, must be kept at reset value.

8.4.28 GPIOH output data register (GPIOH_ODR)

Address offset: 0x1C14

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 OD3 : Port PH3 output data

This bit can be read and written by software.

Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the GPIOH_BSRR and GPIOH_BRR registers.

Bits 2:0 Reserved, must be kept at reset value.

8.4.29 GPIO H bit set/reset register (GPIOH_BSRR)

Address offset: 0x1C18

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 BR3 : Port PH3 reset output data bit [3] in GPIOH_ODR

This bit is read clear-write 1. A read to this bit returns the value 0.

0: No action on the corresponding GPIOH_ODR.OD3

1: Resets the corresponding GPIOH_ODR.OD3.

Note: If both BS3 and BR3 are set, BS3 has priority.

Bits 18:4 Reserved, must be kept at reset value.

Bit 3 BS3 : Port PH3 set output data bit [3] in GPIOH_ODR

This bit is read clear-write 1. A read to this bit returns the value 0.

0: No action on the corresponding GPIOH_ODR.OD3

1: Sets the corresponding GPIOH_ODR.OD3.

Bits 2:0 Reserved, must be kept at reset value.

8.4.30 GPIOH configuration lock register (GPIOH_LCKR)

Address offset: 0x1C1C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to the GPIOH_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK : Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port PH configuration lock key not active

1: Port PH configuration lock key active. GPIOH_LCKR is locked until the next MCU reset or peripheral reset.

LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

RD LCKR

RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

Bits 15:4 Reserved, must be kept at reset value.

Bit 3 LCK3 : Port PH3 lock configuration

This bit is read/write but can only be written when the LCKK bit is 0.

0: Port PH3 configuration not locked

1: Port PH3 configuration locked

Bits 2:0 Reserved, must be kept at reset value.

8.4.31 GPIOH alternate function low register (GPIOH_AFRL)

Address offset: 0x1C20

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 AFSEL3[3:0] : Port PH3 alternate function selection

These bits are written by software to configure alternate function I/Os.

0x0: AF0 selected

0x1: AF1 selected

0x2: AF2 selected

...

0xE: AF14 selected

0xF: AF15 selected

Bits 11:0 Reserved, must be kept at reset value.

8.4.32 GPIOH bit reset register (GPIOH_BRR)

Address offset: 0x1C28

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 BR3 : Port PH3 reset output data bit [3] in GPIOH_ODR

This bit is read clear-write 1. A read to this bit returns the value 0.

0: No action on the corresponding GPIOH_ODR.OD3

1: Resets the corresponding GPIOH_ODR.OD3.

Bits 2:0 Reserved, must be kept at reset value.

8.4.33 GPIOA register map

Table 60. GPIOA register map and reset values

Table 60. GPIOA register map and reset values (continued)

Refer to Section 2.4 for the register boundary addresses.

8.4.34 GPIOB register map

Table 61. GPIOB register map and reset values

Table 61. GPIOB register map and reset values (continued)

Refer to Section 2.4 for the register boundary addresses.

8.4.35 GPIOC register map

Table 62. GPIOC register map and reset values

Table 62. GPIOC register map and reset values (continued)

Refer to Section 2.4 for the register boundary addresses.

8.4.36 GPIOH register map

Table 63. GPIOH register map and reset values

Refer to Section 2.4 for the register boundary addresses.