2. Memory and bus architecture

The following definition is used in this section:

• • CPU = Arm Cortex-M4 with MPU and DSP

2.1 System architecture

The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the following masters and slaves:

• • Five masters:
  • – CPU core I-bus
  • – CPU core D-bus
  • – CPU core S-bus
  • – DMA1
  • – DMA2
• • Eight slaves:
  • – Internal flash memory on the CPU Code bus
  • – Internal flash memory on CPU DCode bus
  • – Internal SRAM1 (up to 32 Kbytes, size depending on the device, refer to the datasheet)
  • – Internal SRAM2 (up to 32 Kbytes, size depending on the device, refer to the datasheet)
  • – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2)
  • – AHB2 peripherals
  • – AHB3 peripherals including AHB to APB bridges and APB peripherals (connected to APB3)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously.

This architecture is shown in the figure below.

Figure 1. System architecture

2.1.1 S0: CPU I-bus

This bus connects the instruction bus of the CPU core to the bus matrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal flash memory, SRAM1 and SRAM2.

2.1.2 S1: CPU D-bus

This bus connects the data bus of the CPU core to the bus matrix. This bus is used by the core for literal load and debug access. The targets of this bus are the internal flash memory, SRAM1 and SRAM2.

2.1.3 S2: CPU S-bus

This bus connects the system bus of the CPU core to the bus matrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the SRAM1, SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3.

2.1.4 S4, S5: DMA-bus

These buses connect the AHB master interface of the DMAs to the bus matrix. The targets of this bus are the internal flash memory, SRAM1, SRAM2 the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3 peripherals.

AHB/APB bridges

The two bridges AHB to APB1 and AHB to APB2 provide full synchronous connections between the AHB1 and the two APB buses, allowing flexible selection of the peripheral frequency.

The bridge AHB to APB3 provides full synchronous connections between the AHB and the APB bus, allowing flexible selection of the frequency between the AHB and peripherals.

Refer to Section 2.4.2: Memory map and register boundary addresses for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled, except for the SRAM1/2 and the flash memory interface. Before using a peripheral, its clock must be enabled in the RCC_AHBxENR and RCC_APBxENR registers.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Boot configuration

Three different CPU boot modes can be selected through the BOOT0 pin and nBOOT1 bit in the user options.

Boot is furthermore conditioned by the CPU boot lock enable and the user flash memory empty check, as shown in the table below.

Table 1. Device boot mode

Table 1. Device boot mode (continued)

Values on BOOT0 and BOOT1 are latched after a reset. It is up to the user to provide the correct value for the required boot mode.

BOOT0 and BOOT1 are also re-sampled when exiting Standby mode. Consequently they must be kept in the required boot mode. After the startup delay, the CPU fetches the top-of-stack from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, main flash memory, system flash memory and SRAM1 are accessible as follows:

• • Boot from main flash memory

The main flash memory is aliased in the CPU boot memory space at address 0x0000 0000 and is also still accessible from its physical address 0x0800 0000. In other words, the flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.

• • Boot from system flash memory

The system flash memory is aliased in the CPU boot memory space at address 0x0000 0000 and is also still accessible from its physical address 0x1FFF 0000.

• • Boot from SRAM memory

The SRAM memory is aliased in the CPU boot memory space at address 0x0000 0000 and is also still accessible from its physical address 0x2000 0000.

CPU SRAM physical remap

Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.

The following memories can be remapped:

• • Main flash memory
• • System flash memory
• • SRAM memory

Embedded bootloader

The embedded bootloader is located in the system flash memory, programmed by STMicroelectronics during production. It is used to program the flash memory using one of the following device interfaces:

• • USART1 on pins PA9 and PA10
• • USART2 on pins PA2 and PA3
• • SPI1 on pins PA4, PA5, PA6 and PA7
• • SPI2S2 on pins PB12, PB13, PB14 and PB15

The embedded bootloader runs on the CPU and can be used to load content in memory areas.

2.3 SRAM erase

SRAM1, SRAM2 and PKA SRAM provide an SRAM erase feature.

These SRAMs are erased under the conditions detailed in the table below.

Table 2. SRAM erase conditions

1. An ongoing SRAM1 or SRAM2 erase can be monitored by SYSCFG_SCSR.SRAMBSY flag.

2. An ongoing PKA SRAM erase can be monitored by SYSCFG_SCSR.PKASRAMBSY flag.

3. POR, NRST, and wake-up from Standby.

4. For more details, see Table 12: RDP regression from level 1 to level 0 and memory erase .

5. To be able to debug without SRAM erase on tamper, especially ITAM6 debug access, the tamper erase must be disabled in the TAMP by firmware.

2.4 Memory organization

2.4.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.4.2 Memory map and register boundary addresses

Figure 2. Memory map

Any memory area not allocated to on-chip memories and peripherals is considered "Reserved".

The table below details the boundary addresses of peripherals available in the device.

Table 3. Memory map and peripheral register boundary addresses

Table 3. Memory map and peripheral register boundary addresses (continued)

Table 3. Memory map and peripheral register boundary addresses (continued)

1. Size depending on the device. Refer to the datasheet for more details.

2. Bus depends on the selected CPU boot area.

2.4.3 CPU bit banding

The CPU map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

The AHB1, APB1, APB2 peripheral registers and the SRAM1 and SRAM2 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The operations are only available for CPU accesses and not from other bus masters (such as DMA).

The peripheral bit-band alias is located from address 0x4200 0000 to 0x425F FFFF.

The SRAM bit-band alias is located from address 0x2200 0000 to 0x221F FFFF.

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region.

The mapping formula is the following:

where:

• • bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
• • bit_band_base is the starting address of the alias region.
• • byte_offset is the number of the byte in the bit_band region that contains the targeted bit.
• • bit_number is the bit position (0-7) of the targeted bit.

Example

The following example shows how to map bit [2] of the byte located at SRAM1 address 0x2000 0300 to the alias region. The formula is then:

Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit [2] of the byte at SRAM1 address 0x2000 0300.

Reading address 0x2200 6008 returns the value 0x01 or 0x00 of bit [2] of the byte at SRAM1 address 0x2000 0300.

For more information on bit-band, refer to the Cortex-M4 programming manual.