RM0461-STM32WLEx

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WLE x microcontrollers memory and peripherals.

STM32WLE x MCUs with integrated sub-GHz radio operating in the 150 - 960 MHz ISM band, belong to a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M4 core, refer to the corresponding Arm ® Technical Reference Manuals available on http://infocenter.arm.com .

STM32WLE x microcontrollers include ST state-of-the-art patented technology.

For information on the device errata with respect to the datasheet and reference manual, refer to the STM32WLE5 x STM32WLE4 x errata sheet (ES0506).

Contents

3.4.1Option bytes description .....82
3.4.2Option bytes programming .....82
3.5Flash memory protection .....85
3.5.1Readout protection (RDP) .....85
3.5.2Proprietary code readout protection (PCROP) .....88
3.5.3Write protection (WRP) .....89
3.5.4Security (ESE) .....90
3.5.5CPU boot lock chain of trust .....90
3.6FLASH program erase suspension .....91
3.7FLASH interrupts .....91
3.8FLASH registers .....92
3.8.1FLASH access control register (FLASH_ACR) .....92
3.8.2FLASH key register (FLASH_KEYR) .....93
3.8.3FLASH option key register (FLASH_OPTKEYR) .....93
3.8.4FLASH status register (FLASH_SR) .....93
3.8.5FLASH control register (FLASH_CR) .....96
3.8.6FLASH ECC register (FLASH_ECCR) .....97
3.8.7FLASH option register (FLASH_OPTR) .....98
3.8.8FLASH PCROP zone A start address register
(FLASH_PCROP1ASR) .....		100
3.8.9FLASH PCROP zone A end address register
(FLASH_PCROP1AER) .....		101
3.8.10FLASH WRP area A address register (FLASH_WRP1AR) .....101
3.8.11FLASH WRP area B address register (FLASH_WRP1BR) .....102
3.8.12FLASH PCROP zone B start address register
(FLASH_PCROP1BSR) .....		103
3.8.13FLASH PCROP zone B end address register
(FLASH_PCROP1BER) .....		103
3.8.14FLASH register map .....104
4Sub-GHz radio (SUBGHZ) .....106
4.1Sub-GHz radio introduction .....106
4.2Sub-GHz radio main features .....106
4.3Sub-GHz radio functional description .....107
4.3.1General description .....107
4.3.2Sub-GHz radio signals .....107
4.3.3Transmitter .....108
4.9Sub-GHz radio application configuration . . . . .156
4.9.1Basic sequence for LoRa, (G)MSK and (G)FSK transmit operation . . .156
4.9.2Basic sequence for LoRa and (G)FSK receive operation . . . . .157
4.9.3Basic sequence for BPSK transmit operation . . . . .158
4.10Sub-GHz radio registers . . . . .158
4.10.1Sub-GHz radio ramp-up MSB register (SUBGHZ_RAM_RAMPUPH) . . .158
4.10.2Sub-GHz radio ramp-up LSB register (SUBGHZ_RAM_RAMPUPL) . . .159
4.10.3Sub-GHz radio ramp-down MSB register
(SUBGHZ_RAM_RAMPDNH) . . . . .		159
4.10.4Sub-GHz radio ramp-down LSB register
(SUBGHZ_RAM_RAMPDNL) . . . . .		159
4.10.5Sub-GHz radio frame limit MSB register
(SUBGHZ_RAM_FRAMELIMH) . . . . .		159
4.10.6Sub-GHz radio frame limit LSB register
(SUBGHZ_RAM_FRAMELIML) . . . . .		160
4.10.7Sub-GHz radio generic bit synchronization register
(SUBGHZ_GBSYNCR) . . . . .		160
4.10.8Sub-GHz radio generic CFO MSB register (SUBGHZ_GCFORH) . . .160
4.10.9Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL) . . . .161
4.10.10Sub-GHz radio generic packet control 1 register
(SUBGHZ_GPKTCTL1R) . . . . .		161
4.10.11Sub-GHz radio generic packet control 1A register
(SUBGHZ_GPKTCTL1AR) . . . . .		161
4.10.12Sub-GHz radio generic whitening LSB register
(SUBGHZ_GWHITEINIRL) . . . . .		162
4.10.13Sub-GHz radio generic payload length register
(SUBGHZ_GRTXPLDLEN) . . . . .		162
4.10.14Sub-GHz radio generic CRC initial MSB register
(SUBGHZ_GCRCINIRH) . . . . .		162
4.10.15Sub-GHz radio generic CRC initial LSB register
(SUBGHZ_GCRCINIRL) . . . . .		163
4.10.16Sub-GHz radio generic CRC polynomial MSB register
(SUBGHZ_GCRCPOLRH) . . . . .		163
4.10.17Sub-GHz radio generic CRC polynomial LSB register
(SUBGHZ_GCRCPOLRL) . . . . .		163
4.10.18Sub-GHz radio generic synchronization word control register 0
(SUBGHZ_GSYNCR0) . . . . .		164
4.10.19Sub-GHz radio generic synchronization word control register 1
(SUBGHZ_GSYNCR1) . . . . .		164
4.10.20Sub-GHz radio generic synchronization word control register 2
(SUBGHZ_GSYNCR2) . . . . .		164
4.10.21Sub-GHz radio generic synchronization word control register 3 (SUBGHZ_GSYNCR3) . . . . .164
4.10.22Sub-GHz radio generic synchronization word control register 4 (SUBGHZ_GSYNCR4) . . . . .165
4.10.23Sub-GHz radio generic synchronization word control register 5 (SUBGHZ_GSYNCR5) . . . . .165
4.10.24Sub-GHz radio generic synchronization word control register 6 (SUBGHZ_GSYNCR6) . . . . .165
4.10.25Sub-GHz radio generic synchronization word control register 7 (SUBGHZ_GSYNCR7) . . . . .165
4.10.26Sub-GHz radio generic node address register (SUBGHZ_GNODEADR) . . . . .166
4.10.27Sub-GHz radio generic broadcast address register (SUBGHZ_GBCASTADDR) . . . . .166
4.10.28Sub-GHz radio generic AFC register (SUBGHZ_GAFCR) . . . . .166
4.10.29Sub-GHz radio LoRa payload length register (SUBGHZ_LPLDLENR) . . . . .166
4.10.30Sub-GHz radio synchro timeout register (SUBGHZ_LSYNCTIMEOUTR) . . . . .167
4.10.31Sub-GHz radio LoRa IQ polarity MSB register (SUBGHZ_LIQPOLR) . . . . .167
4.10.32Sub-GHz radio LoRa IQ polarity LSB register (SUBGHZ_LIQPOLR) . . . . .167
4.10.33Sub-GHz radio LoRa synchronization word MSB register (SUBGHZ_LSYNCRH) . . . . .167
4.10.34Sub-GHz radio LoRa synchronization word LSB register (SUBGHZ_LSYNCRH) . . . . .168
4.10.35Sub-GHz radio Tx address pointer register (SUBGHZ_TXADRPTR) . . . . .168
4.10.36Sub-GHz radio Rx address pointer register (SUBGHZ_RXADRPTR) . . . . .168
4.10.37Sub-GHz radio bandwidth select register (SUBGHZ_BWSELR) . . . . .169
4.10.38Sub-GHz radio random number register 3 (SUBGHZ_RNGR3) . . . . .169
4.10.39Sub-GHz radio random number register 2 (SUBGHZ_RNGR2) . . . . .169
4.10.40Sub-GHz radio random number register 1 (SUBGHZ_RNGR1) . . . . .169
4.10.41Sub-GHz radio random number register 0 (SUBGHZ_RNGR0) . . . . .170
4.10.42Sub-GHz radio SD resolution register (SUBGHZ_SDCFG0R) . . . . .170
4.10.43Sub-GHz radio AGC RSSI control register (SUBGHZ_AGCRSSICTL0R) . . . . .170
4.10.44Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR) . . . . .170
4.10.45Sub-GHz radio AGC reset configuration register (SUBGHZ_AGCGFORSTCFGR) . . . . .171
4.10.46Sub-GHz radio AGC reset power threshold register (SUBGHZ_AGCGFORSTPOWTHR) . . . . .171
4.10.47Sub-GHz radio Tx clamp register (SUBGHZ_TXCLAMPR) . . . . .171
4.10.48Sub-GHz radio disable LNA register (REG_ANA_LNA) . . . . .172
4.10.49Sub-GHz radio disable mixer register (REG_ANA_MIXER) . . . . .172
4.10.50Sub-GHz radio PA over current protection register
(SUBGHZ_PAOCPR) . . . . .		172
4.10.51Sub-GHz radio RTC control register (SUBGHZ_RTCCTLR) . . . . .172
4.10.52Sub-GHz radio RTC period MSB register (SUBGHZ_RTCPRDR2) . . .173
4.10.53Sub-GHz radio RTC period mid-byte register
(SUBGHZ_RTCPRDR1) . . . . .		173
4.10.54Sub-GHz radio RTC period LSB register (SUBGHZ_RTCPRDR0) . . .173
4.10.55Sub-GHz radio HSE32 OSC_IN capacitor trim register
(SUBGHZ_HSEINTRIMR) . . . . .		174
4.10.56Sub-GHz radio HSE32 OSC_OUT capacitor trim register
(SUBGHZ_HSEOUTTRIMR) . . . . .		174
4.10.57Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R) . . . .175
4.10.58Sub-GHz radio power control register (SUBGHZ_PCR) . . . . .175
4.10.59Sub-GHz radio regulator drive control register
(SUBGHZ_REGDRVCR) . . . . .		176
4.10.60Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R) . . . .176
4.10.61Sub-GHz radio register map . . . . .177
5Power control (PWR) . . . . .179
5.1Power supplies . . . . .179
5.1.1Independent analog peripherals supply . . . . .182
5.1.2Battery backup domain . . . . .182
5.1.3Voltage regulator . . . . .184
5.1.4Dynamic voltage scaling management . . . . .184
5.2Power supply supervisor . . . . .185
5.2.1Power-on reset (POR)/power-down reset (PDR)
/Brownout reset (BOR) . . . . .		185
5.2.2Programmable voltage detector (PVD) . . . . .186
5.2.3Peripheral voltage monitoring (PVM) . . . . .187
5.2.4Radio end of life (EOL) . . . . .188
5.3Radio busy management . . . . .188
5.4Low-power modes . . . . .190
5.4.1Run mode . . . . .196
5.4.2Low-power run mode (LPRun) . . . . .196
5.4.3Enter low-power mode . . . . .197
6.2Clocks . . . . .228
6.2.1HSE32 clock with trimming . . . . .231
6.2.2HSI16 clock . . . . .233
6.2.3MSI clock . . . . .234
6.2.4PLL . . . . .235
6.2.5LSE clock . . . . .235
6.2.6LSI clock . . . . .236
6.2.7Clock source stabilization time . . . . .237
6.2.8System clock (SYSCLK) selection . . . . .237
6.2.9Clock source frequency versus voltage scaling . . . . .238
6.2.10Clock security system on HSE32 (CSS) . . . . .238
6.2.11Clock security system on LSE (LSECSS) . . . . .238
6.2.12SPI2S2 clock . . . . .239
6.2.13Sub-GHz radio SPI clock . . . . .239
6.2.14ADC clock . . . . .240
6.2.15RTC clock . . . . .240
6.2.16Timer clock . . . . .240
6.2.17Watchdog clock . . . . .240
6.2.18True RNG clock . . . . .241
6.2.19Clock-out capability . . . . .241
6.2.20Internal/external clock measurement with TIM16/TIM17 . . . . .242
6.2.21Peripheral clocks enable . . . . .244
6.3Low-power modes . . . . .244
6.4RCC registers . . . . .246
6.4.1RCC clock control register (RCC_CR) . . . . .246
6.4.2RCC internal clock sources calibration register (RCC_ICSCR) . . . . .249
6.4.3RCC clock configuration register (RCC_CFGR) . . . . .250
6.4.4RCC PLL configuration register (RCC_PLLCFGR) . . . . .253
6.4.5RCC clock interrupt enable register (RCC_CIER) . . . . .256
6.4.6RCC clock interrupt flag register (RCC_CIFR) . . . . .257
6.4.7RCC clock interrupt clear register (RCC_CICR) . . . . .258
6.4.8RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .259
6.4.9RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .260
6.4.10RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .261
6.4.11RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .261
6.4.12RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .263
6.4.13RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .263

6.4.14 RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . . 264

6.4.15 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 265

6.4.16 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 266

6.4.17 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 266

6.4.18 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . 267

6.4.19 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . 269

6.4.20 RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 270

6.4.21 RCC APB3 peripheral clock enable register (RCC_APB3ENR) . . . . . 271

6.4.22 RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR) . . . . . 271

6.4.23 RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR) . . . . . 272

6.4.24 RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR) . . . . . 273

6.4.25 RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1) . . . . . 274

6.4.26 RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2) . . . . . 275

6.4.27 RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR) . . . . . 276

6.4.28 RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR) . . . . . 277

6.4.29 RCC peripherals independent clock configuration register
(RCC_CCIPR) . . . . . 278

6.4.30 RCC backup domain control register (RCC_BDCR) . . . . . 280

6.4.31 RCC control/status register (RCC_CSR) . . . . . 282

6.4.32 RCC extended clock recovery register (RCC_EXTCFGR) . . . . . 285

6.4.33 RCC register map . . . . . 286

7        Hardware semaphore (HSEM) . . . . . 290

7.1    HSEM introduction . . . . . 290

7.2    HSEM main features . . . . . 290

7.3    Functional description . . . . . 291

7.3.1    HSEM block diagram . . . . . 291

7.3.2    HSEM internal signals . . . . . 291

7.3.3    HSEM lock procedures . . . . . 291

7.3.4    HSEM write/read/read lock register address . . . . . 293

7.3.5    HSEM unlock procedures . . . . . 293

7.3.6    HSEM MASTERID semaphore clear . . . . . 294

7.3.7HSEM interrupts .....294
7.3.8AHB bus master ID verification .....296
7.4HSEM registers .....297
7.4.1HSEM register semaphore x (HSEM_Rx) .....297
7.4.2HSEM read lock register semaphore x (HSEM_RLRx) .....298
7.4.3HSEM interrupt enable register (HSEM_IER) .....299
7.4.4HSEM interrupt clear register (HSEM_ICR) .....299
7.4.5HSEM interrupt status register (HSEM_ISR) .....299
7.4.6HSEM interrupt status register (HSEM_MISR) .....300
7.4.7HSEM clear register (HSEM_CR) .....300
7.4.8HSEM clear semaphore key register (HSEM_KEYR) .....301
7.4.9HSEM register map .....302
8General-purpose I/Os (GPIO) .....303
8.1GPIO introduction .....303
8.2GPIO main features .....303
8.3GPIO functional description .....303
8.3.1General purpose I/O (GPIO) .....306
8.3.2I/O pin alternate function multiplexer and mapping .....306
8.3.3I/O port control registers .....307
8.3.4I/O port data registers .....307
8.3.5I/O data bitwise handling .....307
8.3.6GPIO locking mechanism .....308
8.3.7I/O alternate function input/output .....308
8.3.8External interrupt/wake-up lines .....308
8.3.9Input configuration .....309
8.3.10Output configuration .....309
8.3.11Alternate function configuration .....310
8.3.12Analog configuration .....311
8.3.13Using the LSE oscillator pins as GPIOs .....311
8.3.14Using the GPIO pins in the RTC supply domain .....311
8.3.15Using PH3 as GPIO .....312
8.4GPIO registers .....312
8.4.1GPIOx mode register (GPIOx_MODER) (x = A to B) .....312
8.4.2GPIOx output type register (GPIOx_OTYPER) (x = A to B) .....312
8.4.3GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B) .....313
8.4.4GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) .....313
8.4.5GPIOx input data register (GPIOx_IDR) (x = A to B) . . . . .314
8.4.6GPIOx output data register (GPIOx_ODR) (x = A to B) . . . . .314
8.4.7GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B) . . . . .315
8.4.8GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) . . . . .315
8.4.9GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) . . . . .316
8.4.10GPIOx alternate function high register (GPIOx_AFRH) (x = A to B) . . . . .317
8.4.11GPIOx bit reset register (GPIOx_BRR) (x = A to B) . . . . .317
8.4.12GPIOC mode register (GPIOC_MODER) . . . . .318
8.4.13GPIOC output type register (GPIOC_OTYPER) . . . . .318
8.4.14GPIOC output speed register (GPIOC_OSPEEDR) . . . . .319
8.4.15GPIOC pull-up/pull-down register (GPIOC_PUPDR) . . . . .320
8.4.16GPIOC input data register (GPIOC_IDR) . . . . .320
8.4.17GPIOC output data register (GPIOC_ODR) . . . . .321
8.4.18GPIOC bit set/reset register (GPIOC_BSRR) . . . . .321
8.4.19GPIOC configuration lock register (GPIOC_LCKR) . . . . .322
8.4.20GPIOC alternate function low register (GPIOC_AFRL) . . . . .323
8.4.21GPIOC alternate function high register (GPIOC_AFRH) . . . . .324
8.4.22GPIOC bit reset register (GPIOC_BRR) . . . . .324
8.4.23GPIOH mode register (GPIOH_MODER) . . . . .325
8.4.24GPIO H output type register (GPIOH_OTYPER) . . . . .325
8.4.25GPIOH output speed register (GPIOH_OSPEEDR) . . . . .326
8.4.26GPIOH pull-up/pull-down register (GPIOH_PUPDR) . . . . .326
8.4.27GPIOH input data register (GPIOH_IDR) . . . . .327
8.4.28GPIOH output data register (GPIOH_ODR) . . . . .327
8.4.29GPIO H bit set/reset register (GPIOH_BSRR) . . . . .327
8.4.30GPIOH configuration lock register (GPIOH_LCKR) . . . . .328
8.4.31GPIOH alternate function low register (GPIOH_AFRL) . . . . .329
8.4.32GPIOH bit reset register (GPIOH_BRR) . . . . .330
8.4.33GPIOA register map . . . . .330
8.4.34GPIOB register map . . . . .331
8.4.35GPIOC register map . . . . .332
8.4.36GPIOH register map . . . . .333
9System configuration controller (SYSCFG) . . . . .334
9.1SYSCFG main features . . . . .334
9.2SYSCFG registers . . . . .334
9.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .334
9.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) .....335
9.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) .....		336
9.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) .....		337
9.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) .....		338
9.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) .....		339
9.2.7SYSCFG SRAM control and status register (SYSCFG_SCSR) .....340
9.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) .....340
9.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR) .....341
9.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) .....342
9.2.11SYSCFG radio debug control register (SYSCFG_RFDCR) .....342
9.2.12SYSCFG register map .....342
10Peripherals interconnect matrix .....344
10.1Introduction .....344
10.2Connection summary .....344
10.3Interconnection details .....345
10.3.1From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2) .....345
10.3.2From timer (LPTIM1/LPTIM2) to timer (LPTIM3) .....346
10.3.3From timer (TIM1/TIM2) and GPIO pin EXTI to ADC/DAC .....346
10.3.4From timer (LPTIM1/LPTIM2) to DAC .....347
10.3.5From ADC to timer (TIM1) .....347
10.3.6From HSE32, LSE, LSI, MSI, MCO, RTC to timers
(TIM2/TIM16/TIM17) .....		347
10.3.7From RTC, TAMP, COMP1, COMP2 to low-power timers
(LPTIM1/LPTIM2) .....		348
10.3.8From timer (TIM1/TIM2) to comparators (COMP1/COMP2) .....348
10.3.9From internal analog to ADC .....349
10.3.10From comparators (COMP1/COMP2) to timers
(TIM1/TIM2/TIM16/TIM17) .....		349
10.3.11From system errors to timers (TIM1/TIM16/TIM17) .....350
10.3.12From timers (TIM16/TIM17) to IRTIM .....350
10.3.13From timer (LPTIM1/LPTIM2/LPTIM3/GPIO pin EXTI)
to DMAMUX1 trigger .....		350
10.3.14From timer (LPTIM3) to sub-GHz radio SPI NSS .....351
12.4.6DMAMUX request generator . . . . .384
12.5DMAMUX interrupts . . . . .385
12.6DMAMUX registers . . . . .386
12.6.1DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) . . . . .386
12.6.2DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) . . . . .387
12.6.3DMAMUX request line multiplexer interrupt channel clear flag register (DMAMUX_CCFR) . . . . .387
12.6.4DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) . . . . .388
12.6.5DMAMUX request generator interrupt status register (DMAMUX_RGS) . . . . .389
12.6.6DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR) . . . . .389
12.6.7DMAMUX register map . . . . .391
13Nested vectored interrupt controller (NVIC) . . . . .393
13.1NVIC main features . . . . .393
13.2Interrupt and exception vectors . . . . .393
14Extended interrupts and event controller (EXTI) . . . . .396
14.1EXTI main features . . . . .396
14.2EXTI block diagram . . . . .396
14.3EXTI connections between peripherals and CPU . . . . .398
14.3.1EXTI wake-up interrupt list . . . . .398
14.4EXTI functional description . . . . .400
14.4.1EXTI configurable event input wake-up . . . . .400
14.4.2EXTI direct event input wake-up . . . . .401
14.5EXTI functional behavior . . . . .402
14.6EXTI registers . . . . .403
14.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .403
14.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .404
14.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .405
14.6.4EXTI pending register (EXTI_PR1) . . . . .406
14.6.5EXTI rising trigger selection register (EXTI_RTSR2) . . . . .407
14.6.6EXTI falling trigger selection register (EXTI_FTSR2) . . . . .408
14.6.7EXTI software interrupt event register (EXTI_SWIER2) . . . . .408
14.6.8EXTI pending register (EXTI_PR2) . . . . .409
14.6.9EXTI interrupt mask register (EXTI_IMR1) . . . . .409
14.6.10EXTI event mask register (EXTI_EMR1) . . . . .410
14.6.11EXTI interrupt mask register (EXTI_IMR2) . . . . .411
14.6.12EXTI register map . . . . .411
15Cyclic redundancy check calculation unit (CRC) . . . . .413
15.1CRC introduction . . . . .413
15.2CRC main features . . . . .413
15.3CRC functional description . . . . .414
15.3.1CRC block diagram . . . . .414
15.3.2CRC internal signals . . . . .414
15.3.3CRC operation . . . . .414
15.4CRC registers . . . . .416
15.4.1CRC data register (CRC_DR) . . . . .416
15.4.2CRC independent data register (CRC_IDR) . . . . .416
15.4.3CRC control register (CRC_CR) . . . . .417
15.4.4CRC initial value (CRC_INIT) . . . . .418
15.4.5CRC polynomial (CRC_POL) . . . . .418
15.4.6CRC register map . . . . .419
16Analog-to-digital converter (ADC) . . . . .420
16.1Introduction . . . . .420
16.2ADC main features . . . . .421
16.3ADC functional description . . . . .422
16.3.1ADC pins and internal signals . . . . .422
16.3.2ADC voltage regulator (ADVREGEN) . . . . .423
16.3.3Calibration (ADCAL) . . . . .424
16.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .426
16.3.5ADC clock (CKMODE, PRESC[3:0]) . . . . .427
16.3.6ADC connectivity . . . . .429
16.3.7Configuring the ADC . . . . .430
16.3.8Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .430
16.3.9Programmable sampling time (SMPx[2:0]) . . . . .431
16.3.10Single conversion mode (CONT = 0) . . . . .432
16.3.11Continuous conversion mode (CONT = 1) . . . . .432
16.3.12Starting conversions (ADSTART) . . . . .433
16.3.13Timings . . . . .434
16.3.14Stopping an ongoing conversion (ADSTP) . . . . .435
16.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .435
16.4.1Discontinuous mode (DISCEN) . . . . .436
16.4.2Programmable resolution (RES) - Fast conversion mode . . . . .436
16.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .437
16.4.4End of conversion sequence (EOS flag) . . . . .437
16.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		438
16.4.6Low frequency trigger mode . . . . .440
16.5Data management . . . . .440
16.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .440
16.5.2ADC overrun (OVR, OVRMOD) . . . . .440
16.5.3Managing a sequence of data converted without using the DMA . . . . .442
16.5.4Managing converted data without using the DMA without overrun . . . . .442
16.5.5Managing converted data using the DMA . . . . .442
16.6Low-power features . . . . .443
16.6.1Wait mode conversion . . . . .443
16.6.2Auto-off mode (AUTOFF) . . . . .444
16.7Analog window watchdogs . . . . .445
16.7.1Description of analog watchdog 1 . . . . .446
16.7.2Description of analog watchdog 2 and 3 . . . . .447
16.7.3ADC_AWDx_OUT output signal generation . . . . .447
16.7.4Analog watchdog threshold control . . . . .449
16.8Oversampler . . . . .450
16.8.1ADC operating modes supported when oversampling . . . . .451
16.8.2Analog watchdog . . . . .452
16.8.3Triggered mode . . . . .452
16.9Temperature sensor and internal reference voltage . . . . .452
16.10Battery voltage monitoring . . . . .455
16.11ADC interrupts . . . . .456
16.12ADC registers . . . . .457
16.12.1ADC interrupt and status register (ADC_ISR) . . . . .457
16.12.2ADC interrupt enable register (ADC_IER) . . . . .458
16.12.3ADC control register (ADC_CR) . . . . .460
16.12.4ADC configuration register 1 (ADC_CFGR1) . . . . .462
16.12.5ADC configuration register 2 (ADC_CFGR2) . . . . .465
16.12.6ADC sampling time register (ADC_SMPR) . . . . .467
16.12.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .468
16.12.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .468
16.12.9ADC channel selection register (ADC_CHSELR) . . . . .468
16.12.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .469
16.12.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .471
16.12.12ADC data register (ADC_DR) . . . . .472
16.12.13ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .472
16.12.14ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .473
16.12.15ADC calibration factor (ADC_CALFACT) . . . . .473
16.12.16ADC common configuration register (ADC_CCR) . . . . .474
16.13ADC register map . . . . .475
17Digital-to-analog converter (DAC) . . . . .478
17.1DAC introduction . . . . .478
17.2DAC main features . . . . .478
17.3DAC implementation . . . . .479
17.4DAC functional description . . . . .479
17.4.1DAC block diagram . . . . .479
17.4.2DAC pins and internal signals . . . . .480
17.4.3DAC channel enable . . . . .481
17.4.4DAC data format . . . . .481
17.4.5DAC conversion . . . . .482
17.4.6DAC output voltage . . . . .482
17.4.7DAC trigger selection . . . . .482
17.4.8DMA requests . . . . .483
17.4.9Noise generation . . . . .483
17.4.10Triangle-wave generation . . . . .485
17.4.11DAC channel modes . . . . .486
17.4.12DAC channel buffer calibration . . . . .489
17.4.13DAC channel conversion modes . . . . .490
17.5DAC in low-power modes . . . . .491
17.6DAC interrupts . . . . .491
17.7DAC registers . . . . .492
17.7.1DAC control register (DAC_CR) . . . . .492
17.7.2DAC software trigger register (DAC_SWTRGR) . . . . .494
17.7.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		494
17.7.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		495
17.7.5DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . .		495
17.7.6DAC channel1 data output register (DAC_DOR1) . . . . .496
17.7.7DAC status register (DAC_SR) . . . . .496
17.7.8DAC calibration control register (DAC_CCR) . . . . .497
17.7.9DAC mode control register (DAC_MCR) . . . . .497
17.7.10DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . .		498
17.7.11DAC sample and hold time register (DAC_SHHR) . . . . .498
17.7.12DAC sample and hold refresh time register (DAC_SHRR) . . . . .499
17.7.13DAC register map . . . . .500
18Voltage reference buffer (VREFBUF) . . . . .502
18.1VREFBUF introduction . . . . .502
18.2VREFBUF functional description . . . . .502
18.3VREFBUF registers . . . . .503
18.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .503
18.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .504
18.3.3VREFBUF register map . . . . .505
19Comparator (COMP) . . . . .506
19.1COMP introduction . . . . .506
19.2COMP main features . . . . .506
19.3COMP functional description . . . . .507
19.3.1COMP block diagram . . . . .507
19.3.2COMP pins and internal signals . . . . .507
19.3.3COMP reset and clocks . . . . .509
19.3.4Comparator LOCK mechanism . . . . .509
19.3.5Window comparator . . . . .509
19.3.6Hysteresis . . . . .510
19.3.7Comparator output blanking function . . . . .511
19.3.8COMP power and speed modes . . . . .511
21.4AES functional description . . . . .534
21.4.1AES block diagram . . . . .534
21.4.2AES internal signals . . . . .534
21.4.3AES cryptographic core . . . . .534
21.4.4AES procedure to perform a cipher operation . . . . .540
21.4.5AES decryption round key preparation . . . . .543
21.4.6AES ciphertext stealing and data padding . . . . .543
21.4.7AES task suspend and resume . . . . .544
21.4.8AES basic chaining modes (ECB, CBC) . . . . .544
21.4.9AES counter (CTR) mode . . . . .549
21.4.10AES Galois/counter mode (GCM) . . . . .551
21.4.11AES Galois message authentication code (GMAC) . . . . .556
21.4.12AES counter with CBC-MAC (CCM) . . . . .558
21.4.13AES data registers and data swapping . . . . .563
21.4.14AES key registers . . . . .565
21.4.15AES initialization vector registers . . . . .565
21.4.16AES DMA interface . . . . .566
21.4.17AES error management . . . . .567
21.5AES interrupts . . . . .568
21.6AES processing latency . . . . .568
21.7AES registers . . . . .569
21.7.1AES control register (AES_CR) . . . . .569
21.7.2AES status register (AES_SR) . . . . .571
21.7.3AES data input register (AES_DINR) . . . . .573
21.7.4AES data output register (AES_DOUTR) . . . . .573
21.7.5AES key register 0 (AES_KEYR0) . . . . .574
21.7.6AES key register 1 (AES_KEYR1) . . . . .574
21.7.7AES key register 2 (AES_KEYR2) . . . . .575
21.7.8AES key register 3 (AES_KEYR3) . . . . .575
21.7.9AES initialization vector register 0 (AES_IVR0) . . . . .575
21.7.10AES initialization vector register 1 (AES_IVR1) . . . . .576
21.7.11AES initialization vector register 2 (AES_IVR2) . . . . .576
21.7.12AES initialization vector register 3 (AES_IVR3) . . . . .576
21.7.13AES key register 4 (AES_KEYR4) . . . . .577
21.7.14AES key register 5 (AES_KEYR5) . . . . .577
21.7.15AES key register 6 (AES_KEYR6) . . . . .577
21.7.16AES key register 7 (AES_KEYR7) . . . . .578

21.7.17 AES suspend registers (AES_SUSPxR) . . . . . 578

21.7.18 AES register map . . . . . 579

22 Public key accelerator (PKA) . . . . . 581

22.1 Introduction . . . . . 581

22.2 PKA main features . . . . . 581

22.3 PKA functional description . . . . . 581

22.3.1 PKA block diagram . . . . . 581

22.3.2 PKA internal signals . . . . . 582

22.3.3 PKA reset and clocks . . . . . 582

22.3.4 PKA public key acceleration . . . . . 582

22.3.5 Typical applications for PKA . . . . . 584

22.3.6 PKA procedure to perform an operation . . . . . 586

22.3.7 PKA error management . . . . . 587

22.4 PKA operating modes . . . . . 587

22.4.1 Introduction . . . . . 587

22.4.2 Montgomery parameter computation . . . . . 588

22.4.3 Modular addition . . . . . 589

22.4.4 Modular subtraction . . . . . 589

22.4.5 Modular and Montgomery multiplication . . . . . 589

22.4.6 Modular exponentiation . . . . . 590

22.4.7 Modular inversion . . . . . 591

22.4.8 Modular reduction . . . . . 592

22.4.9 Arithmetic addition . . . . . 592

22.4.10 Arithmetic subtraction . . . . . 592

22.4.11 Arithmetic multiplication . . . . . 593

22.4.12 Arithmetic comparison . . . . . 593

22.4.13 RSA CRT exponentiation . . . . . 593

22.4.14 Point on elliptic curve Fp check . . . . . 594

22.4.15 ECC Fp scalar multiplication . . . . . 595

22.4.16 ECDSA sign . . . . . 596

22.4.17 ECDSA verification . . . . . 598

22.5 Example of configurations and processing times . . . . . 599

22.5.1 Supported elliptic curves . . . . . 599

22.5.2 Computation times . . . . . 601

22.6 PKA interrupts . . . . . 602

22.7PKA registers . . . . .603
22.7.1PKA control register (PKA_CR) . . . . .603
22.7.2PKA status register (PKA_SR) . . . . .604
22.7.3PKA clear flag register (PKA_CLRFR) . . . . .605
22.7.4PKA RAM . . . . .605
22.7.5PKA register map . . . . .606
23Advanced-control timer (TIM1) . . . . .607
23.1TIM1 introduction . . . . .607
23.2TIM1 main features . . . . .608
23.3TIM1 functional description . . . . .610
23.3.1Time-base unit . . . . .610
23.3.2Counter modes . . . . .612
23.3.3Repetition counter . . . . .623
23.3.4External trigger input . . . . .625
23.3.5Clock selection . . . . .626
23.3.6Capture/compare channels . . . . .630
23.3.7Input capture mode . . . . .632
23.3.8PWM input mode . . . . .633
23.3.9Forced output mode . . . . .634
23.3.10Output compare mode . . . . .635
23.3.11PWM mode . . . . .636
23.3.12Asymmetric PWM mode . . . . .639
23.3.13Combined PWM mode . . . . .640
23.3.14Combined 3-phase PWM mode . . . . .641
23.3.15Complementary outputs and dead-time insertion . . . . .642
23.3.16Using the break function . . . . .644
23.3.17Bidirectional break inputs . . . . .650
23.3.18Clearing the OCxREF signal on an external event . . . . .652
23.3.196-step PWM generation . . . . .653
23.3.20One-pulse mode . . . . .654
23.3.21Retriggerable one pulse mode . . . . .655
23.3.22Encoder interface mode . . . . .656
23.3.23UIF bit remapping . . . . .658
23.3.24Timer input XOR function . . . . .659
23.3.25Interfacing with Hall sensors . . . . .659
23.3.26Timer synchronization . . . . .662
23.3.27ADC synchronization . . . . .666
23.3.28DMA burst mode . . . . .666
23.3.29Debug mode . . . . .667
23.4TIM1 registers . . . . .668
23.4.1TIM1 control register 1 (TIM1_CR1) . . . . .668
23.4.2TIM1 control register 2 (TIM1_CR2) . . . . .669
23.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		672
23.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		674
23.4.5TIM1 status register (TIM1_SR) . . . . .676
23.4.6TIM1 event generation register (TIM1_EGR) . . . . .678
23.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .679
23.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		680
23.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .683
23.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		684
23.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		685
23.4.12TIM1 counter (TIM1_CNT) . . . . .689
23.4.13TIM1 prescaler (TIM1_PSC) . . . . .689
23.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .689
23.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .690
23.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		690
23.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		691
23.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		691
23.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		692
23.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		692
23.4.21TIM1 DMA control register
(TIM1_DCR) . . . . .		696
23.4.22TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . .		697
23.4.23TIM1 option register 1 (TIM1_OR1) . . . . .698
23.4.24TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . .		698
23.4.25TIM1 capture/compare register 5 (TIM1_CCR5) .....699
23.4.26TIM1 capture/compare register 6 (TIM1_CCR6) .....700
23.4.27TIM1 alternate function option register 1 (TIM1_AF1) .....701
23.4.28TIM1 Alternate function register 2 (TIM1_AF2) .....702
23.4.29TIM1 timer input selection register (TIM1_TISEL) .....704
23.4.30TIM1 register map .....705
24General-purpose timer (TIM2) .....708
24.1TIM2 introduction .....708
24.2TIM2 main features .....708
24.3TIM2 functional description .....710
24.3.1Time-base unit .....710
24.3.2Counter modes .....712
24.3.3Clock selection .....722
24.3.4Capture/Compare channels .....726
24.3.5Input capture mode .....728
24.3.6PWM input mode .....729
24.3.7Forced output mode .....730
24.3.8Output compare mode .....730
24.3.9PWM mode .....731
24.3.10Asymmetric PWM mode .....735
24.3.11Combined PWM mode .....735
24.3.12Clearing the OCxREF signal on an external event .....736
24.3.13One-pulse mode .....738
24.3.14Retriggerable one pulse mode .....739
24.3.15Encoder interface mode .....740
24.3.16UIF bit remapping .....742
24.3.17Timer input XOR function .....742
24.3.18Timers and external trigger synchronization .....743
24.3.19Timer synchronization .....746
24.3.20DMA burst mode .....751
24.3.21Debug mode .....752
24.4TIM2 registers .....753
24.4.1TIM2 control register 1 (TIM2_CR1) .....753
24.4.2TIM2 control register 2 (TIM2_CR2) .....754
24.4.3TIM2 slave mode control register (TIM2_SMCR) . . . . .756
24.4.4TIM2 DMA/Interrupt enable register (TIM2_DIER) . . . . .759
24.4.5TIM2 status register (TIM2_SR) . . . . .760
24.4.6TIM2 event generation register (TIM2_EGR) . . . . .762
24.4.7TIM2 capture/compare mode register 1 (TIM2_CCMR1) . . . . .763
24.4.8TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) . . . . .764
24.4.9TIM2 capture/compare mode register 2 (TIM2_CCMR2) . . . . .767
24.4.10TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) . . . . .768
24.4.11TIM2 capture/compare enable register
(TIM2_CCER) . . . . .		769
24.4.12TIM2 counter (TIM2_CNT) . . . . .770
24.4.13TIM2 counter [alternate] (TIM2_CNT) . . . . .771
24.4.14TIM2 prescaler (TIM2_PSC) . . . . .771
24.4.15TIM2 auto-reload register (TIM2_ARR) . . . . .771
24.4.16TIM2 capture/compare register 1 (TIM2_CCR1) . . . . .772
24.4.17TIM2 capture/compare register 2 (TIM2_CCR2) . . . . .772
24.4.18TIM2 capture/compare register 3 (TIM2_CCR3) . . . . .773
24.4.19TIM2 capture/compare register 4 (TIM2_CCR4) . . . . .773
24.4.20TIM2 DMA control register (TIM2_DCR) . . . . .774
24.4.21TIM2 DMA address for full transfer (TIM2_DMAR) . . . . .774
24.4.22TIM2 option register 1 (TIM2_OR1) . . . . .775
24.4.23TIM2 alternate function option register 1 (TIM2_AF1) . . . . .775
24.4.24TIM2 timer input selection register (TIM2_TISEL) . . . . .776
24.4.25TIMx register map . . . . .777
25General-purpose timers (TIM16/TIM17) . . . . .780
25.1TIM16/TIM17 introduction . . . . .780
25.2TIM16/TIM17 main features . . . . .780
25.3TIM16/TIM17 functional description . . . . .782
25.3.1Time-base unit . . . . .782
25.3.2Counter modes . . . . .784
25.3.3Repetition counter . . . . .788
25.3.4Clock selection . . . . .789
25.3.5Capture/compare channels . . . . .791
25.3.6Input capture mode . . . . .793
25.3.7Forced output mode . . . . .794
25.3.8Output compare mode . . . . .794
25.3.9PWM mode . . . . .796
25.3.10Complementary outputs and dead-time insertion . . . . .797
25.3.11Using the break function . . . . .799
25.3.12Bidirectional break inputs . . . . .802
25.3.136-step PWM generation . . . . .803
25.3.14One-pulse mode . . . . .805
25.3.15UIF bit remapping . . . . .806
25.3.16Slave mode – combined reset + trigger mode . . . . .806
25.3.17DMA burst mode . . . . .806
25.3.18Using timer output as trigger for other timers (TIM16/TIM17) . . . . .807
25.3.19Debug mode . . . . .808
25.4TIM16/TIM17 registers . . . . .809
25.4.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .809
25.4.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .810
25.4.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .811
25.4.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .812
25.4.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .813
25.4.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		814
25.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		815
25.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .817
25.4.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .819
25.4.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .820
25.4.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .820
25.4.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .821
25.4.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .821
25.4.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .822
25.4.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .824
25.4.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .825
25.4.17TIM16 option register 1 (TIM16_OR1) . . . . .826
25.4.18TIM16 alternate function register 1 (TIM16_AF1) . . . . .826
25.4.19TIM16 input selection register (TIM16_TISEL) . . . . .827
25.4.20TIM17 option register 1 (TIM17_OR1) . . . . .828
25.4.21TIM17 alternate function register 1 (TIM17_AF1) . . . . .828
25.4.22TIM17 input selection register (TIM17_TISEL) . . . . .829
25.4.23TIM16/TIM17 register map . . . . .830
26.7.12LPTIM repetition register (LPTIM_RCR) . . . . .858
26.7.13LPTIM register map . . . . .858
27Infrared interface (IRTIM) . . . . .860
28Independent watchdog (IWDG) . . . . .861
28.1Introduction . . . . .861
28.2IWDG main features . . . . .861
28.3IWDG functional description . . . . .861
28.3.1IWDG block diagram . . . . .861
28.3.2Window option . . . . .862
28.3.3Hardware watchdog . . . . .863
28.3.4Low-power freeze . . . . .863
28.3.5Register access protection . . . . .863
28.3.6Debug mode . . . . .863
28.4IWDG registers . . . . .864
28.4.1IWDG key register (IWDG_KR) . . . . .864
28.4.2IWDG prescaler register (IWDG_PR) . . . . .865
28.4.3IWDG reload register (IWDG_RLR) . . . . .866
28.4.4IWDG status register (IWDG_SR) . . . . .867
28.4.5IWDG window register (IWDG_WINR) . . . . .868
28.4.6IWDG register map . . . . .869
29System window watchdog (WWDG) . . . . .870
29.1WWDG introduction . . . . .870
29.2WWDG main features . . . . .870
29.3WWDG functional description . . . . .870
29.3.1WWDG block diagram . . . . .871
29.3.2WWDG internal signals . . . . .871
29.3.3Enabling the watchdog . . . . .871
29.3.4Controlling the down-counter . . . . .871
29.3.5How to program the watchdog timeout . . . . .872
29.3.6Debug mode . . . . .873
29.4WWDG interrupts . . . . .873
29.5WWDG registers . . . . .873
29.5.1WWDG control register (WWDG_CR) . . . . .874
30.6.9RTC calibration register (RTC_CALR) . . . . .905
30.6.10RTC shift control register (RTC_SHIFTR) . . . . .906
30.6.11RTC timestamp time register (RTC_TSTR) . . . . .907
30.6.12RTC timestamp date register (RTC_TSDR) . . . . .908
30.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .908
30.6.14RTC alarm A register (RTC_ALRMAR) . . . . .909
30.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .910
30.6.16RTC alarm B register (RTC_ALRMBR) . . . . .911
30.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .912
30.6.18RTC status register (RTC_SR) . . . . .913
30.6.19RTC masked interrupt status register (RTC_MISR) . . . . .914
30.6.20RTC status clear register (RTC_SCR) . . . . .915
30.6.21RTC alarm A binary mode register (RTC_ALRABINR) . . . . .916
30.6.22RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .916
30.6.23RTC register map . . . . .917
31Tamper and backup registers (TAMP) . . . . .919
31.1Introduction . . . . .919
31.2TAMP main features . . . . .919
31.3TAMP functional description . . . . .920
31.3.1TAMP block diagram . . . . .920
31.3.2TAMP pins and internal signals . . . . .921
31.3.3TAMP register write protection . . . . .922
31.3.4Tamper detection . . . . .922
31.4TAMP low-power modes . . . . .924
31.5TAMP interrupts . . . . .924
31.6TAMP registers . . . . .925
31.6.1TAMP control register 1 (TAMP_CR1) . . . . .925
31.6.2TAMP control register 2 (TAMP_CR2) . . . . .926
31.6.3TAMP control register 3 (TAMP_CR3) . . . . .927
31.6.4TAMP filter control register (TAMP_FLTCR) . . . . .928
31.6.5TAMP interrupt enable register (TAMP_IER) . . . . .929
31.6.6TAMP status register (TAMP_SR) . . . . .930
31.6.7TAMP masked interrupt status register (TAMP_MISR) . . . . .931
31.6.8TAMP status clear register (TAMP_SCR) . . . . .932
31.6.9TAMP monotonic counter register (TAMP_COUNTR) . . . . .934
32.9.5I2C timing register (I2C_TIMINGR) . . . . .991
32.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .992
32.9.7I2C interrupt and status register (I2C_ISR) . . . . .993
32.9.8I2C interrupt clear register (I2C_ICR) . . . . .996
32.9.9I2C PEC register (I2C_PECR) . . . . .997
32.9.10I2C receive data register (I2C_RXDR) . . . . .997
32.9.11I2C transmit data register (I2C_TXDR) . . . . .998
32.9.12I2C register map . . . . .999
33Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .1000
33.1USART introduction . . . . .1000
33.2USART main features . . . . .1001
33.3USART extended features . . . . .1002
33.4USART implementation . . . . .1002
33.5USART functional description . . . . .1003
33.5.1USART block diagram . . . . .1003
33.5.2USART signals . . . . .1004
33.5.3USART character description . . . . .1005
33.5.4USART FIFOs and thresholds . . . . .1007
33.5.5USART transmitter . . . . .1007
33.5.6USART receiver . . . . .1011
33.5.7USART baud rate generation . . . . .1018
33.5.8Tolerance of the USART receiver to clock deviation . . . . .1019
33.5.9USART auto baud rate detection . . . . .1021
33.5.10USART multiprocessor communication . . . . .1023
33.5.11USART Modbus communication . . . . .1025
33.5.12USART parity control . . . . .1026
33.5.13USART LIN (local interconnection network) mode . . . . .1027
33.5.14USART synchronous mode . . . . .1029
33.5.15USART single-wire half-duplex communication . . . . .1033
33.5.16USART receiver timeout . . . . .1033
33.5.17USART smartcard mode . . . . .1034
33.5.18USART IrDA SIR ENDEC block . . . . .1038
33.5.19Continuous communication using USART and DMA . . . . .1041
33.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .1043
33.5.21USART low-power management . . . . .1046
33.6USART in low-power modes . . . . .1049
33.7USART interrupts . . . . .1050
33.8USART registers . . . . .1051
33.8.1USART control register 1 (USART_CR1) . . . . .1051
33.8.2USART control register 1 [alternate] (USART_CR1) . . . . .1054
33.8.3USART control register 2 (USART_CR2) . . . . .1058
33.8.4USART control register 3 (USART_CR3) . . . . .1062
33.8.5USART baud rate register (USART_BRR) . . . . .1066
33.8.6USART guard time and prescaler register (USART_GTPR) . . . . .1066
33.8.7USART receiver timeout register (USART_RTOR) . . . . .1067
33.8.8USART request register (USART_RQR) . . . . .1068
33.8.9USART interrupt and status register (USART_ISR) . . . . .1069
33.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .1075
33.8.11USART interrupt flag clear register (USART_ICR) . . . . .1080
33.8.12USART receive data register (USART_RDR) . . . . .1082
33.8.13USART transmit data register (USART_TDR) . . . . .1082
33.8.14USART prescaler register (USART_PRESC) . . . . .1083
33.8.15USART register map . . . . .1084
34Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1086
34.1LPUART introduction . . . . .1086
34.2LPUART main features . . . . .1087
34.3LPUART implementation . . . . .1088
34.4LPUART functional description . . . . .1089
34.4.1LPUART block diagram . . . . .1089
34.4.2LPUART signals . . . . .1090
34.4.3LPUART character description . . . . .1091
34.4.4LPUART FIFOs and thresholds . . . . .1092
34.4.5LPUART transmitter . . . . .1093
34.4.6LPUART receiver . . . . .1096
34.4.7LPUART baud rate generation . . . . .1100
34.4.8Tolerance of the LPUART receiver to clock deviation . . . . .1101
34.4.9LPUART multiprocessor communication . . . . .1102
34.4.10LPUART parity control . . . . .1104
34.4.11LPUART single-wire half-duplex communication . . . . .1105
34.4.12Continuous communication using DMA and LPUART . . . . .1105
34.4.13RS232 hardware flow control and RS485 Driver Enable . . . . .1108
34.4.14LPUART low-power management . . . . .1110
34.5LPUART in low-power modes . . . . .1113
34.6LPUART interrupts . . . . .1114
34.7LPUART registers . . . . .1115
34.7.1LPUART control register 1 (LPUART_CR1) . . . . .1115
34.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1118
34.7.3LPUART control register 2 (LPUART_CR2) . . . . .1121
34.7.4LPUART control register 3 (LPUART_CR3) . . . . .1123
34.7.5LPUART baud rate register (LPUART_BRR) . . . . .1126
34.7.6LPUART request register (LPUART_RQR) . . . . .1126
34.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .1127
34.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1131
34.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1134
34.7.10LPUART receive data register (LPUART_RDR) . . . . .1135
34.7.11LPUART transmit data register (LPUART_TDR) . . . . .1135
34.7.12LPUART prescaler register (LPUART_PRESC) . . . . .1136
34.7.13LPUART register map . . . . .1137
35Serial peripheral interface / integrated interchip sound (SPI/I2S) . . . . .1139
35.1Introduction . . . . .1139
35.2SPI main features . . . . .1139
35.3I2S main features . . . . .1140
35.4SPI/I2S implementation . . . . .1140
35.5SPI functional description . . . . .1141
35.5.1General description . . . . .1141
35.5.2Communications between one master and one slave . . . . .1142
35.5.3Standard multislave communication . . . . .1144
35.5.4Multimaster communication . . . . .1145
35.5.5Slave select (NSS) pin management . . . . .1146
35.5.6Communication formats . . . . .1147
35.5.7Configuration of SPI . . . . .1149
35.5.8Procedure for enabling SPI . . . . .1150
35.5.9Data transmission and reception procedures . . . . .1150
35.5.10SPI status flags . . . . .1160
35.5.11SPI error flags . . . . .1161
36.3.6Serial-wire and JTAG debug port . . . . .1199
36.3.7JTAG debug port . . . . .1200
36.3.8Serial-wire debug port . . . . .1203
36.4Debug port (DP) registers . . . . .1204
36.4.1DP identification register (DP_PIDR) . . . . .1206
36.4.2DP abort register (DP_ABORTR) . . . . .1206
36.4.3DP control and status register (DP_CTRLSTATR) . . . . .1207
36.4.4DP data link control register (DP_DLCR) . . . . .1209
36.4.5DP target identification register (DP_TARGETIDR) . . . . .1210
36.4.6DP data link protocol identification register (DP_DLPIDR) . . . . .1210
36.4.7DP resend register (DP_RESENR) . . . . .1211
36.4.8DP access port select register (DP_SELECTR) . . . . .1211
36.4.9DP read buffer register (DP_BUFFR) . . . . .1212
36.4.10DP target identification register (DP_TARGETSELR) . . . . .1212
36.4.11DP register map and reset values . . . . .1213
36.5Access port . . . . .1214
36.5.1AP control/status word register (AP_CSWR) . . . . .1218
36.5.2AP transfer address register (AP_TAR) . . . . .1219
36.5.3AP data read/write register (AP_DRWR) . . . . .1219
36.5.4AP banked data registers x (AP_BDxR) . . . . .1220
36.5.5AP base address register (AP_BASER) . . . . .1220
36.5.6AP identification register (AP_IDR) . . . . .1221
36.5.7AP register map and reset values . . . . .1221
36.6Data watchpoint and trace unit (DWT) . . . . .1222
36.6.1DWT control register (DWT_CTRLR) . . . . .1223
36.6.2DWT cycle count register (DWT_CYCCNTR) . . . . .1225
36.6.3DWT CPI count register (DWT_CPICNTR) . . . . .1225
36.6.4DWT exception count register (DWT_EXCCNTR) . . . . .1225
36.6.5DWT sleep count register (DWT_SLP CNTR) . . . . .1226
36.6.6DWT LSU count register (DWT_LSUCNTR) . . . . .1226
36.6.7DWT fold count register (DWT_FOLDCNTR) . . . . .1226
36.6.8DWT program counter sample register (DWT_PCSR) . . . . .1227
36.6.9DWT comparator register x (DWT_COMPxR) . . . . .1227
36.6.10DWT mask register x (DWT_MASKxR) . . . . .1227
36.6.11DWT function register x (DWT_FUNCTxR) . . . . .1228
36.6.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1229
36.6.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1229
36.6.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1230
36.6.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1230
36.6.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1231
36.6.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1231
36.6.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1231
36.6.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1232
36.6.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1232
36.6.21DWT register map . . . . .1233
36.7ROM table . . . . .1235
36.7.1ROM memory type register (ROM_MEMTYPER) . . . . .1236
36.7.2ROM CoreSight peripheral identity register 4 (ROM_PIDR4) . . . . .1237
36.7.3ROM CoreSight peripheral identity register 0 (ROM_PIDR0) . . . . .1237
36.7.4ROM CoreSight peripheral identity register 1 (ROM_PIDR1) . . . . .1238
36.7.5ROM CoreSight peripheral identity register 2 (ROM_PIDR2) . . . . .1238
36.7.6ROM CoreSight peripheral identity register 3 (ROM_PIDR3) . . . . .1239
36.7.7ROM CoreSight component identity register 0 (ROM_CIDR0) . . . . .1239
36.7.8ROM CoreSight peripheral identity register 1 (ROM_CIDR1) . . . . .1240
36.7.9ROM CoreSight component identity register 2 (ROM_CIDR2) . . . . .1240
36.7.10ROM CoreSight component identity register 3 (ROM_CIDR3) . . . . .1241
36.7.11ROM table register map . . . . .1241
36.8Breakpoint unit (FPB) . . . . .1242
36.8.1FPB control register (FPB_CTRLR) . . . . .1242
36.8.2FPB remap register (FPB_REMAPR) . . . . .1243
36.8.3FPB comparator register x (FPB_COMPxR) . . . . .1243
36.8.4FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . .1244
36.8.5FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . .1245
36.8.6FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . .1245
36.8.7FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . .1246
36.8.8FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . .1246
36.8.9FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . .1247
36.8.10FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . .1247
36.8.11FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . .1248
36.8.12FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . .1248
36.8.13FPB register map . . . . .1248
36.9Instrumentation trace macrocell (ITM) . . . . .1250
36.9.1ITM stimulus register x (ITM_STIMRx) . . . . .1250
36.9.2ITM trace enable register (ITM_TER) . . . . .1251
36.9.3ITM trace privilege register (ITM_TPR) . . . . .1251
36.9.4ITM trace control register (ITM_TCR) . . . . .1252
36.9.5ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .1253
36.9.6ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .1253
36.9.7ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .1254
36.9.8ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .1254
36.9.9ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .1255
36.9.10ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .1255
36.9.11ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .1256
36.9.12ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .1256
36.9.13ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .1257
36.9.14ITM register map . . . . .1257
36.10Trace port interface unit (TPIU) . . . . .1258
36.10.1TPIU supported port size register (TPIU_SSPSR) . . . . .1259
36.10.2TPIU current port size register (TPIU_CSPSR) . . . . .1259
36.10.3TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .1259
36.10.4TPIU selected pin protocol register (TPIU_SPPR) . . . . .1260
36.10.5TPIU formatter and flush status register (TPIU_FFSR) . . . . .1260
36.10.6TPIU formatter and flush control register (TPIU_FFCR) . . . . .1261
36.10.7TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .1262
36.10.8TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .1262
36.10.9TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .1263
36.10.10TPIU device configuration register (TPIU_DEVIDR) . . . . .1263
36.10.11TPIU device type identifier register (TPIU_DEVTYPE) . . . . .1264
36.10.12TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .1264
36.10.13TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .1265
36.10.14TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .1265
36.10.15TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .1266
36.10.16TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .1266
36.10.17TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .1267
36.10.18TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .1267
36.10.19TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .1268
36.10.20TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .1268
36.10.21TPIU register map . . . . .1268
36.11Microcontroller debug unit (DBGMCU) . . . . .1270
36.11.1DBGMCU identity code register (DBGMCU_IDCODER) . . . . .1271
36.11.2DBGMCU configuration register (DBGMCU_CR) . . . . .1271

List of tables

Table 1.Device boot mode . . . . .59
Table 2.SRAM erase conditions . . . . .61
Table 3.Memory map and peripheral register boundary addresses . . . . .64
Table 4.Flash memory - Single bank organization . . . . .70
Table 5.Number of wait states according to flash clock (HCLK3) frequency . . . . .72
Table 6.Page erase overview . . . . .76
Table 7.Mass erase overview . . . . .77
Table 8.Errors in page-based row programming . . . . .81
Table 9.Option bytes organization . . . . .82
Table 10.Option loading control . . . . .84
Table 11.Flash memory readout protection status . . . . .85
Table 12.RDP regression from level 1 to level 0 and memory erase . . . . .87
Table 13.Access status versus protection level and execution modes . . . . .87
Table 16.Flash interrupt requests . . . . .91
Table 17.Flash interface register map and reset values . . . . .104
Table 18.Sub-GHz internal input/output signals . . . . .107
Table 19.Sub-GHz radio transmit high output power . . . . .109
Table 20.FSK mode intermediate frequencies . . . . .110
Table 21.LoRa mode intermediate frequencies . . . . .111
Table 22.Spreading factor, chips/symbol and LoRa SNR . . . . .113
Table 23.LoRa bandwidth setting . . . . .113
Table 24.Coding rate and overhead ratio . . . . .114
Table 25.Operation mode transition BUSY switching time . . . . .126
Table 26.Command structure . . . . .127
Table 27.PA optimal setting and operating modes . . . . .137
Table 28.Recommended CAD configuration settings . . . . .138
Table 29.IRQ bit mapping and definition . . . . .148
Table 30.Image calibration for ISM bands . . . . .151
Table 31.Command format Set_TcxoMode() . . . . .153
Table 32.RegTcxoTrim and Timeout bytes definition . . . . .154
Table 33.Sub-GHz radio SPI commands overview . . . . .154
Table 34.SUBGHZ register map and reset values . . . . .177
Table 35.PVM features . . . . .187
Table 36.Low-power mode summary . . . . .191
Table 37.Functionalities depending on system operating mode . . . . .192
Table 38.MCU and sub-GHz radio operating modes . . . . .195
Table 39.LPRun . . . . .197
Table 40.CPU wakeup versus system operating mode . . . . .198
Table 41.Sleep mode . . . . .199
Table 42.LPSleep . . . . .200
Table 43.Stop 0 mode . . . . .202
Table 44.Stop 1 mode . . . . .203
Table 45.Stop 2 mode . . . . .205
Table 46.Standby mode . . . . .207
Table 47.Shutdown mode . . . . .208
Table 48.PWR register map and reset values . . . . .224
Table 49.Clock source stabilization times . . . . .237
Table 50.Clock source frequency . . . . .238
Table 51.SPI2S2 I2S clock PLL configurations . . . . .239
Table 52.Sub-GHz radio SPI clock configurations . . . . .239
Table 53.Peripheral clock enable . . . . .244
Table 54.Low-power debug configurations . . . . .245
Table 55.RCC register map and reset values . . . . .286
Table 56.HSEM internal input/output signals . . . . .291
Table 57.Authorized AHB bus master ID . . . . .296
Table 58.HSEM register map and reset values . . . . .302
Table 59.Port bit configurations . . . . .305
Table 60.GPIOA register map and reset values . . . . .330
Table 61.GPIOB register map and reset values . . . . .331
Table 62.GPIOC register map and reset values . . . . .332
Table 63.GPIOH register map and reset values . . . . .333
Table 64.SYSCFG register map and reset values . . . . .342
Table 65.STM32WLEx peripherals interconnect matrix . . . . .344
Table 66.DMA1 and DMA2 implementation . . . . .353
Table 67.DMA internal input/output signals . . . . .355
Table 68.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .361
Table 69.DMA interrupt requests . . . . .363
Table 70.DMA register map and reset values . . . . .372
Table 71.DMAMUX instantiation . . . . .376
Table 72.DMAMUX1: assignment of multiplexer inputs to resources . . . . .377
Table 73.DMAMUX1: assignment of trigger inputs to resources . . . . .377
Table 74.DMAMUX1: assignment of synchronization inputs to resources . . . . .378
Table 75.DMAMUX signals . . . . .380
Table 76.DMAMUX interrupts . . . . .385
Table 77.DMAMUX register map and reset values . . . . .391
Table 78.Vector table . . . . .393
Table 79.EXTI pin overview . . . . .397
Table 80.EVG pin overview . . . . .397
Table 81.Wake-up interrupts . . . . .398
Table 82.EXTI event input configurations and register control . . . . .400
Table 83.Masking functionality . . . . .402
Table 84.EXTI register map sections . . . . .403
Table 85.EXTI register map and reset values . . . . .411
Table 86.CRC internal input/output signals . . . . .414
Table 87.CRC register map and reset values . . . . .419
Table 88.ADC input/output pins . . . . .422
Table 89.ADC internal input/output signals . . . . .423
Table 90.External triggers . . . . .423
Table 91.Latency between trigger and start of conversion . . . . .428
Table 92.Configuring the trigger polarity . . . . .435
Table 93.tSAR timings depending on resolution . . . . .437
Table 94.Analog watchdog comparison . . . . .446
Table 95.Analog watchdog 1 channel selection . . . . .446
Table 96.Maximum output results vs N and M. Grayed values indicates truncation . . . . .451
Table 97.ADC interrupts . . . . .456
Table 98.ADC register map and reset values . . . . .475
Table 99.DAC features . . . . .479
Table 100.DAC input/output pins . . . . .480
Table 101.DAC internal input/output signals . . . . .480
Table 102.DAC interconnection . . . . .480
Table 103.Sample and refresh timings . . . . .487
Table 104.Channel output modes summary . . . . .488
Table 105.Effect of low-power modes on DAC . . . . .491
Table 106.DAC interrupts . . . . .491
Table 107.DAC register map and reset values . . . . .500
Table 108.VREF buffer modes . . . . .502
Table 109.VREFBUF register map and reset values. . . . .505
Table 110.COMP1 input plus assignment . . . . .507
Table 111.COMP1 input minus assignment . . . . .508
Table 112.COMP2 input plus assignment . . . . .508
Table 113.COMP2 input minus assignment . . . . .508
Table 114.Comparator behavior in the low-power modes . . . . .512
Table 115.Interrupt control bits . . . . .512
Table 116.COMP register map and reset values. . . . .517
Table 117.RNG internal input/output signals . . . . .519
Table 118.RNG interrupt requests. . . . .526
Table 119.RNG configurations . . . . .527
Table 120.Configuration selection . . . . .528
Table 121.RNG register map and reset map. . . . .532
Table 122.AES internal input/output signals . . . . .534
Table 123.CTR mode initialization vector definition. . . . .550
Table 124.GCM last block definition . . . . .552
Table 125.Initialization of AES_IVRx registers in GCM mode . . . . .553
Table 126.Initialization of AES_IVRx registers in CCM mode . . . . .560
Table 127.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .565
Table 128.AES interrupt requests . . . . .568
Table 129.Processing latency for ECB, CBC and CTR. . . . .568
Table 130.Processing latency for GCM and CCM (in clock cycles). . . . .569
Table 131.AES register map and reset values . . . . .579
Table 132.Internal input/output signals . . . . .582
Table 133.PKA integer arithmetic functions list . . . . .583
Table 134.PKA prime field (Fp) elliptic curve functions list . . . . .583
Table 135.Montgomery parameter computation . . . . .588
Table 136.Modular addition . . . . .589
Table 137.Modular subtraction . . . . .589
Table 138.Montgomery multiplication . . . . .590
Table 139.Modular exponentiation (normal mode) . . . . .591
Table 140.Modular exponentiation (fast mode) . . . . .591
Table 141.Modular inversion . . . . .591
Table 142.Modular reduction . . . . .592
Table 143.Arithmetic addition . . . . .592
Table 144.Arithmetic subtraction . . . . .592
Table 145.Arithmetic multiplication . . . . .593
Table 146.Arithmetic comparison . . . . .593
Table 147.CRT exponentiation . . . . .594
Table 148.Point on elliptic curve Fp check . . . . .595
Table 149.ECC Fp scalar multiplication. . . . .595
Table 150.ECC Fp scalar multiplication (Fast Mode) . . . . .596
Table 151.ECDSA sign - Inputs . . . . .597
Table 152.ECDSA sign - Outputs . . . . .597
Table 153.Extended ECDSA sign (extra outputs) . . . . .598
Table 154.ECDSA verification (inputs) . . . . .598
Table 155.ECDSA verification (outputs) . . . . .598
Table 156.Family of supported curves for ECC operations . . . . .599
Table 157.Modular exponentiation computation times . . . . .601
Table 158.ECC scalar multiplication computation times . . . . .601
Table 159.ECDSA signature average computation times . . . . .601
Table 160.ECDSA verification average computation times . . . . .602
Table 161.Point on elliptic curve Fp check average computation times . . . . .602
Table 162.Montgomery parameters average computation times . . . . .602
Table 163.PKA interrupt requests . . . . .602
Table 164.PKA register map and reset values . . . . .606
Table 165.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .649
Table 166.Break protection disarming conditions . . . . .651
Table 167.Counting direction versus encoder signals . . . . .657
Table 168.TIM1 internal trigger connection . . . . .674
Table 169.Output control bits for complementary OCx and OCxN channels with break feature . . . . .688
Table 170.TIM1 register map and reset values . . . . .705
Table 171.Counting direction versus encoder signals . . . . .741
Table 172.TIM2 internal trigger connection . . . . .759
Table 173.Output control bit for standard OCx channels . . . . .770
Table 174.TIM2 register map and reset values . . . . .777
Table 175.Break protection disarming conditions . . . . .802
Table 176.Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . .		819
Table 177.TIM16/TIM17 register map and reset values . . . . .830
Table 178.STM32WLEEx LPTIM features . . . . .832
Table 179.LPTIM input/output pins . . . . .833
Table 180.LPTIM internal signals . . . . .834
Table 181.LPTIM1 external trigger connections . . . . .834
Table 182.LPTIM2 external trigger connections . . . . .834
Table 183.LPTIM3 external trigger connections . . . . .835
Table 184.LPTIM1 input 1 connections . . . . .835
Table 185.LPTIM1 input 2 connections . . . . .835
Table 186.LPTIM2 input 1 connections . . . . .835
Table 187.LPTIM3 input 1 connections . . . . .835
Table 188.Prescaler division ratios . . . . .837
Table 189.Encoder counting scenarios . . . . .844
Table 190.Effect of low-power modes on the LPTIM . . . . .847
Table 191.Interrupt events . . . . .847
Table 192.LPTIM register map and reset values . . . . .858
Table 193.IWDG register map and reset values . . . . .869
Table 194.WWDG internal input/output signals . . . . .871
Table 195.WWDG register map and reset values . . . . .875
Table 196.RTC input/output pins . . . . .878
Table 197.RTC internal input/output signals . . . . .878
Table 198.RTC interconnection . . . . .879
Table 199.PC13 configuration . . . . .879
Table 200.RTC_OUT mapping . . . . .881
Table 201.Effect of low-power modes on RTC . . . . .894
Table 202.RTC pins functionality over modes . . . . .894
Table 203.Interrupt requests . . . . .895
Table 204.RTC register map and reset values . . . . .917
Table 205.TAMP input/output pins . . . . .921
Table 206.TAMP internal input/output signals . . . . .921
Table 207.TAMP interconnection . . . . .921
Table 208.Effect of low-power modes on TAMP . . . . .924
Table 209.Interrupt requests . . . . .924
Table 210.TAMP register map and reset values . . . . .935
Table 211.I2C implementation . . . . .937
Table 212.I2C input/output pins . . . . .938
Table 213.I2C internal input/output signals . . . . .939
Table 214.Comparison of analog and digital filters . . . . .941
Table 215.I 2 C-bus and SMBus specification data setup and hold times . . . . .943
Table 216.I2C configuration . . . . .947
Table 217.I 2 C-bus and SMBus specification clock timings . . . . .958
Table 218.Timing settings for f I2CCLK of 8 MHz . . . . .968
Table 219.Timing settings for f I2CCLK of 16 MHz . . . . .968
Table 220.SMBus timeout specifications . . . . .970
Table 221.SMBus with PEC configuration . . . . .972
Table 222.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .973
Table 223.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .973
Table 224.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .973
Table 225.Effect of low-power modes to I2C . . . . .983
Table 226.I2C interrupt requests . . . . .983
Table 227.I2C register map and reset values . . . . .999
Table 228.USART / LPUART features . . . . .1002
Table 229.USART/UART input/output pins . . . . .1005
Table 230.USART internal input/output signals . . . . .1005
Table 231.Noise detection from sampled data . . . . .1017
Table 232.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1020
Table 233.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1021
Table 234.USART frame formats . . . . .1026
Table 235.Effect of low-power modes on the USART . . . . .1049
Table 236.USART interrupt requests . . . . .1050
Table 237.USART register map and reset values . . . . .1084
Table 238.USART / LPUART features . . . . .1088
Table 239.LPUART input/output pins . . . . .1090
Table 240.LPUART internal input/output signals . . . . .1090
Table 241.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .1100
Table 242.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .1101
Table 243.Tolerance of the LPUART receiver . . . . .1102
Table 245.Effect of low-power modes on the LPUART . . . . .1113
Table 246.LPUART interrupt requests . . . . .1114
Table 247.LPUART register map and reset values . . . . .1137
Table 248.STM32WLEn SPI and SPI/I2S implementation . . . . .1140
Table 249.SPI interrupt requests . . . . .1165
Table 250.Audio-frequency precision using 48 MHz clock derived from HSE . . . . .1178
Table 251.I2S interrupt requests . . . . .1184
Table 252.SPI/I2S register map and reset values . . . . .1196
Table 253.JTAG/Serial-wire debug port pins . . . . .1198
Table 254.Single-wire trace port pins . . . . .1198
Table 255.JTAG-DP data registers . . . . .1202
Table 256.Packet request . . . . .1203
Table 257.ACK response . . . . .1204
Table 258.Data transfer . . . . .1204
Table 259. Debug port registers . . . . .1205
Table 260. DP register map and reset values . . . . .1213
Table 261. MEM-AP registers. . . . .1215
Table 262. AP register map and reset values. . . . .1221
Table 263. DWT register map and reset values . . . . .1233
Table 264. ROM table. . . . .1235
Table 265. ROM table register map and reset values . . . . .1241
Table 266. FPB register map and reset values . . . . .1248
Table 267. ITM register map and reset values . . . . .1257
Table 268. TPIU register map and reset values . . . . .1268
Table 269. DBGMCU register map and reset values . . . . .1274
Table 270. Document revision history . . . . .1281

List of figures

Figure 1.System architecture . . . . .58
Figure 2.Memory map . . . . .63
Figure 3.Sequential 16 bits instructions execution . . . . .74
Figure 4.Changing the RDP level . . . . .87
Figure 5.Sub-GHz radio system block diagram . . . . .107
Figure 6.High output power PA . . . . .108
Figure 7.Low output power PA . . . . .109
Figure 8.LoRa packet frames format . . . . .115
Figure 9.Generic packet frames format . . . . .118
Figure 10.Sub-GHz RAM data buffer operation . . . . .120
Figure 11.Sub-GHz radio operating modes . . . . .122
Figure 12.Sub-GHz radio BUSY timing . . . . .126
Figure 13.Receiver listening mode timing . . . . .132
Figure 14.Power supply overview . . . . .180
Figure 15.Supply configurations . . . . .181
Figure 16.Brownout reset waveform . . . . .186
Figure 17.PVD thresholds . . . . .187
Figure 18.EOL thresholds . . . . .188
Figure 19.Radio busy management . . . . .189
Figure 20.Simplified diagram of the reset circuit . . . . .227
Figure 21.Clock tree . . . . .230
Figure 22.HSE32 clock sources . . . . .232
Figure 23.HSE32 TCXO control . . . . .233
Figure 24.LSE clock sources . . . . .236
Figure 25.Frequency measurement with TIM16 in capture mode . . . . .242
Figure 26.Frequency measurement with TIM17 in capture mode . . . . .242
Figure 27.HSEM block diagram . . . . .291
Figure 28.Procedure state diagram . . . . .292
Figure 29.Interrupt state diagram . . . . .295
Figure 30.Basic structure of a standard I/O port bit . . . . .304
Figure 31.Basic structure of a 5V-tolerant I/O port bit . . . . .305
Figure 32.Input floating/pull-up/pull-down configurations . . . . .309
Figure 33.Output configuration . . . . .310
Figure 34.Alternate function configuration . . . . .310
Figure 35.High impedance analog configuration . . . . .311
Figure 36.DMA block diagram . . . . .354
Figure 37.DMAMUX block diagram . . . . .379
Figure 38.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .382
Figure 39.Event generation of the DMA request line multiplexer channel . . . . .383
Figure 40.EXTI block diagram . . . . .397
Figure 41.Configurable event trigger logic CPU wake-up . . . . .401
Figure 42.Direct event trigger logic CPU wake-up . . . . .402
Figure 43.CRC calculation unit block diagram . . . . .414
Figure 44.ADC block diagram . . . . .422
Figure 45.ADC calibration . . . . .425
Figure 46.Calibration factor forcing . . . . .425
Figure 47.Enabling/disabling the ADC . . . . .426
Figure 48.ADC clock scheme . . . . .427
Figure 49.ADC connectivity . . . . .429
Figure 50.Analog-to-digital conversion time . . . . .434
Figure 51.ADC conversion timings . . . . .434
Figure 52.Stopping an ongoing conversion . . . . .435
Figure 53.Single conversions of a sequence, software trigger . . . . .438
Figure 54.Continuous conversion of a sequence, software trigger . . . . .438
Figure 55.Single conversions of a sequence, hardware trigger . . . . .439
Figure 56.Continuous conversions of a sequence, hardware trigger . . . . .439
Figure 57.Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .440
Figure 58.Example of overrun (OVR) . . . . .441
Figure 59.Wait mode conversion (continuous mode, software trigger) . . . . .444
Figure 60.Behavior with WAIT = 0, AUTOFF = 1 . . . . .445
Figure 61.Behavior with WAIT = 1, AUTOFF = 1 . . . . .445
Figure 62.Analog watchdog guarded area . . . . .446
Figure 63.ADC_AWDx_OUT signal generation . . . . .448
Figure 64.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .448
Figure 65.ADC_AWDx_OUT signal generation (on a single channel) . . . . .449
Figure 66.Analog watchdog threshold update . . . . .449
Figure 67.20-bit to 16-bit result truncation . . . . .450
Figure 68.Numerical example with 5-bit shift and rounding . . . . .450
Figure 69.Triggered oversampling mode (TOVS bit = 1) . . . . .452
Figure 70.Temperature sensor and VREFINT channel block diagram . . . . .453
Figure 71.VBAT channel block diagram . . . . .455
Figure 72.DAC block diagram . . . . .479
Figure 73.Data registers in single DAC channel mode . . . . .481
Figure 74.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .482
Figure 75.DAC LFSR register calculation algorithm . . . . .484
Figure 76.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .484
Figure 77.DAC triangle wave generation . . . . .485
Figure 78.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .485
Figure 79.DAC sample and hold mode phase diagram . . . . .488
Figure 80.Comparator block diagram . . . . .507
Figure 81.Window mode . . . . .510
Figure 82.Comparator hysteresis . . . . .510
Figure 83.Comparator output blanking . . . . .511
Figure 84.RNG block diagram . . . . .519
Figure 85.NIST SP800-90B entropy source model . . . . .520
Figure 86.RNG initialization overview . . . . .523
Figure 87.AES block diagram . . . . .534
Figure 88.ECB encryption and decryption principle . . . . .536
Figure 89.CBC encryption and decryption principle . . . . .537
Figure 90.CTR encryption and decryption principle . . . . .538
Figure 91.GCM encryption and authentication principle . . . . .539
Figure 92.GMAC authentication principle . . . . .539
Figure 93.CCM encryption and authentication principle . . . . .540
Figure 94.Example of suspend mode management . . . . .544
Figure 95.ECB encryption . . . . .545
Figure 96.ECB decryption . . . . .545
Figure 97.CBC encryption . . . . .546
Figure 98.CBC decryption . . . . .546
Figure 99.ECB/CBC encryption (Mode 1) . . . . .547
Figure 100.ECB/CBC decryption (Mode 3) . . . . .548
Figure 101. Message construction in CTR mode . . . . .549
Figure 102. CTR encryption . . . . .550
Figure 103. CTR decryption . . . . .550
Figure 104. Message construction in GCM . . . . .552
Figure 105. GCM authenticated encryption . . . . .553
Figure 106. Message construction in GMAC mode . . . . .557
Figure 107. GMAC authentication mode . . . . .557
Figure 108. Message construction in CCM mode . . . . .558
Figure 109. CCM mode authenticated encryption . . . . .560
Figure 110. 128-bit block construction with respect to data swap . . . . .564
Figure 111. DMA transfer of a 128-bit data block during input phase . . . . .566
Figure 112. DMA transfer of a 128-bit data block during output phase . . . . .567
Figure 113. PKA block diagram . . . . .582
Figure 114. Advanced-control timer block diagram . . . . .609
Figure 115. Counter timing diagram with prescaler division change from 1 to 2 . . . . .611
Figure 116. Counter timing diagram with prescaler division change from 1 to 4 . . . . .611
Figure 117. Counter timing diagram, internal clock divided by 1 . . . . .613
Figure 118. Counter timing diagram, internal clock divided by 2 . . . . .613
Figure 119. Counter timing diagram, internal clock divided by 4 . . . . .614
Figure 120. Counter timing diagram, internal clock divided by N . . . . .614
Figure 121. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .615
Figure 122. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .615
Figure 123. Counter timing diagram, internal clock divided by 1 . . . . .617
Figure 124. Counter timing diagram, internal clock divided by 2 . . . . .617
Figure 125. Counter timing diagram, internal clock divided by 4 . . . . .618
Figure 126. Counter timing diagram, internal clock divided by N . . . . .618
Figure 127. Counter timing diagram, update event when repetition counter is not used . . . . .619
Figure 128. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .620
Figure 129. Counter timing diagram, internal clock divided by 2 . . . . .621
Figure 130. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .621
Figure 131. Counter timing diagram, internal clock divided by N . . . . .622
Figure 132. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .622
Figure 133. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .623
Figure 134. Update rate examples depending on mode and TIMx_RCR register settings . . . . .624
Figure 135. External trigger input block . . . . .625
Figure 136. TIM1 ETR input circuitry . . . . .625
Figure 137. Control circuit in normal mode, internal clock divided by 1 . . . . .626
Figure 138. TI2 external clock connection example . . . . .627
Figure 139. Control circuit in external clock mode 1 . . . . .628
Figure 140. External trigger input block . . . . .628
Figure 141. Control circuit in external clock mode 2 . . . . .629
Figure 142. Capture/compare channel (example: channel 1 input stage) . . . . .630
Figure 143. Capture/compare channel 1 main circuit . . . . .630
Figure 144. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .631
Figure 145. Output stage of capture/compare channel (channel 4) . . . . .631
Figure 146. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .632
Figure 147. PWM input mode timing . . . . .634
Figure 148. Output compare mode, toggle on OC1 . . . . .636
Figure 149. Edge-aligned PWM waveforms (ARR=8) . . . . .637
Figure 150. Center-aligned PWM waveforms (ARR=8) . . . . .638
Figure 151. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .640
Figure 152. Combined PWM mode on channel 1 and 3 . . . . .641
Figure 153. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .642
Figure 154. Complementary output with dead-time insertion . . . . .643
Figure 155. Dead-time waveforms with delay greater than the negative pulse . . . . .643
Figure 156. Dead-time waveforms with delay greater than the positive pulse. . . . .644
Figure 157. Break and Break2 circuitry overview . . . . .646
Figure 158. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .648
Figure 159. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .649
Figure 160. PWM output state following BRK assertion (OSSI=0) . . . . .650
Figure 161. Output redirection (BRK2 request not represented) . . . . .651
Figure 162. Clearing TIMx OCxREF . . . . .652
Figure 163. 6-step generation, COM example (OSSR=1) . . . . .653
Figure 164. Example of one pulse mode. . . . .654
Figure 165. Retriggerable one pulse mode . . . . .656
Figure 166. Example of counter operation in encoder interface mode. . . . .657
Figure 167. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .658
Figure 168. Measuring time interval between edges on 3 signals . . . . .659
Figure 169. Example of Hall sensor interface . . . . .661
Figure 170. Control circuit in reset mode . . . . .662
Figure 171. Control circuit in Gated mode . . . . .663
Figure 172. Control circuit in trigger mode . . . . .664
Figure 173. Control circuit in external clock mode 2 + trigger mode . . . . .665
Figure 174. General-purpose timer block diagram . . . . .709
Figure 175. Counter timing diagram with prescaler division change from 1 to 2 . . . . .711
Figure 176. Counter timing diagram with prescaler division change from 1 to 4 . . . . .711
Figure 177. Counter timing diagram, internal clock divided by 1 . . . . .712
Figure 178. Counter timing diagram, internal clock divided by 2 . . . . .713
Figure 179. Counter timing diagram, internal clock divided by 4 . . . . .713
Figure 180. Counter timing diagram, internal clock divided by N . . . . .714
Figure 181. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .714
Figure 182. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .715
Figure 183. Counter timing diagram, internal clock divided by 1 . . . . .716
Figure 184. Counter timing diagram, internal clock divided by 2 . . . . .716
Figure 185. Counter timing diagram, internal clock divided by 4 . . . . .717
Figure 186. Counter timing diagram, internal clock divided by N . . . . .717
Figure 187. Counter timing diagram, Update event . . . . .718
Figure 188. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .719
Figure 189. Counter timing diagram, internal clock divided by 2 . . . . .720
Figure 190. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .720
Figure 191. Counter timing diagram, internal clock divided by N . . . . .721
Figure 192. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .721
Figure 193. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .722
Figure 194. Control circuit in normal mode, internal clock divided by 1 . . . . .723
Figure 195. TI2 external clock connection example. . . . .723
Figure 196. Control circuit in external clock mode 1 . . . . .724
Figure 197. External trigger input block . . . . .725
Figure 198. Control circuit in external clock mode 2 . . . . .726
Figure 199. Capture/Compare channel (example: channel 1 input stage) . . . . .726
Figure 200. Capture/Compare channel 1 main circuit . . . . .727
Figure 201. Output stage of Capture/Compare channel (channel 1). . . . .727
Figure 202. PWM input mode timing . . . . .729
Figure 203. Output compare mode, toggle on OC1 . . . . .731
Figure 204. Edge-aligned PWM waveforms (ARR=8) . . . . .732
Figure 205. Center-aligned PWM waveforms (ARR=8) . . . . .734
Figure 206. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .735
Figure 207. Combined PWM mode on channels 1 and 3 . . . . .736
Figure 208. Clearing TIMx_OCxREF . . . . .737
Figure 209. Example of one-pulse mode. . . . .738
Figure 210. Retriggerable one-pulse mode . . . . .740
Figure 211. Example of counter operation in encoder interface mode . . . . .741
Figure 212. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .742
Figure 213. Control circuit in reset mode . . . . .743
Figure 214. Control circuit in gated mode . . . . .744
Figure 215. Control circuit in trigger mode. . . . .745
Figure 216. Control circuit in external clock mode 2 + trigger mode . . . . .746
Figure 217. Master/Slave timer example . . . . .747
Figure 218. Master/slave connection example with 1 channel only timers . . . . .747
Figure 219. Gating TIM2 with OC1REF of TIM1 . . . . .748
Figure 220. Gating TIM2 with Enable of TIM1 . . . . .749
Figure 221. Triggering TIM2 with update of TIM1 . . . . .750
Figure 222. Triggering TIM2 with Enable of TIM1 . . . . .750
Figure 223. TIM16/TIM17 block diagram . . . . .781
Figure 224. Counter timing diagram with prescaler division change from 1 to 2 . . . . .783
Figure 225. Counter timing diagram with prescaler division change from 1 to 4 . . . . .783
Figure 226. Counter timing diagram, internal clock divided by 1 . . . . .785
Figure 227. Counter timing diagram, internal clock divided by 2 . . . . .785
Figure 228. Counter timing diagram, internal clock divided by 4 . . . . .786
Figure 229. Counter timing diagram, internal clock divided by N . . . . .786
Figure 230. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .787
Figure 231. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .787
Figure 232. Update rate examples depending on mode and TIMx_RCR register settings . . . . .789
Figure 233. Control circuit in normal mode, internal clock divided by 1 . . . . .790
Figure 234. TI2 external clock connection example. . . . .790
Figure 235. Control circuit in external clock mode 1 . . . . .791
Figure 236. Capture/compare channel (example: channel 1 input stage) . . . . .792
Figure 237. Capture/compare channel 1 main circuit . . . . .792
Figure 238. Output stage of capture/compare channel (channel 1). . . . .793
Figure 239. Output compare mode, toggle on OC1 . . . . .796
Figure 240. Edge-aligned PWM waveforms (ARR=8) . . . . .797
Figure 241. Complementary output with dead-time insertion. . . . .798
Figure 242. Dead-time waveforms with delay greater than the negative pulse. . . . .798
Figure 243. Dead-time waveforms with delay greater than the positive pulse. . . . .799
Figure 244. Output behavior in response to a break . . . . .801
Figure 245. Output redirection . . . . .803
Figure 246. 6-step generation, COM example (OSSR=1) . . . . .804
Figure 247. Example of one pulse mode . . . . .805
Figure 248. Low-power timer block diagram . . . . .833
Figure 249. Glitch filter timing diagram . . . . .837
Figure 250. LPTIM output waveform, single-counting mode configuration when repetition register content is different than zero (with PRELOAD = 1) . . . . .838
Figure 251. LPTIM output waveform, single-counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .839
Figure 252. LPTIM output waveform, Continuous counting mode configuration . . . . .839
Figure 253. Waveform generation . . . . .841
Figure 254. Encoder mode counting sequence . . . . .845
Figure 255. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1). . . . .846
Figure 256. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .860
Figure 257. Independent watchdog block diagram . . . . .861
Figure 258. Watchdog block diagram . . . . .871
Figure 259. Window watchdog timing diagram . . . . .872
Figure 260. RTC block diagram . . . . .877
Figure 261. TAMP block diagram . . . . .920
Figure 262. Block diagram . . . . .938
Figure 263. I 2 C-bus protocol . . . . .940
Figure 264. Setup and hold timings . . . . .942
Figure 265. I2C initialization flow . . . . .944
Figure 266. Data reception . . . . .945
Figure 267. Data transmission . . . . .946
Figure 268. Target initialization flow . . . . .949
Figure 269. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .951
Figure 270. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .952
Figure 271. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .953
Figure 272. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .954
Figure 273. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .955
Figure 274. Transfer bus diagrams for I2C target receiver (mandatory events only) . . . . .955
Figure 275. Controller clock generation . . . . .957
Figure 276. Controller initialization flow . . . . .959
Figure 277. 10-bit address read access with HEAD10R = 0 . . . . .959
Figure 278. 10-bit address read access with HEAD10R = 1 . . . . .960
Figure 279. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .961
Figure 280. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .962
Figure 281. Transfer bus diagrams for I2C controller transmitter (mandatory events only) . . . . .963
Figure 282. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .965
Figure 283. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .966
Figure 284. Transfer bus diagrams for I2C controller receiver (mandatory events only) . . . . .967
Figure 285. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .971
Figure 286. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .974
Figure 287. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .975
Figure 288. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .976
Figure 289. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .977
Figure 290. Bus transfer diagrams for SMBus controller transmitter . . . . .978
Figure 291. Bus transfer diagrams for SMBus controller receiver . . . . .980
Figure 292. USART block diagram . . . . .1003
Figure 293. Word length programming . . . . .1006
Figure 294. Configurable stop bits . . . . .1008
Figure 295. TC/TXE behavior when transmitting . . . . .1011
Figure 296. Start bit detection when oversampling by 16 or 8. . . . .1012
Figure 297. usart_ker_ck clock divider block diagram. . . . .1015
Figure 298. Data sampling when oversampling by 16. . . . .1016
Figure 299. Data sampling when oversampling by 8. . . . .1017
Figure 300. Mute mode using Idle line detection . . . . .1024
Figure 301. Mute mode using address mark detection . . . . .1025
Figure 302. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .1028
Figure 303. Break detection in LIN mode vs. Framing error detection. . . . .1029
Figure 304. USART example of synchronous master transmission. . . . .1030
Figure 305. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1030
Figure 306. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1031
Figure 307. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1032
Figure 308. ISO 7816-3 asynchronous protocol . . . . .1034
Figure 309. Parity error detection using the 1.5 stop bits . . . . .1036
Figure 310. IrDA SIR ENDEC block diagram. . . . .1040
Figure 311. IrDA data modulation (3/16) - normal mode . . . . .1040
Figure 312. Transmission using DMA . . . . .1042
Figure 313. Reception using DMA . . . . .1043
Figure 314. Hardware flow control between 2 USARTs . . . . .1043
Figure 315. RS232 RTS flow control . . . . .1044
Figure 316. RS232 CTS flow control . . . . .1045
Figure 317. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1048
Figure 318. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1048
Figure 319. LPUART block diagram . . . . .1089
Figure 320. LPUART word length programming . . . . .1092
Figure 321. Configurable stop bits . . . . .1094
Figure 322. TC/TXE behavior when transmitting . . . . .1096
Figure 323. lpuart_ker_ck clock divider block diagram . . . . .1099
Figure 324. Mute mode using Idle line detection . . . . .1103
Figure 325. Mute mode using address mark detection . . . . .1104
Figure 326. Transmission using DMA . . . . .1106
Figure 327. Reception using DMA . . . . .1107
Figure 328. Hardware flow control between 2 LPUARTs . . . . .1108
Figure 329. RS232 RTS flow control . . . . .1108
Figure 330. RS232 CTS flow control . . . . .1109
Figure 331. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		1112
Figure 332. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1112
Figure 333. SPI block diagram. . . . .1141
Figure 334. Full-duplex single master/ single slave application. . . . .1142
Figure 335. Half-duplex single master/ single slave application . . . . .1143
Figure 336. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1144
Figure 337. Master and three independent slaves. . . . .1145
Figure 338. Multimaster application . . . . .1146
Figure 339. Hardware/software slave select management . . . . .1147
Figure 340. Data clock timing diagram . . . . .1148
Figure 341. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1149
Figure 342. Packing data in FIFO for transmission and reception. . . . .1153
Figure 343. Master full-duplex communication . . . . .1156
Figure 344. Slave full-duplex communication . . . . .1157
Figure 345. Master full-duplex communication with CRC . . . . .1158
Figure 346. Master full-duplex communication in packed mode . . . . .1159
Figure 347. NSSP pulse generation in Motorola SPI master mode . . . . .1162
Figure 348. TI mode transfer . . . . .1163
Figure 349. I2S block diagram . . . . .1166
Figure 350. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .1168
Figure 351. I 2 S Philips standard waveforms (24-bit frame) . . . . .1168
Figure 352. Transmitting 0x8EAA33 . . . . .1169
Figure 353. Receiving 0x8EAA33 . . . . .1169
Figure 354. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .1169
Figure 355. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1169
Figure 356. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .1170
Figure 357. MSB justified 24-bit frame length . . . . .1170
Figure 358. MSB justified 16-bit extended to 32-bit packet frame . . . . .1171
Figure 359. LSB justified 16-bit or 32-bit full-accuracy . . . . .1171
Figure 360. LSB justified 24-bit frame length . . . . .1171
Figure 361. Operations required to transmit 0x3478AE. . . . .1172
Figure 362. Operations required to receive 0x3478AE . . . . .1172
Figure 363. LSB justified 16-bit extended to 32-bit packet frame . . . . .1172
Figure 364. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1173
Figure 365. PCM standard waveforms (16-bit) . . . . .1173
Figure 366. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1174
Figure 367. Start sequence in master mode . . . . .1175
Figure 368. Audio sampling frequency definition . . . . .1176
Figure 369. I 2 S clock generator architecture . . . . .1176
Figure 370. Block diagram of debug support infrastructure . . . . .1198
Figure 371. JTAG TAP state machine . . . . .1201
Figure 372. Debug and access port connections . . . . .1214
Figure 373. Debugger connection to debug components . . . . .1217
Figure 374. CPU CoreSight topology . . . . .1236
Figure 375. TPIU architecture . . . . .1258

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