78. Revision history

Table 813. Document revision history

DateRevisionChanges
22-Jun-20211Initial release
20-Sep-20212Updated:
– Figure 1: System architecture
– Figure 3: Memory map based on IDAU mapping for STM32U575/585
– End of Section 6.3.2: Error code correction (SRAM2, SRAM3, BKPSRAM)
– Sentence added in intro of Section 7.6.2: Readout protection (RDP)
– Desc of bit 21 in Section 7.9.14: FLASH option register (FLASH_OPTR)
– First sentence of Section 10.5.3: LDO and SMPS step down converter fast startup
– One sentence removed in Exiting Stop 0 mode , Exiting Stop 2 mode and Exiting Stop 3 mode
– Note added on BREN bit in Section 10.10.9: PWR Backup domain control register 1 (PWR_BDCR1)
– Desc of MSISSRANGE and MSIKSRANGE in Section 11.8.50: RCC control/status register (RCC_CSR)
– Table 125: Peripherals interconnect matrix
– Table 124: Programmed GPDMA1 request
– Bit 7 in Section 25.7.1: OCTOSPI control register (OCTOSPI_CR)
– Section 37.2: PSSI main features
– Table 212: RNG configurations
– Section 34.4.13: AES data registers and data swapping
– Section 42.4.14: SAES operation with shared keys
– Address offset of Section 23.6.19: TIMx option register 1 (TIMx_OR1)(x = 16 to 17)
– Table 121: LPTIM1/2/3 input/output pins, Table 122: LPTIM4 input/output pins and Table 146: LPTIM1/2/3/4 external trigger connection
– Table 533: I2C1, I2C2, I2C4 interconnection and Table 534: I2C3 interconnection
– Table 294: Comparison of analog vs. digital filters
– usart/lpuart_trg6/7 in Table 553: USART interconnection (USART1/2/3 and UART4/5)
– New notes in Section 31.5.20: Continuous communication using USART and DMA
– New Determining the maximum USART baud rate that enables to correctly wake up the microcontroller from low-power mode
– Table 322: LPUART input/output pins
– usart/lpuart_trg6/7 in Table 565: LPUART interconnections (LPUART1)
– New
– Table 576: SPI interconnection (SPI1 and SPI2) and Table 577: SPI interconnection (SPI3)
– New Control of the I/Os
– Structure of Section 65.3: Serial-wire and JTAG debug port (SWJ-DP)
– APSEL range in DP access port select register (DP_SELECTR)
– REV_ID[15:0] in DBGMCU identity code register (DBGMCU_IDCODE)
– TREVISION[3:0] in DP target identification register (DP_TARGETIDR)

Table 813. Document revision history (continued)

DateRevisionChanges
16-Mar-20223Updated:
– Related documents
– New note in Section 2.1.9: SmartRun domain (SRD)
– Section 3.1: Key security features
– Section 3.2: Secure install
– Section 3.3.2: Immutable root of trust in system Flash memory
– Section 3.4: Secure update
– Table 10: Non-secure peripheral functions that are not connected to secure I/Os
– Section 3.5.7: Deactivating TrustZone security
– New note in Section 3.8.1: Hardware secret key management
– Section 3.11: Access controlled debug
– DCMISEC desc in Section 5.6.4: GTZC1 TZSC secure configuration register 3 (GTZC1_TZSC_SECCFGR3)
– DCMIPRIV desc in Section 5.6.7: GTZC1 TZSC privilege configuration register 3 (GTZC1_TZSC_PRIVCFGR3)
– DCMIE desc in Section 5.7.3: GTZC1 TZIC interrupt enable register 3 (GTZC1_TZIC_IER3)
– DCMIF desc in Section 5.7.7: GTZC1 TZIC status register 3 (GTZC1_TZIC_SR3)
– CDCMIF desc in Section 5.7.11: GTZC1 TZIC flag clear register 3 (GTZC1_TZIC_FCR3)
– New warning in Section 6.3.2: Error code correction (SRAM2, SRAM3, BKPSRAM)
– Sentence in Section 7.3.1: Flash memory organization
– New ST production value in Section 7.9.13: FLASH option register (FLASH_OPTR) to Section 7.9.24: FLASH WRP2 area B address register (FLASH_WRP2BR)
– Figure 29: Power supply overview
– V BAT in Section 10.4.1: External power supplies
– Section 10.4.7: Battery Backup domain
– PSSI added in Table 89: Functionalities depending on the working mode
– ULPMEN desc in Section 10.10.1: PWR control register 1 (PWR_CR1)
– Section 10.6.1: Brownout reset (BOR)
– Section 10.6.2: Programmable voltage detector (PVD)
– Section 10.7.8: Stop 2 mode and Section 10.7.9: Stop 3 mode
– Note on Table 99: PWR interrupt requests
– Section 11.4.6: PLL
– Section 11.4.7: LSE clock
– Hardware auto calibration with LSE (PLL-mode)
– Section 11.4.12: Clock security system on LSE
– Section 11.4.18: Clock-out capability
– Section 11.5.1: RCC TrustZone security protection modes
– LSECSS, MSI_PLL_UNLOCK, and notes of Table 107: Interrupt sources and control
– MSIBIAS desc in Section 11.8.2: RCC internal clock sources calibration register 1 (RCC_ICSCR1)
– PLL1P/R desc in Section 11.8.12: RCC PLL1 dividers register (RCC_PLL1DIVR)
– LSESYSEN desc in Section 11.8.49: RCC Backup domain control register (RCC_BDCR)
– LSECSS, MSI_PLL_UNLOCK in Table 153: STM32U575/585 vector table

Table 813. Document revision history (continued)

DateRevisionChanges
16-Mar-20223 (cont'd)
  • – Line 23 in Table 156: EXTI line connections
  • – Bit 23 in Section 21.6.1 to Section 21.6.7, Section 21.6.10, and Section 21.6.11
  • – Section 21.6.8: EXTI external interrupt selection register (EXTI_EXTICRm)
  • – Bulb sampling mode
  • – CALINDEX[3:0] in ADC_CR
  • – New Extended calibration mode
  • – Table 249: Memory location of the temperature sensor calibration values
  • – Section 21.7.13: ADC power register (ADC_PWR)
  • – New Section 55.3: TAMP implementation
  • – Active tamper detection
  • – ATCKSEL desc in Section 50.6.5: TAMP active tamper control register 1 (TAMP_ATCR1)
  • – Note in Table 514: STM32U575/585 IWDG features
  • – Configuring the IWDG when the window option is enabled
  • – New Updating the window comparator
  • – Section 48.4.6: Register access protection
  • – KEY[15:0] desc in Section 48.7.1: IWDG key register (IWDG_KR)
  • – Table 653: UCPD implementation and Table 654: UCPD software trim data
  • – New Section 64.5.5: UCPD software trimming
  • – Section 64.8.3: UCPD configuration register 3 (UCPD_CFGR3)
  • – TREVISION desc in DP target identification register (DP_TARGETIDR)
  • – REV_ID desc in DBGMCU identity code register (DBGMCU_IDCODE)
16-Feb-20234

Full scope updated to cover all STM32U5 series products:

  • – STM32U535/545,
  • – STM32U575/585 rev X and above,
  • – STM32U59x/5Ax,
  • – STM32U5Fx/5Gx.

Updated:

  • – Reset value for Section 5.6.9: GTZC1 TZSC memory x sub-region A watermark register (GTZC1_TZSC_MPCWMxAR) and Section 5.6.10: GTZC1 TZSC memory x sub-region B watermark register (GTZC1_TZSC_MPCWMxBR)
  • – SRAM3 ECC specific management
  • – Section 7.3.8: Flash memory endurance
  • – Section 10: Power control (PWR)
  • – Section 11.4.6: PLL
  • – Section 11.8.12: RCC PLL1 dividers register (RCC_PLL1DIVR)
  • – Reset value for Section 11.8.30: RCC AHB2 peripheral clock enable register 1 (RCC_AHB2ENR1) and Section 11.8.31: RCC AHB2 peripheral clock enable register 2 (RCC_AHB2ENR2)
  • – Table 682: LPUART interconnections (LPUART1)
  • – Section 33: Analog-to-digital converter (ADC12)
  • – DP target identification register (DP_TARGETIDR)
  • – DBGMCU identity code register (DBGMCU_IDCODE)
  • – DBGMCU status register (DBGMCU_SR)
12-Oct-20235Updated the cover page to include STM32U5Fxxx and STM32U5Gxxx documents.

Table 813. Document revision history (continued)

DateRevisionChanges
24-Jan-20256Updated:
– Section 3: System security
– Table 17: Internal tampers in TAMP
– Chapter 5.7.4: GTZC1 TZIC interrupt enable register 4 (GTZC1_TZIC_IER4)
– Section 6: RAM configuration controller (RAMCFG)
– Section 7: Embedded flash memory (FLASH)
– Section 201: Power control (PWR)
– Section 11: Reset and clock control (RCC)
– Section 13: General-purpose I/Os (GPIO)
– Section 16: Peripherals interconnect matrix
Master and slave terms in Section 41: Inter-integrated circuit interface (I2C) replaced with controller and target, respectively.
30-Mar-20267Updated:
– Section 3: System security
– Section 5: Global TrustZone controller (GTZC)
– Section 7: Embedded flash memory (FLASH)
– Section 10: Power control (PWR)
– Section 11: Reset and clock control (RCC)
– Section 13: General-purpose I/Os (GPIO)
– Section 16: Peripherals interconnect matrix
– Section 17: General purpose direct memory access controller (GPDMA)
– Section 34: Analog-to-digital converter (ADC4)
– Section 31: Secure digital input/output MultiMediaCard interface (SDMMC)
– Section 54: Advanced-control timers (TIM1/TIM8)
– Section 67: Low-power universal asynchronous receiver transmitter (LPUART)
– Section 73: USB on-the-go high-speed (OTG_HS)