49. AES hardware accelerator (AES)

This section only applies to STM32U545/585/5Ax/5Gx devices.

49.1 Introduction

The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in Federal information processing standards (FIPS) publication 197.

The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits.

AES is an AMBA AHB slave peripheral accessible through 32-bit single accesses only. Other access types generate an AHB error, and other than 32-bit writes may corrupt the register content.

The peripheral supports DMA single transfers for incoming and outgoing data (two DMA channels required).

49.2 AES main features

• • Compliance with NIST “ Advanced encryption standard (AES), FIPS publication 197 ” from November 2001
• • 128-bit data block processing
• • Support for cipher key lengths of 128-bit and 256-bit
• • Encryption and decryption with multiple chaining modes:
  • – Electronic codebook (ECB) mode
  • – Cipher block chaining (CBC) mode
  • – Counter (CTR) mode
  • – Galois counter mode (GCM)
  • – Galois message authentication code (GMAC) mode
  • – Counter with CBC-MAC (CCM) mode
• • 51 or 75 clock cycle latency in ECB mode for processing one 128-bit block of data with, respectively, 128-bit or 256-bit key
• • Integrated round key scheduler to compute the last round key for ECB/CBC decryption
• • AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
• • 256-bit write-only register for storing the cryptographic key (eight 32-bit registers)
• • 128-bit register for storing initialization vector (four 32-bit registers)
• • 32-bit buffer for data input and output
• • Automatic data flow control with support of single-transfer direct memory access (DMA) using two channels (one for incoming data, one for processed data)
• • Data-swapping logic to support 1-, 8-, 16- or 32-bit data
• • Possibility for software to suspend a message if AES needs to process another message with a higher priority, then resume the original message
• • Hardware key sharing with side-channel resistant SAES peripheral (Shared-key mode), controlled by SAES

49.3 AES implementation

The devices have one AES and one SAES peripheral, implemented as shown in the following table.

Table 467. AES/SAES features

1. X = supported.

49.4 AES functional description

49.4.1 AES block diagram

Figure 459 shows the block diagram of AES.

Figure 459. AES block diagram

49.4.2 AES internal signals

Table 468 describes the user relevant internal signals interfacing the AES peripheral.

49.4.3 AES cryptographic core

Overview

The AES cryptographic core consists of the following components:

• • AES core algorithm (AEA)
• • multiplier over a binary Galois field (GF2mul)
• • key input
• • initialization vector (IV) input
• • chaining algorithm logic (XOR, feedback/counter, mask)

The AES core works on 128-bit data blocks (four words) with 128-bit or 256-bit key length. Depending on the chaining mode, the AES requires zero or one 128-bit initialization vector IV.

The AES features the following modes of operation:

• • Mode 1:
  Plaintext encryption using a key stored in the AES_KEYRx registers
• • Mode 2:
  ECB or CBC decryption key preparation. It must be used prior to selecting Mode 3 with ECB or CBC chaining modes. The key prepared for decryption is stored automatically in the AES_KEYRx registers. Now the AES peripheral is ready to switch to Mode 3 for executing data decryption.
• • Mode 3:
  Ciphertext decryption using a key stored in the AES_KEYRx registers. When ECB and CBC chaining modes are selected, the key must be prepared beforehand, through Mode 2.

Note: Mode 2 is only used when performing ECB and CBC decryption.

The operating mode is selected by programming the MODE[1:0] bitfield of the AES_CR register. It may be done only when the AES peripheral is disabled.

Special key operation is selected using the KMOD[1:0] bitfield of the AES_CR register. See Section 49.4.13 for details.

Typical data processing

Typical usage of the AES is described in Section 49.4.4: AES procedure to perform a cipher operation .

Note: The outputs of the intermediate AEA stages are never revealed outside the cryptographic boundary, with the exclusion of the IVI bitfield.

Chaining modes

The following chaining modes are supported by AES, selected through the CHMOD[2:0] bitfield of the AES_CR register:

• • Electronic code book (ECB)
• • Cipher block chaining (CBC)
• • Counter (CTR)
• • Galois counter mode (GCM)
• • Galois message authentication code (GMAC)
• • Counter with CBC-MAC (CCM)

Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR register cleared).

Principle of each AES chaining mode is provided in the following subsections.

Detailed information is in dedicated sections, starting from Section 49.4.8: AES basic chaining modes (ECB, CBC) .

Electronic codebook (ECB) mode

Figure 460. ECB encryption and decryption principle

ECB is the simplest mode of operation. There are no chaining operations, and no special initialization stage. The message is divided into blocks and each block is encrypted or decrypted separately.

Note: For decryption, a special key scheduling is required before processing the first block.

Cipher block chaining (CBC) mode

Figure 461. CBC encryption and decryption principle

In CBC mode the output of each block chains with the input of the following block. To make each message unique, an initialization vector is used during the first block processing.

Note: For decryption, a special key scheduling is required before processing the first block.

The CTR mode uses the AES core to generate a key stream. The keys are then XOR-ed with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation .

Note: Unlike with ECB and CBC modes, no key scheduling is required for the CTR decryption, since in this chaining scheme the AES core is always used in encryption mode for producing the key stream, or counter blocks.

Galois/counter mode (GCM)

Figure 463. GCM encryption and authentication principle

In Galois/counter mode (GCM), the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC .

GCM mode is based on AES in counter mode for confidentiality. It uses a multiplier over a fixed finite field for computing the message authentication code. It requires an initial value and a particular 128-bit block at the end of the message.

Galois message authentication code (GMAC) principle

Figure 464. GMAC authentication principle

Galois message authentication code (GMAC) allows authenticating a message and generating the corresponding message authentication code (MAC). It is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC .

GMAC is similar to GCM, except that it is applied on a message composed only by plaintext authenticated data (that is, only header, no payload).

Counter with CBC-MAC (CCM) principle

Figure 465. CCM encryption and authentication principle

In Counter with cipher block chaining-message authentication code (CCM) mode, the plaintext message is encrypted while a message authentication code (MAC) is computed in parallel, thus generating the corresponding ciphertext and the corresponding MAC (also known as tag). It is described by NIST in Special Publication 800-38C, Recommendation for Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality .

CCM mode is based on AES in counter mode for confidentiality and it uses CBC for computing the message authentication code. It requires an initial value.

Like GCM, the CCM chaining mode can be applied on a message composed only by plaintext authenticated data (that is, only header, no payload). Note that this way of using CCM is not called CMAC (it is not similar to GCM/GMAC), and its use is not recommended by NIST.

49.4.4 AES procedure to perform a cipher operation

Introduction

A typical cipher operation is explained below. Detailed information is provided in sections starting from Section 49.4.8: AES basic chaining modes (ECB, CBC) .

Initialization of AES

To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform the following steps in any order:

• • Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR register.
  • – For encryption, select Mode 1 (MODE[1:0] = 00).
  • – For decryption, select Mode 3 (MODE[1:0] = 10), unless ECB or CBC chaining modes are used. In this latter case, perform an initial key derivation of the encryption key, as described in Section 49.4.5: AES decryption round key preparation .
• • Select the chaining mode, by programming the CHMOD[2:0] bitfield of the AES_CR register.
• • Configure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE[1:0] bitfield in the AES_CR register.
• • When it is required (for example in CBC or CTR chaining modes), write the initialization vector into the AES_IVRx registers.
• • Configure the key size (128-bit or 256-bit), with the KEYSIZE bitfield of the AES_CR register. This step must be done before writing into key registers.
• • Write a symmetric key into the AES_KEYRx registers (4 or 8 registers depending on the key size).

Note: AES sets KEYVALID in AES_SR when key information defined by KEYSIZE is loaded in AES_KEYRx.

Data append

This section describes different ways of appending data for processing, where the size of data to process is not a multiple of 128 bits when KMOD[1:0] = 00. For other KMOD[1:0] values refer to Section 49.4.13 .

For ECB or CBC mode, refer to Section 49.4.6: AES ciphertext stealing and data padding . The last block management in these cases is more complex than in the sequence described in this section.

Data append through polling

This method uses flag polling to control the data append through the following sequence:

1. 1. Enable the AES peripheral by setting the EN bit of the AES_CR register.
2. 2. Repeat the following sub-sequence until the payload is entirely processed:
   1. a) Write four input data words into the AES_DINR register.
   2. b) Wait until the status flag CCF is set in the AES_SR, then read the four data words from the AES_DOUTR register.
   3. c) Clear the CCF flag, by setting the CCF bit of the AES_ICR register.
   4. d) If the data block just processed is the second-last block of the message and the significant data in the last block to process is inferior to 128 bits, pad the remainder of the last block with zeros and, in case of GCM payload encryption or CCM payload decryption, specify the number of non-valid bytes, using the NPBLB bitfield of the AES_CR register, for AES to compute a correct tag;.
3. 3. As it is the last block, discard the data that is not part of the data, then disable the AES peripheral by clearing the EN bit of the AES_CR register.

Note: Up to three wait cycles are automatically inserted between two consecutive writes to the AES_DINR register, to allow sending the key to the AES processor.

NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

Data append using interrupt

The method uses interrupt from the AES peripheral to control the data append, through the following sequence:

1. 1. Enable interrupts from AES by setting the CCFIE bit of the AES_IER register.
2. 2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. 3. Write first four input data words into the AES_DINR register.
4. 4. Handle the data in the AES interrupt service routine, upon interrupt:
   1. a) Read four output data words from the AES_DOUTR register.
   2. b) Clear the CCF flag and thus the pending interrupt, by setting the CCF bit of the AES_ICR register.
   3. c) If the data block just processed is the second-last block of an message and the significant data in the last block to process is inferior to 128 bits, pad the remainder of the last block with zeros and, in case of GCM payload encryption or CCM payload decryption, specify the number of non-valid bytes, using the NPBLB bitfield of the AES_CR register, for AES to compute a correct tag;. Then proceed with point 4e).
   4. d) If the data block just processed is the last block of the message, discard the data that is not part of the data, then disable the AES peripheral by clearing the EN bit of the AES_CR register and quit the interrupt service routine.
   5. e) Write next four input data words into the AES_DINR register and quit the interrupt service routine.

Note: AES is tolerant of delays between consecutive read or write operations, which allows, for example, an interrupt from another peripheral to be served between two AES computations.

NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

Data append using DMA

With this method, all the transfers and processing are managed by DMA and AES. To use the method, proceed as follows:

1. 1. Prepare the last four-word data block (if the data to process does not fill it completely), by padding the remainder of the block with zeros.
2. 2. Configure the DMA controller so as to transfer the data to process from the memory to the AES peripheral input and the processed data from the AES peripheral output to the memory, as described in Section 49.4.17: AES DMA interface . Configure the DMA controller so as to generate an interrupt on transfer completion. In case of GCM payload encryption or CCM payload decryption, DMA transfer must not include the last four-word block if padded with zeros. The sequence described in Data append through polling must be used instead for this last block, because NPBLB bits must be setup before processing the block, for AES to compute a correct tag.
3. 3. Enable the AES peripheral by setting the EN bit of the AES_CR register
4. 4. Enable DMA requests by setting the DMAINEN and DMAOUTEN bits of the AES_CR register.
5. 5. Upon DMA interrupt indicating the transfer completion, get the AES-processed data from the memory.

Note: The CCF flag has no use with this method, because the reading of the AES_DOUTR register is managed by DMA automatically, without any software action, at the end of the computation phase.

NPBLB bits are not used in header phase of GCM, GMAC, and CCM chaining modes.

49.4.5 AES decryption round key preparation

Internal key schedule is used to generate AES round keys. In AES encryption, the round 0 key is the one stored in the key registers. AES decryption must start using the last round key. As the encryption key is stored in memory, a special key scheduling must be performed to obtain the decryption key. This key scheduling is only required for AES decryption in ECB and CBC modes.

Recommended method is to select the Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR (key process only), then proceed with the decryption by setting MODE[1:0] to 10 (Mode 3, decryption only). Mode 2 usage is described below:

1. 1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. 2. Select Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR. The CHMOD[2:0] bitfield is not significant in this case because this key derivation mode is independent of the chaining algorithm selected. Select normal key mode by setting KMOD[1:0] to 00. For decryption with other KMOD[1:0] values, refer to Section 49.4.13 .
3. 3. Set key length to 128 or 256 bits, via KEYSIZE bit of AES_CR register.
4. 4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Writes to the AES_IVRx registers have no effect.
5. 5. Enable the AES peripheral, by setting the EN bit of the AES_CR register.
6. 6. Wait until the CCF flag is set in the AES_SR register.
7. 7. Clear the CCF flag. Derived key is available in AES core, ready to use for decryption.

Note: The AES is disabled by hardware when the derivation key is available.

To restart a derivation key computation, repeat steps 4, 5, 6, and 7.

Note: The operation of the key preparation lasts 59 or 82 clock cycles, depending on the key size (128- or 256-bit).

49.4.6 AES ciphertext stealing and data padding

When using AES in ECB or CBC modes to manage messages the size of which is not a multiple of the block size (128 bits), ciphertext stealing techniques are used, such as those described in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation: Three Variants of Ciphertext Stealing for CBC Mode . Since the AES peripheral does not support such techniques, the application must complete the last block of input data using data from the second last block.

Note: Ciphertext stealing techniques are not documented in this reference manual.

Similarly, when AES is used in other modes than ECB or CBC, an incomplete input data block (that is, block with input data shorter than 128 bits) must be padded with zeros prior to encryption (that is, extra bits must be appended to the trailing end of the data string). After decryption, the extra bits must be discarded. As AES does not implement automatic data padding operation to the last block , the application must follow the recommendation given

in Section 49.4.4: AES procedure to perform a cipher operation to manage messages the size of which is not a multiple of 128 bits.

Note: Padding data are swapped in a similar way as normal data, according to the DATATYPE[1:0] field of the AES_CR register (see Section 49.4.14: AES data registers and data swapping for details).

49.4.7 AES task suspend and resume

A message can be suspended if another message with a higher priority must be processed. When this highest priority message is sent, the suspended message can resume in both encryption or decryption mode.

Suspend/resume operations do not break the chaining operation and the message processing can resume as soon as AES is enabled again to receive the next data block.

Figure 466 gives an example of suspend/resume operation: Message 1 is suspended in order to send a shorter and higher-priority Message 2.

Figure 466. Example of suspend mode management

A detailed description of suspend/resume operations is in the sections dedicated to each AES mode.

49.4.8 AES basic chaining modes (ECB, CBC)

Overview

This section gives a brief explanation of the four basic operation modes provided by the AES core: ECB encryption, ECB decryption, CBC encryption and CBC decryption. For detailed information, refer to the FIPS publication 197 from November 26, 2001.

Figure 467 illustrates the electronic codebook (ECB) encryption.

In ECB encrypt mode, the 128-bit plaintext input data block P _x in the AES_DINR register first goes through bit/byte/half-word swapping. The swap result I _x is processed with the AES core set in encrypt mode, using a 128- or 256-bit key. The encryption result O _x goes through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit ciphertext output data block C _x . The ECB encryption continues in this way until the last complete plaintext block is encrypted.

Figure 468 illustrates the electronic codebook (ECB) decryption.

To perform an AES decryption in the ECB mode, the secret key has to be prepared by collecting the last-round encryption key (which requires to first execute the complete key schedule for encryption), and using it as the first-round key for the decryption of the ciphertext. This preparation is supported by the AES core.

In ECB decrypt mode, the 128-bit ciphertext input data block C ₁ in the AES_DINR register first goes through bit/byte/half-word swapping. The keying sequence is reversed compared to that of the ECB encryption. The swap result I ₁ is processed with the AES core set in decrypt mode, using the formerly prepared decryption key. The decryption result goes through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit plaintext output data block P ₁ . The ECB decryption continues in this way until the last complete ciphertext block is decrypted.

Figure 469 illustrates the cipher block chaining (CBC) encryption.

In CBC encrypt mode, the first plaintext input block, after bit/byte/half-word swapping ( \( P1' \) ), is XOR-ed with a 128-bit IVI bitfield (initialization vector and counter), producing the \( I1 \) input data for encrypt with the AES core, using a 128- or 256-bit key. The resulting 128-bit output block \( O1 \) , after swapping operation, is used as ciphertext \( C1 \) . The \( O1 \) data is then XOR-ed with the second-block plaintext data \( P2' \) to produce the \( I2 \) input data for the AES core to produce the second block of ciphertext data. The chaining of data blocks continues in this way until the last plaintext block in the message is encrypted.

If the message size is not a multiple of 128 bits, the final partial data block is encrypted in the way explained in Section 49.4.6: AES ciphertext stealing and data padding .

Figure 470 illustrates the cipher block chaining (CBC) decryption.

In CBC decrypt mode, like in ECB decrypt mode, the secret key must be prepared to perform an AES decryption.

After the key preparation process, the decryption goes as follows: the first 128-bit ciphertext block (after the swap operation) is used directly as the AES core input block \( I1 \) for decrypt operation, using the 128-bit or 256-bit key. Its output \( O1 \) is XOR-ed with the 128-bit IVI field (that must be identical to that used during encryption) to produce the first plaintext block \( P1 \) .

The second ciphertext block is processed in the same way as the first block, except that the I1 data from the first block is used in place of the initialization vector.

The decryption continues in this way until the last complete ciphertext block is decrypted.

If the message size is not a multiple of 128 bits, the final partial data block is decrypted in the way explained in Section 49.4.6: AES ciphertext stealing and data padding .

For more information on data swapping, refer to Section 49.4.14: AES data registers and data swapping .

ECB/CBC encryption sequence

The sequence of events to perform an ECB/CBC encryption (more detail in Section 49.4.4 ):

1. 1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. 2. Select the Mode 1 by setting to 00 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 000 or 001, respectively. Data type can also be defined, using DATATYPE[1:0] bitfield. Select normal key mode by setting KMOD[1:0] to 00. For encryption with other KMOD[1:0] values, refer to Section 49.4.13 .
3. 3. Select 128- or 256-bit key length through the KEYSIZE bit of the AES_CR register.
4. 4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Fill the AES_IVRx registers with the initialization vector data if CBC mode has been selected.
5. 5. Enable the AES peripheral by setting the EN bit of the AES_CR register.
6. 6. Write the AES_DINR register four times to input the plaintext (MSB first), as shown in Figure 471 .
7. 7. Wait until the CCF flag is set in the AES_SR register.
8. 8. Read the AES_DOUTR register four times to get the ciphertext (MSB first) as shown in Figure 471 . Then clear the CCF flag by setting the CCF bit of the AES_ICR register.
9. 9. Repeat steps 6-7-8 to process all the blocks with the same encryption key.

Figure 471. ECB/CBC encryption (Mode 1)

ECB/CBC decryption sequence

The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail in Section 49.4.4 ). Select normal key mode by setting KMOD[1:0] to 00. For decryption with other KMOD[1:0] values, refer to Section 49.4.13 .

1. 1. Follow the steps described in Section 49.4.5: AES decryption round key preparation , in order to prepare the decryption key in AES core.
2. 2. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR register to 000 or 001, respectively. Data type can also be defined, using DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.
3. 3. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).
4. 4. Enable AES by setting the EN bit of the AES_CR register.
5. 5. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in Figure 472 .
6. 6. Wait until the CCF flag is set in the AES_SR register.
7. 7. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in Figure 472 . Then clear the CCF flag by setting the CCF bit of the AES_ICR register.
8. 8. Repeat steps 5-6-7 to process all the blocks encrypted with the same key.

Figure 472. ECB/CBC decryption (Mode 3)

Suspend/resume operations in ECB/CBC modes

To suspend the processing of a message, proceed as follows:

1. 1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register.
2. 2. If DMA is not used, read four times the AES_DOUTR register to save the last processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register.
3. 3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1 (computation completed).
4. 4. Clear the CCF flag by setting the CCF bit of the AES_ICR register.
5. 5. Save initialization vector registers (only required in CBC mode as AES_IVRx registers are altered during the data processing).
6. 6. Disable the AES peripheral by clearing the bit EN of the AES_CR register.
7. 7. Save the AES_CR register and clear the key registers if they are not needed, to process the higher priority message.
8. 8. If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers, number of remaining bytes, and so on).

To resume the processing of a message, proceed as follows:

1. 1. If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN and FIFO OUT transfers.
2. 2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
3. 3. Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers.
4. 4. Prepare the decryption key as described in Section 49.4.5: AES decryption round key preparation (only required for ECB or CBC decryption).
5. 5. Restore AES_IVRx registers using the saved configuration (only required in CBC mode).
6. 6. Enable the AES peripheral by setting the EN bit of the AES_CR register.
7. 7. If DMA is used, enable AES DMA transfers by setting the DMAINEN and DMAOUTEN bits of the AES_CR register.

49.4.9 AES counter (CTR) mode

Overview

The counter mode (CTR) uses AES as a key-stream generator. The generated keys are then XOR-ed with the plaintext to obtain the ciphertext.

CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation . A typical message construction in CTR mode is given in Figure 473 .

Figure 473. Message construction in CTR mode

The structure of this message is:

• • A 16-byte initial counter block (ICB), composed of two distinct fields:
  • – Initialization vector (IV) : a 96-bit value that must be unique for each encryption cycle with a given key.
  • – Counter : a 32-bit big-endian integer that is incremented each time a block processing is completed. The initial value of the counter must be set to 1.
• • The plaintext P is encrypted as ciphertext C, with a known length. This length can be non-multiple of 16 bytes, in which case a plaintext padding is required.

CTR encryption and decryption

Figure 474 and Figure 475 describe the CTR encryption and decryption process, respectively, as implemented in the AES peripheral. The CTR mode is selected by writing 010 to the CHMOD[2:0] bitfield of AES_CR register.

Figure 474. CTR encryption

Figure 475. CTR decryption

In CTR mode, the cryptographic core output (also called keystream) \( O_x \) is XOR-ed with relevant input block ( \( P_x' \) for encryption, \( C_x' \) for decryption), to produce the correct output block ( \( C_x' \) for encryption, \( P_x' \) for decryption). Initialization vectors in AES must be initialized as shown in Table 469.

Table 469. CTR mode initialization vector definition

Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first data block, in CTR mode AES_IVRx registers are used for processing each data block, and the AES peripheral increments the counter bits of the initialization vector (leaving the nonce bits unchanged).

CTR decryption does not differ from CTR encryption, since the core always encrypts the current counter block to produce the key stream that is then XOR-ed with the plaintext (CTR encryption) or ciphertext (CTR decryption) input. In CTR mode, the MODE[1:0] bitfield setting 01 (key derivation) is forbidden and all the other settings default to encryption mode.

The sequence of events to perform an encryption or a decryption in CTR chaining mode:

1. 1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. 2. Select CTR chaining mode by setting to 010 the CHMOD[2:0] bitfield of the AES_CR register. Set MODE[1:0] bitfield to any value other than 01.
3. 3. Initialize the AES_KEYRx registers, and load the AES_IVRx registers as described in Table 469 .
4. 4. Set the EN bit of the AES_CR register, to start encrypting the current counter (EN is automatically reset when the calculation finishes).
5. 5. If it is the last block, pad the data with zeros to have a complete block, if needed.
6. 6. Append data in AES, and read the result. The three possible scenarios are described in Section 49.4.4: AES procedure to perform a cipher operation .
7. 7. Repeat the previous step till the second-last block is processed. For the last block, apply the two previous steps and discard the bits that are not part of the payload (if the size of the significant data in the last input block is less than 16 bytes).

Suspend/resume operations in CTR mode

Like for the CBC mode, it is possible to interrupt a message to send a higher priority message, and resume the message that was interrupted. Detailed CBC suspend/resume sequence is described in Section 49.4.8: AES basic chaining modes (ECB, CBC) .

Note: Like for CBC mode, the AES_IVRx registers must be reloaded during the resume operation.

49.4.10 AES Galois/counter mode (GCM)

Overview

The AES Galois/counter mode (GCM) allows encrypting and authenticating a plaintext message into the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, GCM algorithm is based on AES counter mode. It uses a multiplier over a fixed finite field to generate the tag.

GCM chaining is defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC . A typical message construction in GCM mode is given in Figure 476 .

Figure 476. Message construction in GCM

The message has the following structure:

• • 16-byte initial counter block (ICB) , composed of two distinct fields:
  • – Initialization vector (IV) : a 96-bit value that must be unique for each encryption cycle with a given key. Note that the GCM standard supports IVs with less than 96 bits, but in this case strict rules apply.
  • – Counter : a 32-bit big-endian integer that is incremented each time a block processing is completed. According to NIST specification, the counter value is 0x2 when processing the first block of payload.
• • Authenticated header AAD (also known as additional authentication data) has a known length \( Len(A) \) that may be a non-multiple of 16 bytes, and must not exceed \( 2^{64} - 1 \) bits. This part of the message is only authenticated, not encrypted.
• • Plaintext message P is both authenticated and encrypted as ciphertext C, with a known length \( Len(P) \) that may be non-multiple of 16 bytes, and cannot exceed \( 2^{32} - 2 \) 128-bit blocks.
• • Last block contains the AAD header length (bits [32:63]) and the payload length (bits [96:127]) information, as shown in Table 470 .

The GCM standard specifies that ciphertext C has the same bit length as the plaintext P.

When a part of the message (AAD or P) has a length that is a non-multiple of 16-bytes a special padding scheme is required.

Table 470. GCM last block definition

GCM processing

Figure 477 describes the GCM implementation in the AES peripheral. The GCM is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

Figure 477. GCM authenticated encryption

The mechanism for the confidentiality of the plaintext in GCM mode is similar to that in the Counter mode, with a particular increment function (denoted 32-bit increment) that generates the sequence of input counter blocks.

AES_IVRx registers keeping the counter block of data are used for processing each data block. The AES peripheral automatically increments the Counter[31:0] bitfield. The first counter block (CB1) is derived from the initial counter block ICB by the application software (see Table 471).

Table 471. Initialization of AES_IVRx registers in GCM mode

Note: In this mode, the setting 01 of the MODE[1:0] bitfield (key derivation) is forbidden.

The authentication mechanism in GCM mode is based on a hash function called GF2mul that performs multiplication by a fixed parameter, called hash subkey (H), within a binary Galois field.

A GCM message is processed through the following phases, further described in next subsections:

• • Init phase: AES prepares the GCM hash subkey (H).
• • Header phase: AES processes the additional authenticated data (AAD), with hash computation only.
• • Payload phase: AES processes the plaintext (P) with hash computation, counter block encryption and data XOR-ing. It operates in a similar way for ciphertext (C).
• • Final phase: AES generates the authenticated tag (T) using the last block of the message.

GCM init phase

During this first step, the GCM hash subkey (H) is calculated and saved internally, to be used for processing all the blocks. The recommended sequence is:

1. 1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. 2. Select GCM chaining mode, by setting to 011 the CHMOD[2:0] bitfield of the AES_CR register, and optionally, set the DATATYPE[1:0] bitfield.
3. 3. Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR register.
4. 4. Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is only used in payload phase, it is recommended to set it in the Init phase and keep it unchanged in all subsequent phases.
5. 5. Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with the information as defined in Table 471 .
6. 6. Start the calculation of the hash key, by setting to 1 the EN bit of the AES_CR register (EN is automatically reset when the calculation finishes).
7. 7. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1. Alternatively, use the corresponding interrupt.
8. 8. Clear the CCF flag of the AES_SR register, by setting the CCF bit of the AES_ICR register.

GCM header phase

This phase coming after the GCM Init phase must be completed before the payload phase. The sequence to execute, identical for encryption and decryption, is:

1. 1. Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. 2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. 3. If it is the last block and the AAD size in the block is inferior to 128 bits, pad the remainder of the block with zeros. Then append the data block into AES in one of ways described in Section 49.4.4: AES procedure to perform a cipher operation . No data is read during this phase.
4. 4. Repeat the step 3 until the last additional authenticated data block is processed.

Note: The header phase can be skipped if there is no AAD, that is, Len(A) = 0.

GCM payload phase

This phase, identical for encryption and decryption, is executed after the GCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is:

1. 1. Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. 2. If the header phase was skipped, enable the AES peripheral by setting the EN bit of the AES_CR register.
3. 3. If it is the last block and the plaintext (encryption) or ciphertext (decryption) size in the block is inferior to 128 bits, pad the remainder of the block with zeros.
4. 4. Append the data block into AES in one of ways described in Section 49.4.4: AES procedure to perform a cipher operation , and read the result.
5. 5. Repeat the previous step till the second-last plaintext block is encrypted or till the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), execute the two previous steps. For the last block, discard the bits that are not part of the payload when the last block size is less than 16 bytes.

Note: The payload phase can be skipped if there is no payload data, that is, Len(C) = 0 (see GMAC mode).

GCM final phase

In this last phase, the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register. The sequence to execute is:

1. 1. Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR register.
2. 2. Compose the data of the block, by concatenating the AAD bit length and the payload bit length, as shown in Table 470 . Write the block into the AES_DINR register.
3. 3. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1.
4. 4. Get the GCM authentication tag, by reading the AES_DOUTR register four times.
5. 5. Clear the CCF flag of the AES_SR register, by setting the CCF bit of the AES_ICR register.
6. 6. Disable the AES peripheral, by clearing the bit EN of the AES_CR register. If it is an authenticated decryption, compare the generated tag with the expected tag passed with the message.

Note: In the final phase, data is written to AES_DINR normally (no swapping), while swapping is applied to tag data read from AES_DOUTR.

When transiting from the header or the payload phase to the final phase, the AES peripheral must not be disabled, otherwise the result is wrong.

Suspend/resume operations in GCM mode

To suspend the processing of a message , proceed as follows:

1. 1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
2. 2. In the payload phase, if DMA is not used, read four times the AES_DOUTR register to save the last-processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register.
3. 3. Clear the CCF flag of the AES_SR register, by setting the CCF bit of the AES_ICR register.
4. 4. Save the AES_SUSPxR registers in the memory, where x is from 0 to 7.
5. 5. In the payload phase, save the AES_IVRx registers as, during the data processing, they changed from their initial values. In the header phase, this step is not required.
6. 6. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.
7. 7. Save the current AES configuration in the memory, excluding the initialization vector registers AES_IVRx. Key registers do not need to be saved as the original key value is known by the application.
8. 8. If DMA is used, save the DMA controller status (pointers for IN data transfers, number of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers must also be saved.

To resume the processing of a message , proceed as follows:

1. 1. If DMA is used, configure the DMA controller in order to complete the rest of the FIFO IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be configured in the DMA controller.
2. 2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
3. 3. Write the suspend register values, previously saved in the memory, back into their corresponding AES_SUSPxR registers, where x is from 0 to 7.
4. 4. In the payload phase, write the initialization vector register values, previously saved in the memory, back into their corresponding AES_IVRx registers. In the header phase, write initial setting values back into the AES_IVRx registers.
5. 5. Restore the initial setting values in the AES_CR and AES_KEYRx registers.
6. 6. Enable the AES peripheral by setting the EN bit of the AES_CR register.

If DMA is used, enable AES DMA requests by setting the DMAINEN bit (and DMAOUTEN bit if in payload phase) of the AES_CR register.

49.4.11 AES Galois message authentication code (GMAC)

Overview

The Galois message authentication code (GMAC) allows the authentication of a plaintext, generating the corresponding tag information (also known as message authentication code). It is based on GCM algorithm, as defined in NIST Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC .

A typical message construction for GMAC is given in Figure 478.

Figure 478. Message construction in GMAC mode

AES GMAC processing

Figure 479 describes the GMAC mode implementation in the AES peripheral. This mode is selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

Figure 479. GMAC authentication mode

The GMAC algorithm corresponds to the GCM algorithm applied on a message only containing a header. As a consequence, all steps and settings are the same as with the GCM, except that the payload phase is omitted.

Suspend/resume operations in GMAC

In GMAC mode, the sequence described for the GCM applies except that only the header phase can be interrupted.

49.4.12 AES counter with CBC-MAC (CCM)

Overview

The AES counter with cipher block chaining-message authentication code (CCM) algorithm allows encryption and authentication of plaintext, generating the corresponding ciphertext and tag (also known as message authentication code). To ensure confidentiality, the CCM algorithm is based on AES in counter mode. It uses cipher block chaining technique to generate the message authentication code. This is commonly called CBC-MAC.

Note: NIST does not approve this CBC-MAC as an authentication mode outside the context of the CCM specification.

CCM chaining is specified in NIST Special Publication 800-38C, Recommendation for Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality . A typical message construction for CCM is given in Figure 480 .

Figure 480. Message construction in CCM mode

The structure of the message is:

• • 16-byte first authentication block (B0) , composed of three distinct fields:
  • – Q : a bit string representation of the octet length of P (Len(P))
  • – Nonce (N) : a single-use value (that is, a new nonce must be assigned to each new communication) of Len(N) size. The sum Len(N) + Len(P) must be equal to 15 bytes.
  • – Flags : most significant octet containing four flags for control information, as specified by the standard. It contains two 3-bit strings to encode the values t (MAC length expressed in bytes) and Q (plaintext length such that \( \text{Len(P)} < 2^{8Q} \) bytes). The counter blocks range associated to Q is equal to \( 2^{8Q-4} \) , that is, if the maximum value of Q is 8, the counter blocks used in cipher must be on 60 bits.
• • 16-byte blocks (B) associated to the Associated Data (A).
  This part of the message is only authenticated, not encrypted. This section has a

known length \( \text{Len}(A) \) that can be a non-multiple of 16 bytes (see Figure 480 ). The standard also states that, on MSB bits of the first message block ( \( B_1 \) ), the associated data length expressed in bytes ( \( a \) ) must be encoded as follows:

• – If \( 0 < a < 2^{16} - 2^8 \) , then it is encoded as \( [a]_{16} \) , that is, on two bytes.
• – If \( 2^{16} - 2^8 < a < 2^{32} \) , then it is encoded as \( 0xff \parallel 0xfe \parallel [a]_{32} \) , that is, on six bytes.
• – If \( 2^{32} < a < 2^{64} \) , then it is encoded as \( 0xff \parallel 0xff \parallel [a]_{64} \) , that is, on ten bytes.
• • 16-byte blocks (B) associated to the plaintext message \( P \) , which is both authenticated and encrypted as ciphertext \( C \) , with a known length \( \text{Len}(P) \) . This length can be a non-multiple of 16 bytes (see Figure 480 ).
• • Encrypted MAC (T) of length \( \text{Len}(T) \) appended to the ciphertext \( C \) of overall length \( \text{Len}(C) \) .

When a part of the message ( \( A \) or \( P \) ) has a length that is a non-multiple of 16-bytes, a special padding scheme is required.

Note: CCM chaining mode can also be used with associated data only (that is, no payload).

As an example, the C.1 section in NIST Special Publication 800-38C gives the following values (hexadecimal numbers):

N: 10111213 141516 ( \( \text{Len}(N) = 56 \) bits or 7 bytes)
A: 00010203 04050607 ( \( \text{Len}(A) = 64 \) bits or 8 bytes)
P: 20212223 ( \( \text{Len}(P) = 32 \) bits or 4 bytes)
T: 6084341B ( \( \text{Len}(T) = 32 \) bits or 4 bytes)
\( B_0 \) : 4F101112 13141516 00000000 00000004
\( B_1 \) : 00080001 02030405 06070000 00000000
\( B_2 \) : 20212223 00000000 00000000 00000000
\( CTR_0 \) : 0710111213 141516 00000000 00000000
\( CTR_1 \) : 0710111213 141516 00000000 00000001

Generation of formatted input data blocks \( B_x \) (especially \( B_0 \) and \( B_1 \) ) must be managed by the application.

CCM processing

Figure 481 describes the CCM implementation within the AES peripheral (encryption example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR register.

Figure 481. CCM mode authenticated encryption

The data input to the generation-encryption process are a valid nonce, a valid payload string, and a valid associated data string, all properly formatted. The CBC chaining mechanism is applied to the formatted plaintext data to generate a MAC, with a known length. Counter mode encryption that requires a sufficiently long sequence of counter blocks as input, is applied to the payload string and separately to the MAC. The resulting ciphertext C is the output of the generation-encryption process on plaintext P.

AES_IVRx registers are used for processing each data block, AES automatically incrementing the CTR counter with a bit length defined by the first block B0. Table 472 shows how the application must load the B0 data.

Note: The AES peripheral in CCM mode supports counters up to 64 bits, as specified by NIST.

Table 472. Initialization of AES_IVRx registers in CCM mode

Note: In this mode, the setting 01 of the MODE[1:0] bitfield (key derivation) is forbidden.

A CCM message is processed through the following phases, further described in next subsections:

• • Init phase: AES processes the first block and prepares the first counter block.
• • Header phase: AES processes associated data (A), with tag computation only.
• • Payload phase: IP processes plaintext (P), with tag computation, counter block encryption, and data XOR-ing. It works in a similar way for ciphertext (C).
• • Final phase: AES generates the message authentication code (MAC).

CCM Init phase

In this phase, the first block B0 of the CCM message is written into the AES_IVRx register. The AES_DOUTR register does not contain any output data. The recommended sequence is:

1. 1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. 2. Select CCM chaining mode, by setting to 100 the CHMOD[2:0] bitfield of the AES_CR register, and optionally, set the DATATYPE[1:0] bitfield.
3. 3. Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR register.
4. 4. Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is only used in payload phase, it is recommended to set it in the Init phase and keep it unchanged in all subsequent phases.
5. 5. Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with B0 data as described in Table 472 .
6. 6. Start the calculation of the counter, by setting to 1 the EN bit of the AES_CR register (EN is automatically reset when the calculation finishes).
7. 7. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting to 1. Alternatively, use the corresponding interrupt.
8. 8. Clear the CCF flag in the AES_SR register, by setting to 1 the CCF bit of the AES_ICR register.

CCM header phase

This phase coming after the GCM Init phase must be completed before the payload phase. During this phase, the AES_DOUTR register does not contain any output data.

The sequence to execute, identical for encryption and decryption, is:

1. 1. Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. 2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. 3. If it is the last block and the AAD size in the block is inferior to 128 bits, pad the remainder of the block with zeros. Then append the data block into AES in one of ways described in Section 49.4.4: AES procedure to perform a cipher operation . No data is read during this phase.
4. 4. Repeat the step 3 until the last additional authenticated data block is processed.

Note: The header phase can be skipped if there is no associated data, that is, Len(A) = 0.

The first block of the associated data (B1) must be formatted by software, with the associated data length.

CCM payload phase (encryption or decryption)

This phase, identical for encryption and decryption, is executed after the CCM header phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR register. The sequence to execute is:

1. 1. Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. 2. If the header phase was skipped, enable the AES peripheral by setting the EN bit of the AES_CR register.
3. 3. If it is the last data block to encrypt and the plaintext size in the block is inferior to 128 bits, pad the remainder of the block with zeros.
4. 4. Append the data block into AES in one of ways described in Section 49.4.4: AES procedure to perform a cipher operation , and read the result.
5. 5. Repeat the previous step till the second-last plaintext block is encrypted or till the last block of ciphertext is decrypted. For the last block of plaintext (encryption only), apply the two previous steps. For the last block, discard the data that is not part of the payload when the last block size is less than 16 bytes.

Note: The payload phase can be skipped if there is no payload data, that is, \( Len(P) = 0 \) or \( Len(C) = Len(T) \) .

Remove \( LSB_{Len(T)}(C) \) encrypted tag information when decrypting ciphertext C.

CCM final phase

In this last phase, the AES peripheral generates the GCM authentication tag and stores it in the AES_DOUTR register. The sequence to execute is:

1. 1. Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR register.
2. 2. Wait until the end-of-computation flag CCF of the AES_SR register is set.
3. 3. Read four times the AES_DOUTR register: the output corresponds to the CCM authentication tag.
4. 4. Clear the CCF flag of the AES_SR register by setting the CCF bit of the AES_ICR register.
5. 5. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.
6. 6. For authenticated decryption, compare the generated encrypted tag with the encrypted tag padded in the ciphertext.

Note: In this final phase, swapping is applied to tag data read from AES_DOUTR register.

When transiting from the header phase to the final phase, the AES peripheral must not be disabled, otherwise the result is wrong.

Application must mask the authentication tag output with tag length to obtain a valid tag.

Suspend/resume operations in CCM mode

To suspend the processing of a message in header or payload phase, proceed as follows:

1. 1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN bit of the AES_CR register. If DMA is not used, make sure that the current computation is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
2. 2. In the payload phase, if DMA is not used, read four times the AES_DOUTR register to save the last-processed block. If DMA is used, wait until the CCF flag is set in the

1. AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the AES_CR register.
2. 1. 3. Clear the CCF flag of the AES_SR register, by setting to 1 the CCF bit of the AES_ICR register.
   2. 4. Save the AES_SUSPxR registers (where x is from 0 to 7) in the memory.
   3. 5. Save the AES_IVRx registers as, during the data processing, they changed from their initial values.
   4. 6. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.
   5. 7. Save the current AES configuration in the memory, excluding the initialization vector registers AES_IVRx. Key registers do not need to be saved as the original key value is known by the application.
   6. 8. If DMA is used, save the DMA controller status (pointers for IN data transfers, number of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers must also be saved.

To resume the processing of a message , proceed as follows:

1. 1. If DMA is used, configure the DMA controller in order to complete the rest of the FIFO IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be configured in the DMA controller.
2. 2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
3. 3. Write the suspend register values, previously saved in the memory, back into their corresponding AES_SUSPxR registers (where x is from 0 to 7).
4. 4. Write the initialization vector register values, previously saved in the memory, back into their corresponding AES_IVRx registers.
5. 5. Restore the initial setting values in the AES_CR and AES_KEYRx registers.
6. 6. Enable the AES peripheral by setting the EN bit of the AES_CR register.
7. 7. If DMA is used, enable AES DMA requests by setting to 1 the DMAINEN bit (and DMAOUTEN bit if in payload phase) of the AES_CR register.

49.4.13 AES operation with shared keys

The AES peripheral can use the SAES peripheral as security co-processor. In this case, secure application prepares the key in the robust SAES peripheral. When ready, the AES application can load this prepared key through a dedicated hardware key bus.

Recommended sequences are described below and in SAES peripheral section Section 50.4.10: SAES operation with shared keys .

1. 1. In SAES peripheral application encrypts the key to be shared, once, in Shared-key mode (KMOD[1:0] = 10).
2. 2. Each time shared key is needed in AES peripheral application needs to decrypt it in SAES peripheral, selecting the same Shared-key mode (KMOD[1:0] = 10).
3. 3. Once the shared key is decrypted and loaded in SAES_KEYRx registers it can be shared with the AES peripheral. Indeed, when shared key must be loaded in AES peripheral, application sets correct KEYSIZE and write KMOD[1:0] = 10 in AES_CR register. When KEYVALID is cleared, the key information is automatically transferred by hardware into AES_KEYRx, with BUSY set in AES_SR.
4. 4. Once transfer is completed BUSY bit is cleared and KEYVALID bit is set in AES_SR register. If KEYVALID is not set when BUSY bit is cleared, or if a key error flag (KEIF) is set it means that an unexpected event occurred during the transfer (for example

hardware fault) or the KEYVALID bit in SAES_SR was cleared before the end of the transfer. When such errors occur, the whole SAES key sharing process must be restarted through the IPRST bits of control registers in both SAES and AES peripherals (see Section 49.4.18 for details).

At that point AES is initialized with a valid, shared key. Application can proceed with the processing of data, setting KMOD[1:0] to 00.

Note: While KMOD[1:0] = 10 and BUSY = 1, if KEYSIZE in AES peripheral is different from the KEYSIZE in SAES peripheral the key sharing fails and KEIF is set in both peripherals.

49.4.14 AES data registers and data swapping

Data input and output

A 128-bit data block is entered into the AES peripheral with four successive 32-bit word writes into the AES_DINR register (bitfield DIN[31:0]), the most significant word (bits [127:96]) first, the least significant word (bits [31:0]) last.

A 128-bit data block is retrieved from the AES peripheral with four successive 32-bit word reads from the AES_DOUTR register (bitfield DOUT[31:0]), the most significant word (bits [127:96]) first, the least significant word (bits [31:0]) last.

The 32-bit data word for AES_DINR register or from AES_DOUTR register is organized in big endian order, that is:

• • the most significant byte of a word to write into AES_DINR must be put on the lowest address out of the four adjacent memory locations keeping the word to write, or
• • the most significant byte of a word read from AES_DOUTR goes to the lowest address out of the four adjacent memory locations receiving the word

For using DMA for input data block write into AES, the four words of the input block must be stored in the memory consecutively and in big-endian order, that is, the most significant word on the lowest address. See Section 49.4.17: AES DMA interface .

Data swapping

The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no swapping on the input data word in the AES_DINR register, before loading it to the AES processing core, and on the data output from the AES processing core, before sending it to the AES_DOUTR register. The choice depends on the type of data. For example, a byte swapping is used for an ASCII text stream.

The data swap type is selected through the DATATYPE[1:0] bitfield of the AES_CR register. The selection applies both to the input and the output of the AES core.

For different data swap types, Figure 482 shows the construction of AES processing core input buffer data P127 to P0, from the input data entered through the AES_DINR register, or the construction of the output data available through the AES_DOUTR register, from the AES processing core output buffer data P127 to P0.

Figure 482. 128-bit block construction with respect to data swap

Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not sensitive to the swap mode selection.

Data padding

Figure 482 also gives an example of memory data block padding with zeros such that the zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core input buffer. The example shows the padding of an input data block containing:

• • 48 message bits, with DATATYPE[1:0] = 01
• • 56 message bits, with DATATYPE[1:0] = 10
• • 34 message bits, with DATATYPE[1:0] = 11

49.4.15 AES key registers

The AES_KEYRx write-only registers store the encryption or decryption key bitfield KEY[127:0] or KEY[255:0]. The data to write to each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address (reads are not allowed for security reason).

The key is spread over eight registers as shown in Table 473 .

Table 473. Key endianness in AES_KEYRx registers (128- or 256-bit key length)

The key for encryption or decryption may be written into these registers when the AES peripheral is disabled, by clearing the EN bit of the AES_CR register.

The key registers are not affected by the data swapping controlled by DATATYPE[1:0] bitfield of the AES_CR register.

The entire key must be written before starting an AES computation. In normal key mode (KMOD[1:0] = 00), the AES_KEYRx (x = 0 to 3 for KEYSIZE = 0, x = 0 to 7 for KEYSIZE = 1) registers must always be written in either ascending or descending order.

Note: Initiating the key-loading sequence sets the BUSY flag and clears the KEYVALID flag. Once the amount of bits defined by KEYSIZE is transferred to the AES_KEYRx registers, BUSY is cleared, KEYVALID set and the EN bit becomes writable. If an error occurs, BUSY and KEYVALID are cleared and KEIF set (see Section 49.4.18: AES error management for details). For additional information on key modes, refer to Section 49.4.13 .

49.4.16 AES initialization vector registers

The four AES_IVRx registers keep the initialization vector input bitfield IVI[127:0]. The data to write to or to read from each register is organized in the memory in little-endian order, that is, with most significant byte on the highest address. The registers are also ordered from lowest address (AES_IVR0) to highest address (AES_IVR3).

The signification of data in the bitfield depends on the chaining mode selected. When used, the bitfield is updated upon each computation cycle of the AES core.

Write operations to the AES_IVRx registers when the AES peripheral is enabled have no effect to the register contents. For modifying the contents of the AES_IVRx registers, the EN bit of the AES_CR register must first be cleared.

Reading the AES_IVRx registers returns the latest counter value (useful for managing suspend mode).

The AES_IVRx registers are not affected by the data swapping feature controlled by the DATATYPE[1:0] bitfield of the AES_CR register.

49.4.17 AES DMA interface

The AES peripheral provides an interface to connect to the DMA (direct memory access) controller. The DMA operation is controlled through the AES_CR register.

Data input using DMA

Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES peripheral then initiates a DMA request during the input phase each time it requires to write a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 483.

Note: According to the algorithm and the mode selected, special padding / ciphertext stealing might be required. For example, in case of AES GCM encryption or AES CCM decryption, a DMA transfer must not include the last block. For details, refer to Section 49.4.4: AES procedure to perform a cipher operation.

Figure 483. DMA transfer of a 128-bit data block during input phase

Data output using DMA

Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The AES peripheral then initiates a DMA request during the Output phase each time it requires to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 484.

Note: According to the message size, extra bytes might need to be discarded by application in the last block.

Figure 484. DMA transfer of a 128-bit data block during output phase

DMA operation in different operating modes

DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the AES_KEYRx registers must be written by software, enabling the DMA transfer through the DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.

DMA single requests are generated by AES until it is disabled. So, after the data output phase at the end of processing of a 128-bit data block, AES switches automatically to a new data input phase for the next data block, if any.

When the data transferring between AES and memory is managed by DMA, the CCF flag has no use because the reading of the AES_DOUTR register is managed by DMA automatically at the end of the computation phase. The CCF flag must only be cleared when transiting back to data transferring managed by software. See Section 49.4.4: AES procedure to perform a cipher operation , subsection Data append , for details.

49.4.18 AES error management

AES configuration can be changed at any moment by clearing the EN bit of the AES_CR register.

Read error flag (RDERR)

Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR register and the RWEIF flag of the AES_ISR register, and returns zero.

RDERR is triggered during the computation phase or during the input phase.

Note: AES is not disabled upon a RDERR error detection and continues processing.

An interrupt is generated if the RWEIE bit of the AES_IER register is set. For more details, refer to Section 49.5: AES interrupts .

The RDERR and RWEIF flag is cleared by setting the RWEIE bit of the AES_ICR register.

Write error flag (WDERR)

Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR register and the RWEIF flag of the AES_ISR register, and has no effect on the AES_DINR register. The WRERR is triggered during the computation phase or during the output phase.

Note: AES is not disabled after a WRERR error detection and continues processing.

An interrupt is generated if the RWEIE bit of the AES_IER register is set. For more details, refer to Section 49.5: AES interrupts .

The WRERR and RWEIF flag is cleared by setting the RWEIF bit of the AES_ICR register.

Key error interrupt flag (KEIF)

Failure to load a key into key registers, sets the KEIF flag of the AES_ISR register and clears the KEYVALID bit of the AES_SR register.

The KEIF flag is cleared with corresponding bit of the AES_ICR register. An interrupt is generated if the KEIE bit of the AES_IER register is set. For more details, refer to Section 49.5: AES interrupts .

The possible sources of key errors are:

• • Key writing sequence error: an incorrect sequence has been detected when writing key registers. See Section 49.4.15: AES key registers for details.
• • Key sharing size mismatch: error is triggered when KMOD[1:0] = 10 and application sets a KEYSIZE information in AES peripheral that does not match the KEYSIZE stored in SAES peripheral
• • Key sharing error: the copy of key registers from SAES peripheral to AES failed. See Section 49.4.13: AES operation with shared keys for details.

Upon a key sharing error, reset both AES and SAES peripherals through the IPRST bit of their corresponding control register, then restart the key sharing sequence.

Note: For any key error, clear KEIF flag prior to re-configuring AES.

49.5 AES interrupts

Individual maskable interrupt sources generated by the AES peripheral signal the following events:

• • computation completed
• • read error
• • write error
• • key error

These sources are combined into a common interrupt signal from the AES peripheral that connects to the Arm ^® Cortex ^® interrupt controller. Each can individually be enabled/disabled, by setting/clearing the corresponding enable bit of the AES_IER register, and cleared by setting the corresponding bit of the AES_ICR register.

The status of each can be read from the AES_SR and AES_ISR registers.

Table 474 gives a summary of the interrupt sources, their event flags and enable bits.

Table 474. AES interrupt requests

1. Bit of the AES_ICR register.

2. Flag of the AES_SR register, mirrored by the flag RWEIF of the AES_ISR register.

49.6 AES processing latency

The tables below summarize the latency to process a 128-bit block for each mode of operation.

Table 475. Processing latency for ECB, CBC and CTR

Table 476. Processing latency for GCM and CCM (in clock cycles)

1. Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).

49.7 AES registers

49.7.1 AES control register (AES_CR)

Address offset: 0x00

Reset value: 0x0000 0000

Bit 31 IPRST : AES peripheral software reset

Setting the bit resets the AES peripheral, putting all registers to their default values, except the IPRST bit itself. Hence, any key-relative data is lost. For this reason, it is recommended to set the bit before handing over the AES to a less secure application.

The bit must be low while writing any configuration registers.

Bits 30:26 Reserved, must be kept at reset value.

Bits 25:24 KMOD[1:0] : Key mode selection

The bitfield defines how the AES key can be used by the application:

00: Normal key

10: Shared key from SAES co-processor

Others: Reserved

With normal key selection, the key registers are freely usable, no specific usage or protection applies to AES_DIN and AES_DOUT registers.

With selection of shared key from SAES co-processor, the AES peripheral automatically loads its key registers with the data stored in the key registers of the SAES peripheral. The key value is available in key registers when BUSY bit is cleared and KEYVALID is set in the AES_SR register. Key error flag KEIF is set otherwise in the AES_ISR register.

The bitfield must be set only when KEYSIZE is correct, and when a shared key decryption sequence has been successfully completed in SAES co-processor.

Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bits 23:20 NPBLB[3:0] : Number of padding bytes in last block

The bitfield sets the number of padding bytes in last block of payload:

0000: All bytes are valid (no padding)

0001: Padding for one least-significant byte of last block

...

1111: Padding for 15 least-significant bytes of last block

Bit 19 Reserved, must be kept at reset value.

Bit 18 KEYSIZE : Key size selection

This bitfield defines the length of the key used in the AES cryptographic core, in bits:

0: 128
1: 256

Attempts to write the bit are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bit 17 Reserved, must be kept at reset value.

Bit 15 Reserved, must be kept at reset value.

Bits 14:13 GCMPH[1:0] : GCM or CCM phase selection

This bitfield selects the phase of GCM, GMAC or CCM algorithm:

00: Init phase
01: Header phase
10: Payload phase
11: Final phase

The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).

Bit 12 DMAOUTEN : DMA output enable

This bit enables/disables data transferring with DMA, in the output phase:

0: Disable
1: Enable

When the bit is set, DMA requests are automatically generated by AES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).

Bit 11 DMAINEN : DMA input enable

This bit enables/disables data transferring with DMA, in the input phase:

0: Disable
1: Enable

When the bit is set, DMA requests are automatically generated by AES during the input data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).

Bits 10:7 Reserved, must be kept at reset value.

Bits 16, 6:5 CHMOD[2:0] : Chaining mode selection

This bitfield selects the AES chaining mode:

000: Electronic codebook (ECB)
001: Cipher-block chaining (CBC)
010: Counter mode (CTR)
011: Galois counter mode (GCM) and Galois message authentication code (GMAC)
100: Counter with CBC-MAC (CCM)
others: Reserved

Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bits 4:3 MODE[1:0] : AES operating mode

This bitfield selects the AES operating mode:

00: Mode 1: encryption

01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)

10: Mode 3: decryption

11: Reserved

Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bits 2:1 DATATYPE[1:0] : Data type selection

This bitfield defines the format of data written in the AES_DINR register or read from the AES_DOUTR register, through selecting the mode of data swapping:

00: None

01: Half-word (16-bit)

10: Byte (8-bit)

11: Bit

For more details, refer to Section 49.4.14: AES data registers and data swapping .

Attempts to write the bitfield are ignored when the BUSY flag of AES_SR register is set, as well as when the EN bit of the AES_CR register is set before the write access and it is not cleared by that write access.

Bit 0 EN : AES enable

This bit enables/disables the AES peripheral:

0: Disable

1: Enable

At any moment, clearing then setting the bit re-initializes the AES peripheral.

This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2) and upon the completion of GCM/GMAC/CCM initial phase.

The bit cannot be set as long as KEYVALID = 0.

Note: With KMOD[1:0] other than 00, use the IPRST bit rather than the bit EN.

49.7.2 AES status register (AES_SR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

This bit is set by hardware when the amount of key information defined by KEYSIZE in AES_CR has been loaded in AES_KEYx key registers.

0: No valid key information is available in key registers. EN bit in AES_CR cannot be set.

1: Valid key information, defined by KEYSIZE in AES_CR, is loaded in key registers.

In normal mode when KEYSEL equals to zero, the application must write the key registers in the correct sequence, otherwise the KEIF flag of the AES_ISR register is set and KEYVALID stays at zero.

When KEYSEL is different from zero the BUSY flag is automatically set by AES. When key is loaded successfully, the BUSY flag is cleared and KEYVALID set. Upon an error, the KEIF flag of the AES_ISR register is set, the BUSY flag cleared and KEYVALID kept at zero.

When the KEIF flag is set, the application must clear it through the AES_ICR register, otherwise KEYVALID cannot be set. See the KEIF bit description for more details.

For more information on key loading, refer to Section 49.4.15: AES key registers .

Bits 6:4 Reserved, must be kept at reset value.

This flag indicates whether AES is idle or busy during GCM payload encryption phase:

0: Idle

1: Busy

When the flag indicates “idle”, the current GCM encryption processing may be suspended to process a higher-priority message. In other chaining modes, or in GCM phases other than payload encryption, the flag must be ignored for the suspend process.

The flag is set when transferring a shared key from SAES peripheral.

This flag indicates the detection of an unexpected write operation to the AES_DINR register (during computation or data output phase):

0: Not detected

1: Detected

The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the AES_ICR register.

Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the AES_ICR register.

The flag setting has no impact on the AES operation. Unexpected write is ignored.

This flag indicates the detection of an unexpected read operation from the AES_DOUTR register (during computation or data input phase):

0: Not detected

1: Detected

The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the AES_ICR register.

Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the AES_ICR register.

The flag setting has no impact on the AES operation. Unexpected read returns zero.

This bit mirrors the CCF bit of the AES_ISR register.

49.7.3 AES data input register (AES_DINR)

Address offset: 0x08

Reset value: 0x0000 0000

Only 32-bit write access type is supported.

Bits 31:0 DIN[31:0] : Input data word

A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit block of input data to the AES peripheral. From the first to the fourth write, the corresponding data weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into the AES core 128-bit input buffer.

The data signification of the input data block depends on the AES operating mode:

• - Mode 1 (encryption): plaintext
• - Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input)
• - Mode 3 (decryption): ciphertext

The data swap operation is described in Section 49.4.14: AES data registers and data swapping on page 1951 .

49.7.4 AES data output register (AES_DOUTR)

Address offset: 0x0C

Reset value: 0x0000 0000

Only 32-bit read access type is supported.

Bits 31:0 DOUT[31:0] : Output data word

This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon the computation completion (CCF set), virtually reads a complete 128-bit block of output data from the AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled by the data swap block according to the DATATYPE[1:0] bitfield.

Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0].

The data signification of the output data block depends on the AES operating mode:

• - Mode 1 (encryption): ciphertext
• - Mode 2 (key derivation): the bitfield is not used
• - Mode 3 (decryption): plaintext

The data swap operation is described in Section 49.4.14: AES data registers and data swapping on page 1951 .

49.7.5 AES key register 0 (AES_KEYR0)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:0 KEY[31:0] : Cryptographic key, bits [31:0]

This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the operating mode:

• - In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption key.
• - In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before being used for decryption.

The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES peripheral is disabled (EN bit of the AES_CR register cleared). A special writing sequence is also required, as described in KEYVALID bit of the AES_SR register. Note that, if KMOD[1:0] = 10 (shared key), the key is directly loaded from SAES peripheral to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set).

Refer to Section 49.4.15: AES key registers on page 1953 for more details.

49.7.6 AES key register 1 (AES_KEYR1)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:0 KEY[63:32] : Cryptographic key, bits [63:32]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

49.7.7 AES key register 2 (AES_KEYR2)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:0 KEY[95:64] : Cryptographic key, bits [95:64]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

49.7.8 AES key register 3 (AES_KEYR3)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:0 KEY[127:96] : Cryptographic key, bits [127:96]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

49.7.9 AES initialization vector register 0 (AES_IVR0)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:0 IVI[31:0] : Initialization vector input, bits [31:0]

Refer to Section 49.4.16: AES initialization vector registers on page 1953 for description of the IVI[127:0] bitfield.

The initialization vector is only used in chaining modes other than ECB.

The AES_IVRx registers may be written only when the AES peripheral is disabled

49.7.10 AES initialization vector register 1 (AES_IVR1)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:0 IVI[63:32] : Initialization vector input, bits [63:32]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

49.7.11 AES initialization vector register 2 (AES_IVR2)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:0 IVI[95:64] : Initialization vector input, bits [95:64]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

49.7.12 AES initialization vector register 3 (AES_IVR3)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:0 IVI[127:96] : Initialization vector input, bits [127:96]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

49.7.13 AES key register 4 (AES_KEYR4)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:0 KEY[159:128] : Cryptographic key, bits [159:128]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

49.7.14 AES key register 5 (AES_KEYR5)

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:0 KEY[191:160] : Cryptographic key, bits [191:160]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

49.7.15 AES key register 6 (AES_KEYR6)

Address offset: 0x38

Reset value: 0x0000 0000

Bits 31:0 KEY[223:192] : Cryptographic key, bits [223:192]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

49.7.16 AES key register 7 (AES_KEYR7)

Address offset: 0x3C

Reset value: 0x0000 0000

Bits 31:0 KEY[255:224] : Cryptographic key, bits [255:224]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used in that case).

49.7.17 AES suspend registers (AES_SUSPxR)

Address offset: 0x040 + 0x4 * x, (x = 0 to 7)

Reset value: 0x0000 0000

These registers contain the complete internal register states of the AES processor when the AES processing of the current task is suspended to process a higher-priority task.

Upon suspend, the software reads and saves the AES_SUSPxR register contents (where x is from 0 to 7) into memory, before using the AES processor for the higher-priority task.

Upon completion, the software restores the saved contents back into the corresponding suspend registers, before resuming the original task.

Note: These registers are used only when GCM, GMAC, or CCM chaining mode is selected.

These registers can be read only when AES is enabled. Reading these registers while AES is disabled returns 0x0000 0000.

Bits 31:0 SUSP[31:0] : AES suspend

Upon suspend operation, this bitfield of the corresponding AES_SUSPxR register takes the value of one of internal AES registers.

49.7.18 AES interrupt enable register (AES_IER)

Address offset: 0x300

Reset value: 0x0000 0000

Bits 31:3 Reserved , must be kept at reset value.

Bit 2 KEIE: Key error interrupt enable

This bit enables or disables (masks) the AES interrupt generation when KEIF (key error flag) is set.

• 0: Disabled (masked)
• 1: Enabled (not masked)

Bit 1 RWEIE: Read or write error interrupt enable

This bit enables or disables (masks) the AES interrupt generation when RWEIF (read and/or write error flag) is set.

• 0: Disabled (masked)
• 1: Enabled (not masked)

Bit 0 CCFIE: Computation complete flag interrupt enable

This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete flag) is set.

• 0: Disabled (masked)
• 1: Enabled (not masked)

49.7.19 AES interrupt status register (AES_ISR)

Address offset: 0x304

Reset value: 0x0000 0000

Bits 31:3 Reserved , must be kept at reset value.

Bit 2 KEIF : Key error interrupt flag

This read-only bit is set by hardware when key information failed to load into key registers.

0: No key error detected

1: Key information failed to load into key registers

Setting the corresponding bit of the AES_ICR register clears the KEIF and generates interrupt if the KEIE bit of the AES_IER register is set.

KEIF is triggered upon any of the following errors:

• – AES_KEYRx register write does not respect the correct order. (For KEYSIZE = 0, AES_KEYR0 then AES_KEYR1 then AES_KEYR2 then AES_KEYR3 register, or reverse. For KEYSIZE = 1, AES_KEYR0 then AES_KEYR1 then AES_KEYR2 then AES_KEYR3 then AES_KEYR4 then AES_KEYR5 then AES_KEYR6 then AES_KEYR7 , or reverse).

KEIF must be cleared by the application software, otherwise KEYVALID cannot be set.

Bit 1 RWEIF : Read or write error interrupt flag

This read-only bit is set by hardware when a RDERR or a WRERR error flag is set in the AES_SR register.

0: No read or write error detected

1: Read or write error detected (see AES_SR register for details)

RWEIF bit is cleared when application sets the corresponding bit of AES_ICR register. An interrupt is generated if the RWEIE bit has been previously set in the AES_IER register.

This flags has no meaning when key derivation mode is selected.

Bit 0 CCF : Computation complete flag

This flag indicates whether the computation is completed:

0: Not completed

1: Completed

The flag is set by hardware upon the completion of the computation. It is cleared by software, upon setting the CCF bit of the AES_ICR register.

Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_IER register.

The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.

49.7.20 AES interrupt clear register (AES_ICR)

Address offset: 0x308

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 KEIF : Key error interrupt flag clear

Setting this bit clears the KEIF status bit of the AES_ISR register.

Bit 1 RWEIF : Read or write error interrupt flag clear

Setting this bit clears the RWEIF status bit of the AES_ISR register, and both RDERR and WRERR flags in the AES_SR register.

Bit 0 CCF : Computation complete flag clear

Setting this bit clears the CCF status bit of the AES_SR and AES_ISR registers.

49.7.21 AES register map

Table 477. AES register map and reset values