39. Multi-function digital filter (MDF)

39.1 MDF introduction

The multi-function digital filter (MDF) is a high-performance module dedicated to the connection of external sigma-delta ( \( \Sigma\Delta \) ) modulators. It is mainly targeted for the following applications:

• • audio capture signals
• • motor control
• • metering

The MDF features up to 6 digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible digital processing options to offer up to 24-bit final resolution.

The DFLTx of the MDF also include the filters of the audio digital filter (ADF).

The MDF can receive, via its serial interfaces, streams coming from various digital sensors.

The MDF supports the following standards allowing the connection of various \( \Sigma\Delta \) modulator sensors:

• • SPI interface
• • Manchester coded 1-wire interface
• • PDM interface

A flexible bitstream matrix (BSMX) allows the connection of any incoming bitstream to any filter.

The MDF converts an input data stream into clean decimated digital data words. This conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is possible to insert a high-pass filter or a DC offset correction block.

The conversion speed and resolution are adjustable according to configurable parameters for digital processing: filter type, filter order, decimation ratio, integrator length. The maximum output data resolution is up to 24 bits. There are two conversion modes: single conversion and continuous modes. The data can be automatically stored in a system RAM buffer through DMA, thus reducing the software overhead.

A flexible trigger interface can be used to control the conversion start. This timing control can trigger simultaneous conversions or insert a programmable delay between conversions.

The MDF features an out-of-limit detectors (OLD) function. There is one OLD for each digital filter chain. Independent programmable thresholds are available for each OLD, making it very suitable for over-current detection.

A short circuit detector (SCD) is also available for every selected bitstream. The SCD is able to detect a short-circuit condition with a very short latency. Independent programmable thresholds are offered in order to define the short circuit condition.

The digital processing is performed using only the kernel clock. The MDF requests the bus interface clock (AHB clock) only when data must be transferred or when a specific event requests the attention of the system processor.

39.2 MDF main features

• • AHB interface
• • up to 6 serial digital inputs:
  • – configurable SPI interface to connect various digital sensors
  • – configurable Manchester coded interface support
  • – compatible with PDM interface to support digital microphones
• • 2 common clocks input/output for \( \Sigma\Delta \) modulators
• • Flexible matrix (BSMX) for connection between filters and digital inputs
• • 2 inputs to connect the internal ADCs
• • up to 6 flexible digital filter paths, including:
  • – A configurable CIC filter:
    • - Can be split into 2 CIC filters: high-resolution filter and out-off limit detector
    • - Can be configured in Sinc ⁴ filter
    • - Can be configured in Sinc ⁵ filter
    • - Adjustable decimation ratio
  • – A reshape filter to improve the out-off band rejection and in-band ripple
  • – A high-pass filter to cancel the DC offset
  • – An offset error cancellation
  • – Gain control
  • – Saturation blocks
  • – An out-off limit detector
• • Short-circuit detector
• • Clock absence detector
• • 16- or 24-bit signed output data resolution
• • Continuous or single conversion
• • Possibility to delay independently each bitstream
• • Various trigger possibilities
• • Break generation on out-of limit or short-circuit detector events
• • Autonomous functionality in Stop mode(s)
• • DMA can be used to read the conversion data
• • Interrupts services

39.3 MDF implementation

The devices embed one MDF instance and one ADF instance, both being digital filters with common features.

Table 367. ADF/MDF features ⁽¹⁾

1. 'X' = supported, '-' = not supported.

2. Only Stop 0, Stop 1, and Stop 2 modes.

3. Only Stop 0 and Stop 1 modes.

39.4 MDF functional description

39.4.1 MDF block diagram

Figure 327. MDF block diagram

1. 1. Refer to Section 39.3: MDF implementation to check if the ADCITF is available, and which ADCs are connected.
2. 2. Not always implemented, refer to the vector table of the product for details.
3. 3. Refer to Section 39.3: MDF implementation to check the number of filter instances available.
4. 4. The number of trigger inputs depends on the product. Refer to Section 39.3: MDF implementation for details.

39.4.2 MDF pins and internal signals

Table 368. MDF external pins

1. The number of inputs available depends on the number of filters. Refer to Section 39.3 for details.

Table 369. MDF internal signals

1. The number of signals available depends on the number of filters. Refer to Section 39.3 for details.

2. Not always connected. See the interrupt vector table for details.

The table below shows the way the trigger inputs of the MDF are connected.

Table 370. MDF trigger connections

The table below shows the way the break outputs of the MDF are connected.

The table below shows the way the ADC data are connected to the MDF.

1. Only available in STM32U59x/5Ax/5Fx/5Gx. It is not connected in STM32U535/545/575/585.

39.4.3 Serial input interfaces (SITF)

The SITFx input interfaces allow the connection of the external sensors to the digital filters, via the bitstream matrix (BSMX). The SITFx serial interface can be configured in the following modes:

• • LF_MASTER SPI mode (low-frequency)
• • normal SPI mode
• • Manchester mode

The amount of SITFx instances is equal to the amount of filters.

The data from each serial interface can be routed to any filter in order to perform:

• • the PDM to PCM conversion
• • the out-of limit detection
• • the short detection

The serial interfaces are enabled by setting the corresponding SITFEN bit to 1. Once the interface is enabled, it receives serial data from the external \( \Sigma\Delta \) modulator.

Note: Before enabling the serial interface, the user must insure that the mdf_proc_ck is already enabled (see Section 39.4.5 for details).

The SITFx are controlled via the MDF serial interface control register x (MDF_SITFxCxR) .

As shown in Figure 328 , for each SITF, there is a large choice of clocking possibilities:

• • If the serial interface is programmed in SPI mode, the selected clock source is a copy of the clock present on MDF_CCK0 or MDF_CCK1 or MDF_CKlx pin (see 2 in Figure 328 ).
• • If the serial interface is programmed in LF_MASTER SPI mode, the selected clock source must be the clock directly provided by the CCKDIV to the MDF_CCK0 or MDF_CCK1 pin (see 1 in Figure 328 ). In this case MDF_CKlx must not be selected.

See Table 373 for additional information.

Note: Using the common clock (MDF_CCK0 or MDF_CCK1) can be helpful to share the same clock between several SITFx.

Figure 328. SITFx overview

LF_MASTER and normal SPI modes

The LF_MASTER SPI mode is a special mode allowing the usage of a mdf_proc_ck clock frequency, only two times higher than the sensor clock. This mode is dedicated to low-power use-cases, using low-speed sensors.

In LF_MASTER SPI mode, the MDF must provide the bitstream clock to the external sensors via MDF_CCK0 and MDF_CCK1 pins, and receives the bitstream data via the serial data input MDF_SDIx.

For each SITFx, the application must select the same clock than the one provided to the external sensor (MDF_CCK0 or MDF_CCK1), in order to guarantee optimal timing performances. This selection is done via SCKSRC[1:0].

Warning: The MDF_CKIx pin cannot be used in LF_MASTER SPI mode.

The normal SPI interface is a more flexible interface than the LF_MASTER SPI, but the mdf_proc_ck frequency must be at least four times higher than the sensor clock.

The application can select MDF_CCK0, MDF_CCK1 or MDF_CKIx clock for the capture of the data received via the MDF_SDIx pin.

The MDF can generate a clock to the sensors via MDF_CCK0 or MDF_CCK1 if needed.

For all SPI modes, all SITFs can share the same clock input (MDF_CCK0 or MDF_CCK1), in order to optimize the amount of requested I/Os.

For all SPI modes, the serial data is captured using the rising and the falling edge of the selected clock. The SITFx always provides the following bitstreams:

• • bitstream received using the bitstream clock falling edge (bsx_f)
• • bitstream received using the bitstream clock rising edge (bsx_r)

According to the sensors connected, one of the two bitstreams may not be available.

The application can select the wanted stream via the BSMX matrix.

Figure 329. SPI timing example

To properly synchronize/receive the data stream, the frequency of the mdf_proc_ck clock must be adjusted according to the constraints listed in Table 374 .

Clock absence detection

A no-clock-transition period may be detected when the serial interface works in normal SPI mode. This feature can be used to detect a clock failure in the SPI link.

The application can program a timeout value via the STH[4:0] bitfield of the corresponding SITFx. If the MDF does not detect clock transitions for a duration of \( STH[4:0] \times T_{mdf\_proc\_ck} \) , then the CKABF flag is set.

An interrupt can be generated if CKABIE is set to 1. The STH[4:0] bitfield is in the MDF serial interface control register x (MDF_SITFxCN) .

When the serial interface is enabled, the CKABF flag remains to 1 until a first clock transition is detected.

To avoid spurious clock absence detection, the following sequence must be respected:

1. 1. Configure the serial interface in normal SPI mode and enable it.
2. 2. Clear the CKABF flag by writing CKABF bit to 1.
   If no clock transition is detected on the serial interface, the hardware immediately sets the CKABF flag to 1.
3. 3. Read the CKABF flag:
   • – If CKABF = 1, go back to step 2.
   • – If CKABF = 0, a clock has been detected. The CKABIE bit can be set to 1 if the application wants an interrupt on detection of a clock absence.

Note: The clock absence detection feature is not available in the LF_MASTER SPI mode.

Manchester mode

In Manchester coded format, the MDF receives data stream from the external sensor via the MDF_SDlx pin only.

The MDF_CKlx pins are not needed in this mode.

Decoded data and clock signals are recovered from serial stream after Manchester decoding. They are available on bsx_r. There are two possible settings of Manchester codings:

• • signal rising edge decoded as 0 and signal falling edge decoded as 1
• • signal rising edge decoded as 1 and signal falling edge decoded as 0

Figure 330. Manchester timing example (SITFMOD = 11)

To decode the incoming Manchester stream, the user must program the STH[4:0] bitfield in the MDF serial interface control register x (MDF_SITFxCN) . The STH[4:0] bitfield is used by the SITFx to estimate the Manchester symbol length and to detect a clock absence. An internal counter (MCNT) is restarted every time a transition is detected in the MDF_SDix input. It is used to detect short transitions, long transitions or clock absence. A long transition indicates that the data value changed. Figure 330 shows a case where the OVR is around height and STH[4:0] = 5.

The estimated Manchester symbol rate ( \( T_{SYMB} \) ) must respect the following formula:

It is recommended to compute STH as follows:

where OVR represents the ratio between the mdf_proc_ck frequency and the expected Manchester symbol frequency. OVR must be higher than five, and the mdf_proc_ck clock must be adjusted according to the constraints listed in Table 374 .

The clock absence flag CKABF is set to 1 when no transition is detected during more than \( 2 \times STH[4:0] \times T_{mdf\_proc\_ck} \) , or when the SITFx is not yet synchronized to the incoming Manchester stream. In addition, an interrupt can be generated if the bit CKABIE is set to 1.

When the serial interface is enabled, the MDF must first be synchronized to the incoming Manchester stream. The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (pink circle in the Figure 330 ) is detected.

The end of the synchronization phase can be checked by following the software sequence:

1. 1. Clear the CKABF flag in the MDF_DFLT \( x \) interrupt status register \( x \) (MDF_DFLT \( x \) ISR) by writing CKABF bit to 1. If the serial interface is not yet synchronized, the hardware immediately sets the CKABF flag to 1.
2. 2. Read the CKABF flag.
   • – If CKABF = 1, go back to step 1.
   • – If CKABF = 0, the Manchester interface is synchronized and provides valid data.

Programming example

In the following example, the MDF kernel clock frequency ( \( F_{\text{mdf\_ker\_ck}} \) ) is 100 MHz and the received Manchester stream is at about 6 MHz ( \( F_{\text{SYMB}} \) ).

1. 1. Provide a valid \( \text{mdf\_proc\_ck} \) to the SITF \( x \) .

The \( \text{mdf\_proc\_ck} \) frequency must be at least six times higher than the Manchester symbol frequency (means at least 36 MHz).

PROCDIV is programmed to 1 to perform a division by two of the kernel clock. In that case, \( F_{\text{mdf\_proc\_ck}} = 50 \) MHz (8.33 times higher than the Manchester symbol frequency).

1. 2. Compute STH.

OVR is given by: \( \text{OVR} = F_{\text{mdf\_proc\_ck}} / F_{\text{SYMB}} = 50 \text{ MHz} / 6 \text{ MHz} = 8.33 \) .

The minimum allowed frequency for the Manchester stream is then:

The maximum allowed frequency for the Manchester stream is then:

39.4.4 ADC slave interface (ADCITF)

The ADCs are not always connected to the MDF. Refer to Section 39.3 to check the situation for this product.

The MDF allows the connection of up to two ADCs to the filter path. For each filter, the DATSRC[1:0] bitfield in the MDF digital filter configuration register \( x \) (MDF_DFLT \( x \) CICR) allows the application to select either data from the ADCs.

Warning: The MDF does not support receiving interleaved data from one of the ADCITF input.

39.4.5 Clock generator (CKGEN)

The RCC (reset and clock controller) provides the following clocks to the MDF:

• • AHB clock (mdf_hclk) used for the register interface
• • kernel clock (mdf_ker_ck) mainly used by all other parts of the circuit via the CKGEN

Those clocks are not supposed to be phase locked, so all signals crossing those clock domains are resynchronized.

The clock generator (CKGEN) is responsible of the generation of the processing clock, and the clock provided to the MDF_CCK0 and MDF_CCK1 pins. All those clocks are generated from the mdf_ker_ck.

The processing clock (mdf_proc_ck) is used to run all the signals processing and to re-sample the incoming serial or parallel stream.

Note: The reshape filter (RSFLT) needs up to 24 cycles of mdf_proc_ck clock to process a sample.

To adapt the kernel clock frequency provided by the RCC, the following dividers are available:

• • PROCDIV[6:0] used to adapt the kernel clock frequency to the constraints of the parallel and serial interfaces, and to the processing blocks
• • CCKDIV[3:0] used to adapt the frequency of the MDF_CCK0 and MDF_CCK1 clocks

PROCDIV[6:0] and CCKDIV[3:0] must be programmed when no clock is provided to the dividers (CKGDEN = 0).

The mdf_proc_ck generation is controlled by CKGDEN.

In addition, the CKGMOD bit allows the application to define the way to trigger the CCKDIV divider:

• • When CKGMOD = 0, the CCKDIV divider is started as soon as CKGDEN is set to 1.
• • When CKGMOD = 1, the CCKDIV divider is started when CKGDEN is set to 1 and the programmed trigger condition occurred.

All bits and fields controlling the CKGEN are in MDF_CKGCR.

Figure 331. CKGEN overview

The trigger logic for CKGEN is handled by the TRG_CK block. As shown in Figure 340 , the CCKDIV divider can be triggered on the rising or falling edge of one of the 16 trigger sources. When the proper trigger condition occurs, the cck_trg signal goes to high, allowing the CCKDIV divider to start. The TRG_CK logic is reset when CKGDEN is set to 0.

This feature can be helpful to synchronize the MDF_CCKy (y = 0,1) clock of several MDF instances, or to synchronize the clock generation to a timer event.

The application can control the activation of the MDF_CCK0 or MDF_CCK1 pin CCK0EN/CCK1EN and CCK0DIR/CCK1DIR bits:

• • CCKyEN is used to enable the CCKDIV, and thus generates a clock for the external sensors.
• • CCKyDIR is used to control the direction of the ADF_CCKy pin (input or output)

1. The configuration with CCKyEN = 1 and CCKyDIR = 0 must be avoided (no interest).

When CCKyDIR = 1, as soon as the CCKyEN bit is set to 1, a clock is generated to the corresponding output without any spurs.

Note: The mdf_proc_ck must be enabled (by CKGDEN = 1) before enabling other blocks (such as SITFx or DFLT _x ).

1. 1. Set CKGDEN to 0.
2. 2. Wait for CKGACTIVE = 0. If CKGDEN was previously enabled, this phase can take two periods of mdf_hclk and two periods of mdf_proc_ck.
3. 3. Program PROCDIV[6:0], CKGMOD, CCKDIV[3:0], TRGSRC[3:0] and TRGSENS.
4. 4. Set CKGDEN to 1.
5. 5. Set CCKxDIR to 1 (optional).
6. 6. Set CCKxEN to 1 (optional).

When needed, at any moment, the CCK0EN or CCK1EN value can be changed without disabling the clock generator.

The table below shows the frequency constraints to receive and process properly the samples.

Table 374. Clock constraints with respect to the incoming stream ⁽¹⁾

1. \( F_{MDF\_CCKy} \) represents the frequency of the clock received via MDF_CKIx and MDF_CCKy, or generated via MDF_CCKy. \( F_{SYMB} \) represents the frequency of the received symbol rate for Manchester mode.

The BSMX receives the bitstreams from all serial interfaces (SITFx) and provides the selected input to the digital filters (DFLTx) and to the short-circuit detectors (SCDx). For each filter path, any of the bitstream input can be selected.

As shown in the Figure 328 , each SITFx block provides two bitstreams (bsx_r and bsx_f) to the BSMX.

The application to select the wanted stream via the MDF bitstream matrix control register x (MDF_BSMXxCR) . This selection is intended to be static.

Figure 332. BSMX overview

BSMX programming sequence example

The BSSEL[4:0] bitfield cannot be changed if the corresponding SCDx, OLDx or DFLTx is enabled. The following steps are needed to change the value of BSMX, for filter path x:

1. 1. Set SCDEN of SCDx to 0.
2. 2. Set DFLTEN of DFLTx to 0.
3. 3. Set OLDEN of OLDx to 0.
4. 4. Wait for BSMXACTIVE = 0.
5. 5. Program BSSEL[4:0] of filter path x.
6. 6. Set SCDEN of SCDx to 1 (optional).
7. 7. Set DFLTEN of DFLTx to 1 (optional).
8. 8. Set OLDEN of OLDx block to 1 (optional).

39.4.7 Short-circuit detectors (SCD)

The SCDx detects, with a very fast response time, if an analog signal reached saturated values (out-of-full scale ranges) and remained on this value for a given time.

This behavior can detect short-circuit or open-circuit errors (such as over current or over voltage). An interrupt event or/and a break signal can be generated.

Figure 333. SCD functional view

The SCDx is counting consecutive zeros or consecutive ones received from the serial interface (SITFx). A counter is restarted if there is a change in the data stream received. If this counter reaches a short-circuit threshold value (SCDT[7:0] in the MDF short circuit detector control register x (MDF_SCDxCR) ), then a short-circuit event is invoked. Each BSMX output has its own short-circuit detector. Any BSMX output can be continuously monitored by setting the corresponding SCDEN bit to 1 in MDF_SCDxCR . Each SCD has its own threshold settings (SCDT) and its own status bit (SCDF).

The figure below shows an example where SCDT[7:0] is set to six. The break signal remains high as long as the short circuit condition is present.

No overrun event is generated when the interrupt event is pending while a new short-circuit condition is detected.

Figure 334. SCD timing example

The SCDx event generated by the SCDx block can be assigned to break output signals mdf_break[3:0]. The break signal assignment to a given short-circuit detector event is done by BKSCD[3:0] in MDF_SCDxCR. The break outputs are shared with the over-current function.

Note: SCDs cannot be used to monitor the ADC data interface (ADCITF).

SCD activation sequence example

1. 1. Enable and configure CKGEN to generate the mdf_proc_ck.
2. 2. Set SCDEN to 0.
3. 3. Wait for SCDACTIVE = 0. If SCDEN was previously enabled, this phase can take two periods of mdf_hclk, and two periods of mdf_proc_ck.
4. 4. Program BKSCD[3:0] and SCDT[7:0].
5. 5. Set SCDEN to 1.

Note: BKSCD[3:0] and SCDT[7:0] must not be changed when SCDACTIVE = 1.

39.4.8 Digital filter processing (DFLT)

The digital filter processing includes the following sub-blocks:

• • symbol remap (SBR)
• • source selector
• • clock skipper delay (DLY)
• • CIC decimation filter that can be configured:
  • – in single Sinc ⁴ or Sinc ⁵ order CIC (MCIC)
  • – in two CIC filters:
    • - a main filter (MCIC), high resolution
    • - an auxiliary filter (ACIC), low-latency, for the out-of-limit detector (OLD)
    • - both MCIC and ACIC can be configured as Sinc ¹ , Sinc ² , Sinc ³ or FastSinc
• • gain control (SCALE)
• • signal saturation (SAT)
• • reshape filter (RSFLT)
• • high-pass filter (HPF)
• • integrator (INT)
• • receive RXFIFO

Figure 335 shows the filter-path configuration according to CICMOD[2:0]. Several configuration bits are available to configure the digital filter to the application needs.

Figure 335. DFLT overview

Symbol remap and source selection

The symbol remap (SBR) converts the bitstream selected by the BSMX into data usable by the filter path. More especially:

• • The high levels are converted into a 16-bit signed number + 1.
• • The low levels are converted into a 16-bit signed number - 1.

The signal source of the digital filter can be selected via DATSRC[1:0] between the two following:

• • data coming from the BSMX
• • data coming from one of the ADC interfaces (ADCITF2 or 1)

Programmable micro-delay control (DLY)

The digital filter has a delay line that allows the timing adjustment of each stream with the resolution of the bitstream clock.

This feature is particularly helpful in the case of microphone beam forming applications where delays smaller than the final sampling rate, must be applied to the incoming stream. This feature is helpful when the MDF is synchronized with other ADF or MDF blocks for a beam forming application for example.

The delay is performed by discarding a given number of samples from the selected input stream, before samples enter into the CIC filter. This data discarding is performed by skipping a given number of data strobe, preventing the CIC filter to take into account those data.

When the wanted amount of data strobe has been skipped, the next incoming samples are strobed normally.

Figure 336 shows an example of how to apply dynamically small delay to an incoming stream. For simplification, the CIC filter performs a decimation by height in this example. CIC1 represents the CIC included in the ADF and CIC0 represents a filter from another ADF or MDF instance.

Figure 336. Programmable delay

The CIC of filter 1 (CIC1) receives a command in order to skip three incoming samples. So the input samples named b10, b11 and b12 are not processed by CIC1. As a consequence, the output sample N+1 generated by CIC0 is build from input samples a[23:16] while the sample N+1 of CIC1 is build from input samples b[26:19].

Finally, the non-skipped data stream looks delayed by three bitstream periods.

Note: When the input data strobes are skipped, the decimation counter remains frozen. As a consequence, the samples delivered by the CIC1 are a bit delayed.

Warning: It is not recommended to apply a delay bigger than the programmed decimation ratio (CIC + RSFLT decimation), especially if the MDF is programmed in interleaved acquisition mode. There is a strong risk of data misalignment inside the FIFOs.

The following steps are needed to program the amount of bitstream clock periods to be skipped:

1. 1. Wait for SKPBF equal to 0.
2. 2. Write SKPDLY[6:0] to the wanted number of bitstream clock periods to be skipped. The SKPBF flag goes immediately to 1, indicating that the delay value entered into SKPDLY[6:0] is under process.
   • – If the corresponding DFLT _x is not yet enabled (DFLTEN = 0), then the DLY logic waits for DFLTEN = 1. When the application sets DFLTEN to 1, the DLY logic starts to skip the amount of wanted data strobes.
   • – If the corresponding digital filter is already enabled (DFLTEN = 1), then the DLY logic immediately starts to skip the amount of wanted data strobes.

When the MDF skipped the amount of wanted data strobes, then SKPBF goes back to 0.

1. 3. If the application needs to skip more data strobes, then the operation must be restarted from step 1.

The effect of the delay performed with this mechanism is cumulative as long as the MDF is enabled. In a given filter, if the application performs a D1 delay, followed by a D2 delay, then all other active filters are delayed by D1 + D2.

Data coming from ADCs can also benefit of this feature.

In interleaved acquisition mode, it is up to the application to insure that the delay applied on the different microphones is in line with the depth of the RXFIFO buffers. If the relative delay between each activated filter is less than the decimation ratio, then it costs one FIFO location.

If the interleaved acquisition mode is not used, then the delay value has no impact on the RXFIFO buffering.

Note: If SKPDLY[6:0] is written when SKPBF = 1, the write operation is ignored.

Cascaded-integrator-comb (CIC) filter

The CIC digital filters are an efficient implementation of low-pass filters, often used for decimation and interpolation. The CIC frequency response is equal to a \( \text{Sinc}^N \) function, this is why they are often called Sinc filters.

The \( \text{Sinc}^N \) digital filter embedded into the MDF is configurable according to the application targeted.

• • For audio applications, such as speech capture from digital microphones, the application can select a high-resolution low-pass decimation filter by setting CICMOD to 100 or 101.
• • If the targeted application is motor control or any other sensor capture, then the application can configure the CIC in order to offer a main filter path for acquisition (MCIC) and an auxiliary filter for fast-event generation (ACIC). This auxiliary filter can be used for example, to detect over-current conditions. This mode is selected by setting CICMOD[2:0] = 0xx.

When CICMOD[2:0] = 0xx, the following CIC filters are available:

• • main filter (MCIC)
• • auxiliary CIC filter (ACIC)

Both of them are configurable in FastSinc, \( \text{Sinc}^1 \) to \( \text{Sinc}^3 \) .

When CICMOD[2:0] = 100, the CIC is configured into a single \( \text{Sinc}^4 \) and when CICMOD[2:0] = 101, the CIC is configured into a single \( \text{Sinc}^5 \) filter.

The filters have the following transfer function (impulse response in z domain):

• • \( \text{Sinc}^N \) filter type:
  \[ H(z) = \left( \frac{1 - z^{-D}}{1 - z^{-1}} \right)^N \]
• • FastSinc filter type:
  \[ H(z) = \left( \frac{1 - z^{-D}}{1 - z^{-1}} \right)^2 \cdot (1 + z^{-(2 \cdot D)}) \]

where N can be 1, 2, 3, 4 or 5, and D is the decimation ratio.

D is equal to MCICD+1 or ACICD+1.

Figure 337. CIC3 and CIC5 frequency response with decimation ratio = 32

CIC output data size

The size of samples delivered by the CIC ( \( DS_{CIC} \) ) depends on the following parameters:

• • CIC order (N)
• • CIC decimation ratio (D)
• • data size of the input stream ( \( DS_{IN} \) )

The CIC order and decimation ratio must be programmed in order to insure that the data size does not exceed the 26-bit CIC capability.

The following formula gives the output data size ( \( DS_{CIC} \) ) according to the parameters above.

and the CIC gain is given by this formula:

The decimation ratio can be adjusted from 2 to 512 for the main CIC filter and from 1 to 32 for the auxiliary CIC filter.

The table below gives some data output size in bits for some decimation values, when the data source is a full-scale signal coming from the serial interface or from a 12-bit ADC.

Note: \( DS_{IN} = 1 \) bit for a serial bitstream but can be up to 16 bits when coming from the ADCITF.

Table 375. Data size according to CIC order and CIC decimation values

The LSB part of the data provided by the CIC is not necessarily significant: it depends on the sensor performances and the ability of the CIC to reject the out-of-band noise.

The sample size at CIC output can be adjusted thanks to the SCALE block.

The table below shows the maximum allowed decimation ratio for the CIC filter, depending on the input data size. Bigger decimation ratio causes a wrap-around of the signal at CIC output, for strong input signals.

Note: The MDF cannot detect or prevent a CIC wrap-around.

Scaling (SCALE) and saturation (SAT)

The SCALE block allows the application to adjust the amplitude of the signal provided by the CIC, by steps of 3 dB ( \( \pm 0.5 \) dB).

The signal amplitude can be decreased by up to 8 bits ( \( -48.2 \) dB) and can be increased by up to 12 bits ( \( +72.2 \) dB).

The gain is adjusted by the SCALE[5:0] bitfield in the MDF digital filter configuration register x (MDF_DFLTxCICR) .

SCALE[5:0] can be changed even if the corresponding DLFTx is enabled. During the gain transition, the signal provided by the filter is disturbed.

Due to internal resynchronization, there is a delay of some cycles of mdf_proc_ck clock between the moment where the application writes the new gain, and the moment where the gain is effectively applied to the samples. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back SCALE[5:0] informs the application on the current gain value.

The table below shows the possible gain values.

Table 377. Possible gain values

The SAT blocks avoid having a wrap-around of the binary code when the code exceeds its maximal or minimal value.

The MDF performs saturation operations at the following levels:

• • after the SCALE block (performed by the SAT block). The signal is saturated at 24 bits.
• • inside the RSFLT, to insure a good filter behavior
• • at the output of the HPF, to insure that the output signal does not exceed 24 bits

The SATF bit informs the application that a saturation occurred either after the SCALE, inside the RSFLT or after the HPF. In addition, an interrupt can be generated if SATIE is set to 1. As soon as a saturation is detected, the SATF flag is set to 1. It is up to the application to clear this flag in order to be able to detect a new saturation.

Those bits are in the MDF DFLTx interrupt enable register x (MDF_DFLTxIER) and MDF DFLTx interrupt status register x (MDF_DFLTxISR) .

Gain adjustment policy

To get the best MDF performances, it is important to properly adjust the gain value via SCALE[5:0].

A usual way to adjust the gain is to select the SCALE[5:0] value that gives a final signal amplitude as close as possible to the 24-bit full scale, for the maximum input signal.

A way to select the optimal gain is detailed below:

1. 1. Check that, for the expected input signal, the data size into the CIC filter does not exceed 26 bits. This can be checked using this formula:

where N represents the CIC order, D the decimation ratio and \( \text{SIN}_{\text{pp}} \) the maximum peak-to-peak amplitude of the input signal.

\( \text{SIN}_{\text{pp}} \) can take:

• – a maximum peak-to-peak amplitude of \( 2 (\pm 1) \) , for samples coming from SITF
• – a maximum peak-to-peak amplitude of 4095 (+ 2047, - 2048) for samples coming from a 12-bit ADC

Example: a \( \text{Sinc}^4 \) can be used with a decimation ratio of 96, if the maximum input signal does not exceed \( \pm 0.35 \) . Indeed:

1. 2. Adjust the SCALE value.

To select the most appropriate SCALE value, the user must check if the RSFLT is used or not. If the RSFLT is used, the data size at SCALE output must not exceed 22 bits, otherwise the data size can be up to 24 bits.

The SCALE value in dB is selected using this formula:

where NB is equal to 22 if RSFLT is enabled, or 24 if RSFLT is bypassed. \( \text{SCALE}_{\text{dB}} \) represents the gain value selected by SCALE[5:0].

Example: for a \( \text{Sinc}^4 \) with a decimation ratio of 96 and a \( \text{SIN}_{\text{pp}} \) of 0.7:

• – If the RSFLT is bypassed:

\( \text{SCALE}_{\text{dB}} \) value must be lower than - 11 dB. The closest lower value is - 12dB (SCALE[5:0] = 0x2C).

• – If the RSFLT is enabled:

\( \text{SCALE}_{\text{dB}} \) value must be lower than - 23 dB, the closest lower value is - 24.1 dB (SCALE[5:0] = 0x28).

If SCALE[5:0] is set to a higher value, then a saturation may occur. An event flag informs the user if a saturation occurred.

The table below proposes gain values for different filter configurations, when the data comes from the SITFx, according to the CIC order, and the CIC decimation ratio. This table is not exhaustive, and considers a full-scale input signal (see Section 39.7.5 for details).

Table 378. Recommended maximum gain values versus CIC decimation ratios

Reshaping filter (RSFLT)

In addition to the CIC, the MDF offers a reshaping IIR filter mainly dedicated to the audio application but also usable in other applications.

When the RSFLT is used, the sample size at its input must not exceed 22 bits.

The samples at the RSFLT output can be decimated by four or not according to the RSFLTD bit in the MDF reshape filter configuration register x (MDF_DFLTxRSFR) .

The RSFLT can be bypassed by setting RSFBYP to 1 in MDF_DFLTxRSFR .

The table below shows which sampling rate must be provided to the RSFLT in order to process the most common audio streams.

The RSFLT cutoff frequency ( \( F_C \) ) depends on the sample rates at its input ( \( F_{RS} \) ), and is given by the following formula:

Table 379. Most common microphone settings

The figure below shows the frequency response of the reshape filter.

Figure 338. Reshape filter frequency response normalized ( \( F_{RS} / 2 = 1 \) )

The RSFLT gain is about 9.3 dB, so the output data size is a little bit lower than 24 bits for a 22-bit wide input signal.

The RSFLT takes 24 clock cycles of mdf_proc_ck clock to process one sample at \( F_{RS} \) . When the RSFLT is enabled, the application must insure that the mdf_proc_ck is at least 24 times faster \( F_{RS} \) .

The RSFLT generates an event (rfov_evt) and sets the RFOVRF flag, if the RSFLT receives a new sample while the previous one is still under processing.

When RFOVRF is set, the samples provided by the RSFLT are invalid. The application must then stop the data acquisition and provide a faster mdf_proc_ck clock to the RSFLT.

High-pass filter (HPF)

The high-pass filter suppresses the low-frequency content from the final output data stream in case of continuous conversion mode. The high-pass filter can be enabled or disabled via HPFBYP in the MDF reshape filter configuration register x (MDF_DFLTxRSFR) .

The HPF is useful when there is parasitic low-frequency noise (or DC signal) in the input data source and it must be removed from the final data.

The HPF is a first order IIR filter and the cut-off frequency can be selected via HPFC[1:0] in the MDF reshape filter configuration register x (MDF_DFLTxRSFR) , among the following values:

• • \( 0.000625 \times F_{PCM} \)
• • \( 0.00125 \times F_{PCM} \)
• • \( 0.00250 \times F_{PCM} \)
• • \( 0.00950 \times F_{PCM} \)

Table 380. HPF 3 dB cut-off frequencies examples

The HPF output is saturated at 24 bits. The SATF flag is set if a sample is saturated.

Offset error compensation (OEC)

Each digital filter has its own OEC. The offset correction is performed by subtracting to the signal provided by the CIC, the OFFSET[25:0] in the MDF offset error compensation control register x (MDF_OECxCR) .

Due to the internal resynchronization, there is a delay of some cycles of mdf_proc_ck clock between the moment where the application writes the new offset, and the moment where the new offset value is effectively applied to the samples. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back OFFSET[25:0] informs the application on the current offset value.

Integrator (INT)

The INT performs additional decimation and a resolution increase of data coming from the digital filter. The INT simply performs the sum of data from a digital filter for a given number of data samples from a filter.

The INT is enabled by setting INTVAL[6:0] to a value different from 0.

The amount of integrated values can be defined by INTVAL[6:0] in the range of 2 to 128.

In order to control the data width at the integrator output, the resulting data can be divided by 1, 4, 32 or 128. This feature is controlled by INTDIV[1:0].

39.4.9 Out-of-limit detector (OLD)

The OLD triggers an event when a signal reaches or crosses given maximum and minimum threshold values. The generated event can drive an interrupt or break signals (mdf_break[3:0]) when conditions are met.

The OLD can be used only if the CIC filter is configured in motor and sensing mode (CICMOD[2:0] = 0xx).

The OLD takes the input signal selected by the main filter, process it using a Sinc ^N or FastSinc filter (ACIC), and compares the resulting signal to programmed thresholds.

The OLD is enabled via the OLDEN bit in MDF_OLD0CR. Once enabled, the input data are continuously monitored. There is no need to have the DFLT _x enabled for using the OLD function.

The MDF offers a high- and low-threshold register that are compared with given data values.

The application can generate an event if the signal is inside or outside the boundary defined by those two thresholds. This behavior is controlled via THINB in the MDF_OLD0CR.

If the application only wants to generate an event when the input signal is higher than OLDTHH, then THINB and OLDTHL must both be cleared to 0.

If the application only wants to generate an event when the input signal is lower than OLDTHH, then THINB must be set to 1 and OLDTHL must be cleared to 0.

Note: It is not recommended to set a OLDTHL to a value bigger than OLDTHH.

The response time of the OLD depends on several parameters, the most important are listed hereafter:

• • sampling rate frequency used by the external sensor
• • ACIC decimation ratio
• • ACIC order

The OLD can be used for over-current detection but also as current limiter if the PWM signal is generated by a timer receiving a old_brk signal. Generally, to get a fast response time for over-current detection, it is recommended to use the ACIC with lowest order as possible and the minimum decimation ratio. FastSinc is also a good choice for over-current detection.

The application must perform a trade-off between the filter resolution and the response time.

Figure 339. Out-of-limit detector thresholds

Status flags are available in order to inform the application that an OLD event is detected. Latched events are cleared by writing 1 into the OLDF bit.

As shown in Figure 339 , when THINB = 0, the interrupt signal remains active as long as the signal is outside the gray area. At position A, the application clears the interrupt, but the interrupt is re-asserted because the signal is still outside the gray area. When the application clears OLDF, THHF and THLF are cleared as well.

An OLD event can be assigned to one or several break output signals (mdf_break[3:0]). The break signal assignment to a given OLD event is done by BKOLD[3:0] in the MDF out-of limit detector control register x (MDF_OLDFxCR) .

Note: The generation of break signals is independent from the interrupts generation.

OLD activation sequence example

1. 1. Enable and configure CKGEN.
2. 2. Set OLDEN to 0.

1. 3. Wait for OLDACTIVE = 0. If OLDEN was previously enabled, this phase can take two periods of mdf_hclk and two periods of mdf_proc_ck.
2. 4. Program BKOLD[3:0], ACICN[1:0], ACICD[4:0], THINB, OLDTHL[25:0] and OLDTHH[25:0].
3. 5. Set OLDEN to 1.

39.4.10 Digital filter acquisition modes

The MDF offers the following modes to perform a data capture:

• • asynchronous continuous acquisition mode
• • asynchronous single-shot acquisition mode
• • synchronous continuous acquisition mode
• • synchronous single-shot acquisition mode
• • window continuous acquisition mode
• • synchronous snapshot acquisition mode

For each filter, one of these modes can be selected independently.

Note: To perform a data capture, the filters, the interfaces providing the data (SITFx or ADCITF) and the CKGEN must be enabled. If needed, MDF_CCK0 or MDF_CCK1 must be enabled as well.

The filter can be stopped immediately when DFLTEN is set to 0. This resets the filters and flushes the RXFIFO of the corresponding filter path. The DFLTACTIVE flag also goes back to 0 when the RXFIFO and the filters are reset.

The figure below shows a simplified view of the trigger logic available for each filter and for the clock generator.

Figure 340. Trigger logic for DFLT and CKGEN

A block common to all TRIG blocks performs the rising and falling edges detection and the resynchronization of the input triggers to the mdf_ker_ck clock domain. This implementation allows the application to use triggers with pulse width smaller than the mdf_ker_ck period.

In synchronous modes, the TRIG block offers the possibility to select one of the following trigger sources:

• • mdf_trgi[13:0] signals (refer to Table 370 for the trigger connections)
• • TRGO bit in MDF_GCR
• • OLD event of each filter path

The edge sensitivity can also be selected, except for TRGO and OLD events.

Asynchronous continuous acquisition mode

This mode allows the application to start a continuous acquisition on one or several filters by simply writing their DFLTEN bits to 1.

The Asynchronous continuous acquisition mode is selected when ACQMOD[2:0] = 0.

The sequence below shows the most important programming steps (assuming that DFLTEN bits of the filters are set to 0):

1. 1. Configure and enable the clock generator (CKGEN) so that the mdf_proc_ck frequency is compatible with the targeted application (see examples in Table 384 ).
2. 2. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
3. 3. Program the filter configuration and set the ACQMOD[2:0] to 0.
4. 4. Set to 1 the SITFEN bit of the requested data interfaces.
5. 5. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
6. 6. When DFLTEN is set to 1 for the filters to enable, the acquisition sequence starts immediately.

The figure below shows a simplified example of the samples generated by the DFLT _x .

Figure 341. Asynchronous continuous mode (ACQMOD[2:0] = 0)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Asynchronous single-shot acquisition mode

This mode allows the application to start the acquisition of one sample on one or several filters by simply writing their DFLTEN bits to 1.

The Asynchronous single-shot acquisition mode is selected when ACQMOD[2:0] = 001.

The sequence below shows the most important programming steps (assuming that DFLTEN bits of the filters are cleared to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the mdf_proc_ck frequency is compatible with the targeted application (see examples in Table 380 ).
2. 2. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
3. 3. Program the filter configuration and set the ACQMOD[2:0] to 001.
4. 4. Set to 1 the SITFEN bit of the requested data interfaces.

1. 5. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
2. 6. When DFLTEN is set to 1 for the filters to enable, each selected filter provides one data to the RXFIFO and stops the acquisition.

To trigger a new acquisition, for each filter, the application must:

1. 1. Check that the previous acquisition is completed, by waiting that DFLTRUN = 0.
2. 2. Set again DFLTEN to 1.

This sequence can be repeated every time a new data must be converted.

As shown in the Figure 342 , every time DFLTEN is set to 1, an acquisition sequence is triggered. The first samples provided by the filter can be discarded if needed. At the end of each conversion, the decimation counters and filter taps are reset, and the filter is ready to start a new conversion.

If the DFLTEN is set to 0 while an acquisition is ongoing, the ongoing conversion is stopped (in the example, S3 is lost). This situation can be avoided with the following steps:

1. 1. Wait for DFLTRUN = 0.
2. 2. Read the sample from the RXFIFO.
3. 3. Set DFLTEN to 0.

Figure 342. Asynchronous single-shot mode (ACQMOD[2:0] = 001)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Synchronous continuous acquisition mode

This mode allows the application to start a continuous acquisition on one or several filters by using the following trigger sources:

• • one of the mdf_trg[13:0] signals
• • OLD event of the corresponding filter
• • TRGO bit

The Synchronous continuous acquisition mode is selected when ACQMOD[2:0] = 010.

The sequence below shows the most important programming steps (assuming that DFLTEN bits of the filters are set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of mdf_proc_ck clock is compatible with the targeted application (see examples in Table 380 ).
2. 2. Enable the CKGEN (CKGDEN = 1) and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
3. 3. Program the filter configuration, and set the ACQMOD[2:0] to 010.
4. 4. Set to 1 the SITFEN bit of the requested data interfaces.
5. 5. Select the proper trigger source and sensitivity for each filter.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence terminated properly.
7. 7. Set DFLTEN to 1 for the filters to enable.
8. 8. When the trigger condition is met, the filters start the acquisition.

The TRGSENS bit allows the selection of the trigger edge (rising or falling). The trigger is ignored if an acquisition is ongoing or if DFLTEN is set to 0.

The figure below shows a simplified example where the trigger logic is sensitive to a rising edge trigger (TRGSENS = 0). The first rising edge of the trigger signal is ignored because DFLTEN = 0. The next rising edge is taken into account and starts the acquisition. All other rising edges are ignored. The trigger logic is re-initialized when DFLTRUN goes back to 0.

Figure 343. Synchronous continuous mode (ACQMOD[2:0] = 010)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Synchronous single-shot acquisition mode

This mode allows the application to start a single acquisition on one or several filters by using the following trigger sources:

• • one of the mdf_trg[13:0] signals
• • OLD event of the corresponding filter
• • TRGO bit

The Synchronous single-shot acquisition mode is selected when ACQMOD[2:0] = 011.

The sequence below shows the most important programming steps (assuming that DFLTEN bits of the filters are set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of mdf_proc_ck clock is compatible with the targeted application (see examples in Table 380 ).
2. 2. Enable the CKGEN and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
3. 3. Program the wanted filter configuration and set the ACQMOD[2:0] to 011.
4. 4. Set to 1 the SITFEN bit of the requested data interfaces.
5. 5. Select the proper trigger source and sensitivity for each filter.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence has been properly terminated.
7. 7. Set DFLTEN to 1 for the filters to enable.
8. 8. Then when the trigger condition is met, the filters start the acquisition and provide one data to the RXFIFO, then the filters are ready to accept a new trigger.

TRGSENS allows the selection of the trigger edge (rising or falling). The trigger is ignored if an acquisition is ongoing or if DFLTEN is set to 0.

The figure below shows a simplified example where the trigger logic is sensitive to a rising edge trigger (TRGSENS = 0). Every time a trigger rising edge is detected with DFLTEN = 1, an acquisition sequence is triggered. The first samples provided by the filter can be discarded if needed. At the end of each conversion, the decimation counters and filter taps are reset. DFLTRUN is set to 0 and the filter is ready to start a new conversion.

Figure 344. Synchronous single-shot mode (ACQMOD[2:0] = 011)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Figure 344 shows a case where DFLTEN is cleared to 0 while an acquisition is ongoing: thus the sample S2 is lost. This situation can be avoided with the following steps:

1. 1. Wait for DFLTRUN = 0.
2. 2. Read the sample from the RXFIFO.
3. 3. Clear DFLTEN to 0.

Note: The ongoing DMA transfer is properly terminated.

Window continuous acquisition mode

This mode allows the application to start or stop a continuous acquisition on one or several filters controlled by consecutive edges of one of the following trigger sources:

• • one of the mdf_trg[13:0] signals
• • TRGO bit

The window continuous acquisition mode is selected when ACQMOD[2:0] = 100.

The sequence below shows the most important programming steps (assuming that DFLTEN bits of the filters are set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of mdf_proc_ck clock is compatible with the targeted application (see examples in Table 380 ).
2. 2. Enable the CKGEN and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
3. 3. Program the wanted filter settings and set the ACQMOD[2:0] to 100.
4. 4. Set to 1 the SITFEN bit of the requested data interfaces.
5. 5. Select the proper trigger source and sensitivity for each filter.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence has been properly terminated.
7. 7. Set DFLTEN to 1 for the filters to enable.
8. 8. If TRGSENS = 0, the acquisition starts on trigger rising edge and stops on trigger falling edge. If TRGSENS = 1, the acquisition starts on trigger falling edge and stops on trigger rising edge.

Note: The acquisition may restart if the trigger condition becomes again active.

Figure 345 shows a simplified example of window continuous acquisition mode, with TRGSENS = 1. Once DFLTEN is set to 1, the MDF waits for a falling edge on the selected trigger input. When the trigger condition is met, DFLTRUN goes to 1 and the acquisition starts. The acquisition stops if the MDF detects a rising edge on the selected trigger input. If DFLTEN is still set to 1, the MDF waits again for a falling edge on the selected trigger input.

Figure 345. Window continuous mode (ACQMOD[2:0] = 100)

Note: The acquisition can be stopped by setting DFLTEN back to 0. This resets the filter and flushes the RXFIFO, so the samples located into the RXFIFO are lost. The ongoing DMA

transfer is properly terminated. DFLTACTIVE goes back to 0 when the filter chain is reset and the RXFIFO flushed.

Synchronous snapshot acquisition mode

In the acquisition modes described on previous sections, the application must wait for filters settlings time or the end of conversion before getting a new valid sample. For applications very critical in latency, the last valid sample can be get immediately, with an information on the age of this sample by using the snapshot acquisition mode.

In snapshot mode, the DFLT \( x \) is continuously acquiring the samples, but the processed samples are not stored into the RXFIFO. When a trigger occurs, the last valid sample, the current decimation value of MCIC and the sample counter of the INT are stored in MDF_SNPS0DR.

The possible trigger sources are the following:

• • one of the mdf_trg[13:0] signals
• • OLD event of the corresponding filter
• • TRGO bit

The Synchronous snapshot acquisition mode is selected when ACQMOD[2:0] = 101.

The sequence below shows the most important programming steps (assuming that DFLTEN bits of the filters are set to 0):

1. 1. Configure and enable the clock generator (CKGEN), so that the frequency of mdf_proc_ck clock is compatible with the targeted application (see examples in Table 380 ).
2. 2. Enable the CKGEN and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
3. 3. Program the wanted filter settings and set the ACQMOD[2:0] to 101. FTH is usually cleared to 0 to receive an interrupt as soon as the RXFIFO is not empty.
4. 4. Set the SITFEN bit of the requested data interfaces to 1.
5. 5. Select the proper trigger source and sensitivity for each filter.
6. 6. Before setting DFLTEN to 1, wait for DFLTACTIVE = 0: it insures that the previous filter deactivation sequence has been properly terminated,
7. 7. Set DFLTEN to 1 for the filters to enable.

When the trigger condition is met,

1. 1. The MDF stores the last valid data provided by the corresponding filter, the value of the MCIC decimation counter, and the counter value of INT if selected by SNPSFMT into a shadow register.
2. 2. The snps_evt is activated, indicating that a data is ready. If SSDRIE is set to 1, the MDF requests the AHB clock.
3. 3. When the AHB clock is available the shadow register is stored in MDF snapshot data register x (MDF_SNPSxDR) and an interrupt is generated.
4. 4. In the interrupt sub-routine, the application must do the following:
   1. a) Read the data located in MDF_SNPS \( x \) DR.
   2. b) Clear the SSDRF flag by writing it to 1.

As shown in the Figure 346 , in snapshot mode, when the trigger event occurs, it is resynchronized with the processing clock (mdf_proc_ck), the decimation counter of the MCIC (MCIC_CNTR), the integrator counter (INT_CNTR) and the last valid sample ( \( S_{N+2} \) ), are stored into a shadow register, and the snps_evt event is generated. When the AHB

clock is available, an interrupt is generated and the shadow register is copied in MDF_SNPSxDR . The application can read immediately the sample and the timing information.

The SSOVRF overrun flag is also available, allowing the application to check if an overrun condition occurs. A snapshot overrun condition is detected when the SSDRF flag is set to 1 while a new trigger event occurs.

In that case, the new trigger event is not taken into account. The application must clear the SSOVRF flag.

Figure 346. Snapshot mode example

Note: When an activated filter did not receive a data strobe, the filter is frozen. If the interface providing the stream is not enabled (SITF or ADCITF), the filter is frozen. Once a DFLT x is activated, CIC, HPF, IIR and INT are reinitialized. For each filter a status bit indicates if the filter is currently running or not.

Starting several filters synchronously

To start the acquisition of several filters synchronously, the following sequence must be performed (assuming that DFLTEN is set to 0):

1. 1. Enable the CKGEN and, if needed, enable the MDF_CCK0 and MDF_CCK1 clocks.
2. 2. Set the SITFEN bit of the requested data interfaces to 1.
3. 3. For each filter, set the acquisition mode to synchronous ( ACQMOD[2:0] = 01x ).
4. 4. For each filter, set TRGSRC[3:0] to 0 ( TRGO is selected).
5. 5. For each filter, set TRGSENS to 0 (rising edge).
6. 6. For each filter, set DFLTEN to 1.
7. 7. Read TRGO bit until it is read to 0.
8. 8. Set TRGO to 1. Then the acquisition sequence for all selected filters starts immediately.

To trigger a new acquisition (in case of single-shot), the application must do the following:

1. 1. Check that the previous acquisition is completed, by waiting DFLTRUN = 0.
2. 2. Read TRGO until it is read to 0.
3. 3. Set again TRGO to 1.

Discarded samples

The MDF offers the possibility to program the amount of samples to be discarded after each restart:

• • to avoid capturing samples affected by the impulse response of the filter
• • to delay the acquisition of filters by a specific amount of samples

The discard function is controlled via NBDIS[7:0] as follows:

• • When NBDIS[7:0] = 0, the discard function is disabled.
• • When NBDIS[7:0] ≠ 0, the discard function is activated in one of the following condition:
  • – when the DFLTEN bit goes to 1
  • – every time an acquisition is started in (A)synchronous single-shot modes

Refer to Figure 341 to Figure 345 , Figure 348 and Figure 349 .

In the example shown in the figure below, the discard function is used to drop the first five samples provided by the digital filter (S1 to S5). The first sample transferred to the RXFIFO (or INT block if enabled) is S6.

Figure 347. Discard function example

Warning: All filters working in interleaved DMA mode must have the same NBDIS[7:0] value.

Data interface activation

The data interfaces are enabled by setting the corresponding SITFEN or ADCITFEN bit to 1. Once the digital filter is enabled, it receives the serial data from the external \( \Sigma\Delta \) modulator or parallel internal data sources (ADC).

39.4.11 Start-up sequence examples

Figure 348 details an acquisition sequence start of a digital filter triggered by DFLTEN (ACQMOD[2:0] = 0), with NBDIS[7:0] = 3 (three samples to discard before acquisition).

The DFLT _x is configured for audio application: MCIC, RSFLT and HPF activated. The data interface (SITF _x or ADCITF) is assumed to be already activated.

Note: NBDIS[7:0] is set on purpose to a low value to simplify the drawing.

Figure 348. Start sequence with DFLTEN, in continuous mode, audio configuration

The DFLTEN bit is re-sampled into the MDF processing clock domain. When DFLTEN is detected high, the filter chain is enabled and the decimation counter of the MCIC filter is incremented at the rate of the bitstream clock.

When the MCIC decimation counter reaches its programmed value N, a sample is available for the RSFLT.

The RSFLT processes all the samples provided by the MCIC and delivers a sample to the HPF every time it processes four samples (decimation by 4). The RSFLT needs up to 24 cycles of mdf_proc_ck clock before delivering a sample (P1).

The HPF processes all the samples provided by the RSFLT, but the NBDIS function prevents the data writing in the RXFIFO as long as NBDIS_CNTR does not reach 0. This counter is decremented every time the HPF delivers a sample.

When NBDIS_CNTR reaches 0, the samples provided by the HPF are stored into the RXFIFO.

The example shown in Figure 349 is based in a motor-control filter configuration:

• • MCIC and INT are enabled.
• • SFLT and HPF are disabled.
• • ACQMOD[2:0] is set to 1 and uses a mdf_trgiy input as trigger.
• • NBDIS[7:0] is set to 3.
• • INTVAL[6:0] is set to 2.

The mdf_trgiy input signal is re-sampled into the MDF processing clock domain to avoid any metastability issues. When the trigger condition is met (rising edge), the decimation counter of the MCIC filter is incremented at the rate of the bitstream clock.

When the MCIC decimation counter reaches its programmed value N, a sample is available. The NBDIS function prevents the samples writing in the INT as long as NBDIS_CNTR does not reach 0. This counter is decremented every time the MCIC delivers a sample.

When NBDIS_CNTR reaches 0, the new samples are provided to the INT, that performs the integration of three consecutive samples and stores them into the RXFIFO.

Figure 349. Start sequence with trigger input, in continuous mode, motor configuration

39.4.12 Break interface

The break interface merges the break events coming from the OLDx and SDCx blocks into four break signals connected to various peripherals of the product (see Table 370 for details).

As shown in Figure 350 , several blocks can share the same break line. A same block can also drive several break lines. The break interface is controlled via MDF_OLDxCR and MDF_SCDxCR.

Figure 350. Break interface simplified view

39.4.13 Data transfer to memory

Data format

The samples processed by DFLTx are stored into a RXFIFO. The application can read the samples stored into the FIFOs via the MDF digital filter data register x (MDF_DFLTxDR) . The samples inside this register are signed and left aligned. The bit 31 always represents the sign.

The MDF provides 24-bit left-aligned data. Performing a 16-bit access to MDF_DFLTxDR allows the application to get the 16 most significant bits. Performing a 32-bit access to MDF_DFLTxDR allows the application to get a 24-bit data size.

Figure 351. MDF_DFLTxDR data format

Data resynchronization

The samples stored into the RXFIFOs can be transferred into the memory by using either DMA requests or interrupt signaling.

Note: The RXFIFOs are located into the mdf_ker_ck clock domain, while MDF_DFLTxDR are located into the mdf_hclk (AHB) clock domain.

When the AHB clock is available, if MDF_DFLTxDR is empty and if a sample is available into the RXFIFO, this sample is transferred into MDF_DFLTxDR.

The sample transfer from the RXFIFO to MDF_DFLT \( x \) DR takes two periods of the AHB clock (mdf_hclk) and two periods of the mdf_ker_ck clock. The MDF inserts automatically wait-states if the application performs a read operation of MDF_DFLT \( x \) DR while the transfer of the new sample from the RXFIFO to MDF_DFLT \( x \) DR is not yet completed.

Figure 352. Data resynchronization

The MDF can also combine two transfer types: the independent-transfer and the interleaved-transfer modes.

Independent-transfer mode

In this mode, each RXFIFO has its own DMA channel and its own FTHF flag event.

Both single and burst DMA transfers are supported in this mode, but the application must care about the following points:

• • The RXFIFO must contain at least the same amount of samples than the burst size.
• • The burst mode efficiency may be reduced due to the data resynchronization explained in the previous section.

In addition, the application can select the RXFIFO threshold (FTH bit) to trigger the data transfer: a data transfer can be triggered as soon as the RXFIFO is not empty, or when the RXFIFO is half-full (containing \( \text{depth} / 2 \) samples).

For the DMA transfer, as soon as one of the RXFIFO reaches the threshold level, the corresponding DMA request is asserted in order to ask for data transfer. Successive DMA requests are performed as long as the corresponding RXFIFO is not empty.

The DMA mode of the RXFIFO \( x \) is enabled via the corresponding DMAEN bit in the MDF digital filter control register \( x \) (MDF_DFLT \( x \) CR) .

For the interrupt signaling, the following cases must be considered:

• • If FTH = 0, as soon as a data is available in MDF_DFLT \( x \) DR, the corresponding FTHF is set, allowing the generation of an interrupt. FTHF is released as soon as MDF_DFLT \( x \) DR is read.
• • If FTH = 1, as soon as one of the RXFIFO reaches the threshold level and a data is available into MDF_DFLT \( x \) DR, the corresponding FTHF is set, allowing the generation of an interrupt. The FTHF flag is released as soon as one data is read. FTHF is set again if the threshold condition is met again. In this mode, every time an interrupt occurs, the application is supposed to read \( \text{FIFO\_SIZE} / 2 \) data.

The independent-transfer mode must be used when the sample rates provided by each filter paths are not perfectly synchronous, or when the streams are independent. This situation may occur for example:

• • when SITF is in SLAVE mode and each external sensor provides its own sampling clock

• • when the decimation ratios of the DFLT _x are not the same
• • when all the streams are not starting at the same time

Interleaved-transfer mode

This mode optimizes the DMA request resources by sharing a single DMA request with several RXFIFOs.

Only single DMA transfers are supported in this mode.

In interleaved-transfer mode, FTH cannot be used and only the FTHF of RXFIFO0 is available for the interrupt signaling.

For the DMA transfer, when all the RXFIFOs working in interleaved-transfer mode are not empty, some DMA requests are generated in order to read sequentially one sample of each RXFIFOs, via MDF_DFLT0DR.

For the RXFIFOs working in interleaved-transfer mode, the DMA channel is enabled by setting to 1 DMAEN in MDF_DFLT0DR and by defining the amount of RXFIFOs working in interleaved mode via ILVNB[3:0]. DMAEN for the other RXFIFOs working in interleaved-transfer mode (RXFIFO 1 to ILVNB[3:0]) are not taken into account.

Figure 353 shows four RXFIFOs working in interleaved-transfer mode. Each RXFIFO has a delay due to the programming of the DLY block.

When all the RXFIFOs have at least one sample available (in this example the last FIFO receiving a sample is RXFIFO1), the MDF requests the data transfer to the memory (see 1 in Figure 353 ). In this figure, the DMA is assumed to be used for the data transfer to memory.

The acquisition can be simply stopped by setting DFLTEN to 0 for one of the filter configured in interleaved-transfer mode. In the example, when a DFLTEN is set to 0 (see 2 in Figure 353 ), the transfer to memory is immediately stopped. Samples M2S(N), M3S(N) and M4S(N) may be lost.

Figure 353. Data transfer in interleaved-transfer mode

In interrupt mode, when all the RXFIFOs working in interleaved-transfer mode have a data ready, the FTHF flag of RXFIFO0 is asserted to allow the interrupt generation. The application is then supposed to read sequentially one sample of each RXFIFOs, via MDF_DFLT0DR. The FTHF event is released when the first data is read.

For the RXFIFOs working in interleaved-transfer mode, the interrupt mode is enabled by setting FTHIE to 1 in MDF_DFLT0DR and by defining the amount of RXFIFOs working in interleaved-transfer mode via ILVNB[3:0]. FTHIE of the other RXFIFOs working in interleaved-transfer mode (RXFIFO1 to ILVNB[3:0]) are not taken into account.

The interleaved-transfer mode can only be applied starting at RXFIFO0 up to RXFIFO \( k \) . The number of RXFIFOs working in interleaved-transfer mode are defined by ILVNB[3:0].

When ILVNB[3:0] = 0, all RXFIFOs work in independent-transfer mode.

The interleaved-transfer mode can be used only for digital filters delivering samples perfectly synchronous each other. This is typically the case of sound capture with an array of digital microphones sharing the same bitstream clock.

Caution: To make the MDF working properly in interleaved-transfer mode, the following rules must be respected:

• • All filters working in interleaved-transfer mode must be all synchronized together, meaning that all filters must select the same ACQMOD[2:0] (must be equal to 010 or 011), the same trigger source and the same trigger sensitivity.
• • All filters working in interleaved-transfer mode must have the same configuration.
• • All sensors providing the data for the filters working in interleaved-transfer mode must use the same bitstream clock frequency.
• • The maximum delay difference applied with SPKDLY[6:0] for the filters working in interleaved-transfer mode must remain strictly lower than the RXFIFO depth. Normally this delay does not need to exceed one \( T_{PCM} \) period.

Note: Both independent- and interleaved-transfer modes can work in parallel: for example, the first RXFIFOs (RXFIFO0 to RXFIFO \( k \) ) may work in interleaved-transfer mode when the others (RXFIFO( \( k+1 \) ) to RXFIFO( \( N \) )) works in independent-transfer mode.

If the AHB clock is not present when a data transfer must be performed, the MDF first requests the AHB clock (refer to Section 39.4.5: Clock generator (CKGEN) for details).

The figure below shows the data path for a configuration in independent-transfer mode (left-hand figure) and a configuration mixing both independent- and interleaved-transfer modes (right-hand figure).

Figure 354. Data path for interleaved- and independent-transfer modes

In the right-hand figure, the DFLT0 and DFLT1 filters are configured in interleaved-transfer mode. For those filters, FTH is no longer taken into account by the hardware. The samples provided by DFLT0 and DFLT1 are read from MDF_DFLT0DR. When both RXFIFOs are no longer empty, the MDF generates two DMA requests to read the sample from DFLT0 and the sample from DFLT1. If both RXFIFOs are not empty again, the same sequence is triggered.

Note: When one of the filter working in interleaved-transfer mode is disabled, the data transfer to memory of all filters in interleaved-transfer mode is stopped immediately as well.

RXFIFO overrun

A RXFIFO overrun condition is detected when the RXFIFO is full and a new sample from the DFLTx must be written.

In this case, DOVRF is set and the new sample is dropped. When the RXFIFO has at least one location available, the new incoming sample is written into the RXFIFO.

Figure 355 shows an example based on a RXFIFO depth of four words and FTH set to 1, so that FTHF goes to 1 when the RXFIFO is half-full.

The S7 sample is lost due to an overrun: the RXFIFO is full while S7 must be written into the RXFIFO. The S7 write operation is not performed. DOVRF is set to 1 at the moment where the write operation was expected. The overflow event remains to 1 as long as it is not cleared by the application.

In this example, DOVRIE is set to 1 to have an interrupt if an overrun condition is detected.

After the S7 sample, the application manages to read data from the RXFIFO and the MDF can write the S8 sample and consecutive. Later, the application clears DOVR, allowing the detection of a new overrun situation.

In the mdf_hclk line, the gray boxes indicate that the MDF requested the AHB clock. The figure below shows the AHB clock available only when the MDF requests it. In real applications, the AHB clock may also be present if the MDF does not request it.

Figure 355. Example of overflow and transfer to memory

Note: If the MDF works in interleaved-transfer mode, the application must check the overrun status of all RXFIFOs that works in interleaved-transfer mode.

39.4.14 Autonomous mode

The MDF can work even if the AHB bus clock is not available (Stop modes). The MDF uses the AHB clock only for the register interface. All the processing part is clocked with the kernel clock.

In Stop mode, the MDF receives a kernel clock if the selected clock source is an oscillator available in Stop mode

In Stop mode, the MDF receives the AHB clock if the following conditions are met:

• • The MDF autonomous mode is enabled in the RCC.
• • The MDF requests the AHB clock, in the following situations:
  • – when the MDF must transfer data into the memory via the DMA
    The data are directly transferred to the SRAM thanks to the DMA while the product remains in Stop mode. The AHB clock request is maintained until the DMA transfer is completed.
  • – when the MDF must generate an interrupt
    An interrupt generally wakes up the device from Stop mode, as an action from the application is needed. Once the AHB clock is available, the interrupt is generated. The AHB clock request is maintained as long as an enabled interrupt

flag is active. More precisely, when an interrupt must be generated, the MDF requests the AHB clock.

39.4.15 Register protection

The MDF embeds some hardware protection to prevent invalid situations. The table below shows the list of write-protected and unprotected fields.

Table 381. Register protection summary

Table 381. Register protection summary (continued)

All the MDF processing is performed in the mdf_proc_ck clock domain. For that reason, enabling or disabling a MDF sub-block may take some time due to the resynchronization between the AHB clock domain and the mdf_proc_ck clock domain. XXXACTIVE flags are available to allow the application to check that the synchronization between the two clock domains is completed.

To change a write-protected bitfield, the application must follow this sequence:

1. 1. Set the enable bit of the sub-block to 0.
2. 2. Wait for corresponding flag XXXACTIVE = 0.
3. 3. Modify the wanted fields.
4. 4. Set the enable bit of the sub-block to 1.

Refer to the description of each sub-block for more details.

39.5 MDF low-power modes

Table 382. Effect of low-power modes on MDF

1. 1. Refer to Section 39.3: MDF implementation for details about Stop modes supported by the MDF.

39.6 MDF interrupts

To increase the CPU performance, the MDF offers the following interrupt lines per digital filter:

• • receive interrupt MDF_FLT _x _RX (mdf_fltx_rx_it)
• • event interrupt MDF_FLT _x _EVT (mdf_fltx_evt_it)
• • a combination of both interrupts MDF_FLT _x (mdf_fltx_it)

Note: Interrupts are not always connected to the device (see Section 39.3: MDF implementation for more details).
The status flags are available even if the corresponding interrupt enable flag is not enabled.

The interrupt interface is controlled via the MDF_DFLT _x interrupt enable register x (MDF_DFLT _x IER) and the MDF_DFLT _x interrupt status register x (MDF_DFLT _x ISR) .

Figure 356. MDF interrupt interface

(1) Not always implemented. Refer to the vector table of the product for details.

MSv63600V2

The table below shows which interrupt line is affected by which event, and how to clear and activate each interrupt/event.

Table 383. MDF interrupt requests

1. Refer to Section 39.3: MDF implementation for details.

2. MDF_FLTx vector corresponds to the assertion of mdf_fltx_it signal

3. MDF_FLTx_RX vector corresponds to the assertion of mdf_fltx_rx signal.

4. MDF_FLTx_EVT vector corresponds to the assertion of mdf_fltx_evt signal.

39.7 MDF application informations

39.7.1 MDF configuration examples for audio capture

Table 384 gives some examples of the MDF settings for the digital microphones, focusing on 16 and 48 kHz output data rate. In these examples, the following is expected:

• • The INT block is bypassed (INTVAL = 0).
• • The offset error compensation is disabled (OFFSET = 0).

Configurations #1 and #2 are for very low-power use-cases and have a reduced signal-to-noise ratio. The user must also insure that the selected digital microphone can work properly at 512 kHz. These configurations can be used for sound detection. The RSFLT is not used to reduce as much as possible the frequency of the kernel clock (mdf_ker_ck).

Configurations #3, #4, #9, #10, #11 give signal-to-noise ratios around 115 dB, with an ideal microphone model, with a sinus signal of 997 Hz. Using the RSFLT allows a good control on the in-band ripple and a good image rejection.

Configurations #7, #8, #10 give signal-to-noise ratio around 120 dB, with an ideal microphone model, using a sinus signal of 997 Hz.

Table 384. Examples of MDF settings for microphone capture

1. CICMOD = 100 for CIC order equal to 4. CICMOD = 101 for CIC order equal to 5.

39.7.2 Programming examples

This example describes how to capture sound from four microphones, assuming that each microphone pair shares the same data line. The MDF_SD0 and MDF_SD2 data lines are used. The microphone clock is provided by the MDF via MDF_CCK0 pin.

Table 385. Programming sequence

Table 385. Programming sequence (continued)

Table 385. Programming sequence (continued)

39.7.3 Connection examples

Figure 357 shows simple connection examples of the MDF to external sensors:

• • Picture on the left: four digital microphones connected to the MDF
  In this connection, DMIC1 is intended to be used alone. This is why it uses a dedicated clock (MDF_CCK0). DMIC1 is also connected to a dedicated data line in case the application intends to power-down DMIC2/3/4, when only DMIC1 is used. If the application keeps DMIC2/3/4 powered, DMIC2 and DMIC1 can share the same data line, reducing the connection to four I/Os.
  If the power consumption is not an issue, when a single microphone is used, all the microphones can be connected to the same common clock (MDF_CCK0) and each

microphone pair can share the same data line. In this case, only three I/Os are required.

In this example, the data transfer to memory can be performed either using the interleaved- or the independent-transfer mode.

• • Picture in the center: sensor providing several data lines with a common clock

Each data line can represent different parameters (such as current or voltage). The common clock can be provided either by the sensor or by the MDF. The data line can be shared or not by two sensors if the sensor allows it. In the figure below, the sensor does not allow the sharing of the data lines.

In this example, the data transfer to memory can be performed either using the interleaved- or independent-transfer mode.

• • Picture on the right: two independent sensors connected to the MDF

Each of them has its dedicated clock and data lines. In this case, the data transfer to memory must use the independent-transfer mode.

Figure 357. Sensor connection examples

39.7.4 Global frequency response

Figure 358 shows the global frequency response for a 16 kHz audio signal with a digital microphone working at 1.024 MHz. The filter configuration is the following:

• • CIC order 4 or 5, with a decimation ratio of 16
• • RSFLT enabled, with a decimation ratio of 4
• • HPF enable with a cut-off frequency of 40 Hz

The figure below shows the theoretical frequency response using a CIC4 and a CIC5.

Figure 358. Global frequency response

Figure 359 shows the in-band ripple for a 16 kHz audio signal with a digital microphone working at 1.024 MHz. The filter configuration is the following:

• • CIC order 4 or 5, with a decimation ratio of 16
• • RSFLT enabled, with a decimation ratio of 4
• • HPF enable with a cut-off frequency of 20 Hz

The resulting in-band ripple is \( \pm 0.41 \) dB for CIC5, and \( \pm 0.45 \) for CIC4.

The -3 dB cut-off frequency is 7061 Hz.

Figure 359. Detailed frequency response

39.7.5 Total MDF gain

This section details how to compute the signal level provided by the MDF according to the filter settings. The formula does not take into account the filters transfer function.

A signal level may be expressed in dBFS (decibel full scale). A 0 dBFS level is assigned to the maximum possible digital level. For example, a signal that reaches 50 % of the maximum level, has a - 6 dBFS level (6 dB below full scale).

For example, for the MDF offering a final data width of 24 bits, a signal having an amplitude of \( 2 \times 10^6 \) LSB has a level of:

In addition, the data size of a signal having an amplitude (Amp) expressed in LSB is given by:

One bit need to be added for negative values.

So a signal having an amplitude of \( 2 \cdot 10^6 \) LSB, has a data size of 21.9 bits.

CIC gain

The CIC gain ( \( G_{\text{CIC}} \) and \( GdB_{\text{CIC}} \) ) can be deduced from the following formula giving data size in bits ( \( DS_{\text{CIC}} \) ).

And the bit growth is:

where N represents the CIC order (selected by CICMOD[2:0]), and D1 is the decimation ratio (given by MCICD).

\( DS_{\text{IN}} \) represents the data size (in bits) of the input signal.

Warning: \( DS_{\text{CIC}} \) is very important for CIC filters. In order to work fine, \( DS_{\text{CIC}} \) must not exceed 26 bits.

which gives, in decibels:

Note: The same formulas are valid for the ACIC.

Data size at SCALE output

The data size at SCALE output (including the CIC gain) is a key information as the RSFLT starts to have some saturations if the peak-to-peak signal amplitude at SCALE output is higher than 22 bits.

If the RSFLT is bypassed, then a peak-to-peak signal amplitude of 24 bits is accepted. The resulting data size is given by:

The data size at SCALE output ( \( DS_{\text{SCALE}} \) ) is expressed in bits and \( GdB_{\text{SCALE}} \) represents the gain selected by SCALE[5:0], in dB.

RSFLT gain

The RSFLT gain in the useful bandwidth is typically 9.5 dB, but due to ripple a margin of about \( \pm 0.5 \) dB must be considered. Typically, the RSFLT increases the bit size by \( BG_{RSFLT} \) :

INT gain

The INT block can also introduce a gain if the rescaling value is different from the integration value.

and:

The bit growth of the INT is then given by the following formula:

IVAL represents the integration value selected by INTVAL[6:0], and IDIV represents the integrator output division selected by INTDIV[1:0].

Note: The HPF filter has a gain of 0 dB.

The figure below shows a simplified view of the filter path, and gives for each significant component the expression of the bit growth and the gain.

Figure 360. Simplified DFLT view with gain information

The table below summarizes the final data size for different filter configurations.

Table 386. Output signal levels

Example using the main filter chain

If the MDF filter is programmed as follows:

• • The input signal is coming from a serial interface ( \( DS_{IN} = 1 \) bit).
• • CIC order = 5 (N), with a decimation value of 24 (D1).
• • SCALE[5:0] is set to -12 dB.
• • RSFLT is enabled and the decimation by four is enabled.
• • HPF is enabled.
• • INT is disabled.

Check first the data size at CIC output:

The size is lower than 26 bits, so the CIC works in good conditions.

The data size at CIC output is very close to 24 bits, so the SCALE must be adjusted in order to provide a signal 22 bits max to the RSFLT. An attenuation of 12 dB is needed.

Then the signal level provided to the RSFLT is:

At the end, the final signal amplitude is:

or

The RSFLT ripple a margin of about \( \pm 0.41 \) dB (in this configuration) must be considered.

Example using the OLD filter chain

In the following example, the application wants to trigger an OLD event when the voltage coming from a shunt resistor reaches \( \pm 200 \) mV.

Hypothesis:

• • The \( \Sigma\Delta \) sensor is specified to support a full-scale signal of \( \pm 350 \) mV.
• • The ACIC decimation ratio (D2) is fixed to 32.
• • The ACIC order (N) is fixed to 3.

The \( \Sigma\Delta \) sensor provides a full-scale digital signal (amplitude of one bit) for a signal higher or equal to \( \pm 350 \) mV. If the input signal is equal 200 mV, then the digital signal amplitude provided by the sensor is \( 200 / 350 = 0.571 \) .

The gain of the ACIC filter is:

A signal having an amplitude of 200 mV at sensor input has then an amplitude of about \( 32768 * 0.571 = 18725 \) LSB at ACIC output.

OLDTHH must be set to 18725 and OLDTHL must be set to -18725.

39.8 MDF registers

All the MDF registers must be accessed either in word (32-bit) or half-word (16-bit) formats.

The registers are described for the MDF instance having the biggest number of filters.

For registers related to filters, the number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

39.8.1 MDF global control register (MDF_GCR)

Address offset: 0x000

Reset value: 0x0000 0000

This register is used for controls common to all digital filters.

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 ILVNB[3:0] : Interleaved number

This bitfield is set and reset by software. it enables or disables the interleaved-transfer mode and defines how many digital filters work in this mode.

This bitfield cannot be changed when DFLTEN = 1 in MDF_DFLT0CR.

0000: Interleaved-transfer mode disabled

0001: Data from DFLT0 and DFLT1 are interleaved.

0010: Data from DFLT0, DFLT1 and DFLT2 are interleaved.

...

1111: Data from DFLT0 to DFLT15 are interleaved.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 TRGO : Trigger output control

This bit is set by software and reset by hardware. It is used to start the acquisition of several filters synchronously. It is also able to synchronize several MDF together by controlling the mdf_trgo signal.

0: Write 0 has no effect. Read 0 means that the trigger can be set again to 1.

1: Write 1 generates a positive pulse on mdf_trgo signal and triggers the acquisition on the enabled filters having ACQMOD[2:0] = 0x1 and selecting TRGO as trigger. Read 1 means that the trigger pulse is still active.

39.8.2 MDF clock generator control register (MDF_CKGCR)

Address offset: 0x004

Reset value: 0x0000 0000

This register is used to control the clock generator. The mdf_proc_ck clock must be enabled before enabling other MDF parts.

Bit 31 CKGACTIVE : Clock generator active flag

This bit is set and cleared by hardware. This flag must be used by the application to check if the clock generator is effectively enabled (active) or not. The protected fields of this function can only be updated when CKGACTIVE = 0 (refer to Section 39.4.15 for details). The delay between a transition on CKGDEN and a transition on CKGACTIVE is two periods of AHB clock and two periods of mdf_proc_ck.

0: The clock generator is not active and can be configured if needed.

1: The clock generator is active and protected fields cannot be configured.

Bits 30:24 PROCDIV[6:0] : Divider to control the serial interface clock

This bitfield is set and reset by software. It is used to adjust the frequency of the clock provided to the SITF.

This bitfield must not be changed if one of the filters is enabled (DFTEN = 1).

0: mdf_ker_ck provided to the SITF

1: mdf_ker_ck/2 provided to the SITF

2: mdf_ker_ck/3 provided to the SITF

...

127: mdf_ker_ck/128 provided to the SITF

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:16 CCKDIV[3:0] : Divider to control the MDF_CCK clock

This bitfield is set and reset by software. It is used to adjust the frequency of the MDF_CCK clock. The input clock of this divider is the clock provided to the SITF. More globally, the frequency of the MDF_CCK is given by the following formula:

This bitfield must not be changed if one of the filters is enabled (DFTEN = 1).
0000: The MDF_CCK clock is mdf_proc_ck.
0001: The MDF_CCK clock is mdf_proc_ck / 2.
0010: The MDF_CCK clock is mdf_proc_ck / 3.
...
1111: The MDF_CCK clock is mdf_proc_ck / 16.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 15:12 TRGSRC[3:0] : Digital filter trigger signal selection

This bitfield is set and cleared by software. It is used to select which external signals trigger for the corresponding filter. This bitfield is not significant if CKGMOD = 0.
000x: TRGO selected
0010: mdf_trg[0] selected
0011: mdf_trg[1] selected
...
1111: mdf_trg[13] selected

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details.)

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 TRGSENS : CKGEN trigger sensitivity selection

This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0.
0: A rising edge event triggers the activation of CKGEN dividers.
1: A falling edge even triggers the activation of CKGEN dividers.

Note: When the trigger source is TRGO, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge. This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 7 Reserved, must be kept at reset value.

Bit 6 CCK1DIR : MDF_CCK1 direction

This bit is set and reset by software. It is used to control the direction of the MDF_CCK1 pin.
0: MDF_CCK1 pin direction is in input.
1: MDF_CCK1 pin direction is in output.

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 5 CCK0DIR : MDF_CCK0 direction

This bit is set and reset by software. It is used to control the direction of the MDF_CCK0 pin.
0: MDF_CCK0 pin direction is in input.
1: MDF_CCK0 pin direction is in output.

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 4 CKGMOD : Clock generator mode

This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if one of the filters is enabled (DFTEN = 1).

0: The kernel clock is provided to the dividers as soon as CKGDEN is set to 1.

1: The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met.

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 3 Reserved, must be kept at reset value.

Bit 2 CCK1EN : MDF_CCK1 clock enable

This bit is set and reset by software. It is used to control the generation of the bitstream clock on the MDF_CCK1 pin.

0: Bitstream clock not generated

1: Bitstream clock generated on the MDF_CCK1 pad

Bit 1 CCK0EN : MDF_CCK0 clock enable

This bit is set and reset by software. It is used to control the generation of the bitstream clock on the MDF_CCK0 pin.

0: Bitstream clock not generated

1: Bitstream clock generated on the MDF_CCK0 pad

Bit 0 CKGDEN : CKGEN dividers enable

This bit is set and reset by software. It is used to enable/disable the clock dividers of the CKGEN: PROCDIV and CCKDIV.

0: CKGEN dividers disabled

1: CKGEN dividers enabled

39.8.3 MDF serial interface control register x (MDF_SITFxCr)

Address offset: 0x080 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 1F00

This register is used to control the serial interfaces (SITFx). The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bit 31 SITFACTIVE : Serial interface active flag

This bit is set and cleared by hardware. It is used by the application to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set to 0 (refer to Section 39.4.15 for details).

The delay between a transition on SITFEN and a transition on SITFACTIVE is two periods of AHB clock and two periods of mdf_proc_ck.

0: The serial interface is not active and can be configured if needed.

1: The serial interface is active and protected fields cannot be configured.

Bits 30:13 Reserved, must be kept at reset value.

Bits 12:8 STH[4:0] : Manchester symbol threshold/SPI threshold

This bitfield is set and cleared by software. It is used for Manchester mode to define the expected symbol threshold levels (refer to Manchester mode for details on computation). In addition this bitfield is used to define the timeout value for the clock absence detection in Normal SPI mode. STH[4:0] values lower than four are invalid.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 SITFMOD[1:0] : Serial interface type

This bitfield is set and cleared by software. it is used to define the serial interface type.

00: LF_MASTER SPI mode

01: Normal SPI mode

10: Manchester mode: rising edge = logic 0, falling edge = logic 1

11: Manchester mode: rising edge = logic 1, falling edge = logic 0

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bit 3 Reserved, must be kept at reset value.

Bits 2:1 SCKSRC[1:0] : Serial clock source

This bitfield is set and cleared by software. it is used to select the clock source of the serial interface.

00: Serial clock source is MDF_CCK0.

01: Serial clock source is MDF_CCK1.

1x: Serial clock source is MDF_CK1x (not allowed in LF_MASTER SPI mode).

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bit 0 SITFEN : Serial interface enable

This bit is set and cleared by software. It is used to enable/disable the serial interface.

0: Serial interface disabled

1: Serial interface enabled

39.8.4 MDF bitstream matrix control register x (MDF_BSMXxCR)

Address offset: 0x084 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bit 31 BSMXACTIVE : BSMX active flag

This bit is set and cleared by hardware. It is used by the application to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to 0. This BSMXACTIVE flag is a logical OR between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to 0 in order to update BSSEL[4:0] bitfield.

0: BSMX is not active and can be configured if needed.

1: BSMX is active and protected fields cannot be configured.

Bits 30:5 Reserved, must be kept at reset value.

Bits 4:0 BSSEL[4:0] : Bitstream Selection

This bitfield is set and cleared by software. It is used to select the bitstream to be processed for DFLTx and SCDx. The size of this bitfield depends on the number of DFLTx instantiated. If this bitfield selects a not instantiated input, the MDF selects the valid stream bsx_f having the higher index number.

00000: bs0_r provided to DFLTx and SCDx

00001: bs0_f provided to DFLTx and SCDx

00010: bs1_r provided to DFLTx and SCDx (if instantiated)

00011: bs1_f provided to DFLTx and SCDx (if instantiated)

...

11110: bs15_r provided to DFLTx and SCDx (if instantiated)

11111: bs15_f provided to DFLTx and SCDx (if instantiated)

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

39.8.5 MDF digital filter control register x (MDF_DFLTxCR)

Address offset: 0x088 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bit 31 DFLTACTIVE : Digital filter active flag

This bit is set and cleared by hardware. It indicates if the digital filter is active: can be running or waiting for events.

0: Digital filter not active (can be re-enabled again, via DFLTEN, if needed)

1: Digital filter active

Bit 30 DFLTRUN : Digital filter run status flag

This bit is set and cleared by hardware. It indicates if the digital filter is running or not.

0: Digital filter not running and ready to accept a new trigger event

1: Digital filter running

Bits 29:28 Reserved, must be kept at reset value.

Bits 27:20 NBDIS[7:0] : Number of samples to be discarded

This bitfield is set and cleared by software. It is used to define the number of samples to be discarded every time the DFLT _x is re-started.

0: No sample discarded

1: 1 sample discarded

2: 2 samples discarded

...

255: 255 samples discarded

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 SNPSFMT : Snapshot data format

This bit is set and cleared by software. It is used to select the data format for the snapshot mode.

0: Integrator counter (INT_CNT) not inserted into MDF_SNPS _x DR, leaving a data resolution of 23 bits

1: Integrator counter (INT_CNT) inserted at position [15:9] of MDF_SNPS _x DR, leaving a data resolution of 16 bits.

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bits 15:12 TRG SRC[3:0] : Digital filter trigger signal selection

This bitfield is set and cleared by software. It is used to select which external signals trigger the corresponding filter.

0000: TRGO selected

0001: OLD _x event selected

0010: mdf_trg[0] selected

...

1111: mdf_trg[13] selected

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 TRG SENS : Digital filter trigger sensitivity selection

This bit is set and cleared by software. It is used to select the trigger sensitivity of the external signals

0: A rising edge event triggers the acquisition.

1: A falling edge even triggers the acquisition.

Note: When the trigger source is TRGO or OLD _x event, TRG SENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLD _x event is selected, the sensitivity is forced to rising edge.

This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ACQ MOD[2:0] : Digital filter trigger mode

This bitfield is set and cleared by software. It is used to select the filter trigger mode.

000: Asynchronous continuous acquisition mode

001: Asynchronous single-shot acquisition mode

010: Synchronous continuous acquisition mode

011: Synchronous, single-shot acquisition mode

100: Window continuous acquisition mode

101: Synchronous snapshot mode

Others: same a 000

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bit 3 Reserved, must be kept at reset value.

Bit 2 FTH : RXFIFO threshold selection

This bit is set and cleared by software. It is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved-transfer mode (see Interleaved-transfer mode for details).

0: RXFIFO threshold event generated when the RXFIFO is not empty

1: RXFIFO threshold event generated when the RXFIFO is half-full

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 1 DMAEN : DMA requests enable

This bit is set and cleared by software. It is used to control the generation of DMA request to transfer the processed samples into the memory.

0: DMA interface for the corresponding digital filter disabled

1: DMA interface for the corresponding digital filter enabled

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bit 0 DFLTEN : Digital filter enable

This bit is set and cleared by software. It is used to control the start of acquisition of the corresponding digital filter path. This bit behavior depends on ACQMOD[2:0] and external events. The serial or parallel interface delivering the samples must be enabled as well.

0: Acquisition immediately stopped

1: Acquisition immediately started if ACQMOD[2:0] = 00x or 101, or acquisition started when the proper trigger event occurs if ACQMOD[2:0] = 01x or 100.

39.8.6 MDF digital filter configuration register x (MDF_DFLTxCICR)

Address offset: 0x08C + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register is used to control the main CIC filter. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:26 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output (refer to Table 377 for details). If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value.

000000: 0 dB

000001: + 3.5 dB

000010: + 6 dB or shift left by 1 bit

...

011000: + 72 dB or shift left by 12 bits

100000: - 48.2 dB or shift right by 8 bits (default value)

100001: - 44.6 dB

100010: - 42.1 dB or shift right by 7 bits

100011: - 38.6 dB

...

101110: - 6 dB or shift right by 1 bit

101111: - 2.5 dB

Others: Reserved

Bits 19:17 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the CIC decimation ratio. A decimation ratio smaller than two is not allowed. The decimation ratio is given by (CICDEC+1).

0: Decimation ratio is 2.

1: Decimation ratio is 2.

2: Decimation ratio is 3..

3: Decimation ratio is 4

...

511: Decimation ratio is 512.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bit 7 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the configuration and the order of the MCIC. When CICMOD[2:0] = 0xx, the CIC is split into two filters: the main CIC (MCIC) and the auxiliary CIC (ACIC, used for the out-of limit detector).

000: CIC split in two filters and MCIC configured in FastSinc filter

001: CIC split in two filters and MCIC configured in Sinc ¹ filter

010: CIC split in two filters and MCIC configured in Sinc ² filter

011: CIC split in two filters and MCIC configured in Sinc ³ filter

100: CIC configured in single Sinc ⁴ filter

others: CIC configured in single Sinc ⁵ filter

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 3:2 Reserved, must be kept at reset value.

This bitfield is set and cleared by software.

0x: Stream coming from the BSMX selected

10: Stream coming from the ADCITF1 selected

11: Stream coming from the ADCITF2 selected

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

39.8.7 MDF reshape filter configuration register x (MDF_DFLTxRSFR)

Address offset: \( 0x090 + 0x80 * x \) , ( \( x = 0 \) to \( 5 \) )

Reset value: \( 0x0000\ 0000 \)

This register is used to control the reshape and HPF filters. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:8 HPFC[1:0] : High-pass filter cut-off frequency

This bitfield is set and cleared by software. It is used to select the cut-off frequency of the high-pass filter. \( F_{PCM} \) represents the sampling frequency at HPF input.

00: Cut-off frequency = \( 0.000625 \times F_{PCM} \)

01: Cut-off frequency = \( 0.00125 \times F_{PCM} \)

10: Cut-off frequency = \( 0.00250 \times F_{PCM} \)

11: Cut-off frequency = \( 0.00950 \times F_{PCM} \)

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bit 7 HPFBYP : High-pass filter bypass

This bit is set and cleared by software. It is used to bypass the high-pass filter.

0: HPF not bypassed (default value)

1: HPF bypassed

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 RSFLTD : Reshaper filter decimation ratio

This bit is set and cleared by software. It is used to select the decimation ratio for the reshape filter.

0: Decimation ratio is 4 (default value).

1: Decimation ratio is 1.

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 RSFLTBY : Reshaper filter bypass

This bit is set and cleared by software. It is used to bypass the reshape filter and its decimation block.

0: Reshape filter not bypassed (default value)

1: Reshape filter bypassed

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

39.8.8 MDF integrator configuration register x (MDF_DFLTxINTR)

Address offset: 0x094 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register is used to the integrator (INT) settings. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:4 INTVAL[6:0] : Integration value selection

This bitfield is set and cleared by software. It is used to select the integration value.

0: The integration value is 1, meaning bypass mode (default after reset).

1: The integration value is 2.

2: The integration value is 3.

...

127: The integration value is 128.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 INTDIV[1:0] : Integrator output division

This bitfield is set and cleared by software. It is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits.

00: The integrator data outputs are divided by 128 (default value).

01: The integrator data outputs are divided by 32.

10: The integrator data outputs are divided by 4.

11: The integrator data outputs are not divided.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

39.8.9 MDF out-of limit detector control register x (MDF_OLDxCR)

Address offset: 0x098 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register is used to configure the OLDx. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

This bit is set and cleared by hardware. It is used to check if the OLDx is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to 0 (refer to Section 39.4.15 for details).

The delay between a transition on OLDEN and a transition on OLDACTIVE is two periods of AHB clock and two periods of mdf_proc_ck.

0: OLDx not active and can be configured if needed

1: OLDx active and protected fields cannot be configured

Bits 30:22 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the decimation ratio of the ACIC. It is only taken into account by the MDF when CICMOD[2:0] = 0xx. The decimation ratio is given by (ACICD + 1).

0: Decimation ratio is 1.

1: Decimation ratio is 2.

2: Decimation ratio is 3.

3: Decimation ratio is 4.

...

31: Decimation ratio is 32.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 16:14 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. It is used to select the ACIC type and order. It is only taken into account by the MDF when CICMOD[2:0] = 0xx.

00: FastSinc filter type

01: Sinc ¹ filter type

10: Sinc ² filter type

11: Sinc ³ filter type

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 11:8 Reserved, must be kept at reset value.

This bitfield is set and cleared by software.

BKOLD[i] = 0: Break signal (mdf_break[i]) not assigned to threshold event

BKOLD[i] = 1: Break signal (mdf_break[i]) assigned to threshold event

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 3:2 Reserved, must be kept at reset value.

This bit is set and cleared by software.

0: The OLDx generates an event if the signal is lower than OLDTHL or higher than OLDTHH (default value).

1: The OLDx generates an event if the signal is lower than OLDTHH and higher than OLDTHL.

Note: This bit can be write-protected (refer to Section 39.4.15 for details).

This bit is set and cleared by software.

0: OLDx disabled (default value)

1: OLDx enabled, including the ACIC filter working in continuous mode

39.8.10 MDF OLDx low threshold register x (MDF_OLDxTHLR)

Address offset: \( 0x09C + 0x80 * x \) , ( \( x = 0 \) to \( 5 \) )

Reset value: \( 0x0000\ 0000 \)

This register is used for the adjustment of the out-of-limit low threshold. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 OLDTHL[25:0] : OLD low threshold value

This bitfield is set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

39.8.11 MDF OLDx high threshold register x (MDF_OLDxTHHR)

Address offset: \( 0x0A0 + 0x80 * x \) , ( \( x = 0 \) to \( 5 \) )

Reset value: \( 0x0000\ 0000 \)

This register is used for the adjustment of the OLDx high threshold. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 OLDTHH[25:0] : OLDx high threshold value

This bitfield is set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

39.8.12 MDF delay control register x (MDF_DLYxCR)

Address offset: \( 0x0A4 + 0x80 * x \) , ( \( x = 0 \) to \( 5 \) )

Reset value: \( 0x0000\ 0000 \)

This register is used for the adjustment stream delays. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bit 31 SKPBF: Skip busy flag

This bit is set and cleared by hardware. It is used to control if the delay sequence is completed.

0: MDF ready to accept a new value into SKPDLY[6:0]

1: Last valid SKPDLY[6:0] still under processing

Bits 30:7 Reserved, must be kept at reset value.

Bits 6:0 SKPDLY[6:0]: Delay to apply to a bitstream

This bitfield is set and cleared by software. It defines the number of input samples that are skipped. Skipping is applied immediately after writing to this bitfield, if SKPBF = 0 and the corresponding DFLTEN = 1. If SKPBF = 1, the value written into the register is ignored by the delay state machine.

0: No input sample skipped

1: 1 input sample skipped

...

127: 127 input samples skipped

39.8.13 MDF short circuit detector control register x (MDF_SCDxCR)

Address offset: \( 0x0A8 + 0x80 * x \) , ( \( x = 0 \) to \( 5 \) )

Reset value: \( 0x0000\ 0000 \)

This register is used for the adjustment stream delays. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

This bit is set and cleared by hardware. It is used to check if the SCDx is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to 0 (refer to Section 39.4.15 for details).

The delay between a transition on SCDEN and a transition on SCDACTIVE is two periods of AHB clock and two periods of mdf_proc_ck.

0: SCDx not active and can be configured if needed

1: SCDx active and protected fields cannot be configured

Bits 30:20 Reserved, must be kept at reset value.

This bitfield is set and cleared by software. These bits are written by software to define the threshold counter for SCDx. If this value is reached, a short-circuit detector event occurs on a given input stream.

0: 2 consecutive 1's or 0's generate an event.

1: 2 consecutive 1's or 0's generate an event.

2: 3 consecutive 1's or 0's generate an event.

...

255: 256 consecutive 1's or 0's generate an event.

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 11:8 Reserved, must be kept at reset value.

This bitfield is set and cleared by software.

BKSCD[i] = 0: Break signal (mdf_break[i]) not assigned to this SCD event

BKSCD[i] = 1: Break signal (mdf_break[i]) assigned to this SCD event

Note: This bitfield can be write-protected (refer to Section 39.4.15 for details).

Bits 3:1 Reserved, must be kept at reset value.

This bit is set and cleared by software.

0: SCDx disabled

1: SCDx enabled,

39.8.14 MDF DFLT0 interrupt enable register 0 (MDF_DFLT0IER)

Address offset: 0x0AC

Reset value: 0x0000 0000

This register is used for allowing or not the events to generate an interrupt.

Bits 31:12 Reserved, must be kept at reset value.

1. Bit 11 RFOVRIE : Reshape filter overrun interrupt enable
   This bit is set and cleared by software.
   0: Reshape filter overrun interrupt disabled
   1: Reshape filter overrun interrupt enabled
2. Bit 10 CKABIE : Clock absence detection interrupt enable
   This bit is set and cleared by software.
   0: Clock absence interrupt disabled
   1: Clock absence interrupt enabled
3. Bit 9 SATIE : Saturation detection interrupt enable
   This bit is set and cleared by software.
   0: Saturation interrupt disabled
   1: Saturation interrupt enabled
4. Bit 8 SCDIE : SCD0 interrupt enable
   This bit is set and cleared by software.
   0: SCD0 interrupt disabled
   1: SCD0 interrupt enabled
5. Bit 7 SSOVRIE : Snapshot overrun interrupt enable
   This bit is set and cleared by software.
   0: Snapshot overrun interrupt disabled
   1: Snapshot overrun interrupt enabled
6. Bits 6:5 Reserved, must be kept at reset value.
7. Bit 4 OLDIE : OLD0 interrupt enable
   This bit is set and cleared by software.
   0: OLD0 event interrupt disabled
   1: OLD0 event interrupt enabled
8. Bit 3 Reserved, must be kept at reset value.
9. Bit 2 SSDRIE : Snapshot data ready interrupt enable
   This bit is set and cleared by software.
   0: Snapshot data ready interrupt disabled
   1: Snapshot data ready interrupt enabled
10. Bit 1 DOVRIE : Data overflow interrupt enable
    This bit is set and cleared by software.
    0: Data overflow interrupt disabled
    1: Data overflow interrupt enabled
11. Bit 0 FTHIE : RXFIFO threshold interrupt enable
    This bit is set and cleared by software.
    0: RXFIFO threshold interrupt disabled
    1: RXFIFO threshold interrupt enabled

39.8.15 MDF DFLT x interrupt enable register x (MDF_DFLT x IER)

Address offset: \( 0x12C + 0x80 \times (x - 1) \) , ( \( x = 1 \) to \( 5 \) )

Reset value: 0x0000 0000

This register is used for allowing or not, the events to generate an interrupt. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 RFOVRIE : Reshape filter overrun interrupt enable
This bit is set and cleared by software.
0: Reshape filter overrun interrupt disabled
1: Reshape filter overrun interrupt enabled

Bit 10 CKABIE : Clock absence detection interrupt enable
This bit is set and cleared by software.
0: Clock absence interrupt disabled
1: Clock absence interrupt enabled

Bit 9 SATIE : Saturation detection interrupt enable
This bit is set and cleared by software.
0: Saturation interrupt disabled
1: Saturation interrupt enabled

Bit 8 SCDIE : SCD x interrupt enable
This bit is set and cleared by software.
0: SCD x interrupt disabled
1: SCD x interrupt enabled

Bit 7 SSOVRIE : Snapshot overrun interrupt enable
This bit is set and cleared by software.
0: Snapshot overrun interrupt disabled
1: Snapshot overrun interrupt enabled

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OLDIE : OLD x interrupt enable
This bit is set and cleared by software.
0: OLD x event interrupt disabled
1: OLD x event interrupt enabled

Bit 3 Reserved, must be kept at reset value.

Bit 2 SSDRIE : Snapshot data ready interrupt enable
This bit is set and cleared by software.
0: Snapshot data ready interrupt disabled
1: Snapshot data ready interrupt enabled

Bit 1 DOVRIE : Data overflow interrupt enable

This bit is set and cleared by software.

0: Data overflow interrupt disabled

1: Data overflow interrupt enabled

Bit 0 FTHIE : RXFIFO threshold interrupt enable

This bit is set and cleared by software.

0: RXFIFO threshold interrupt disabled

1: RXFIFO threshold interrupt enabled

39.8.16 MDF DFLT0 interrupt status register 0 (MDF_DFLT0ISR)

Address offset: 0x0B0

Reset value: 0x0000 0000

This register contains the status flags for each digital filter path.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 RFOVRF : Reshape filter overrun detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no reshape filter overrun is detected. Write 0 has no effect.

1: Read 1 means that reshape filter overrun is detected. Write 1 clears this flag.

Bit 10 CKABF : Clock absence detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no clock absence is detected. Write 0 has no effect.

1: Read 1 means that a clock absence is detected. Write 1 clears this flag.

Bit 9 SATF : Saturation detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no saturation is detected. Write 0 has no effect.

1: Read 1 means that a saturation is detected. Write 1 clears this flag.

Bit 8 SCDF : Short-circuit detector flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no SCD0 event is detected. Write 0 has no effect.

1: Read 1 means that a SCD0 event is detected. Write 1 clears this flag.

Bit 7 SSOVR : Snapshot overrun flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no snapshot overrun event is detected. Write 0 has no effect.

1: Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag.

This bit is set by hardware and cleared by software by writing this bit to 1. It indicates the status of the high-threshold comparator when the last OLD0 event occurred. This bit gives additional information on the conditions triggering the last OLD0 event. It can be cleared by writing OLDF flag to 1.

0: The signal was lower than OLDTHH when the last OLD0 event occurred.

1: The signal was higher than OLDTHH when the last OLD0 event occurred.

This bit is set by hardware and cleared by software by writing this bit to 1. It indicates the status of the low-threshold comparator when the last OLD0 event occurred. This bit gives additional information on the conditions triggering the last OLD0 event. It can be cleared by writing OLDF flag to 1.

0: The signal was higher than OLDTHL when the last OLD0 event occurred.

1: The signal was lower than OLDTHL when the last OLD0 event occurred.

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no OLD0 event is detected. Write 0 has no effect.

1: Read 1 means that an OLD0 event is detected Write 1 clears THHF, THLF and OLDF.

this bit is set and cleared by hardware according to the RXFIFO level.

0: RXFIFO empty

1: RXFIFO not empty

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no data is available. Write 0 has no effect.

1: Read 1 means that a new data is available. Write 1 clears this flag.

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no overflow is detected. Write 0 has no effect.

1: Read 1 means that an overflow is detected; Write 1 clears this flag.

This bit is set by hardware and cleared by hardware when the RXFIFO level is lower than the threshold.

0: RXFIFO threshold not reached

1: RXFIFO threshold reached

39.8.17 MDF DFLTx interrupt status register x (MDF_DFLTxISR)

Address offset: \( 0x130 + 0x80 * (x - 1) \) , ( \( x = 1 \) to \( 5 \) )

Reset value: 0x0000 0000

This register contains the status flags for each digital filter path. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 RFOVRF : Reshape filter overrun detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no reshape filter overrun is detected. Write 0 has no effect.

1: Read 1 means that reshape filter overrun is detected. Write 1 clears this flag.

Bit 10 CKABF : Clock absence detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no clock absence is detected. Write 0 has no effect.

1: Read 1 means that a clock absence is detected. Write 1 clears this flag.

Bit 9 SATF : Saturation detection flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no saturation is detected. Write 0 has no effect.

1: Read 1 means that a saturation is detected. Write 1 clears this flag.

Bit 8 SCDF : Short-circuit detector flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no SCD event is detected. Write 0 has no effect.

1: Read 1 means that a SCD event is detected. Write 1 clears this flag.

Bit 7 SSOVRF : Snapshot overrun flag

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no snapshot overrun event is detected. Write 0 has no effect.

1: Read 1 means that a snapshot overrun event is detected. Write 1 clears this flag.

Bit 6 THHF : High-threshold status flag

This bit is set by hardware and cleared by software by writing this bit to 1. It indicates the status of the high-threshold comparator when the last OLDx event occurred. This bit gives additional information on the conditions triggering the last OLDx event. It can be cleared by writing OLDF flag to 1.

0: The signal was lower than OLDTHH when the last OLDx event occurred.

1: The signal was higher than OLDTHH when the last OLDx event occurred.

This bit is set by hardware and cleared by software by writing this bit to 1. It indicates the status of the low-threshold comparator when the last OLDx event occurred. This bit gives additional information on the conditions triggering the last OLDx event. It can be cleared by writing OLDF flag to 1.

0: The signal was higher than OLDTHL when the last OLDx event occurred.

1: The signal was lower than OLDTHL when the last OLDx event occurred.

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no OLDx event is detected. Write 0 has no effect.

1: Read 1 means that an OLDx event is detected Write 1 clears THHF, THLF and OLDF.

this bit is set and cleared by hardware according to the RXFIFO level.

0: RXFIFO empty

1: RXFIFO not empty

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no data is available. Write 0 has no effect.

1: Read 1 means that a new data is available. Write 1 clears this flag.

This bit is set by hardware and cleared by software by writing this bit to 1.

0: Read 0 means that no overflow is detected. Write 0 has no effect.

1: Read 1 means that an overflow is detected; Write 1 clears this flag.

This bit is set by hardware and cleared by hardware when the RXFIFO level is lower than the threshold.

0: RXFIFO threshold not reached

1: RXFIFO threshold reached

39.8.18 MDF offset error compensation control register x (MDF_OECxCR)

Address offset: 0x0B4 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register contains the offset compensation value. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:0 OFFSET[25:0] : Offset error compensation

This bitfield is set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back this bitfield informs the application on the current offset value.

This bitfield represents the value to be subtracted to the signal before going to the SCALE.

39.8.19 MDF snapshot data register x (MDF_SNPSxDR)

Address offset: 0x0EC + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register is used to read the data processed by each digital filter in snapshot mode. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:16 SDR[15:0] : Contains the 16 MSB of the last valid data processed by the digital filter.

Bits 15:9 EXTSDR[6:0] : Extended data size

If SNPSFMT = 0, this bitfield contains the bits 7 to 1 of the last valid data processed by the digital filter.

If SNPSFMT = 1, this bitfield contains the INT accumulator counter value when the last trigger event occurs (INT_CNT).

Bits 8:0 MCICDC[8:0] : Contains the MCIC decimation counter value when the last trigger event occurs (MCIC_CNT)

39.8.20 MDF digital filter data register x (MDF_DFLTxDR)

Address offset: 0x0F0 + 0x80 * x, (x = 0 to 5)

Reset value: 0x0000 0000

This register is used to read the data processed by each digital filter. The number of registers is equal to the amount of filters. Refer to Section 39.3 for details.

Bits 31:8 DR[23:0] : Data processed by digital filter

Bits 7:0 Reserved, must be kept at reset value.

39.8.21 MDF register map

Table 387. MDF register map and reset values

Table 387. MDF register map and reset values (continued)