30. Hexadeca-SPI interface (HSPI)

30.1 HSPI introduction

The HSPI supports most external serial memories such as serial PSRAMs, serial NAND and serial NOR flash memories, HyperRAM™ and HyperFlash™ memories, with the following functional modes:

• • indirect mode: all the operations are performed using the HSPI registers to preset commands, addresses, data, and transfer parameters.
• • automatic status-polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting. This feature is only available in regular-command protocol.
• • memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an internal memory, supporting both read and write operations.

The HSPI supports the following protocols with associated frame formats:

• • the regular-command frame format with the command, address, alternate byte, dummy cycles, and data phase
• • the HyperBus™ frame format

30.2 HSPI main features

• • Functional modes: indirect, automatic status-polling, and memory-mapped
• • Read and write support in memory-mapped mode
• • Support for single, dual, quad, and octal communication
• • Dual-memory configuration, where 8 bits can be sent/received simultaneously by accessing two quad or two octal memories in parallel
• • HSPI mode accessing a single 16-bit memory
• • SDR (single-data rate) and DTR (double-transfer rate) support
• • Data strobe support
• • Fully programmable opcode
• • Fully programmable frame format
• • Support wrapped-type access to memory in read direction
• • HyperBus support
• • Integrated FIFO for reception and transmission
• • 8-, 16-, and 32-bit data accesses allowed
• • DMA protocol support
• • DMA channel for indirect mode operations
• • Interrupt generation on FIFO threshold, timeout, operation complete, and access error
• • AHB interface with transaction acceptance limited to one: the interface accepts the next transfer on AHB bus only once the previous is completed on memory side.

30.3 HSPI implementation

Table 262. Instances on STM32U5 series devices

Table 263. HSPI implementation

30.4 HSPI functional description

30.4.1 HSPI block diagram

The block diagrams provided below correspond to a single HSPI connected to the I/O ports.

Figure 164. HSPI block diagram for 16-bit configuration

Figure 165. HSPI block diagram for dual-octal configuration

Figure 166. HSPI block diagram for octal configuration

Figure 167. HSPI block diagram in quad configuration

Figure 168. HSPI block diagram for dual-quad configuration

30.4.2 HSPI pins and internal signals

Table 264. HSPI input/output pins

Caution: Use the same configuration (output speed, HSLV) for all HSPI input/output pins to avoid any data corruption.

Table 265. HSPI internal signals

30.4.3 HSPI interface to memory modes

The HSPI supports the following protocols:

• • regular-command protocol
• • HyperBus protocol

The HSPI uses from 6 to 21 signals to interface with a memory, depending on the functional mode:

• • NCS: chip-select.
• • CLK: communication clock
• • NCLK: inverted clock used only in the 1.8 V HyperBus protocol
• • DQS0, DQS1: data strobe used only in regular-command protocol
• • IO[3:0]: data bus LSB
• • IO[7:4]:
  • – data bus MSB used in dual-quad and octal configurations
  • – data bus used as possible remap for quad-SPI mode
• • IO[15:8]:
  • – data bus MSB used in dual-quad, dual-octal and 16-bit configurations
  • – data bus used as possible remap for octal-SPI mode
  • – IO[15:12] and IO[11:8] can also be used as possible remap for quad-SPI mode

30.4.4 HSPI regular-command protocol

When in regular-command protocol, the HSPI communicates with the external device using commands. Each command can include the following phases:

• • instruction phase
• • address phase
• • alternate-byte phase
• • dummy-cycle phase
• • data phase

Only the data phase uses 16 bits. Instruction, address, and alternate phases use only the eight LSB of the bus as for octal configuration.

Any of these phases can be configured to be skipped, but single-phase commands supported are only those with instruction phase.

The NCS falls before the start of each command and rises again after each command finishes.

In memory-mapped mode, both read and write operation are supported: as a consequence, some of the configuration registers are duplicated to specify write operations (read operations are configured using regular registers).

Figure 169. SDR read command in 16-bit configuration

1. 1. Data (such as D0, D1, D2) are sent in 16-bit configuration mode over IO[15:0]. Only the command and address are sent over IO[7:0] as for octal mode.

The specific regular-command protocol features are configured through the registers in the 0x0100-0x01FC offset range.

Instruction phase

During this phase, a 1- to 4-byte instruction is sent to the external device specifying the type of operation to be performed. The size of the instruction to be sent is configured in ISIZE[1:0] of HSPI_CCR and the instruction is programmed in INSTRUCTION[31:0] of HSPI_IR.

The instruction phase can optionally send:

• • 1 bit at a time (over IO0, SO signal in single-SPI mode)
• • 2 bits at a time (over IO0/IO1 in dual-SPI mode)
• • 4 bits at a time (over IO0 to IO3 in quad-SPI mode)
• • 8 bits at a time (over IO0 to IO7 in octal-SPI mode, or in 16-bit SPI mode)

This can be configured using IMODE[2:0] of HSPI_CCR.

The instruction can be sent in DTR (double-transfer rate) mode on each rising and falling edge of the clock, by setting IDTR in HSPI_CCR.

When IMODE[2:0] = 000 in HSPI_CCR, the instruction phase is skipped, and the command sequence starts with the address phase, if present.

When in memory-mapped mode, the instruction used for the write operation is specified in HSPI_WIR and the instruction format is specified in HSPI_WCCR. The instruction used for the read operation and the instruction format are specified in HSPI_IR and HSPI_CCR.

Address phase

In the address phase, 1 to 4 bytes are sent to the external device, to indicate the address of the operation. The number of address bytes to be sent is configured in ADSIZE[1:0] of HSPI_CCR.

In indirect and automatic status-polling modes, the address bytes to be sent are specified in ADDRESS[31:0] of HSPI_AR. In memory-mapped mode, the address is given directly via the AHB (from any master in the system).

The address phase can send:

• • 1 bit at a time (over IO0, SO signal in single-SPI mode)
• • 2 bits at a time (over IO0/IO1 in dual-SPI mode)
• • 4 bits at a time (over IO0 to IO3 in quad-SPI mode)
• • 8 bits at a time (over IO0 to IO7 in octal-SPI mode, or in 16-bit SPI mode)

This can be configured using ADMODE[2:0] of HSPI_CCR.

The address can be sent in DTR mode (on each rising and falling edge of the clock) setting ADDTR in HSPI_CCR.

When ADMODE[2:0] = 000, the address phase is skipped and the command sequence proceeds directly to the next phase, if any.

In memory-mapped mode, the address format for the write operation is specified in HSPI_WCCR. The address format for the read operation is specified in HSPI_CCR.

Warning: Some memory specifications consider that each address corresponds to a 16-bit value. HSPI considers that each address corresponds to an 8-bit value. So the software needs to multiply the address by two when accessing the memory registers.

Alternate-byte phase

In the alternate-bytes phase, 1 to 4 bytes are sent to the external device, generally to control the mode of operation. The number of alternate bytes to be sent is configured in ABSIZE[1:0] of HSPI_CCR. The bytes to be sent are specified in HSPI_ABR.

The alternate-byte phase can send:

• • 1 bit at a time (over IO0, SO signal in single-SPI mode)
• • 2 bits at a time (over IO0/IO1 in dual-SPI mode)
• • 4 bits at a time (over IO0 to IO3 in quad-SPI mode)
• • 8 bits at a time (over IO0 to IO7 in octal-SPI mode, or in 16-bit SPI mode)

This can be configured using ABMODE[2:0] of HSPI_CCR.

The alternate bytes can be sent in DTR mode (on each rising and falling edge of the clock) setting ABDTR of HSPI_CCR.

When ABMODE[2:0] = 000, the alternate-bytes phase is skipped and the command sequence proceeds directly to the next phase, if any.

Only a single nibble may need to be sent during the alternate-byte phase rather than a full byte, such as when the dual-SPI mode is used and only two cycles are used for the alternate bytes.

In this case, the firmware can use the quad-SPI mode (ABMODE[2:0] = 011), and send a byte with bits 7 and 3 of ALTERNATE[31:0] set to 1 (keeping the IO3 line high), and bits 6 and 2 set to 0 (keeping the IO2 line low), in HSPI_IR.

The upper two bits of the nibble to be sent are then placed in bits 5:4 of ALTERNATE[31:0], while the lower two bits are placed in bits 1:0. For example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE[31:0] must be set to 0x8A (1000_1010).

In memory-mapped mode, the alternate bytes used for the write operation are specified in HSPI_WABR, and the alternate byte format is specified in HSPI_WCCR. The alternate bytes used for read operation and the alternate byte format are specified in HSPI_ABR and HSPI_CCR.

Dummy-cycle phase (memory latency)

In the dummy-cycle phase, 1 to 31 cycles are given without any data being sent or received, in order to give the external device, the time to prepare for the data phase when higher clock frequencies are used. The number of cycles given during this phase is specified in DCYC[4:0] of HSPI_TCR. In both SDR and DTR modes, the duration is specified as a number of full CLK cycles.

When DCYC[4:0] = 00000, the dummy-cycle phase is skipped, and the command sequence proceeds directly to the data phase, if present.

In order to assure enough “turn-around” time for changing the data signals from the output mode to the input mode, there must be at least one dummy cycle when using the dual-, quad-, octal-, or 16-bit SPI mode, to receive data from the external device.

In memory-mapped mode, the dummy cycles for the write operations are specified in HSPI_WTCR. The dummy cycles for the read operation are specified in HSPI_TCR.

Data phase

During the data phase, any number of bytes can be sent to or received from the external device.

In indirect mode, the number of bytes to be sent/received is specified in HSPI_DLR. In this mode, the data to be sent to the external device must be written to HSPI_DR. In indirect-read mode, the data received from the external device is obtained by reading HSPI_DR.

In automatic status-polling mode, the number of bytes to be received is specified in HSPI_DLR, and the data received from the external device can be obtained by reading HSPI_DR.

In memory-mapped mode, the data read or written, is sent or received directly over the AHB to the Cortex core or to a DMA.

The data phase can send/receive:

• • 1 bit at a time (over IO0/IO1 (SO/SI respectively) in single-SPI mode)
• • 2 bits at a time (over IO0/IO1 in dual-SPI mode)
• • 4 bits at a time (over IO0 to IO3 in quad-SPI mode)
• • 8 bits at a time (over IO0 to IO7 in octal-SPI mode)
• • 16 bits at a time (over IO0 to IO15 in 16-bit SPI mode)

This can be configured using DMODE[2:0] of HSPI_CCR.

The data can be sent or received in DTR mode (on each rising and falling edge of the clock) setting DDTR of HSPI_CCR.

When DMODE[2:0] = 000, the data phase is skipped, and the command sequence finishes immediately by raising the NCS. This configuration must be used only in indirect-write mode.

In memory-mapped mode, the data format for the write operation is specified in HSPI_WCCR. The data format for the read operation is specified in HSPI_CCR.

DQS use

The DQS signal can be used for data strobing during the read transactions when the device toggles the DQS aligned with the data.

The DQS management can be enabled by setting DQSE of HSPI_CCR.

Figure 170. DTR read in octal-SPI mode with DQS (Macronix mode) example

30.4.5 HSPI regular-command protocol signal interface

Single-SPI mode

The legacy SPI mode allows just a single bit to be sent/received serially. In this mode, the data is sent to the external device over the SO signal (Single-SPI Output) (whose I/Os are shared with IO0). The data received from the external device arrives via SI (Single-SPI Input) (whose I/Os are shared with IO1).

Compared to the SPI legacy mode, IO/SO and I1/SI are respectively equivalent to MOSI and MISO, having the HSPI generating the clock.

The different phases can each be configured separately to use this single-bit mode by setting to 001 the IMODE, ADMODE, ABMODE, and DMODE fields in HSPI_CCR and HSPI_WCCR.

In each phase configured in single-SPI mode:

• • IO0 (SO) is in output mode.
• • IO1 (SI) is in input mode (high impedance).
• • IO2 is in output mode and forced to 0.
• • IO3 is in output mode and forced to 1 (to deactivate the “hold” function).
• • IO4 to IO15 are in output mode and forced to 0.

This is the case even for the dummy phase if DMODE[2:0] = 001.

Dual-SPI mode

In dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.

The different phases can each be configured separately to use dual-SPI mode by setting to 010 the IMODE, ADMODE, ABMODE, and DMODE fields in HSPI_CCR and HSPI_WCCR.

In each phase configured in dual-SPI mode:

• • IO0/IO1 are at high-impedance (input) during the data phase for the read operations, and outputs in all other cases.
• • IO2 is in output mode and forced to 0.

• • IO3 is in output mode and forced to 1.
• • IO4 to IO15 are in output mode and forced to 0.

In the dummy phase, when DMODE[2:0] = 010, IO0 and IO1 are in a high-impedance state during read transactions, and are forced to either high or low levels during write transactions.

Quad-SPI mode

In quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals.

The different phases can each be configured separately to use the quad-SPI mode by setting to 011 the IMODE, ADMODE, ABMODE, and DMODE fields in HSPI_CCR and HSPI_WCCR.

In each phase configured in quad-SPI mode:

• • IO0 to IO3 are all at high-impedance (inputs) during the data phase for the read operations, and outputs in all other cases.
• • IO4 to IO15 are in output mode and forced to 0.

In the dummy phase, when DMODE[2:0] = 011, IO0 to IO3 are in a high-impedance state during read transactions, and are forced to either high or low levels during write transactions.

Octal-SPI mode

In regular octal-SPI mode, the eight bits are sent/received simultaneously over the IO[0:7] signals.

The different phases can each be configured separately to use the octal-SPI mode by setting to 100 the IMODE, ADMODE, ABMODE, and DMODE fields in HSPI_CCR and HSPI_WCCR.

In each phase that is configured in octal-SPI mode, IO[0:7] are all at high-impedance (input) during the data phase for read operations, and outputs in all other cases.

In the dummy phase, when DMODE[2:0] = 100, IO[0:7] are in a high-impedance state during read transactions, and are forced to either high or low levels during write transactions.

HSPI mode

In HSPI mode, the 16 bits are sent/received simultaneously over the IO[0:15] signals during the data phase.

The following phases must be configured separately to use the HSPI mode:

1. 1. Set to 100 the IMODE, ADMODE, and ABMODE fields (in HSPI_CCR and HSPI_WCCR).
2. 2. Set to 101 the DMODE fields (in HSPI_CCR and HSPI_WCCR).

In each phase that is configured in HSPI mode, IO[0:15] are all at high-impedance (input) during the data phase for read operations, and outputs in all other cases.

In the dummy phase, when DMODE[2:0] = 101, IO[0:15] are in a high-impedance state during read transactions, and are forced to either high or low levels during write transactions.

IO[8:15] are used only in HSPI mode. If none of the phases are configured to use this mode, then the pins corresponding to IO[8:15] can be used for other functions, even while the HSPI is active.

Single-data rate (SDR) mode

By default, all the phases operate in single-data rate (SDR) mode.

In SDR mode, when the HSPI drives the IO0/SO and IO1 to IO15 signals, these signals transition only with the falling edge of CLK.

When receiving data in SDR mode, the HSPI assumes that the external devices also send the data using CLK falling edge. By default (when SSHIFT = 0 in HSPI_TCR), the signals are sampled using the following (rising) edge of CLK.

Figure 171. SDR write command in octal-SPI mode example

Double-transfer rate (DTR) mode

Each of the instruction, address, alternate-byte, and data phases can be configured to operate in DTR mode setting IDTR, ADDTR, ABDTR, and DDTR in HSPI_CCR.

In memory-mapped mode, the DTR mode for each phase of the write operations is specified in HSPI_WCCR. The DTR mode for each phase of the read operations is specified in HSPI_CCR.

In DTR mode, when the HSPI drives the IO0/SO and IO1 to IO7 signals in the instruction, address, and alternate-byte phases, a bit is sent or received on each of the falling and rising edges of CLK.

In DTR mode, when the HSPI drives the IO0 to IO15 signals in the data phases, a bit is sent or received on each of the falling and rising edges of CLK.

When receiving data in DTR mode, the HSPI assumes that the external devices also send the data using both CLK rising and falling edges. When DDTR = 1 in HSPI_CCR, the software must clear SSHIFT in HSPI_TCR. Thus, the signals are sampled one half of a CLK cycle later (on the following, opposite edge).

Figure 172. DTR write in octal-SPI mode (Macronix mode) example

Dual-quad configuration

When DMM = 1 in HSPI_CR, the HSPI is in dual-memory configuration: if DMODE = 011, two external quad-SPI devices (device A and device B) are used in order to send/receive eight bits (or 16 bits in DTR mode) every cycle, effectively doubling the throughput.

Each device (A or B) uses the same CLK and NCS signals, but each has separate IO0 to IO3 signals.

The dual-quad configuration can be used in conjunction with the single-SPI, dual-SPI, and quad-SPI modes, as well as with either SDR or DTR mode.

The device size, as specified in DEVSIZE[4:0] of HSPI_DCR1, must reflect the total external device capacity that is the double of the size of one individual component.

If address X is even, then the byte that the HSPI gives for address X is the byte at the address X/2 of device A, and the byte that the HSPI gives for address X + 1 is the byte at the address X/2 of device B. In other words, the bytes at even addresses are all stored in device A and the bytes at odd addresses are all stored in device B.

When reading the status registers of the devices in dual-quad configuration, twice as many bytes must be read compared to the same read in regular-command protocol: if each device gives eight valid bits after the instruction for fetching the status register, then the HSPI must be configured with a data length of 2 bytes (16 bits), and the HSPI receives one byte from each device.

If each device gives a status of 16 bits, then the HSPI must be configured to read 4 bytes to get all the status bits of both devices in dual-quad configuration. The least-significant byte of the result (in the data register) is the least-significant byte of device A status register. The next byte is the least-significant byte of device B status register. Then, the third byte of the data register is the device A second byte. The forth byte is the device B second byte (if devices have 16-bit status registers).

An even number of bytes must always be accessed in dual-quad configuration. For this reason, bit 0 of DL[31:0] in HSPI_DLR is stuck at 1 when DMM = 1.

In dual-quad configuration, the behavior of device A interface signals is basically the same as in normal mode. Device B interface signals have exactly the same waveforms as device A ones during the instruction, address, alternate-byte, and dummy-cycle phases. In other words, each device always receives the same instruction and the same address.

Then, during the data phase, the AIOx and the BIOx buses both transfer data in parallel, but the data that is sent to (or received from) device A is distinct than the one from device B.

Dual-octal configuration

When DMM = 1 in HSPI_CR, the HSPI is in dual-memory configuration: when DMODE = 100, two external octal-SPI devices (device A and device B) are used in order to receive 32 bits in DTR mode every cycle, effectively doubling the throughput as well as the capacity.

Each device (A or B) uses the same CLK and NCS signals, but each has separate IO0 to IO7 signals.

The dual-octal configuration can be used in DTR mode exclusively in conjunction with the single-SPI, dual-SPI, quad-SPI and octal-SPI modes.

The device size, as specified in DEVSIZE[4:0] of HSPI_DCR1, must reflect the total external device capacity that is the double of the size of one individual component.

If address X is even, then the byte that the HSPI gives for address X is the byte at the address X/2 of device A, and the byte that the HSPI gives for address X + 1 is the byte at the address X/2 of device B. In other words, the bytes at even addresses are all stored in device A and the bytes at odd addresses are all stored in device B.

When reading the status registers of the devices in dual-octal DTR mode, twice as many bytes must be read compared to the same read in regular DTR mode: if each device gives twice eight valid bits after the instruction for fetching the status register, then the HSPI must be configured with a data length of 4 bytes. The LSB is the LSB of device A, and the third byte is the LSB of device B.

If each device gives a status of 16 bits, then the HSPI must be configured to read 4 bytes to get all the status bits of both devices in dual-octal DTR mode. In such case, the order of retrieved status bits is as follows:

• • first byte: LSB of device A
• • second byte: second byte of device A
• • third byte: LSB of device B
• • fourth byte: second byte of device B

In indirect mode using DTR mode, a number of bytes multiple of four must always be accessed in HSPI mode. For this reason, bit 0 and bit 1 of the DL[31:0] bitfield in HSPI_DLR are stuck at 0 when DMODE[2:0] = 101.

In dual-octal configuration, the behavior of device A interface signals is basically the same as in normal mode. Device B interface signals have exactly the same waveforms as device A ones during the instruction, address, alternate-byte, and dummy-cycles phases. In other words, each device always receives the same instruction and the same address.

Then, during the data phase, the AIOx and the BIOx buses both transfer data in parallel, but the data that is sent to (or received from) device A is distinct than the one from device B.

Note: The variable latency is not supported in dual-octal configuration.

HSPI mode

When DMODE[2:0] = 0b101 in HSPI_CCR, the HSPI is in single 16-bit-memory configuration: when DMODE[2:0] = 0b101 with DMM value ignored in that case. A single external HSPI device is used in order to send/receive 16 bits (or 32 bits in DTR mode) every cycle, effectively doubling the throughput.

The device provides/receives two separate DQS signals: DQS0 for the eight LSBs and DQS1 for the eight MSBs.

The HSPI mode can be used in conjunction with the single-SPI, dual-SPI, quad-SPI and octal-SPI modes, as well as with either the SDR or the DTR mode.

The device size, as specified in DEVSIZE[4:0] of HSPI_DCR1, must reflect the total external device capacity.

In SDR mode, a number of bytes multiple of two must always be accessed in HSPI mode. For this reason, bit 0 of DL[31:0] in HSPI_DLR is stuck at 0 when DMODE = 101.

In DTR mode, a number of bytes multiple of four must always be accessed in HSPI mode. For this reason, bit 0 and 1 of DL[31:0] in HSPI_DLR are stuck at 0 when DMODE = 101.

30.4.6 HyperBus protocol

The HSPI can communicate with the external device using the HyperBus protocol.

The HyperBus uses 11 to 12 pins in 8-bit data mode, or 19 to 20 pins in 16-bit data mode depending on the operating voltage:

• • IO[7:0] as bidirectional data bus for 8-bit data mode and IO[15:0] as bidirectional data bus for 16-bit data mode
• • DQS for read and write data strobe and latency insertion
• • NCS
• • CLK
• • NCLK for 1.8 V operations (to support this mode, the device must be powered with 1.8 V)

The HyperBus does not require any command specification nor any alternate bytes. As a consequence, a separate register set is used to define the timing of the transaction.

The HyperBus frame is composed of the following phases:

• • command/address phase
• • data phase

The NCS falls before the start of a transaction and rises again after each transaction finishes.

Figure 173. Example of HyperBus read operation (8-bit data mode)

The specific HyperBus features are configured through the registers in the 0x0200-0x02FC offset range.

Command/address phase

During this initial phase, the HSPI sends 48 bits over IO[7:0] to specify the operations to be performed with the external device.

Table 266. Command/address phase description

The address space is configured through the memory type MTYP[2:0] of HSPI_DCR1.

The total size of the device must be considered through DEVSIZE[4:0] of HSPI_DCR1. In case of multi-chip product (MCP), the device size is the sum of all the sizes of all the MCP dies.

Warning: Some memory specifications consider that each address corresponds to a 16-bit value. The HSPI considers that each address corresponds to an 8-bit value. So, the software needs to multiply the address by two when accessing the memory registers.

Read/write operation with initial latency

The HyperBus read and write operations need to respect two timings:

• • \( t_{RWR} \) : minimal read/write recovery time for the device (defined by TRWR[7:0] in HSPI_HLCR)
• • \( t_{ACC} \) : access time for the device (defined in TACC[7:0] of HSPI_HLCR) according to the memory latency

During the read operation, the DQS0/1 is used by the device, in two ways (see Figure 173 ):

• • during the command/address phase, to request an additional latency
• • during the data phase, for data strobing

During the write operation, the DQS0/1 is used:

• • by the device, during the command/address phase, to request an additional latency.
• • by the HSPI, during the data phase, for write data masking.

Figure 174. HyperBus write operation with initial latency (8-bit data mode)

Read/write operation with additional latency

If the device needs an additional latency (during refresh period of an SDRAM for example), DQS0/1 must be tied to one during one of the DQS signals, during the command/address phase.

An additional \( t_{ACC} \) duration is added by the HSPI to meet the device request.

Figure 175. HyperBus read operation with additional latency (8-bit data mode)

Figure 176. HyperBus write operation with additional latency (8-bit data mode)

Fixed latency mode

Some devices or some applications may not want to operate with a variable latency time as described above.

The latency can be forced to \( 2 \times t_{ACC} \) by setting LM of HSPI_HLCR.

In this HSPI latency mode, the state of the DQS signal is not taken into account by the HSPI and an additional latency is always added leading to a fixed \( 2 \times t_{ACC} \) latency time.

Write operation with no latency

Some devices can also require a zero latency for the write operations. This write-zero latency can be forced by setting WZL in HSPI_HLCR.

Figure 177. HyperBus write operation with no latency (register write)

Latency on page-crossing during the read operations

An additional latency can be needed by some devices for the read operation when crossing pages.

The initial latency must be respected for any page access, as a consequence, when the first access is close to the page boundary, a latency is automatically added at the page crossing to respect the \( t_{ACC} \) time.

Figure 178. HyperBus read operation page crossing with latency (8-bit data mode)

16-bit data transfer using HyperBus

In the HyperBus protocol, the HSPI supports a dual-octal configuration (16-bit data transfers) when DMM = 1 in HSPI_CR. In this configuration, one octal HyperBus memory is connected to IO0-IO7, and another is connected to IO8-IO15, following the same principle as the dual-octal configuration described in the regular command protocol. These memories share all signals except DQS, which are dedicated.

For 16-bit data transfers, DMODE[2:0] must be equal to 101. Any other value in DMODE[2:0] correspond to 8-bit data transfer (quad-, dual-, and single-bit data transfer do not exist in HyperBus protocol). Command-address phase is always using 8 bits in HyperBus protocol (from IO8-IO15). Only the data is on 16-bit for write or read operations accessing the memory space (from IO0-IO15) as shown for instance in Figure 179 . For the memory register accesses, the data is on 8-bit (from IO0 to IO7, IO8 to IO15 being not used but driven by the controller) as shown in Figure 177 .

The behavior of the interface at protocol-level is exactly the same as for HyperBus octal configuration, as described above, except that the variable latency is not supported in dual-octal HyperBus configuration. LM in HSPI_HLCR must be set.

Figure 179. HyperBus write operation with initial latency (16-bit mode)

30.4.7 Specific features

The HSPI supports some specific features, such as:

• • wrap support
• • NCS boundary and refresh

Wrap support

The HSPI supports an hybrid wrap as defined by the HyperBus protocol. A hybrid wrap is also supported in the regular-command protocol.

In hybrid wrap, the transaction can continue after the initial wrap with an incremental access.

The wrap size supported by the target memory is configured by WRAPSIZE in HSPI_DCR2.

Wrap is supported only in memory-read direction and only for data size = 4 bytes. Wrapped reads are supported for both HyperBus and regular-command protocols. To enable wrapped-read accesses, the dedicated registers HSPI_WPxxx must be programmed according to the wrapped-read access characteristics. The dedicated HSPI_WPxxx registers apply for both HyperBus and regular-command protocols.

If the target memory is not supporting the hybrid wrap, WRAPSIZE must be set to 0.

Note: Hybrid wrap requires that the nonwrapped registers (HSPI_CCR, HSPI_TCR, HSPI_IR) are set according to the memory configuration to satisfy its correct data prefetch (initiated after the wrap command).

The wrap operation cannot be interrupted by a refresh. The refresh event is only considered after the wrap completion.

NCS boundary and refresh

Two processes can be activated to regulate the HSPI transactions:

• • NCS boundary
• • refresh

The NCS boundary feature limits a transaction to a boundary of aligned addresses. The size of the address to be aligned with is configured in CSBOUND[4:0] of HSPI_DCR3 and it is equal to \( 2^{\text{CSBOUND}} \) .

As an example, if CSBOUND[4:0] = 0x4, the boundary is set to \( 2^4 = 16 \) bytes. As a consequence, the NCS is released each time that the LSB address is equal to 0xF, and each time that a new transaction is issued to address the next data.

If CSBOUND[4:0] = 0, the feature is disabled. A minimum value of three is recommended.

The NCS boundary feature cannot be used for flash memory devices in write mode since a command is necessary to program another page of the flash memory.

The refresh feature limits the duration of the transactions to the value programmed in REFRESH[31:0] of HSPI_DCR4. The duration is expressed in number of cycles. This allows an external RAM to perform its internal refresh operation regularly.

The refresh value must be greater than the minimal transaction size in terms of number of cycles including the command, address, alternate/dummy phases.

If NCS boundary and refresh are enabled at the same time, the NCS is released on the first condition met.

Restarting after an interrupted transfer

When a read or write operation is interrupted by a timeout, the HSPI interface, as soon as possible after getting back the port ownership, re-issues the initial command sequence together with the address following the last address actually accessed before interruption. The transfer initially set goes on and ends seamlessly.

30.4.8 HSPI operating modes introduction

The HSPI has the following operating modes regardless of the low-level protocol used (either regular-command or HyperBus):

• • indirect mode (read or write)
• • automatic status-polling mode (only in regular-command protocol)
• • memory-mapped mode

30.4.9 HSPI indirect mode

In indirect mode, the commands are started by writing to the HSPI registers, and the data is transferred by writing or reading the data register, in a similar way to other communication peripherals.

When FMODE[1:0] = 00 in HSPI_CR, the HSPI is in indirect-write mode: bytes are sent to the external device during the data phase. Data are provided by writing to HSPI_DR.

When FMODE[1:0] = 01, the HSPI is in indirect-read mode: bytes are received from the external device during the data phase. Data are recovered by reading HSPI_DR.

In indirect mode, when the HSPI is configured in DTR mode over eight lanes with DQS disabled, the given starting address and the data length must be even.

Note: The HSPI_AR register must be updated even if the start address is the same as the start address of the previous indirect access.

The number of bytes to be read/written is specified in HSPI_DLR:

• • If DL[31:0] = 0xFFFF FFFF, the data length is considered undefined and the HSPI simply continues to transfer data until it reaches the end of the external device (as defined by DEVSIZE). If no bytes are to be transferred, DMODE[2:0] must be set to 0 in HSPI_CCR.
• • If DL[31:0] = 0xFFFF FFFF and DEVSIZE[4:0] = 0x1F (its maximum value indicating at 4-Gbyte device), the transfers continue indefinitely, stopping only after an abort request or after the HSPI is disabled. After the last memory address is read (at address 0xFFFF FFFF), reading continues with address = 0x0000 0000.

When the programmed number of bytes to be transmitted or received is reached, TCF bit is set in HSPI_SR and an interrupt is generated if TCIE = 1 in HSPI_CR. In the case of an undefined number of data, TCF is set when the limit of the external SPI memory is reached, according to the device size defined in HSPI_DCR1.

Triggering the start of a transfer in regular-command protocol

Depending on the HSPI configuration, there are three different ways to trigger the start of a transfer in indirect mode when using regular-command protocol. In general, the start of transfer is triggered as soon as the software gives the last information that is necessary for the command. More specifically in indirect mode, a transfer starts when one of the following sequence of events occurs:

• • if no address is necessary (ADMODE[2:0] = 000) and if no data needs to be provided by the software (FMODE[1:0] = 01 or DMODE[2:0] = 000), and at the moment when a write is performed to INSTRUCTION[31:0] in HSPI_IR
• • if an address is necessary (when ADMODE[2:0] ≠ 000) and if no data needs to be provided by the software (when FMODE[1:0] = 01 or DMODE[2:0] = 000), and at the moment when a write is performed to ADDRESS[31:0] in HSPI_AR
• • if data needs to be provided by the software (when FMODE[1:0] = 00 and DMODE[2:0] ≠ 000), and at the moment when a write is performed to DATA[31:0] in HSPI_DR

A write to HSPI_ABR never triggers the communication start. If alternate bytes are required, they must have been programmed before.

As soon as a command is started, the BUSY bit is automatically set in HSPI_SR.

Triggering the start of a transfer in HyperBus protocol

Depending on the HSPI configuration, there are different ways to trigger the start of a command in indirect mode. In general, it is triggered as soon as the firmware gives the last information that is necessary for the transfer to start, and more specifically, a communication in indirect mode is triggered by one of the following register settings, when it is the last one to be executed:

• • when a write is performed to ADDRESS[31:0] (HSPI_AR) with ADMODE[2:0] ≠ 000 in indirect read mode (FMODE[1:0] = 01)
• • when a write is performed to DATA[31:0] (HSPI_DR) in indirect-write mode (when FMODE = 00)
• • when a (dummy) write is performed to INSTRUCTION[31:0] (HSPI_IR) for indirect read mode (with ADMODE[2:0] = 000 and FMODE = 01)

As soon as a transfer is started, the BUSY bit (HSPI_SR[5]) is automatically set.

FIFO and data management

Data in indirect mode pass through a 64-byte FIFO that is internal to the HSPI. FLEVEL in HSPI_SR indicates how many bytes are currently being held in the FIFO.

In indirect-write mode (FMODE[1:0] = 00), the software adds data to the FIFO when it writes in the HSPI_DR. A word write adds 4 bytes to the FIFO, a half-word write adds 2 bytes, and a byte write adds only 1 byte. If the software adds too many bytes to the FIFO (more than indicated in DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation (when TCF is set).

The byte/half-word accesses to the HSPI_DR must be done only to the least significant byte/halfword of the 32-bit register.

FTHRES is used to define a FIFO threshold after which point the FIFO threshold flag, FTF, gets set. In indirect-read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold. FTF is also set if there is any data left in the FIFO after the last byte is read from the external device, regardless of FTHRES setting. In indirect-write mode, the FTF is set when the number of empty bytes in the FIFO is above the threshold.

If FTIE = 1, there is an interrupt when the FTF is set. If DMAEN = 1, a DMA transfer is initiated when the FTF is set. The FTF is cleared by hardware as soon as the threshold condition is no longer true (after enough data has been transferred by the CPU or DMA).

In indirect-read mode, when the FIFO becomes full, the HSPI temporarily stops reading bytes from the external device to avoid an overrun.

The last data read in RX FIFO remains valid as long as there is no request for the next line. This means that, when the application reads several times in a row at the same location, the data is provided from the RX FIFO and not read again from the distant memory.

30.4.10 HSPI automatic status-polling mode

In automatic status-polling mode, the HSPI periodically starts a command to read a defined number of status bytes (up to four). The received bytes can be masked to isolate some status bits and an interrupt can be generated when the selected bits have a defined value.

The automatic status-polling mode must be used only in regular-command protocol. For HyperBus protocol, it is not exploitable since the read status register into the HyperFlash memory must be performed in two steps (a write operation followed by a read operation).

The access to the device begins in the same manner as in indirect-read mode. BUSY in HSPI_SR goes high at this point, and stays high even between the periodic accesses.

The content of MASK[31:0] in HSPI_PSMAR is used to mask the data from the external device in automatic status-polling mode:

• • If the MASK[n] = 0, then bit n of the result is masked and not considered.
• • If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] in HSPI_PSMAR, then there is a match for bit n.

If PMM = 0 in HSPI_CR, the AND-match mode is activated: SMF is set in HSPI_SR only when there is a match on all of the unmasked bits.

If PMM = 1 in HSPI_CR, the OR-match mode is activated: SMF gets set if there is a match on any of the unmasked bits.

An interrupt is called when SMF = 1 if SMIE = 1.

If APMS is set in HSPI_CR, the operation stops and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at 1 and the periodic accesses continue until there is an abort or until the HSPI is disabled (EN = 0).

HSPI_DR contains the latest received status bytes (FIFO deactivated). The content of this register is not affected by the masking used in the matching logic. FTF in HSPI_SR is set as soon as a new reading of the status is complete. FTF is cleared as soon as the data is read.

In automatic status-polling mode, variable latency is not supported. As a consequence, the memory must be configured in fixed latency.

30.4.11 HSPI memory-mapped mode

When configured in memory-mapped mode, the external SPI device is seen as an internal memory.

Note: No more than 256 Mbytes can be addressed even if the external device capacity is larger.

If an access is made to an address outside of the range defined by DEVSIZE[4:0] but still within the 256-Mbyte range, then an AHB error is given. The effect of this error depends on the AHB master that attempted the access:

• • If it is the Cortex CPU, a hard-fault interrupt is generated.
• • If it is a DMA, a DMA transfer error is generated, and the corresponding DMA channel is automatically disabled.

Byte, half-word, and word access types are all supported.

A support for execute in place (XIP) operation is implemented, where the HSPI continues to load the bytes to the addresses following the most recent access. If subsequent accesses are continuous to the bytes that follow, then these operations end up quickly since their results were prefetched.

By default, the HSPI never stops its prefetch operation, it either keeps the previous read operation active with the NCS maintained low or it relaunches a new transfer, even if no access to the external device occurs for a long time.

Since external devices tend to consume more power when the NCS is held low, the application may want to activate the timeout counter (TCEN = 1 in HSPI_CR): the NCS is released after a period defined by TIMEOUT[15:0] in HSPI_LPTR, when x cycles have elapsed without an access since the clock is inactive.

BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is an abort, or the peripheral is disabled.

It is not recommended to program the flash memory using the memory-mapped writes. The indirect-write mode fulfills this operation.

However, if the application requires the use of the MCE for encryption (check MCE product availability), the memory-mapped write mode may be used to program encrypted data to external flash memory under the following conditions:

• • Prefetch must be enabled.
• • In block cipher mode, the CPU must write a complete 128-bit data block to prevent the MCE from initiating read-modify-write operations when only a few bytes need to be

programmed. This precaution avoids incorrect programming operations. There are no specific constraints to respect if the MCE is used in stream cipher mode.

• • Apply the abort sequence to exit memory-mapped mode when the data linked to the page has been written in the external memory buffers. The abort sequence triggers the start of the page programming.
• • Switch to the automatic status-polling mode to monitor the completion of the page programming phase.
• • Relaunch the write enable command in indirect mode, then switch back to the memory-mapped mode configuration to continue to program additional pages if any.

It is recommended to add a synchronization barrier between the end of the controller registers configuration and the first memory-mapped access to the external memory when the controller is configured in memory-mapped mode.

30.4.12 HSPI configuration introduction

The HSPI configuration is done in three steps:

1. 1. HSPI system configuration
2. 2. HSPI device configuration
3. 3. HSPI mode configuration

30.4.13 HSPI system configuration

The HSPI is configured using HSPI_CR. The user must program:

• • the functional mode with FMODE[1:0]
• • the automatic status-polling mode behavior if needed with PMM and APMS
• • the FIFO level with FTHRES
• • DMA use with DMAEN
• • the timeout counter use with TCEN
• • the dual-memory configuration, if needed, with DMM

In case of an interrupt use, the respective enable bit can also be set during this phase.

If the timeout counter is used, the timeout value is programmed in HSPI_LPTR.

The DMA channel must not be enabled during the HSPI configuration: it must be enabled only when the operation is fully configured, to avoid any unexpected request generation.

The DMA and HSPI must be configured in a coherent manner regarding data length: FTHRES value must reflect the DMA burst size.

30.4.14 HSPI device configuration

The parameters related to the external device targeted are configured through HSPI_DCR1 and HSPI_DCR2. The user must program:

• • the device size with DEVSIZE[4:0]
• • the chip-select minimum high time with CSHT[5:0]
• • the device frequency with PRESCALER[7:0]

DEVSIZE[4:0] defines the size of external memory using the following formula:

where DEVSIZE+1 is the number of address bits required to address the external device. The external device capacity can go up to 4 Gbytes (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes.

If DMM = 1, DEVSIZE[4:0] must reflect the total capacity of the two devices together considering the above formula (DEVSIZE[4:0] value is so equal to one of the two memory capacities).

When the HSPI executes two commands, one immediately after the other, it raises the NCS high between the two commands, at least one CLK cycle by default.

If the external device requires more time between commands, CSHT[5:0] can be used to specify the minimum number of CLK cycles (up to 64) for which the NCS must remain high.

CKMODE indicates the level that the CLK takes between commands (when NCS = 1).

In HyperBus protocol, the device timing ( \( t_{ACC} \) and \( t_{RWR} \) ) and the Latency mode must be configured in HSPI_HLCR.

Memory types

External memory providers may have architecture and slight data formatting differences. The bitfield MTYP[2:0] into the HSPI_CR register allows targeting the right controller configuration depending on the associated memory type selected in the application. It is the responsibility of the software developer to align the controller configuration to fit with the targeted memory type.

The memory types are grouped in this way:

• • D0/D1 data ordering in octal-SPI data mode (DMODE[2:0] = 100) in DTR mode by configuring MTYP[2:0] = 000. For instance, Micron is using such data ordering. In this configuration, the DQS is sent with a polarity inverted respect to the clock polarity.

Figure 180. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access

• • D1/D0 data ordering in octal-SPI data mode (DMODE[2:0] = 100) in DTR mode by configuring MTYP[2:0] = 001. For instance, Macronix is using this reverse data ordering in its Octaflash portfolio (this configuration is not adapted to its OctaRAM™ memories). DQS is keeping the same polarity as the clock when reading data from the memory. Refer to Figure 170: DTR read in octal-SPI mode with DQS (Macronix mode) example .
• • D1/D0 data ordering in octal-SPI data mode (DMODE[2:0] = 100) in DTR mode by configuring MTYP[2:0] = 011 with specific address phase built with row and column to fit with Macronix OctaRAM™ memories requirement (refer to Table 267: OctaRAM )

command address bit assignment (based on 64 Mb OctaRAM) . This is the controller which translates internally the targeted address provided by the software in row/column address formatting to sent to the memory. DQS is keeping the same polarity as the clock when reading data from the memory.

Figure 181. OctaRAM read operation with reverse data ordering D1/D0

Table 267. OctaRAM command address bit assignment
(based on 64 Mb ⁽¹⁾ OctaRAM)

1. Example of 64 Mb OctaRAM address assignment:
Row Address [RA12:RA0]: 8K. Column address [CA9:CA0]: 1K. 64 Mb density = 8K x 1K x 8 bits

2. Column address A0 must be always 0.

• HyperBus memories need to be selected when targeted by the application. The configuration to set depends on the access type:
  • HyperBus memory mode: The protocol follows the HyperBus specification. MTYP[2:0] = 100 is the configuration to use to access the memory space.
  • HyperBus register mode (addressing register space): the memory-mapped accesses in this mode must be noncacheable, or the indirect read/write modes

must be used. The configuration to be set for this particular register space access is MTYP[2:0] = 101.

• • The software must configure MTYP[2:0] = 110 when the memory targeted comes from APmemory and DMODE[2:0] = 101 to fit with the memory provider requirements concerning the address formatting.
• • Standard mode. It is the mode to use whenever the targeted memory is not corresponding to any others configurations described in this section. MTYP[2:0] = 010 for this standard mode.

30.4.15 HSPI regular-command mode configuration

Indirect mode configuration

When FMODE[1:0] = 00, the indirect-write mode is selected and data can be sent to the external device. When FMODE[1:0] = 01, the indirect-read mode is selected and data can be read from the external device.

When the HSPI is used in indirect mode, the frames are constructed in the following way:

1. 1. Specify a number of data bytes to read or write in HSPI_DLR.
2. 2. Specify the frame timing in HSPI_TCR.
3. 3. Specify the frame format in HSPI_CCR.
4. 4. Specify the instruction in HSPI_IR.
5. 5. Specify the optional alternate byte to be sent right after the address phase in HSPI_ABR.
6. 6. Specify the targeted address in HSPI_AR.
7. 7. Enable the DMA channel if needed.
8. 8. Read/write the data from/to the FIFO through HSPI_DR (if no DMA usage).

If neither the address register (HSPI_AR) nor the data register (HSPI_DR) need to be updated for a particular command, then the command sequence starts as soon as HSPI_IR is written. This is the case when both ADMODE[2:0] and DMODE[2:0] equal 000, or if just ADMODE[2:0] = 000 when in indirect-read mode (FMODE[1:0] = 01).

When an address is required (ADMODE[2:0] ≠ 000) and the data register does not need to be written (FMODE[1:0] = 01 or DMODE[2:0] = 000), the command sequence starts as soon as the address is updated with a write to HSPI_AR.

In case of data transmission (FMODE[1:0] = 00 and DMODE[2:0] ≠ 000), the communication start is triggered by a write in the FIFO through HSPI_DR.

Automatic status-polling mode configuration

The automatic status-polling mode is enabled by setting FMODE[1:0] = 10. In this mode, the programmed frame is sent and the data is retrieved periodically.

The maximum amount of data read in each frame is 4 bytes. If more data is requested in HSPI_DLR, it is ignored, and only 4 bytes are read. The periodicity is specified in HSPI_PIR.

Once the status data has been retrieved, the following can be processed:

• • Set SMF (an interrupt is generated if enabled).
• • Stop automatically the periodic retrieving of the status bytes.

The received value can be masked with the value stored in HSPI_PSMKR, and can be ORed or ANDed with the value stored in HSPI_PSMAR.

In case of a match, SMF is set and an interrupt is generated if enabled. The HSPI can be automatically stopped if AMPS is set. In any case, the latest retrieved value is available in HSPI_DR.

When the HSPI is used in automatic status-polling mode, the frames are constructed in the following way:

1. 1. Specify the input mask in HSPI_PSMKR.
2. 2. Specify the comparison value in HSPI_PSMAR.
3. 3. Specify the read period in HSPI_PIR.
4. 4. Specify a number of data bytes to read in HSPI_DLR.
5. 5. Specify the frame timing in HSPI_TCR.
6. 6. Specify the frame format in HSPI_CCR.
7. 7. Specify the instruction in HSPI_IR.
8. 8. Specify the optional alternate byte to be sent right after the address phase in HSPI_ABR.
9. 9. Specify the optional targeted address in HSPI_AR.

If the address register (HSPI_AR) does not need to be updated for a particular command, then the command sequence starts as soon as HSPI_CCR is written. This is the case when ADMODE[2:0] = 000.

When an address is required (ADMODE[2:0] ≠ 000), the command sequence starts as soon as the address is updated with a write to HSPI_AR.

Memory-mapped mode configuration

In memory-mapped mode, the external device is seen as an internal memory but with some latency during accesses. Read and write operations are allowed to the external device in this mode.

It is not recommended to program the flash memory using memory-mapped writes, as the internal flags for erase or programming status have to be polled. The indirect-write mode fulfills this operation, possibly in conjunction with the automatic status-polling mode.

Memory-mapped mode is entered by setting FMODE[1:0] = 11 in HSPI_CR.

The programmed instruction and frame are sent when an AHB master accesses the memory mapped space.

The FIFO is used as a prefetch buffer to anticipate any linear reads. Any access to HSPI_DR in this mode returns zero.

The data length register (HSPI_DLR) has no meaning in memory-mapped mode.

When the HSPI is used in memory-mapped mode, the frames are constructed in the following way:

1. 1. Specify the frame timing in HSPI_TCR for read operation.
2. 2. Specify the frame format in HSPI_CCR for read operation.
3. 3. Specify the instruction in HSPI_IR.
4. 4. Specify the optional alternate byte to be sent right after the address phase in HSPI_ABR for read operation.

1. 5. Specify the frame timing in HSPI_WTCR for write operation.
2. 6. Specify the frame format in HSPI_WCCR for write operation.
3. 7. Specify the instruction in HSPI_WIR.
4. 8. Specify the optional alternate byte to be sent right after the address phase in HSPI_WABR for write operation.

All the configuration operations must be completed (ensured by checking BUSY = 0) before the first access to the memory area: any register write operation when BUSY = 1 have no effect and is not signaled with an error response. On the first access, the HSPI becomes busy, and no further configuration is allowed. Then, the only way to get BUSY low is to clear the ENABLE bit or to abort by setting the ABORT bit.

HSPI delayed data sampling when no DQS is used

By default, when no DQS is used, the HSPI samples the data driven by the external device one half of a CLK cycle after the external device drives the signal.

In case of any external signal delays, it may be useful to sample the data later. Using SSHIFT in HSPI_TCR, the sampling of the data can be shifted by half of a CLK cycle.

The firmware must clear SSHIFT when the data phase is configured in DTR mode (DDTR = 1).

HSPI delayed data sampling when DQS is used

When external DQS is used as a sampling clock, it is shifted precisely by one quarter of the SPI clock cycle, for all frequencies above freq_min, to compensate the data propagation delay in the “high-speed interface” when the product embeds one.

30.4.16 HSPI HyperBus protocol configuration

Indirect mode configuration (HyperBus)

When FMODE[1:0] = 00, the indirect-write mode is selected and data can be sent to the external device. When FMODE[1:0] = 01, the indirect-read mode is selected where data can be read from the external device. ADMODE must be configured with a value different from 000 (for instance ADMODE = 100).

When the HSPI is used in indirect mode, the frames are constructed in the following way:

1. 1. Specify a number of data bytes to read or write in HSPI_DLR.
2. 2. Specify the targeted address in HSPI_AR.
3. 3. Enable the DMA channel if needed.
4. 4. Read/write the data from/to the FIFO through HSPI_DR (if no DMA usage).

In indirect-read mode, the command sequence starts as soon as the address is updated with a write to HSPI_AR.

In indirect-write mode, the communication start is triggered by a write in the FIFO through HSPI_DR.

Memory-mapped mode configuration (HyperBus)

In memory-mapped mode, the external device is seen as an internal memory but with some latency during the accesses. Read and write operations are allowed to the external device in this mode.

It is not recommended to program the flash memory using the memory-mapped writes: the indirect-write mode fulfills this operation.

The memory-mapped mode is entered by setting FMODE[1:0] = 11. The programmed instruction and frame is sent when an AHB master is accessing the memory mapped space.

The FIFO is used as a prefetch buffer to anticipate any linear reads. Any access to HSPI_DR in this mode returns zero.

The data length register (HSPI_DLR) has no meaning in memory-mapped mode.

All the configuration operation must be completed before the first access to the memory area. On the first access, the HSPI becomes busy, and no configuration is allowed. Then, the only way to get BUSY low is to clear the ENABLE bit or to abort by setting the ABORT bit.

30.4.17 HSPI error management

The following errors set the TEF flag in HSPI_SR and generates an interrupt if enabled (TEIE = 1 in HSPI_CR):

• • in indirect or automatic status-polling mode, when a wrong address has been programmed in HSPI_AR (according to the device size defined by DEVSIZE[4:0]).
• • in indirect mode, if the address plus the data length exceed the device size. TEF is set as soon as the access is triggered.

In memory-mapped mode, the HSPI generates an AHB slave error in the following situations:

• • The memory-mapped mode is disabled and an AHB read or write request occurs.
• • Read or write address exceeds the size of the external memory.
• • Abort is received while a read or write burst is ongoing when the abort condition is present at the moment of transfer phases preceding the data phase (In incremental or wrap burst type modes). To avoid the error, refer to Section 30.4.19: HSPI BUSY and ABORT .
• • The HSPI is disabled while a read or write burst is requested.
• • A write wrap burst is received.
• • A write request is received while DQSE = 0 in HSPI_WCCR in octal DTR mode, in dual-memory configuration, in hyperbus mode or 16-bit mode.
• • A read or write request is received while DMODE[2:0] = 000 (no data phase), except when MTYP[2:0] is HyperBus.
• • Illegal access size when wrap read burst. This means AHB Bus transfer size (HSIZE) is different from 4 bytes (only for memory-mapped mode).
• • Bit DMM is set in HSPI_CR (dual-memory configuration) and 16-bit mode is set.

30.4.18 HSPI high-speed interface and calibration

To reach higher frequencies, a dedicated high-speed interface is inserted between the HSPI (or the I/O manager in case the product embeds one), and the I/O pads.

The following is valid for all data bus sizes 1, 2, 4, 8 or 16 bits.

The high-speed interface block embeds resynchronization registers that are clocked by a delayed clock created from a DLL (delay locked loop) also located in the high-speed interface. The high-speed interface features are controlled by registers located in the HSPI.

The purpose of resynchronization is primary to shift data or data strobe by one quarter of controller bus clock period, with a correct timing accuracy. DLL must be calibrated versus this clock period.

The calibration process is automatically enabled when one of the three conditions below is met:

• • The HSPI exits reset state.
• • A value is written in PRESCALER[7:0] of HSPI_DCR2.
• • A value is written in HSPI_CCR.

The calibration process starts when the two following conditions are both met:

• • The calibration has been enabled by one of the three conditions above.
• • An action that sets BUSY = 1 is performed. For example the first transfer to memory after calibration is enabled. When the calibration is completed, BUSY returns to 0.

In case a periodic recalibration is needed (for example to take in account possible variations in temperature or power supply on a long duration), this recalibration must be triggered by writing periodically in PRESCALER[7:0] of HSPI_DCR2, while BUSY = 0.

Once the calibration is completed, the value of the SPI bus clock period, expressed in number of unitary delay, is available to user in COARSE[5:0] and FINE[6:0] of HSPI_CALFCR.

After auto-calibration, HSPI_CALSOR and HSPI_CALSIR are automatically loaded with the same value that corresponds to the delay for a quarter cycle.

The automatic calibration is not executed if at least one of both registers HSPI_CALSOR/HSPI_CALSIR is written between the last write operation on HSPI_DCR2 or HSPI_CCR and the next transfer start. In such case, the calibration values must be set by the software code into HSPI_CALSOR and HSPI_CALSIR registers. It may improve the flash programming time without relaunching the automatic calibration processing between two programming pages.

When the memory is not supporting DQS (DQSE = 0), the automatic calibration is not used in reception. The DLL Master is used instead for delaying the feedback clock (HSPI_CALMR). This delay needs to be adjusted by the application itself, using a software sequence that determines which delay is optimal to guarantee the correct read operations.

When the clock is divided in DTR transmission mode, the quarter cycle delays on DQS/data are not inserted by the DLLs themselves, but by internal flops design scheme. In SDR transmission mode, the DLLs are not used and this, whatever the clock prescaler value.

In case of DTR mode and prescaler bypassed (PRESCALER[7:0] = 0), the kernel clock provided to interface must have a 50 % duty-cycle.

When using the high-speed-interface, the system clock (AHB clock) must be at least as fast as the SPI clock.

30.4.19 HSPI BUSY and ABORT

Once the HSPI starts an operation with the external device, BUSY is automatically set in HSPI_SR.

In indirect mode, BUSY is reset once the HSPI has completed the requested command sequence and the FIFO is empty.

In automatic status-polling mode, BUSY goes low only after the last periodic access is complete, due to a match when APMS = 1 or due to an abort.

After the first access in memory-mapped mode, BUSY goes low only on an abort.

Any operation can be aborted by setting ABORT in HSPI_CR. Once the abort is completed, BUSY and ABORT are automatically reset, and the FIFO is flushed.

Before setting ABORT, the software must ensure that all the current transactions are finished using the synchronization barriers. When DMA is enabled to handle the data read or write operations in HSPI_DR, it is recommended to disable the DMA channel before aborting the HSPI.

Note: Some devices may misbehave if a write operation to a status register is aborted.

30.4.20 HSPI reconfiguration or deactivation

Before any HSPI reconfiguration, the software must ensure that all the transactions are completed:

• • After a memory-mapped write, the software must perform a dummy read followed by a synchronization barrier, then an abort.
• • After a memory-mapped read, the software must perform a synchronization barrier then an abort.

30.4.21 NCS behavior

By default, NCS is high, deselecting the external device. NCS falls before an operation begins and rises as soon as it finishes.

When CKMODE = 0 (clock mode 0: CLK stays low when no operation is in progress), NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation final rising CLK edge (see the figure below).

Figure 182. NCS when CKMODE = 0 (T = CLK period)

When CKMODE = 1 (clock mode 3: CLK goes high when no operation is in progress) and when in SDR mode, NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation final rising CLK edge (see the figure below).

Figure 183. NCS when CKMODE = 1 in SDR mode (T = CLK period)

When the CKMODE = 1 (clock mode 3) and DDTR = 1 (data DTR mode), NCS falls one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the operation final active rising CLK edge (see the figure below). Because the DTR operations must finish with a falling edge, the CLK is low when NCS rises, and CLK rises back up one half of a CLK cycle afterwards.

Figure 184. NCS when CKMODE = 1 in DTR mode (T = CLK period)

When the FIFO stays full during a read operation, or if the FIFO stays empty during a write operation, the operation stalls and CLK stays low until the software services the FIFO. If an abort occurs when an operation is stalled, NCS rises just after the abort is requested and then CLK rises one half of a CLK cycle later (see the figure below).

Figure 185. NCS when CKMODE = 1 with an abort (T = CLK period)

30.5 Address alignment and data number

The following table summarizes the effect of the address alignment and programmed data number depending on the use case.

Table 268. Address alignment cases

Table 268. Address alignment cases (continued)

1. 1. To be respected by the software.
2. 2. IND = indirect mode.
3. 3. MM = memory-mapped mode.
4. 4. Extra data at transfer start.
5. 5. Extra data at transfer end.
6. 6. WDM = write data mask.
7. 7. If the FTHRES bitfield is set to the maximum value with DLR value greater than the data burst length, and if the DMA is enabled or the interrupt based on FIFO THRESHOLD Flag is enabled (FTF), the address must be modulo 2 aligned in DTR mode when the initiator (DMA, CPU, ...) is writing the data with a burst length equal to the FIFO size.
8. 8. If the FTHRES bitfield is set to the maximum value with DLR value greater than the data burst length, and if the DMA is enabled or the interrupt based on FIFO THRESHOLD Flag is enabled (FTF), the address must be modulo 4 aligned in DTR mode or modulo 2 in SDR mode when the initiator (DMA, CPU, ...) is writing the data with a burst length equal to the FIFO size.
9. 9. If the FTHRES bitfield is set to the maximum value with DLR value greater than the data burst length, and if the DMA is enabled or the interrupt based on FIFO THRESHOLD Flag is enabled (FTF), the address must be modulo 4 aligned in DTR mode when the initiator (DMA, CPU, ...) is writing the data with a burst length equal to the FIFO size.

30.6 HSPI interrupts

An interrupt can be produced on the following events:

• • timeout
• • status match
• • FIFO threshold
• • transfer complete
• • transfer error

Separate interrupt enable bits are available to provide more flexibility.

Table 269. HSPI interrupt requests

Table 269. HSPI interrupt requests

30.7 HSPI registers

30.7.1 HSPI control register (HSPI_CR)

Address offset: 0x000

Reset value: 0x0000 0000

Bits 31:30 MSEL[1:0] : Flash select

These bits select the memory to be addressed in single-, dual-, quad-, or octal-SPI mode in single-memory configuration (when DMM = 0).

- when in quad-SPI mode:

00: Data exchanged over IO[3:0]

01: Data exchanged over IO[7:4]

10: Data exchanged over IO[11:8]

11: Data exchanged over IO[15:12]

- when in octal-SPI mode or dual-quad configuration:

0x: Data exchanged over IO[7:0]

1x: Data exchanged over IO[15:8]

These bits are ignored when in dual-octal configuration (data on 8 bits and DMM = 1) or 16-bit configuration (data exchanged over IO[15:0]).

Note: Bit 30 is mirrored in bit 7. This bitfield can be modified only when BUSY = 0.

Bits 29:28 FMODE[1:0] : Functional mode

This bitfield defines the HSPI functional mode of operation.

00: Indirect-write mode

01: Indirect-read mode

10: Automatic status-polling mode (relevant in regular-command protocol only)

11: Memory-mapped mode

If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value.

Note: This bitfield can be modified only when BUSY = 0.

Bits 27:24 Reserved, must be kept at reset value.

This bit indicates which method must be used to determine a match during the automatic status-polling mode.

0: AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register.

1: OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register.

Note: This bit can be modified only when BUSY = 0.

This bit determines if the automatic status-polling mode is stopped after a match.

0: Automatic status-polling mode is stopped only by abort or by disabling the HSPI.

1: Automatic status-polling mode stops as soon as there is a match.

Note: This bit can be modified only when BUSY = 0.

This bit enables the timeout interrupt.

0: Interrupt disabled

1: Interrupt enabled

This bit enables the status match interrupt.

0: Interrupt disabled

1: Interrupt enabled

This bit enables the FIFO threshold interrupt.

0: Interrupt disabled

1: Interrupt enabled

This bit enables the transfer complete interrupt.

0: Interrupt disabled

1: Interrupt enabled

This bit enables the transfer error interrupt.

0: Interrupt disabled

1: Interrupt enabled

This bitfield defines, in indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in HSPI_SR, to be set.

000000: FTF is set if there are one or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in indirect-read mode.

000001: FTF is set if there are two or more free bytes available to be written to in the FIFO in indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in indirect-read mode.

...

111111: FTF is set if there are 64 free bytes available to be written to in the FIFO in indirect-write mode, or if there are 64 valid bytes can be read from the FIFO in indirect-read mode.

Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value.

Bit 7 Reserved, must be kept at reset value.

This bit activates the dual-memory configuration, where two external devices are used simultaneously to double the throughput and the capacity.

0: Dual-memory configuration disabled

1: Dual-memory configuration enabled

Note: This bit can be modified only when BUSY = 0.

Bits 5:4 Reserved, must be kept at reset value.

This bit is valid only when the memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter.

0: The timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in memory-mapped mode.

1: The timeout counter is enabled, and thus the chip-select is released in the memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity.

Note: This bit can be modified only when BUSY = 0.

In indirect mode, the DMA can be used to input or output data via HSPI_DR. DMA transfers are initiated when FTF is set.

0: DMA disabled for indirect mode

1: DMA enabled for indirect mode

Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation.

This bit aborts the ongoing command sequence. This bit stops the current transfer.

0: No abort requested

1: Abort requested

Note: This bit is always read as 0.

Bit 0 EN : Enable

This bit enables the HSPI.

0: HSPI disabled

1: HSPI enabled

Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active.

30.7.2 HSPI device configuration register 1 (HSPI_DCR1)

Address offset: 0x008

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 MTYP[2:0] : Memory type

This bitfield indicates the type of memory to be supported.

000: Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes. In this mode, DQS signal polarity is inverted with respect to the memory clock signal. This is the default value and care must be taken to change MTYP[2:0] for memories different from Micron.

001: Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes.

010: Standard mode

011: Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping (address is built with row and column to fit with Macronix requirements).

100: HyperBus memory mode, the protocol follows the HyperBus specification.

101: HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be noncacheable, or indirect read/write modes must be used.

110: APmemory mode. If DMODE = 101, there is a special hardware operation on address word from the bit 10 and above to fit the provider requirement (shift operation on the left from the address bit 10, keeping this last at 0).

Others: Reserved

Bits 23:21 Reserved, must be kept at reset value.

Bits 20:16 DEVSIZE[4:0] : Device size

This bitfield defines the size of the external device using the following formula:
Number of bytes in device = \( 2^{[\text{DEVSIZE}+1]} \) .
DEVSIZE + 1 is effectively the number of address bits required to address the external device. The device capacity can be up to 4 Gbytes (addressed using 32-bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256 Mbytes.
In regular-command protocol, if DMM = 1, DEVSIZE[4:0] must reflect the total capacity of the two devices together considering the above formula (DEVSIZE[4:0] value is so equal to one of the two memory capacities).

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:8 CSHT[5:0] : Chip-select high time

CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must remain high between commands issued to the external device.
0x0: NCS stays high for at least 1 cycle between external device commands.
0x1: NCS stays high for at least 2 cycles between external device commands.
...
0x3F: NCS stays high for at least 64 cycles between external device commands.

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 FRCK : Free running clock

This bit configures the free running clock.
0: CLK is not free running.
1: CLK is free running (always provided).

Note: Once the bit has been set to 1, the BSY bit is set, the NCS signal remains set to 1 and the clock is sent. The only way to stop the clock is to perform an abort (which clears the BSY bit). Then, the FRCK bit must be cleared by software to allow controller transactions to take place with the external memory.

Bit 0 CKMODE : Clock mode 0/mode 3

This bit indicates the level taken by the CLK between commands (when NCS = 1).
0: CLK must stay low while NCS is high (chip-select released), referred to as clock mode 0.
1: CLK must stay high while NCS is high (chip-select released), referred to as clock mode 3.

30.7.3 HSPI device configuration register 2 (HSPI_DCR2)

Address offset: 0x00C

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 WRAPSIZE[2:0] : Wrap size

This bitfield indicates the wrap size to which the memory is configured. For memories, which have a separate command for wrapped instructions, this bitfield indicates the wrap-size associated with the command held in HSPI_WPIR.

000: Wrapped reads are not supported by the memory.
010: External memory supports wrap size of 16 bytes.
011: External memory supports wrap size of 32 bytes.
100: External memory supports wrap size of 64 bytes.
101: External memory supports wrap size of 128 bytes.
Others: Reserved

Bits 15:8 Reserved, must be kept at reset value.

Bits 7:0 PRESCALER[7:0] : Clock prescaler

This bitfield defines the scaler factor for generating the CLK based on the kernel clock (value + 1).

0: \( F_{CLK} = F_{KERNEL} \) , kernel clock used directly as HSPI CLK (prescaler bypassed). In this case, if the DTR mode is used, it is mandatory to provide to the HSPI a kernel clock that has 50% duty-cycle.

1: \( F_{CLK} = F_{KERNEL}/2 \)

2: \( F_{CLK} = F_{KERNEL}/3 \)

...

255: \( F_{CLK} = F_{KERNEL}/256 \)

For odd clock division factors, the CLK duty cycle is not 50%. The clock signal remains low one cycle longer than it stays high.

Writing this bitfield automatically starts a new calibration of high-speed interface DLL at the start of next transfer, except in case HSPI_CALSOR or HSPI_CALSIR have been written in the meantime. BUSY stays high during the whole calibration execution.

30.7.4 HSPI device configuration register 3 (HSPI_DCR3)

Address offset: 0x010

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 CSBOUND[4:0] : NCS boundary

This bitfield enables the transaction boundary feature. When active, a minimum value of three is recommended.

The NCS is released on each boundary of \( 2^{CSBOUND} \) bytes.

0: NCS boundary disabled

Others: NCS boundary set to \( 2^{CSBOUND} \) bytes

Bits 15:0 Reserved, must be kept at reset value.

30.7.5 HSPI device configuration register 4 (HSPI_DCR4)

Address offset: 0x014

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 REFRESH[31:0] : Refresh rate

This bitfield enables the refresh rate feature. The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock cycles for reads. These two values can be extended with few clock cycles when refresh occurs during a byte transmission in single-, dual-, or quad-SPI mode, because the byte transmission must be completed.

0: Refresh disabled

Others: Maximum communication length is set to REFRESH + 1 clock cycles.

30.7.6 HSPI status register (HSPI_SR)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:8 FLEVEL[6:0] : FIFO level

This bitfield gives the number of valid bytes that are being held in the FIFO.FLEVEL = 0 when the FIFO is empty, and 64 when it is full. In automatic-status polling mode, FLEVEL is zero.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 BUSY : Busy

This bit is set when an operation is ongoing. It is cleared automatically when the operation with the external device is finished and the FIFO is empty.

Bit 4 TOF : Timeout flag

This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.

Bit 3 SMF : Status match flag

This bit is set in automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (HSPI_PSMAR).

It is cleared by writing 1 to CSMF.

Bit 2 FTF : FIFO threshold flag

In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete.

It is cleared automatically as soon as the threshold condition is no longer true.

In automatic status-polling mode this bit is set every time the status register is read, and the bit is cleared when the data register is read.

Bit 1 TCF : Transfer complete flag

This bit is set in indirect mode when the programmed number of data has been transferred or in any mode when the transfer has been aborted. It is cleared by writing 1 to CTCF.

Bit 0 TEF : Transfer error flag

This bit is set in indirect mode when an invalid address is being accessed in indirect mode. It is cleared by writing 1 to CTEF.

30.7.7 HSPI flag clear register (HSPI_FCR)

Address offset: 0x024

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF : Clear timeout flag

Writing 1 clears the TOF flag in the HSPI_SR register.

Bit 3 CSMF : Clear status match flag

Writing 1 clears the SMF flag in the HSPI_SR register.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CTCF : Clear transfer complete flag

Writing 1 clears the TCF flag in the HSPI_SR register.

Bit 0 CTEF : Clear transfer error flag

Writing 1 clears the TEF flag in the HSPI_SR register.

30.7.8 HSPI data length register (HSPI_DLR)

Address offset: 0x040

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 DL[31:0] : Data length

Number of data to be retrieved (value + 1) in indirect and automatic status-polling modes.

A value not greater than three (indicating 4 bytes) must be used for automatic status-polling mode.

All 1's in indirect mode means undefined length, where HSPI continues until the end of the memory, as defined by DEVSIZE.

0x0000_0000: 1 byte is to be transferred.

0x0000_0001: 2 bytes are to be transferred.

0x0000_0002: 3 bytes are to be transferred.

0x0000_0003: 4 bytes are to be transferred.

...

0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred.

0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred.

0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F.

DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to this bit, thus assuring that each access transfers an even number of bytes.

This bitfield has no effect when in memory-mapped mode.

30.7.9 HSPI address register (HSPI_AR)

Address offset: 0x048

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0 and FMODE ≠ 11.

Bits 31:0 ADDRESS[31:0] : Address

Address to be sent to the external device. In HyperBus protocol, this bitfield must be even as this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 0.

Caution: Some memory specifications consider that each address corresponds to a 16-bit value. HSPI considers that each address corresponds to an 8-bit value. So the software needs to multiply the address by two when accessing the memory registers.

30.7.10 HSPI data register (HSPI_DR)

Address offset: 0x050

Reset value: 0x0000 0000

Bits 31:0 DATA[31:0] : Data

Data to be sent/received to/from the external SPI device

In indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase. If the FIFO is too full, a write operation is stalled until the FIFO has enough space to accept the amount of data being written.

In indirect-read mode, reading this register gives (via the FIFO) the data that was received from the external device. If the FIFO does not have as many bytes as requested by the read operation and if BUSY = 1, the read operation is stalled until enough data is present or until the transfer is complete, whichever happens first.

In automatic status-polling mode, this register contains the last data read from the external device (without masking).

Word, half-word, and byte accesses to this register are supported. In indirect-write mode, a byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes.

Similarly, in indirect-read mode, a byte read removes 1 byte from the FIFO, a half-word read 2 bytes, and a word read 4 bytes. Accesses in indirect mode must be aligned to the bottom of this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0].

30.7.11 HSPI polling status mask register (HSPI_PSMKR)

Address offset: 0x080

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 MASK[31:0] : Status mask

Mask to be applied to the status bytes received in automatic status-polling mode

For bit n:

0: Bit n of the data received in automatic status-polling mode is masked and its value is not considered in the matching logic.

1: Bit n of the data received in automatic status-polling mode is unmasked and its value is considered in the matching logic.

30.7.12 HSPI polling status match register (HSPI_PSMAR)

Address offset: 0x088

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 MATCH[31:0] : Status match

Value to be compared with the masked status register to get a match

30.7.13 HSPI polling interval register (HSPI_PIR)

Address offset: 0x090

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 INTERVAL[15:0] : Polling interval

Number of CLK cycles between a read during the automatic status-polling phases

30.7.14 HSPI communication configuration register (HSPI_CCR)

Address offset: 0x100

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DQSE : DQS enable

This bit enables the data strobe management.

0: DQS disabled

1: DQS enabled

Bit 28 Reserved, must be kept at reset value.

Bit 27 DDTR : Data double transfer rate

This bit sets the DTR mode for the data phase.

0: DTR mode disabled for the data phase

1: DTR mode enabled for the data phase

Bits 26:24 DMODE[2:0] : Data mode

This bitfield defines the data phase mode of operation.

000: No data

001: Data on a single line

010: Data on two lines

011: Data on four lines

100: Data on eight lines

101: Data on 16 lines

Others: Reserved

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:20 ABSIZE[1:0] : Alternate-byte size

This bitfield defines the alternate-byte size.

00: 8-bit alternate bytes

01: 16-bit alternate bytes

10: 24-bit alternate bytes

11: 32-bit alternate bytes

Bit 19 ABDTR : Alternate-byte double transfer rate

This bit sets the DTR mode for the alternate-byte phase.

0: DTR mode disabled for the alternate-byte phase

1: DTR mode enabled for the alternate-byte phase

Bits 18:16 ABMODE[2:0] : Alternate-byte mode

This bitfield defines the alternate-byte phase mode of operation.

000: No alternate bytes

001: Alternate bytes on a single line

010: Alternate bytes on two lines

011: Alternate bytes on four lines

100: Alternate bytes on eight lines

Others: Reserved

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:12 ADSIZE[1:0] : Address size

This bitfield defines the address size.

00: 8-bit address

01: 16-bit address

10: 24-bit address

11: 32-bit address

Bit 11 ADDTR : Address double transfer rate

This bit sets the DTR mode for the address phase.

0: DTR mode disabled for the address phase

1: DTR mode enabled for the address phase

Bits 10:8 ADMODE[2:0] : Address mode

This bitfield defines the address phase mode of operation.

000: No address

001: Address on a single line

010: Address on two lines

011: Address on four lines

100: Address on eight lines

Others: Reserved

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 ISIZE[1:0] : Instruction size

This bitfield defines the instruction size.

00: 8-bit instruction

01: 16-bit instruction

10: 24-bit instruction

11: 32-bit instruction

Bit 3 IDTR : Instruction double transfer rate

This bit sets the DTR mode for the instruction phase.

0: DTR mode disabled for the instruction phase

1: DTR mode enabled for the instruction phase

Bits 2:0 IMODE[2:0] : Instruction mode

This bitfield defines the instruction phase mode of operation.

000: No instruction

001: Instruction on a single line

010: Instruction on two lines

011: Instruction on four lines

100: Instruction on eight lines

Others: Reserved

30.7.15 HSPI timing configuration register (HSPI_TCR)

Address offset: 0x108

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bit 31 Reserved, must be kept at reset value.

Bit 30 SSHIFT : Sample shift

By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device.

This bit allows the data to be sampled later in order to consider the external signal delays.

0: No shift

1: 1/2 cycle shift

The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1.)

Bits 29:5 Reserved, must be kept at reset value.

Bits 4:0 DCYC[4:0] : Number of dummy cycles

This bitfield defines the duration of the dummy phase according to the memory latency.

In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).

30.7.16 HSPI instruction register (HSPI_IR)

Address offset: 0x110

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 INSTRUCTION[31:0] : Instruction
Instruction to be sent to the external SPI device

30.7.17 HSPI alternate bytes register (HSPI_ABR)

Address offset: 0x120

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 ALTERNATE[31:0] : Alternate bytes
Optional data to be sent to the external SPI device right after the address.

30.7.18 HSPI low-power timeout register (HSPI_LPTR)

Address offset: 0x130

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TIMEOUT[15:0] : Timeout period

After each access in memory-mapped mode, the HSPI prefetches the subsequent bytes and hold them in the FIFO.

This bitfield indicates how many CLK cycles the HSPI waits after the clock becomes inactive and until it raises the NCS, putting the external device in a lower-consumption state.

30.7.19 HSPI wrap communication configuration register (HSPI_WPCCR)

Address offset: 0x140

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DQSE : DQS enable

This bit enables the data strobe management.

0: DQS disabled

1: DQS enabled

Bit 28 Reserved, must be kept at reset value.

Bit 27 DDTR : Data double transfer rate

This bit sets the DTR mode for the data phase.

0: DTR mode disabled for the data phase

1: DTR mode enabled for the data phase

Bits 26:24 DMODE[2:0] : Data mode

This bitfield defines the data phase mode of operation.

000: No data

001: Data on a single line

010: Data on two lines

011: Data on four lines

100: Data on eight lines

101: Data on 16 lines

Others: Reserved

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:20 ABSIZE[1:0] : Alternate-byte size

This bitfield defines the alternate-byte size.

00: 8-bit alternate bytes

01: 16-bit alternate bytes

10: 24-bit alternate bytes

11: 32-bit alternate bytes

Bit 19 ABDTR : Alternate-byte double transfer rate

This bit sets the DTR mode for the alternate-byte phase.

0: DTR mode disabled for the alternate-byte phase

1: DTR mode enabled for the alternate-byte phase

Bits 18:16 ABMODE[2:0] : Alternate-byte mode

This bitfield defines the alternate byte phase mode of operation.

000: No alternate bytes

001: Alternate bytes on a single line

010: Alternate bytes on two lines

011: Alternate bytes on four lines

100: Alternate bytes on eight lines

Others: Reserved

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:12 ADSIZE[1:0] : Address size

This bitfield defines the address size.

00: 8-bit address

01: 16-bit address

10: 24-bit address

11: 32-bit address

Bit 11 ADDTR : Address double transfer rate

This bit sets the DTR mode for the address phase.

0: DTR mode disabled for the address phase

1: DTR mode enabled for the address phase

Bits 10:8 ADMODE[2:0] : Address mode

This bitfield defines the address phase mode of operation.

000: No address

001: Address on a single line

010: Address on two lines

011: Address on four lines

100: Address on eight lines

Others: Reserved

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 ISIZE[1:0] : Instruction size

This bitfield defines the instruction size.

00: 8-bit instruction

01: 16-bit instruction

10: 24-bit instruction

11: 32-bit instruction

Bit 3 IDTR : Instruction double transfer rate

This bit sets the DTR mode for the instruction phase.

0: DTR mode disabled for the instruction phase

1: DTR mode enabled for the instruction phase

Bits 2:0 IMODE[2:0] : Instruction mode

This bitfield defines the instruction phase mode of operation.

000: No instruction

001: Instruction on a single line

010: Instruction on two lines

011: Instruction on four lines

100: Instruction on eight lines

Others: Reserved

30.7.20 HSPI wrap timing configuration register (HSPI_WPTCR)

Address offset: 0x148

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bit 31 Reserved, must be kept at reset value.

Bit 30 SSHIFT : Sample shift

By default, the HSPI samples data 1/2 of a CLK cycle after the data is driven by the external device.

This bit allows the data to be sampled later in order to consider the external signal delays.

0: No shift

1: 1/2 cycle shift

The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode (when DDTR = 1).

Bits 29:5 Reserved, must be kept at reset value.

Bits 4:0 DCYC[4:0] : Number of dummy cycles

This bitfield defines the duration of the dummy phase according to the memory latency.

In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).

30.7.21 HSPI wrap instruction register (HSPI_WPIR)

Address offset: 0x150

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 INSTRUCTION[31:0] : Instruction
Instruction to be sent to the external SPI device

30.7.22 HSPI wrap alternate byte register (HSPI_WPABR)

Address offset: 0x160

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:0 ALTERNATE[31:0] : Alternate bytes
Optional data to be sent to the external SPI device right after the address

30.7.23 HSPI write communication configuration register (HSPI_WCCR)

Address offset: 0x180

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0. Its content has a meaning only when requesting write operations in memory-mapped mode.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DQSE : DQS enable

This bit enables the data strobe management.

0: DQS disabled

1: DQS enabled

Bit 28 Reserved, must be kept at reset value.

Bit 27 DDTR : Data double transfer rate

This bit sets the DTR mode for the data phase.

0: DTR mode disabled for the data phase

1: DTR mode enabled for the data phase

Bits 26:24 DMODE[2:0] : Data mode

This bitfield defines the data phase mode of operation.

000: No data

001: Data on a single line

010: Data on two lines

011: Data on four lines

100: Data on eight lines

101: Data on 16 lines

Others: Reserved

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:20 ABSIZE[1:0] : Alternate-byte size

This bitfield defines the alternate-byte size:

00: 8-bit alternate bytes

01: 16-bit alternate bytes

10: 24-bit alternate bytes

11: 32-bit alternate bytes

Bit 19 ABDTR : Alternate-byte double-transfer rate

This bit sets the DTR mode for the alternate-byte phase.

0: DTR mode disabled for the alternate-byte phase

1: DTR mode enabled for the alternate-byte phase

Bits 18:16 ABMODE[2:0] : Alternate-byte mode

This bitfield defines the alternate-byte phase mode of operation.

000: No alternate bytes

001: Alternate bytes on a single line

010: Alternate bytes on two lines

011: Alternate bytes on four lines

100: Alternate bytes on eight lines

Others: Reserved

Bits 15:14 Reserved, must be kept at reset value.

Bits 13:12 ADSIZE[1:0] : Address size

This bitfield defines the address size.

00: 8-bit address

01: 16-bit address

10: 24-bit address

11: 32-bit address

Bit 11 ADDTR : Address double transfer rate

This bit sets the DTR mode for the address phase.

0: DTR mode disabled for the address phase

1: DTR mode enabled for the address phase

Bits 10:8 ADMODE[2:0] : Address mode

This bitfield defines the address phase mode of operation.

000: No address

001: Address on a single line

010: Address on two lines

011: Address on four lines

100: Address on eight lines

Others: Reserved

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 ISIZE[1:0] : Instruction size

This bitfield defines the instruction size:

00: 8-bit instruction

01: 16-bit instruction

10: 24-bit instruction

11: 32-bit instruction

Bit 3 IDTR : Instruction double transfer rate

This bit sets the DTR mode for the instruction phase.

0: DTR mode disabled for the instruction phase

1: DTR mode enabled for the instruction phase

Bits 2:0 IMODE[2:0] : Instruction mode

This bitfield defines the instruction phase mode of operation.

000: No instruction

001: Instruction on a single line

010: Instruction on two lines

011: Instruction on four lines

100: Instruction on eight lines

Others: Reserved

30.7.24 HSPI write timing configuration register (HSPI_WTCR)

Address offset: 0x188

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0. Its content has a meaning only when requesting write operations in memory-mapped mode.

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 DCYC[4:0] : Number of dummy cycles

This bitfield defines the duration of the dummy phase according to the memory latency.

In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).

30.7.25 HSPI write instruction register (HSPI_WIR)

Address offset: 0x190

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0. Its content has a meaning only when requesting write operations in memory-mapped mode.

Bits 31:0 INSTRUCTION[31:0] : Instruction

Instruction to be sent to the external SPI device

30.7.26 HSPI write alternate byte register (HSPI_WABR)

Address offset: 0x1A0

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0. Its content has a meaning only when requesting write operations in memory-mapped mode.

Bits 31:0 ALTERNATE[31:0] : Alternate bytes

Optional data to be sent to the external SPI device right after the address

30.7.27 HSPI HyperBus latency configuration register (HSPI_HLCR)

Address offset: 0x200

Reset value: 0x0000 0000

This register can be modified only when BUSY = 0.

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 TRWR[7:0] : Read-write minimum recovery time

Device Read-to-write/write-to-read minimum recovery time expressed in number of communication clock cycles

Bits 15:8 TACC[7:0] : Access time

Device access time according to the memory latency, expressed in number of communication clock cycles

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 WZL : Write zero latency

This bit enables zero latency on write operations.

0: Latency on write accesses

1: No latency on write accesses

Bit 0 LM : Latency mode

This bit selects the latency mode.

0: Variable initial latency

1: Fixed latency

Note: This bit must be set when using the dual-octal HyperRAM configuration. It must be kept cleared for HyperFLASH memory.

30.7.28 HSPI full-cycle calibration configuration (HSPI_CALFCR)

Address offset: 0x210

Reset value: 0x0000 0000

This read-only register gives the calibration code needed by the DLL master so that its delay is equivalent to a full memory-clock cycle. The value of this register is updated every time that auto-calibration finishes.

Bit 31 CALMAX : Max value

This bit gets set when the memory-clock period is outside the range of DLL master, in which case HSPI_CALFCR and HSPI_CALSR are updated with the values for the maximum delay.

Bits 30:21 Reserved, must be kept at reset value.

Bits 20:16 COARSE[4:0] : Coarse calibration

The delay unitary value for this bitfield depends on product technology (see the datasheet).

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 FINE[6:0] : Fine calibration

The delay unitary value for this bitfield depends on product technology (see the datasheet).

30.7.29 HSPI DLL master calibration configuration (HSPI_CALMR)

Address offset: 0x218

Reset value: 0x0000 0000

The DLL Master is used for delaying the feedback clock when reading without DQS.

The delay of the master DLL is determined by the value in this register.

This register can always be read by software and can be modified only when BUSY = 0.

This register never gets updated automatically by hardware.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 COARSE[4:0] : Coarse calibration

The delay unitary value for this bitfield depends on product technology (see the datasheet).

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 FINE[6:0] : Fine calibration

The delay unitary value for this bitfield depends on product technology (see the datasheet).

30.7.30 HSPI DLL slave output calibration configuration (HSPI_CALSOR)

Address offset: 0x220

Reset value: 0x0000 0000

The DLL output slave is used to delay the output data in DDR mode for write operations. The delay of the output slave DLL is determined by the value in this register.

This register is updated automatically by hardware at the end of calibration (at the same moment that HSPI_CALFCR is updated).

If this register is written after the last write to HSPI_DCR2 or HSPI_CCR, then auto-calibration is not executed on the next transfer (auto-calibration is not performed for HSPI_CALSIR as well).

This register can always be read by software and can be modified only when BUSY = 0.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 COARSE[4:0] : Coarse calibration

The delay unitary value for this bitfield depends on product technology.

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 FINE[6:0] : Fine calibration

The delay unitary value for this bitfield depends on product technology.

30.7.31 HSPI DLL slave input calibration configuration (HSPI_CALSIR)

Address offset: 0x228

Reset value: 0x0000 0000

The DLL input slave is used to delay the DQS input for sampling the data when DQS is enabled for read operations. The delay of the input slave DLL is determined by the value in this register.

This register is updated automatically by hardware at the end of calibration (at the same moment that HSPI_CALFCR is updated).

If this register is written after the last write to HSPI_DCR2 or HSPI_CCR, then auto-calibration is not executed on the next transfer (auto-calibration is not performed for HSPI_CALSOR as well).

This register can always be read by software and can be modified only when BUSY = 0.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 COARSE[4:0] : Coarse calibration

The delay unitary value for this bitfield depends on product technology.

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:0 FINE[6:0] : Fine calibration

The delay unitary value for this bitfield depends on product technology.

30.7.32 HSPI register map

Table 270. HSPI register map and reset values

Table 270. HSPI register map and reset values

Table 270. HSPI register map and reset values

Table 270. HSPI register map and reset values

Refer to Section 2.3: Memory organization for the register boundary addresses.