29. Octo-SPI I/O manager (OCTOSPIM)

This section does not apply to STM32U535/545 devices.

29.1 Introduction

The Octo-SPI I/O manager is a low-level interface that enables an efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map), and multiplex of single/dual/quad/octal SPI interfaces over the same bus.

29.2 OCTOSPIM main features

• • Supports up to two single/dual/quad/octal SPI interfaces
• • Supports up to two ports for pin assignment
• • Fully programmable I/O matrix for pin assignment by function (data/control/clock)

29.3 OCTOSPIM implementation

The following table describes the OCTOSPIM implementation.

Table 259. OCTOSPIM implementation

29.4 OCTOSPIM functional description

29.4.1 OCTOSPIM block diagram

The block diagram of the OCTOSPI I/O manager is shown in Figure 163 .

Figure 163. OCTOSPIM block diagram

1. 1. The number of ports (n) is 2.
2. 2. Arbitration is possible for both I/O matrix input ports.

29.4.2 OCTOSPIM input/output pins

Table 260. OCTOSPIM input/output pins

1. 1. x = 1 to 2.

29.4.3 OCTOSPIM matrix

The OCTOSPI I/O manager matrix allows the user to set a fully programmable premapping of functions:

• • Any OCTOSPIM_Pn_CLK / OCTOSPIM_Pn_NCLK pair can be mapped independently to OCTOSPI1_CLK/OCTOSPI1_NCLK or OCTOSPI2_CLK/OCTOSPI2_NCLK
• • Any OCTOSPIM_Pn_DQS can be mapped independently to OCTOSPI1_DQS or OCTOSPI2_DQS
• • Any OCTOSPIM_Pn_NCS can be mapped independently to OCTOSPI1_NCS or OCTOSPI2_NCS
• • Any OCTOSPIM_Pn_IO[3:0] and OCTOSPIM_Pn_IO[7:4] can be mapped independently to OCTOSPI1_IO[3:0], OCTOSPI1_IO[7:4], OCTOSPI2_IO1[3:0] or OCTOSPI2_IO[7:4]

For each OCTOSPI I/O manager port, individual signal enables and mapping are configured through the corresponding OCTOSPI I/O manager Port n configuration register (OCTOSPIM_PnCR).

When several I/O pins have the same configuration and are enabled at the same time, the result can be unpredictable.

In the default out-of-reset configuration, the OCTOSPI1 and OCTOSPI2 signals are mapped, respectively, on Port 1 and on Port 2.

The OCTOSPIM configuration can be changed only when all OCTOSPIs are disabled.

29.4.4 OCTOSPIM multiplexed mode

When this mode is set, the OCTOSPIs are time-multiplexed over the same bus. They get the ownership of the bus (in turn) through a request/acknowledge protocol with REQ/ACK signals.

The time-multiplexing is enabled by setting the MUXEN bit of the configuration register OCTOSPIM_CR.

The fairness counter (MAXTRAN) of each OCTOSPI can be used to manage accurately the maximum duration for which a given OCTOSPI takes the bus: this feature ensures a maximum bus access latency for the other OCTOSPI(s). When the bus is released by one OCTOSPI, an arbitration phase occurs, which is round-robin: when another OCTOSPI requests the bus, it gets it.

When the multiplexed mode is enabled, either the fairness counter or the refresh timeout counter of both OCTOSPI interfaces must be activated.

OCTOSPI_n_NCS are not part of the multiplexing. Only OCTOSPI_n_IOs, OCTOSPI_n_DQS and OCTOSPI_n_CLK / OCTOSPI_n_NCLK are multiplexed.

When the multiplexed mode is used, only clock mode 0 is supported on the OCTOSPIs.

Due to arbitration and bus sharing, the auto polling interval time of the OCTOSPI, when used, may increase.

Minimum switching duration

The minimum number of cycles needed to switch from an OCTOSPI to another can be configured.

This internal timer guarantees a latency between the falling edge of the REQ signal of the active OCTOSPI (the active one releases the bus), and the rising edge of the ACK signal to the requesting OCTOSPI (the bus is granted to the requesting one).

The REQ2ACK_TIME field of the configuration register OCTOSPIM_CR defines the duration.

Pin mapping in multiplexed mode

In multiplexed mode, the mapping of the bus is done as described below:

• • OCTOSPI1_NCS and OCTOSPI2_NCS work in the same way, then in Non-multiplexed mode they have to be assigned to their respective OCTOSPIM_Pn_NCS.
• • All the other signals are seen by the I/O matrix as if they were seen from OCTOSPI1.

29.5 OCTOSPIM registers

29.5.1 OCTOSPIM control register (OCTOSPIM_CR)

Address offset: 0x0000

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 REQ2ACK_TIME[7:0] : REQ to ACK time

In multiplexed mode (MUXEN = 1), this field defines the time between two transactions.

The value is the number of OCTOSPI clock cycles - 1

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 MUXEN : Multiplexed mode enable

This bit enables the multiplexing of the two OCTOSPIs.

0: No multiplexing, hence no arbitration

1: OCTOSPI1 and OCTOSPI2 are multiplexed over the same bus.

29.5.2 OCTOSPIM Port n configuration register (OCTOSPIM_PnCR)

Address offset: 0x0000 + 0x4 * n (n = 1 to 2)

Reset value: 0x0301 0111, 0x0705 0333

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:25 IOHSRC[1:0] : IO[7:4] source for Port n

This bits select the source of Port n IO[7:4].

00: OCTOSPI1_IO[3:0] in non multiplexed mode / multiplexed_IO[3:0] in multiplexed mode

01: OCTOSPI1_IO[7:4] in non multiplexed mode / multiplexed_IO[7:4] in multiplexed mode

10: OCTOSPI2_IO[3:0] in non multiplexed mode / unused in multiplexed mode

11: OCTOSPI2_IO[7:4] in non multiplexed mode / unused in multiplexed mode

Bit 24 IOHEN : IO[7:4] enable for Port n
This bit enables the Port n IO[7:4].

0: IO[7:4] for Port n disabled
1: IO[7:4] for Port n enabled

Bits 23:19 Reserved, must be kept at reset value.

Bits 18:17 IOLSRC[1:0] : IO[3:0] source for Port n
This bits select the source of Port n IO[3:0].

00: OCTOSPI1_IO[3:0] in non multiplexed mode / multiplexed_IO[3:0] in multiplexed mode
01: OCTOSPI1_IO[7:4] in non multiplexed mode / multiplexed_IO[7:4] in multiplexed mode
10: OCTOSPI2_IO[3:0] in non multiplexed mode / unused in multiplexed mode
11: OCTOSPI2_IO[7:4] in non multiplexed mode / unused in multiplexed mode

Bit 16 IOLEN : IO[3:0] enable for Port n
This bit enables the Port n IO[3:0].

0: IO[3:0] for Port n disabled
1: IO[3:0] for Port n enabled

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 NCSSRC : NCS source for Port n
This bit selects the source of Port n NCS.

0: OCTOSPI1_NCS
1: OCTOSPI2_NCS

Bit 8 NCSEN : NCS enable for Port n
This bit enables the Port n NCS.

0: NCS for Port n is disabled
1: NCS for Port n is enabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 DQSSRC : DQS source for Port n
This bit selects the source of Port n DQS.

0: OCTOSPI1_DQS in non multiplexed mode / multiplexed_DQS in multiplexed mode
1: OCTOSPI2_DQS in non multiplexed mode / unused port in multiplexed mode

Bit 4 DQSEN : DQS enable for Port n
This bit enables the Port n DQS.

0: DQS for Port n is disabled
1: DQS for Port n is enabled

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 CLKSRC : CLK/NCLK source for Port n
This bit selects the source of Port n CLK/NCLK.

0: OCTOSPI1_CLK/NCLK in non multiplexed mode / multiplexed_CLK/CLKn in multiplexed mode
1: OCTOSPI2_CLK/NCLK in non multiplexed mode / unused port in multiplexed mode

Bit 0 CLKEN : CLK/NCLK enable for Port n
This bit enables the Port n CLK/NCLK.

0: CLK/NCLK for Port n is disabled
1: CLK/NCLK for Port n is enabled

29.5.3 OCTOSPIM register map

Table 261. OCTOSPIM register map and reset values

Refer to Section 2.3 on page 140 for the register boundary addresses.