18. Low-power direct memory access controller (LPDMA)

18.1 LPDMA introduction

The low-power direct memory access (LPDMA) controller is a bus master and system peripheral.

The LPDMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.

18.2 LPDMA main features

• • Single bidirectional AHB master
• • Memory-mapped data transfers from a source to a destination:
  • – Peripheral-to-memory
  • – Memory-to-peripheral
  • – Memory-to-memory
  • – Peripheral-to-peripheral
• • Autonomous data transfers during Stop mode (see Section 18.4.17 )
• • Transfers arbitration based on a 4-grade programmed priority at channel level:
  • – One high-priority traffic class, for time-sensitive channels (queue 3)
  • – Three low-priority traffic classes, with a weighted round-robin allocation for non time-sensitive channels (queues 0, 1, 2)
• • Per channel event generation, on any of the following events: transfer complete, half-transfer complete, data transfer error, user setting error, link transfer error, completed suspension and trigger overrun
• • Per channel interrupt generation, with separately programmed interrupt enable per event
• • 4 concurrent LPDMA channels:
  • – Intra-channel LPDMA transfers chaining via programmable linked-list into memory, supporting two execution modes: run-to-completion and link step mode
  • – Intra-channel and inter-channel LPDMA transfers chaining via programmable LPDMA input triggers connection to LPDMA task completion events
• • Per linked-list item within a channel:
  • – Separately programmed source and destination transfers
  • – Programmable data handling between source and destination: byte-based padding or truncation, sign extension and left/right realignment
  • – Programmable number of data bytes to be transferred from the source, defining the block level
  • – Linear source and destination addressing: either fixed or contiguously incremented addressing, programmed at a block level, between successive single transfers
  • – Programmable LPDMA request and trigger selection
  • – Programmable LPDMA half-transfer and transfer-complete events generation

• – Pointer to the next linked-list item and its data structure in memory, with automatic update of the LPDMA linked-list control registers
• • Debug:
  • – Channel suspend and resume support
  • – Channel status reporting and event flags
• • TrustZone support
  • – Support for secure and nonsecure LPDMA transfers, independently at a first channel level, and independently at a source/destination and link sub-levels
  • – Secure and nonsecure interrupts reporting, resulting from any of the respectively secure and nonsecure channels
  • – TrustZone-aware AHB slave port, protecting any LPDMA secure resource (register, register field) from a nonsecure access
• • Privileged/unprivileged support:
  • – Support for privileged and unprivileged LPDMA transfers, independently at a channel level
  • – Privileged-aware AHB slave port

18.3 LPDMA implementation

Table 145.LPDMA1 channels implementation

18.3.1 LPDMA channels

A given LPDMA channel x is implemented with the hardware parameters as per the table below.

Table 146.LPDMA1 channels implementation

18.3.2 LPDMA autonomous mode in low-power modes

The LPDMA autonomous mode and wake-up features are implemented in the device low-power modes as per the table below.

Table 147. LPDMA1 autonomous mode and wake-up in low-power modes

18.3.3 LPDMA requests

A LPDMA request from a peripheral can be assigned to a LPDMA channel x, via the REQSEL[4:0] field in the LPDMA channel x transfer register 2 (LPDMA_CxTR2) , provided that SWREQ = 0.

The LPDMA requests mapping is specified in the table below.

Table 148. Programmed LPDMA1 request

18.3.4 LPDMA block requests

Some LPDMA requests must be programmed as a block request, and not as a single request. Then the BREQ bit in LPDMA channel x transfer register 2 (LPDMA_CxTR2) must

be set for a correct LPDMA execution of the requested peripheral transfer at the hardware level.

The LPDMA block requests are listed in the table below.

Table 149. Programmed LPDMA1 request as a block request

18.3.5 LPDMA triggers

A LPDMA trigger can be assigned to a LPDMA channel x, via the TRIGSEL[4:0] field in the LPDMA channel x transfer register 2 (LPDMA_CxTR2) , provided that TRIGPOL[1:0] defines a rising or a falling edge of the selected trigger (TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).

The LPDMA triggers mapping is specified in the table below.

Table 150. Programmed LPDMA1 trigger

Table 150. Programmed LPDMA1 trigger (continued)

18.4 LPDMA functional description

18.4.1 LPDMA block diagram

The LPDMA block diagram is illustrated in the figure below.

Figure 72. LPDMA block diagram

18.4.2 LPDMA channel state and direct programming without any linked-list

After a LPDMA reset, a LPDMA channel x is in idle state. When the software writes 1 into the in LPDMA_CxCR.EN enable control bit, the channel takes into account the value of the different channel configuration registers (LPDMA_CxXXX), switches to the active/non-idle state and starts to execute the corresponding requested data transfers.

After enabling/starting a LPDMA channel transfer by writing 1 into the LPDMA_CxCR.EN bit, a LPDMA channel interrupt on a complete transfer notifies the software that the LPDMA channel is back in idle state (EN is then de-asserted by hardware) and that the channel is ready to be reconfigured then enabled again.

The figure below illustrates this LPDMA direct programming without any linked-list (LPDMA_CxLLR = 0).

Figure 73. LPDMA channel direct programming without linked-list (LPDMA_CxLLR = 0)

graph TD; subgraph Idle; A[Initialize DMA channel
(keeping DMA_CxLLR[31:0] = 0)]; B[Reconfigure DMA channel
(keeping DMA_CxLLR[31:0] = 0)]; end; A --> C[Enable DMA channel]; B --> C; C --> D{Valid user setting?}; subgraph Active; D -- Y --> E[Executing the data transfer
from the register file]; E --> F{No transfer error?}; F -- Y --> G[Setting TCF = 1
Disabling DMA channel]; F -- N --> H[Setting DTEF = 1
Disabling DMA channel]; D -- N --> I[Setting USEF = 1
Disabling DMA channel]; end; G --> J((End)); H --> J; I --> J;

MSv62626V1

18.4.3 LPDMA channel suspend and resume

The software can suspend on its own a channel still active, with the following sequence:

1. 1. The software writes 1 into the LPDMA_CxCR.SUSP bit.
2. 2. The software polls the suspended flag LPDMA_CxSR.SUSPF until SUSPF = 1, or waits for an interrupt previously enabled by writing 1 to LPDMA_CxCR.SUSPIE. Wait for the channel to be effectively in suspended state means wait for the completion of

any ongoing LPDMA transfer over its master port. Then the software can observe, in a steady state, any read register or register field that is hardware modifiable.

Note that an ongoing LPDMA transfer can be a data transfer (a read-followed-by-write single transfer) or a link transfer for the internal update of the linked-list register file from the next linked-list item.

1. 3. The software safely resumes the suspended channel by writing 0 to LPDMA_CxCR.SUSP.

The suspend and resume sequence is illustrated in the figure below.

Figure 74. LPDMA channel suspend and resume sequence

graph TD; subgraph Active1 [Channel state = Active]; A1[Suspend the DMA channel<br/>(write 1 to CxCR.SUSP)]; end; A1 --> SUSPF{SUSPF=1?}; SUSPF -- N --> SUSPF; SUSPF -- Y --> subgraph Suspended [Channel state = Suspended and Idle]; I[Receiving suspended interrupt]; R[Resume the DMA channel<br/>(write 0 to CxCR.SUSP)]; end; R --> subgraph Active2 [Channel state = Active]; end;

Note: A suspend and resume sequence does not impact the LPDMA_CxCR.EN bit. Suspending a channel (transfer) does not suspend a started trigger detection.

18.4.4 LPDMA channel abort and restart

Alternatively, like for aborting a continuous LPDMA transfer with a circular buffering or a double buffering, the software can abort, on its own, a still active channel with the following sequence:

1. 1. The software writes 1 into the LPDMA_CxCR.SUSP bit.
2. 2. The software polls suspended flag LPDMA_CxSR.SUSPF until SUSPF = 1, or waits for an interrupt previously enabled by writing 1 to LPDMA_CxCR.SUSPIE. Wait for the channel to be effectively in suspended state means wait for the completion of any ongoing LPDMA transfer over its master port.
3. 3. The software resets the channel by writing 1 to LPDMA_CxCR.RESET. This causes the reset of the channel internal state, the reset of the LPDMA_CxCR.EN bit, and the reset of the LPDMA_CxCR.SUSP bit.

1. 4. The software safely reconfigures the channel. The software must reprogram the hardware-modified LPDMA_CxBR1, LPDMA_CxSAR, and LPDMA_CxDAR registers.
2. 5. In order to restart the aborted then reprogrammed channel, the software enables it again by writing 1 to the LPDMA_CxCR.EN bit.

The abort and restart sequence is illustrated in the figure below.

Figure 75. LPDMA channel abort and restart sequence

graph TD; subgraph State1 [Channel state = Active]; A1[Suspend the DMA channel<br/>(write 1 to CxCR.SUSP)]; A1 -- or --> D1{SUSPF=1?}; D1 -- N --> A1; D1 -- Y --> State2; end; subgraph State2 [Channel state = Suspended<br/>(and Idle)]; S1[Receiving suspended interrupt]; S1 --> R1[Reset the DMA channel<br/>(write 1 to CxCR.RESET)]; end; subgraph State3 [Channel state = Idle]; Re1[Reconfigure the DMA channel]; En1[Enable the DMA channel]; end; State2 --> R1; R1 --> State3; State3 --> En1; En1 --> State4 [Channel state = Active];

18.4.5 LPDMA linked-list data structure

Alternatively to the direct programming mode, a channel can be programmed by a list of transfers, known as a list of linked-list items (LLI). Each LLI is defined by its data structure.

The base address in memory of the data structure of a next \( LLI_{n+1} \) of a channel x is the sum of the following:

• • the link base address of the channel x (in LPDMA_CxLBAR)
• • the link address offset (LA[15:2] field in LPDMA_CxLLR)

The data structure for each LLI may be specific.

A linked-list data structure is addressed following the value of the UT1, UT2, UB1, USA, UDA and ULL bits of the LPDMA_CxLLR register.

In linked-list mode, each LPDMA linked-list register (LPDMA_CxTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR or LPDMA_CxLLR) is conditionally and automatically updated from the next linked-list data structure in the memory, following the current value of the LPDMA_CxLLR register that was conditionally updated from the linked-list data structure of the previous LLI.

Caution: The user must program the pointer to the next linked-list data structure (LPDMA_CxLLR[15:0]) not to exceed the 64-Kbyte addressable space defined by the link base address register (LPDMA_CxLBAR). The complete linked-list data structure must be included in the 64-Kbyte addressable space.

Static linked-list data structure

For example, when the update bits (UT1, UT2, UB1, USA, UDA and ULL) of the LPDMA_CxLLR register are all asserted, the linked-list data structure in memory is maximal with six contiguous 32-bit locations, including LPDMA_CxTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR (see the figure below) and including the first linked-list register file (LLI ₀ ) and the next LLIs (LLI ₁ , LLI ₂ ,...) in the memory.

Figure 76. Static linked-list data structure (all Uxx = 1) of channel x

Dynamic linked-list data structure

Alternatively, the memory organization for the full list of LLIs can be compacted with specific data structure for each LLI.

If UT1 = 0 and UT2 = 1, the link address offset of the register LPDMA_CxLLR is pointing to the updated value of the LPDMA_CxTR2 instead of the LPDMA_CxTR1 which is not to be modified.

Example: if UT1 = UB1 = USA = 0, and if UT2 = UDA = ULL = 1, the next LLI does not contain an updated value for LPDMA_CxTR1, nor LPDMA_CxBR1, nor LPDMA_CxSAR. The next LLI contains an updated value for LPDMA_CxTR2, LPDMA_CxDAR, and LPDMA_CxLLR, as shown in the figure below.

Figure 77. LPDMA dynamic linked-list data structure of an addressing channel x

18.4.6 Linked-list item transfer execution

A LLI _n transfer is the sequence of:

1. 1. a data transfer: LPDMA executes the data transfer as described by the LPDMA internal register file (this data transfer can be void/null for LLI ₀ )
2. 2. a conditional link transfer: LPDMA automatically and conditionally updates its internal register file by the data structure of the next LLI _n+1 , as defined by the LPDMA_CxLLR value of the LLI _n .

Note: The initial data transfer as defined by the internal register file (LLI ₀ ) can be null (LPDMA_CxBR1.BNDT[15:0] = 0) provided that the conditional update bit UB1 in LPDMA_CxLLR is set (meaning there is a non-null data transfer described by the next LLI ₁ in the memory to be executed).

Depending on the intended LPDMA usage, a LPDMA channel x can be executed as described by the full linked-list (run-to-completion mode, LPDMA_CxCR.LSM = 0) or a LPDMA channel x can be programmed for a single execution of a LLI (link step mode, LPDMA_CxCR.LSM = 1), as described in the next paragraphs.

18.4.7 LPDMA channel state and linked-list programming in run-to-completion mode

When LPDMA_CxCR.LSM = 0, a LPDMA channel x is initially programmed, started by writing 1 to LPDMA_CxCR.EN, and after (possibly) completed at channel level. The channel transfer is:

• • configured with at least the following:
  • – the first LLI ₀ , internal linked-list register file: LPDMA_CxTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR
  • – the last LLI _N , described by the linked-list data structure in memory, as defined by the LPDMA_CxLLR reflecting the before last LLI _N-1
• • completed when LPDMA_CxLLR[31:0] = 0 and LPDMA_CxBR1.BNDT[15:0] = 0, at the end of the last LLI _N-1 transfer

LPDMA_CxLLR[31:0] = 0 is the condition of a linked-list based channel completion and means the following:

• • The 16 low significant bits LPDMA_CxLLR.LA[15:0] of the next link address are null.
• • All the update bits Uxx of LPDMA_CxLLR are null (UT1, UT2, UB1, USA, UDA, ULL).

The channel may never be completed when LPDMA_CxLLR.LSM = 0:

• • If the last LLI _N is recursive, pointing to itself as a next LLI:
  • – either LPDMA_CxLLR.ULL = 1 and LPDMA_CxLLR.LA[15:2] is updated with the same value
  • – or LPDMA_CxLLR.ULL = 0
• • If LLI _N is pointing to a previous LLI.

In the typical run-to-completion mode, the allocation of a LPDMA channel, including its fine programming, is done once during the LPDMA initialization. In order to have a reserved data communication link and LPDMA service during run-time, for continuously repeated transfers (from/to a peripheral respectively to/from memory or for memory-to-memory transfers). This reserved data communication link can consist of a channel, or the channel can be shared and a repeated transfer consists of a sequence of LLIs.

Figure 78 depicts the LPDMA channel execution and its registers programming in run-to-completion mode.

Note: Figure 78 is not intended to illustrate how often a TCEF can be raised, depending on the programmed value of TCEM[1:0] in LPDMA_CxTR2. It can be raised at (each) block completion, at (each) 2D block completion, at (each) LLI completion, or only at channel completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at the channel completion, the hardware always set TCEF = 1 and disables the channel.

Figure 78. LPDMA channel execution and linked-list programming in run-to-completion mode (LPDMA_CxCR.LSM = 0)

graph TD; subgraph Idle [Channel state = Idle]; Init[Initialize DMA channel] --> Enable[Enable DMA channel]; end; Enable --> Active [Channel state = Active]; subgraph Active; Valid1{Valid user setting?}; BNDT{BNDT ≠ 0?}; Exec[Executing once the data transfer from the register file]; NoError1{No transfer error?}; LLR{LLR ≠ 0?}; Load[Loading next LLI into the register file]; NoError2{No transfer error?}; Valid2{Valid user setting?}; TCF[Setting TCF = 1 Disabling DMA channel]; USEF1[Setting USEF = 1 Disabling DMA channel]; DTEF[Setting DTEF = 1 Disabling DMA channel]; ULEF[Setting ULEF = 1 Disabling DMA channel]; USEF2[Setting USEF = 1 Disabling DMA channel]; End[/End/]; Init --> Valid1; Valid1 -- N --> USEF1; USEF1 --> Reconfig[Reconfigure DMA channel]; Reconfig --> Init; Valid1 -- Y --> BNDT; BNDT -- N --> DTEF; DTEF --> Reconfig; BNDT -- Y --> Exec; Exec --> NoError1; NoError1 -- N --> DTEF; NoError1 -- Y --> LLR; LLR -- N --> TCF; TCF --> End; LLR -- Y --> Load; Load --> NoError2; NoError2 -- N --> ULEF; ULEF --> Reconfig; NoError2 -- Y --> Valid2; Valid2 -- N --> USEF2; USEF2 --> Reconfig; Valid2 -- Y --> TCF; TCF --> End;

MSv62631V1

Run-time inserting a \( LLI_n \) via an auxiliary channel, in run-to-completion mode

The start of the link transfer of the \( LLI_{n-1} \) (start of the \( LLI_n \) loading) can be conditioned by the occurrence of a trigger, when programming the following fields of the LPDMA_CxTR2 in the data structure of the \( LLI_{n-1} \) :

• • TRIGM[1:0] = 10 (link transfer triggering mode)
• • TRIGPOL[1:0] = 01 or 10 (rising or falling edge)
• • TRIGSEL[4:0] (see Section 18.3.5 for the trigger selection details)

Another auxiliary channel y can be used to store the channel x \( LLI_n \) in the memory and to generate a transfer complete event lpdma_chy_tc. By selecting this event as the input trigger of the link transfer of the \( LLI_{n-1} \) of the channel x, the software can pause the primary channel x after its \( LLI_{n-1} \) data transfer, until it is indeed written the \( LLI_n \) .

Figure 79 depicts such a dynamic elaboration of a linked-list of a primary channel x, via another auxiliary channel y.

Caution: This use case is restricted to an application with a \( LLI_{n-1} \) data transfer that does not need a trigger. The triggering mode of this \( LLI_{n-1} \) is used to load the next \( LLI_n \) .

Figure 79. Inserting a \( LLI_n \) with an auxiliary LPDMA channel y

18.4.8 LPDMA channel state and linked-list programming in link step mode

When LPDMA_CxCR.LSM = 1, a channel transfer is executed and completed after each single execution of a LLI, including its (conditional) data transfer and its (conditional) link transfer.

A LPDMA channel transfer can be programmed at LLI level, started by writing 1 into LPDMA_CxCR.EN, and after completed at LLI level:

• • The current LLI _n transfer is described with:
  • – LPDMA_CxTR1 defines the source/destination elementary single transfers.
  • – LPDMA_CxBR1 defines the number of bytes at a block level (BNDT[15:0]).
  • – LPDMA_CxTR2 defines the input control (request, trigger) and the output control (transfer complete event) of the transfer.
  • – LPDMA_CxSAR/LPDMA_CxDAR defines the source/destination transfer start address.
  • – LPDMA_CxLLR defines the data structure and the address offset of the next LLI _n+1 in the memory.
• • The current LLI _n transfer is completed after the single execution of the current LLI _n :
  • – after the (conditional) data transfer completion (when LPDMA_CxBR1.BNDT[15:0] = 0)
  • – after the (conditional) update of the LPDMA link register file from the data structure of the next LLI _n+1 in memory

Note: If a LLI is recursive (pointing to itself as a next LLI, either LPDMA_CxLLR.ULL = 1 and LPDMA_CxLLR.LA[15:2] is updated with the same value, or LPDMA_CxLLR.ULL = 0), a channel in link step mode is completed after each repeated single execution of this LLI.

Figure 80 depicts the LPDMA channel execution mode, and its programming in link step mode.

Note: Figure 80 is not intended to illustrate how often a TCEF can be raised, depending on the programmed value of TCEM[1:0] in LPDMA_CxTR2. It can be raised at (each) block completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI data transfer completion. In link step mode, the channel is disabled after each single execution of a LLI, and depending on the value of TCEM[1:0] a TCEF is raised or not.

graph TD; subgraph Idle; A[Initialize DMA channel] --> B[Enable DMA channel]; B --> C{Valid user setting?}; C -- N --> D[Setting USEF = 1
Disabling DMA channel]; D --> E[Reconfigure DMA channel]; E --> C; C -- Y --> F{BNDT ≠ 0?}; F -- N --> D; F -- Y --> G[Executing once the data transfer from the register file]; G --> H{No transfer error?}; H -- N --> I[Setting DTEF = 1
Disabling DMA channel]; H -- Y --> J{LLR ≠ 0?}; J -- N --> K[Setting TCF = 1
Disabling DMA channel]; J -- Y --> L[Loading next LLI into the register file]; L --> M{No transfer error?}; M -- N --> I; M -- Y --> N1{Valid user setting?}; N1 -- N --> O[Setting USEF = 1
Disabling DMA channel]; N1 -- Y --> K; K --> P{End}; O --> P; I --> P; E --> P;

MSv62633V1

The link step mode can be used to elaborate dynamically LLIs in memory during run-time. The software can be facilitated by using a static data structure for any \( LLI_n \) (all update bits of LPDMA_CxLLR have a static value, \( LLI_n.LLR.LA = LLI_{n-1}.LLR.LA + \text{constant} \) ).

Run-time adding a \( LLI_{n+1} \) in link step mode

During run-time, the software can defer the elaboration of the \( LLI_{n+1} \) (and next LLIs), until/after LPDMA executed the transfer from the \( LLI_{n-1} \) and loaded the \( LLI_n \) from the memory, as shown in the figure below.

Figure 81. Building \( LLI_{n+1} \) : LPDMA dynamic linked-lists in link step mode

sequenceDiagram
    participant DMA Channel
    participant CPU
    Note right of DMA Channel: LSM = 1 with 2-stage linked-list programming: DMA executes LLI_{n-1} and loads LLI_n while CPU builds LLI_{n+1}
    DMA Channel->>DMA Channel: LLI_{n-2} transfer
    DMA Channel->>CPU: Transfer complete interrupt
    CPU->>DMA Channel: Enable DMA channel
    DMA Channel->>DMA Channel: LLI_{n-1} transfer (Executing LLI_{n-1} data transfer, Loading LLI_n)
    DMA Channel->>CPU: Transfer complete interrupt
    CPU->>CPU: Build and store LLI_{n+1}
    CPU->>DMA Channel: Enable DMA channel
    DMA Channel->>DMA Channel: LLI_n transfer
    Note right of DMA Channel: (dashed arrow pointing down)

Run-time replacing a \( LLI_n \) with a new \( LLI_{n'} \) in link step mode (in linked-list register file)

In this link step mode, during run-time, the software can build and insert a new \( LLI_{n'} \) , after LPDMA executed the transfer from the \( LLI_{n-1} \) and loaded a formerly elaborated \( LLI_n \) from the memory by overwriting directly the linked-list register file with the new \( LLI_{n'} \) , as shown in Figure 82.

The software can build and insert a new LLI _n' and LLI _n+1' in the memory, after LPDMA executed the transfer from the LLI _n-1 and loaded a formerly elaborated LLI _n from the memory, by overwriting partly the linked-list register file (LPDMA_CxBR1.BNDT[15:0] to be null and LPDMA_CxLLR to point to new LLI _n' ) as shown in Figure 83 .

Figure 83. Replace with a new LLI _n' and LLI _n+1' in memory in link step mode (option 1)

sequenceDiagram
    participant DMA Channel
    participant CPU

    Note over DMA Channel: LLI_{n-1} transfer
    DMA Channel->>DMA Channel: Executing LLI_{n-1} data transfer
    DMA Channel->>DMA Channel: Loading LLI_n
    DMA Channel->>CPU: Transfer complete interrupt
    Note over CPU: Build LLI_{n'} and LLI_{n+1'} in memory
    Note over CPU: Write DMA_CxBR1.BNDT = 0
Write DMA_CxLLR to point to new LLI_{n'}
    Note over CPU: Enable DMA channel
    Note over DMA Channel: LLI_{n'} transfer
    DMA Channel->>DMA Channel: Loading LLI_{n'}
    DMA Channel->>CPU: Transfer complete interrupt
    Note over CPU: Enable DMA channel
    Note over DMA Channel: LLI_{n+1'} transfer
    DMA Channel->>DMA Channel: Executing LLI_{n+1'} data transfer
    DMA Channel->>DMA Channel: Loading LLI_{n+1'}
    DMA Channel->>CPU: Transfer complete interrupt

Run-time replacing a \( LLI_n \) with a new \( LLI_{n'} \) in link step mode

Other software implementations exist. Meanwhile LPDMA executes the transfer from the \( LLI_{n-1} \) and loads a formerly elaborated \( LLI_n \) from the memory (or even earlier), the software can do the following:

1. 1. Disable the NVIC for not being interrupted by the interrupt handling.
2. 2. Build a new \( LLI_{n'} \) and a new \( LLI_{n+1'} \) .
3. 3. Enable again the NVIC for the channel interrupt (transfer complete) notification.

The software in the interrupt handler for \( LLI_{n-1} \) is then restricted to overwrite LPDMA_CxBR1.BNDT[15:0] to be null and LPDMA_CxLLR to point to new \( LLI_{n'} \) , as shown in Figure 84.

Figure 84. Replace with a new \( LLI_{n'} \) and \( LLI_{n+1'} \) in memory in link step mode (option 2)

sequenceDiagram
    participant DMA as DMA channel
    participant CPU as CPU

    Note over DMA, CPU: LSM = 1 with 1-stage linked-list programming

    rect rgb(240, 240, 240)
    Note left of DMA: LLI_{n-1} transfer
    DMA->>DMA: Executing LLI_{n-1} data transfer
    DMA->>DMA: Loading LLI_n
    end

    CPU->>CPU: Disable NVIC DMA irq channel
    CPU->>CPU: Build LLI_{n'} & LLI_{n+1'} in memory
    CPU->>CPU: Enable NVIC DMA irq channel

    DMA-->>CPU: Transfer complete interrupt

    CPU->>DMA: Write DMA_CxBR1.BNDT = 0
    CPU->>DMA: Write DMA_CxLLR to point to new LLI_{n'}
    CPU->>CPU: Enable DMA channel

    rect rgb(240, 240, 240)
    Note left of DMA: LLI_{n'} transfer
    DMA->>DMA: Loading LLI_{n'}
    end

    DMA-->>CPU: Transfer complete interrupt
    CPU->>CPU: Enable DMA channel

    rect rgb(240, 240, 240)
    Note left of DMA: LLI_{n+1'} transfer
    DMA->>DMA: Executing LLI_{n+1'} data transfer
    DMA->>DMA: Loading LLI_{n+1'}
    end

    DMA-->>CPU: Transfer complete interrupt

18.4.9 LPDMA channel state and linked-list programming

The software can reconfigure a channel when the channel is disabled (LPDMA_CxCR.EN = 0) and update the execution mode (LPDMA_CxCR.LSM) to change from/to run-to-completion mode to/from link step mode.

In any execution mode, the software can:

• • reprogram \( LLI_{n+1} \) in the memory to finally complete the channel by this \( LLI_{n+1} \) (clear the LPDMA_CxLLR of this \( LLI_{n+1} \) ), before this \( LLI_{n+1} \) is loaded/used by the LPDMA channel
• • abort and reconfigure the channel with a LSM update (see Section 18.4.4 )

In link step mode, the software can clear LSM after each a single execution of any LLI, during \( LLI_{n-1} \) .

Figure 85 shows the overall and unified LPDMA linked-list programming, whatever is the execution mode.

Note: Figure 85 is not intended to illustrate how often a TCEF can be raised, depending on the programmed value of TCEM[1:0] in LPDMA_CxTR2. It can be raised at (each) block completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI data transfer completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at the channel completion the hardware always set TCEF = 1 and disables the channel. In link step mode, the channel is disabled after each single execution of a LLI, and depending on the value of TCEM[1:0] a TCEF is raised or not.

Figure 85. LPDMA channel execution and linked-list programming

graph TD; subgraph Idle; A[Initialize DMA channel] --> B[Enable DMA channel]; B --> C{Valid user setting?}; C -- N --> D[Reconfigure DMA channel]; D --> C; end; subgraph Active; C -- Y --> E{BNDT ≠ 0?}; E -- N --> F[Setting USEF = 1
Disabling DMA channel]; E -- Y --> G[Executing once the data transfer from the register file]; G --> H{No transfer error?}; H -- N --> I[Setting DTEF = 1
Disabling DMA channel]; H -- Y --> J{LLR ≠ 0?}; J -- N --> K[Loading next LLI into the register file]; J -- Y --> L{No transfer error?}; L -- N --> M[Setting ULEF = 1
Disabling DMA channel]; L -- Y --> N1{Valid user setting?}; N1 -- N --> O[Setting USEF = 1
Disabling DMA channel]; N1 -- Y --> P{LSM = 1?}; P -- N --> G; P -- Y --> Q[Setting TCF = 1
Disabling DMA channel]; end; Q --> R[/End/];

MSv62638V1

18.4.10 LPDMA direct transfers

There is a single transfer operation mode called the direct mode. Any LPDMA channel is used in direct mode. Any channel is implemented without any FIFO (for every channel x, dma_fifo_size[x] = 0).

LPDMA single

A programmed transfer at the lowest level is called a LPDMA single.

A LPDMA single data width is 1, 2 or 4 bytes, as defined by the SDW_LOG2[1:0] and DDW_LOG2[1:0] fields of LPDMA_CxTR1 (respectively for source and destination).

Note: The user must not assign a 8-byte data width (SDW_LOG2[1:0] = 0b11 or DDW_LOG2[1:0] = 0b11) else a user setting is reported and no transfer is issued.

The addressing mode after each data of a LPDMA single is defined by the SINC and DINC bits of LPDMA_CxTR1 (respectively for source and destination): either a fixed addressing or an incremented addressing with contiguous data.

The start and next addresses of a LPDMA source/destination single (defined by LPDMA_CxSAR and LPDMA_CxDAR) must be aligned with the respective data width.

The table below lists the main characteristics of a LPDMA single.

The next single address in the table is the next source/destination address, pointed by LPDMA_CxSAR and LPDMA_CxDAR, once the programmed source/destination single is completed.

Table 151. Programmed LPDMA source/destination single

In direct mode, a LPDMA single is an AHB single transfer.

LPDMA data handling: byte-based padding/truncation, sign extension and left/right alignment

The user can configure some data manipulation between a transferred data from the source and its transfer to the destination. Data handling is controlled by the LPDMA_CxTR1 register:

• • If destination data width = source data width (DDW_LOG2[1:0] = SDW_LOG2[1:0]), the source data is copied as is and transferred to the destination.
• • Else, depending on PAM:
  • – If destination data width > source data width, the source data can be either right-aligned and padded with 0 s, or sign extended up to the destination data width.
  • – If destination data width < source data width, the source data can be either right-aligned and left-truncated down to the destination data width, or left-aligned and right-truncated down to the destination data width.

There is no data manipulation between two distinct transferred data from the source, before the generation of the destination transfer.

The table below lists possible data handling from the source to the destination.

Table 152. Programmed data handling

1. Data stream is timely ordered starting from the byte with the lowest index a.k.a B ₀ .

2. RA = right aligned. LA = left aligned. RT= right truncated. LT = left truncated.

3. 0P = zero bit padding up to the destination data width.

4. SE = sign bit extended up to the destination data width.

18.4.11 LPDMA transfer request and arbitration

LPDMA transfer request

As defined by LPDMA_CxTR2, a programmed LPDMA data transfer is requested with one of the following:

• • a software request if the control bit SWREQ = 1: This is used typically by the CPU for a data transfer from a memory-mapped address to another memory mapped address (memory-to-memory, GPIO to/from memory)
• • an input hardware request coming from a peripheral if SWREQ = 0: The selection of the LPDMA hardware peripheral request is driven by the REQSEL[4:0] field (see Section 18.3.4 ). The selected hardware request can be one of the following:
  • – a hardware request from a peripheral configured in LPDMA mode (for a transfer from/to the peripheral data register respectively to/from the memory)
  • – a hardware request from a peripheral for its control registers update from the memory
  • – a hardware request from a peripheral for a read of its status registers transferred to the memory

Caution: The user must not assign a same input hardware peripheral LPDMA request via LPDMA_CxTR.REQSEL[4:0] to two different channel if at a given time this request is asserted by the peripheral and each channel is ready to execute this requested data transfer. There is no user setting error reporting.

LPDMA transfer request for arbitration

For a given channel, a LPDMA requested data transfer from the source address to the destination address is arbitrated versus simultaneous requested LPDMA transfers from other channels, in order to be scheduled over the AHB master port. A LPDMA data transfer is atomic to the LPDMA arbitration: it consists of an AHB read single, immediately followed by an AHB write single. It is granted by the arbiter once for both AHB transfers, based on the channel priority defined by LPDMA_CxCR.PRIO[1:0].

An arbitrated LPDMA requested link transfer consists of one 32-bit read from the linked-list data structure in the memory to one of the linked-list registers (LPDMA_CxTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR or LPDMA_CxLLR). Each 32-bit read from the memory is arbitrated with the same channel priority as for data transfers, in order to be scheduled over the master port.

The re arbitration occurs after each granted single transfer:

• • whatever how the requested data transfer is programmed:
  • – with a software request for a memory-to-memory transfer (LPDMA_CxTR2.SWREQ = 1)
  • – with a hardware request (LPDMA_CxTR2.SWREQ = 0) for a memory-to-peripheral transfer or a peripheral-to-memory transfer
• • whatever the hardware request type

When the requested data transfer is programmed with a hardware request from a peripheral (LPDMA_CxTR2.SWREQ = 0), the first memory read of a block is gated by the occurrence of the corresponding and selected hardware request, whatever the peripheral is source or destination of the transfer. This first read request to the memory is not taken into account earlier by the arbiter (not as soon as the block transfer is enabled and executable).

LPDMA arbitration

The LPDMA arbitration is directed from the 4-grade assigned channel priority (LPDMA_CxCR.PRIO[1:0]). The arbitration policy, as illustrated in Figure 86, is defined by:

• one high-priority traffic class (queue 3), dedicated to the assigned channels with priority 3, for time-sensitive channels

This traffic class is granted via a fixed-priority arbitration against any other low-priority traffic class. Within this class, requested single transfers are round-robin arbitrated.

• three low-priority traffic classes (queues 0, 1 or 2) for non time-sensitive channels with priority 0, 1 or 2

Each requested single transfer within this class is round-robin arbitrated, with a weight that is monotonically driven from the programmed priority:

• Requests with priority 0 are allocated to the queue 0.
• Requests with priority 1 are allocated and replicated to the queue 0 and queue 1.
• Requests with priority 2 are allocated and replicated to the queue 0, queue 1, and queue 2.
• Any queue 0, 1 or 2 equally grants any of its active input requests in a round-robin manner, provided there are simultaneous requests.
• Additionally, there is a second stage for the low-traffic with a round-robin arbiter that fairly alternates between simultaneous selected requests from queue 0, queue 1 and queue 2.

Figure 86. LPDMA arbitration policy

1. 1. RRA: round-robin arbitration
2. 2. FPA: fixed-priority arbitration

LPDMA arbitration and bandwidth

With this arbitration policy, the following is guaranteed:

• Equal maximum bandwidth between requests with same priority
• Reserved bandwidth (noted as \( B_{Q3} \) ) to the time-sensitive requests (with priority 3)
• Residual weighted bandwidth between different low-priority requests (priority 0 versus priority 1 versus priority 2).

The two following examples highlight that the weighted round-robin arbitration is driven by the programmed priorities:

• Example 1: basic application with two non time-sensitive LPDMA requests: req0 and req1. There are the following programming possibilities:
  • – If they are assigned with same priority, the allocated bandwidth by the arbiter to req0 ( \( B_{\text{req0}} \) ) is equal to the allocated bandwidth to req1 ( \( B_{\text{req1}} \) ).
    
    \[ B_{\text{req0}} = B_{\text{req1}} = 1/2 * (1 - B_{\text{Q3}}) \]
  • – If req0 is assigned to priority 0 and req1 to priority 1, the allocated bandwidth to req0 ( \( B_{\text{P0}} \) ) is 3 times less than the allocated bandwidth to req1 ( \( B_{\text{P1}} \) ).
    
    \[ B_{\text{req0}} = B_{\text{P0}} = 1/2 * 1/2 * (1 - B_{\text{Q3}}) = 1/4 * (1 - B_{\text{Q3}}) \]
    \[ B_{\text{req1}} = B_{\text{P1}} = (1/2 + 1) * 1/2 * (1 - B_{\text{Q3}}) = 3/4 * (1 - B_{\text{Q3}}) \]
  • – If req0 is assigned to priority 0 and req1 to priority 2, the allocated bandwidth to req0 ( \( B_{\text{P0}} \) ) is 5 times less than the allocated bandwidth to req1 ( \( B_{\text{P2}} \) ).
    
    \[ B_{\text{req0}} = B_{\text{P0}} = 1/2 * 1/3 * (1 - B_{\text{Q3}}) = 1/6 * (1 - B_{\text{Q3}}) \]
    \[ B_{\text{req1}} = B_{\text{P2}} = (1/2 + 1 + 1) * 1/3 * (1 - B_{\text{Q3}}) = 5/6 * (1 - B_{\text{Q3}}) \]

The above computed bandwidth calculation is based on a theoretical input request, always active for any LPDMA clock cycle. This computed bandwidth from the arbiter must be weighted by the frequency of the request given by the application, that cannot be always active and may be quite much variable from one LPDMA client (example I2C at 400 kHz) to another one (PWM at 1 kHz) than the above x3 and x5 ratios.

• Example 2: application where the user distributes a same non-null N number of LPDMA requests to every non time-sensitive priority 0, 1 and 2. The bandwidth calculation is then the following:
  • – The allocated bandwidth to the set of requests of priority 0 ( \( B_{\text{P0}} \) ) is
    
    \[ B_{\text{P0}} = 1/3 * 1/3 * (1 - B_{\text{Q3}}) = 1/9 * (1 - B_{\text{Q3}}) \]
  • – The allocated bandwidth to the set of requests of priority 1 ( \( B_{\text{P1}} \) ) is
    
    \[ B_{\text{P1}} = (1/3 + 1/2) * 1/3 * (1 - B_{\text{Q3}}) = 5/18 * (1 - B_{\text{Q3}}) \]
  • – The allocated bandwidth to the set of requests of priority 2 ( \( B_{\text{P2}} \) ) is
    
    \[ B_{\text{P2}} = (1/3 + 1/2 + 1) * 1/3 * (1 - B_{\text{Q3}}) = 11/18 * (1 - B_{\text{Q3}}) \]
  • – The allocated bandwidth to any request n ( \( B_n \) ) among the N requests of that priority Pi (i = 0 to 2) is \( B_n = 1/N * B_{\text{Pi}} \)
  • – The allocated bandwidth to any request n of priority 0i ( \( B_{n, P_i} \) ) is
    
    \[ B_{n, P_0} = 1/N * 1/9 * (1 - B_{\text{Q3}}) \]
    \[ B_{n, P_1} = 1/N * 5/18 * (1 - B_{\text{Q3}}) \]
    \[ B_{n, P_2} = 1/N * 11/18 * (1 - B_{\text{Q3}}) \]

In this example, when the master port bus bandwidth is not totally consumed by the time-sensitive queue 3, the residual bandwidth is such that 2.5 times less bandwidth is allocated to any request of priority 0 versus priority 1, and 5.5 times less bandwidth is allocated to any request of priority 0 versus priority 2.

More generally, assume that the following requests are present:

• • I requests ( \( I \geq 0 \) ) assigned to priority 0
  If \( I > 0 \) , these requests are noted from \( i = 0 \) to \( I-1 \) .
• • J requests ( \( J \geq 0 \) ) assigned to priority 1
  If \( J > 0 \) , these requests are noted from \( j = 0 \) to \( J-1 \) .
• • K requests ( \( K > 0 \) ) assigned to priority 2
  These requests are noted from \( k = 0 \) to \( K-1 \)
• • L requests ( \( L \geq 0 \) ) assigned to priority 3
  If \( L > 0 \) , these requests are noted from \( l = 0 \) to \( L-1 \) .

As \( B_{Q3} \) is the reserved bandwidth to time-sensitive requests, the bandwidth for each request L with priority 3 is:

• • \( B_l = B_{Q3} / L \) for \( L > 0 \) (else: \( B_l = 0 \) )

The bandwidth for each non-time sensitive queue is:

• • \( B_{Q0} = 1/3 * (1 - B_{Q3}) \)
• • \( B_{Q1} = 1/3 * (1 - B_{Q3}) \)
• • \( B_{Q2} = 1/3 * (1 - B_{Q3}) \)

The bandwidth for the set of requests with priority 0 is:

• • \( B_{P0} = I / (I + J + K) * B_{Q0} \)

The bandwidth for each request i with priority 0 is:

• • \( B_i = B_{P0} / I \) for \( L > 0 \) (else \( B_{P0} = 0 \) )

The bandwidth for the set of requests with priority 1 and routed to queue 0 is:

• • \( B_{P1,Q0} = J / (I + J + K) * B_{Q0} \)

The bandwidth for the set of requests with priority 1 and routed to queue 1 is:

• • \( B_{P1,Q1} = J / (J + K) * B_{Q1} \)

The total bandwidth for the set of requests with priority 1 is:

• • \( B_{P1} = B_{P1,Q0} + B_{P1,Q1} \)

The bandwidth for each request j with priority 1 is:

• • \( B_j = B_{P1} / J \) for \( J > 0 \) (else \( B_j = 0 \) )

The bandwidth for the set of requests with priority 2 and routed to queue 0 is:

• • \( B_{P2,Q0} = K / (I + J + K) * B_{Q0} \)

The bandwidth for the set of requests with priority 2 and routed to queue 1 is:

• • \( B_{P2,Q1} = K / (J + K) * B_{Q1} \)

The bandwidth for the set of requests with priority 2 and routed to queue 2 is:

• • \( B_{P2,Q2} = B_{Q2} \)

The total bandwidth for the set of requests with priority 2 is:

• • \( B_{P2} = B_{P2,Q0} + B_{P2,Q1} + B_{P2,Q2} \)

The bandwidth for each request k with priority 2 is:

• • \( B_k = B_{P2} / K \) ( \( K > 0 \) in the general case)

Thus finally the maximum allocated residual bandwidths for any i, j, k non-time sensitive request are:

• • in the general case (when there is at least one request k with a priority 2 (K > 0)):
  • – \( B_i = 1/I * 1/3 * I/(I + J + K) * (1 - B_{Q3}) \)
  • – \( B_j = 1/J * 1/3 * [J/(I + J + K) + J/(J + K)] * (1 - B_{Q3}) \)
  • – \( B_k = 1/K * 1/3 * [K/(I + J + K) + K/(J + K) + 1] * (1 - B_{Q3}) \)
• • in the specific case (when there is no request k with a priority 2 (K = 0)):
  • – \( B_i = 1/I * 1/2 * I/(I + J) * (1 - B_{Q3}) \)
  • – \( B_j = 1/J * 1/2 * [J/(I + J) + 1] * (1 - B_{Q3}) \)

Consequently, the LPDMA arbiter can be used as a programmable weighted bandwidth limiter, for each queue and more generally for each request/channel. The different weights are monotonically resulting from the programmed channel priorities.

18.4.12 LPDMA triggered transfer

A programmed LPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event, as defined by LPDMA_CxTR2.TRIGPOL[1:0] and LPDMA_CxTR2.TRIGSEL[4:0] (see Section 18.3.5 for the trigger selection).

The triggered transfer, as defined by the trigger mode in LPDMA_CxTR2.TRIGM[1:0], can be at LLI data transfer level, to condition the first single read of a block, or each programmed single read. The trigger mode can also be programmed to condition the LLI link transfer (see the TRIGM[1:0] description in LPDMA channel x transfer register 2 (LPDMA_CxTR2) for more details).

Trigger hit memorization and trigger overrun flag generation

The LPDMA monitoring of a trigger for a channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (respectively TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).

The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer. If a new trigger is detected, this hit is internally memorized to grant the next transfer, as long as the defined rising/falling edge and TRIGSEL[4:0] are not modified, and the channel is enabled.

Transferring a next LLI _n+1 , that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the possible memorized hit of the formerly defined LLI _n trigger.

Caution: After a first new trigger hit _n+1 is memorized, if another trigger hit _n+2 is detected and if the hit _n triggered transfer is still not completed, hit _n+2 is lost and not memorized. A trigger overrun flag is reported (LPDMA_CxSR.TOF = 1) and an interrupt is generated if enabled (if LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.

The figure below illustrates the trigger hit, memorization and overrun in the configuration example with a block-level trigger mode and a rising edge trigger polarity.

Figure 87. Trigger hit, memorization and overrun waveform

Note: The user can assign the same input trigger event to different channels. This can be used to trigger different channels on a broadcast trigger event.

18.4.13 LPDMA circular buffering with linked-list programming

LPDMA circular buffering for memory-to-peripheral and peripheral-to-memory transfers

For a circular buffering, with a continuous memory-to-peripheral (or peripheral-to-memory) transfer, the software must set up a channel with half-transfer and complete transfer events/interrupts generation (LPDMA_CxCR.HTIE = 1 and LPDMA_CxCR.TCIE = 1), in order to enable a concurrent buffer software processing.

LLI ₀ is configured for the first block transfer. A continuously-executed LLI ₁ is needed to restore the memory source (or destination) start address, for the memory-to-peripheral transfer (respectively the peripheral-to-memory transfer). LPDMA automatically reloads the initially programmed LPDMA_CxBR1.BNDT[15:0] when a block transfer is completed, and there is no need to restore LPDMA_CxBR1.

The figure below illustrates this programming with a LPDMA channel and a source circular buffer.

Figure 88. LPDMA circular buffer programming: update of the memory start address

If circular buffering must be executed after some other transfers over the shared LPDMA channel x, the before-last LLI _N-1 in memory is needed to configure the first block transfer. And the last LLI _N restores the memory source (or destination) start address in memory-to-peripheral transfer (respectively in peripheral-to-memory transfer).

The figure below illustrates this programming with a shared LPDMA channel, and a source circular buffer.

Figure 89. Shared LPDMA channel with circular buffering: update of the memory start address

18.4.14 LPDMA secure/nonsecure channel

The LPDMA controller is compliant with the TrustZone hardware architecture at channel level, partitioning all its resources so that they exist in one of the secure and nonsecure worlds at any given time.

Any channel x is a secure or a nonsecure hardware resource, as configured by LPDMA_SECCFGR.SECx.

When a channel x is configured in secure state by a secure and privileged agent, the following access control rules are applied:

• • A nonsecure read access to a register field of this channel is forced to return 0, except for LPDMA_SECCFGR, LPDMA_PRIVCFGR, LPDMA_RCFGLOCKR that are readable by a nonsecure agent.
• • A nonsecure write access to a register field of this channel has no impact.

When a channel x is configured in secure state, a secure agent can configure separately as secure or nonsecure the LPDMA data transfer from the source (LPDMA_CxTR1.SSEC) and the LPDMA data transfer to the destination (LPDMA_CxTR1.DSEC).

When a channel x is configured in secure state and in linked-list mode, the loading of the next linked-list data structure from the LPDMA memory into its register file, is automatically performed with secure transfers via the master port.

LPDMA generates the DMA channel state versus security, reflecting LPDMA_SECCFGR, to keep the other peripherals informed of the secure/nonsecure state of each LPDMA channel x.

LPDMA also generates a security illegal access pulse signal on an illegal nonsecure access to a secure LPDMA register. This signal is routed to the TrustZone interrupt controller.

When the secure software must switch a channel from a secure state to a nonsecure state, the secure software must abort the channel or wait until the secure channel is completed before switching. This is needed to dynamically re-allocate a channel to a next nonsecure transfer as a nonsecure software is not allowed to do so and must have LPDMA_CxCR.EN = 0 before the nonsecure software can reprogram the LPDMA_CxCR for a next transfer. The secure software may reset not only the channel x (LPDMA_CxCR.RESET = 1) but also the full channel x register file to its reset value.

18.4.15 LPDMA privileged/unprivileged channel

Any channel x is a privileged or unprivileged hardware resource, as configured by a privileged agent via LPDMA_PRIVCFG.R.PRIVx.

When a channel x is configured in a privileged state by a privileged agent, the following access control rules are applied:

• • An unprivileged read access to a register field of this channel is forced to return 0, except for LPDMA_PRIVCFG.R, LPDMA_SECCFG.R, that are readable by an unprivileged agent.
• • An unprivileged write access to a register field of this channel has no impact.

When a channel is configured in a privileged (or unprivileged) state, the source and destination data transfers are privileged (respectively unprivileged) transfers over the AHB master port.

When a channel is configured in a privileged (or unprivileged) state and in linked-list mode, the loading of the next linked-list data structure from the LPDMA memory into its register file, is automatically performed with privileged (respectively unprivileged) transfers, via the master port.

LPDMA generates a DMA channel state versus privilege, reflecting LPDMA_PRIVCFG.R, to keep the other peripherals informed of the privileged/unprivileged state of each DMA channel x.

Additionally, the LPDMA generates the privileged illegal access pulse signal on an illegal unprivileged access to a privileged LPDMA register. This signal may be used or not, depending on the product (see the system security section for more details).

When the privileged software must switch a channel from a privileged state to an unprivileged state, the privileged software must abort the channel or wait until that the privileged channel is completed before switching. This is needed to dynamically re-allocate a channel to a next unprivileged transfer as an unprivileged software is not allowed to do so, and must have LPDMA_CxCR.EN = 0 before the unprivileged software can reprogram the LPDMA_CxCR for a next transfer. The privileged software may reset not only the channel x (LPDMA_CxCR.RESET = 1) but also the full channel x register file to its reset value.

18.4.16 LPDMA error management

LPDMA is able to manage and report to the user a transfer error, as follows, depending on the root cause.

Data transfer error

On a bus access (as a AHB single) to the source or the destination:

• • The source or destination target reports an AHB error.
• • The programmed channel transfer is stopped (LPDMA_CxCR.EN cleared by the LPDMA hardware). The channel status register reports an idle state (LPDMA_CxSR.IDLEF = 1) and the data error (LPDMA_CxSR.DTEF = 1).
• • After a LPDMA data transfer error, the user must perform a debug session, taking care of the product-defined memory mapping of the source and destination, including the protection attributes.
• • After a LPDMA data transfer error, the user must issue a channel reset (set LPDMA_CxCR.RESET) to reset the hardware LPDMA channel data path before the user enables again the same channel for a next transfer.

Link transfer error

On a tentative update of a LPDMA channel register from the programmed LLI in the memory:

• • The linked-list memory reports an AHB error.
• • The programmed channel transfer is stopped (LPDMA_CxCR.EN cleared by the LPDMA hardware), the channel status register reports an idle state (LPDMA_CxSR.IDLEF = 1) and the link error (LPDMA_CxSR.ULEF = 1).
• • After a LPDMA link error, the user must perform a debug session, taking care of the product-defined memory mapping of the linked-list data structure (LPDMA_CxLBAR and LPDMA_CxLLR), including the protection attributes.
• • After a LPDMA link error, the user must explicitly write the linked-list register file (LPDMA_CxTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR), before the user enables again the same channel for a next transfer.

User setting error

On a tentative execution of a LPDMA transfer with an unauthorized user setting:

• • The programmed channel transfer is disabled (LPDMA_CxCR.EN forced and cleared by the LPDMA hardware) preventing the next unauthorized programmed data transfer from being executed. The channel status register reports an idle state (LPDMA_CxSR.IDLEF = 1) and a user setting error (LPDMA_CxSR.USEF = 1).
• • After a LPDMA user setting error, the user must perform a debug session, taking care of the LPDMA channel programming. A user setting error can be caused by one of the following:
  • – a programmed null source block size without a programmed update of this value from the next LLI _i (LPDMA_CxBR1.BNDT[15:0] = 0 and LPDMA_CxLLR.UB1 = 0)
  • – a programmed non-null source block size being not a multiple of the programmed data width of a source single transfer (LPDMA_CxBR1.BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0])

• – a programmed unaligned source start address, being not a multiple of the programmed data width of a source single transfer (LPDMA_CxSAR[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0])
• – a programmed unaligned destination start address, being not a multiple of the programmed data width of a destination single transfer (LPDMA_CxDAR[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0])
• – a programmed double-word source data width (LPDMA_CxTR1.SDW_LOG2[1:0] = 0b11)
• – a programmed double-word destination data width (LPDMA_CxTR1.DDW_LOG2[1:0] = 0b11)
• – a programmed linked-list item \( LLI_{n+1} \) with a null data transfer (LPDMA_CxLLR.UB1 = 1 and LPDMA_CxBR1.BNDT = 0)

18.4.17 LPDMA autonomous mode

To save dynamic power consumption while LPDMA executes the programmed linked-list transfers, LPDMA hardware automatically manages its own clock gating and generates a clock request output signal to the RCC, whenever the device is in Run, Sleep or Stop mode, provided that the RCC is programmed with the corresponding LPDMA enable control bits.

For more details about the RCC programming, refer to the RCC section of the reference manual.

For mode details about the availability of the LPDMA autonomous feature vs the device low-power modes, refer to Section 18.3.2 .

Note: design/firmware: In low power modes, DMA clock request is asserted upon a DMA request/trigger from an autonomous peripheral or upon a DMA trigger from an EXTI line.

The user can program and schedule the execution of a given LPDMA transfer at a \( LLI_n \) level of a LPDMA channel x, with LPDMA_CxTR2 as follows:

• • The software controls and conditions the input of a transfer with TRIGM[1:0], TRIGPOL[1:0], TRIGSEL[y ^(a) :0], SWREQ, and REQSEL[z ^(a) :0] for the input trigger and request.
• • The software controls and signals the output of a transfer with TCEM[1:0] for generating or not a transfer complete event, and generating or not an associated half-transfer event).

See LPDMA channel x transfer register 2 (LPDMA_CxTR2) for more details.

The output channel x transfer complete event, lpdma_chx_tc , can be programmed as a selected input trigger for a channel if this event is looped-back and connected at the LPDMA level (see Section 18.3.5 ), allowing autonomous and fine DMA inter-channel transfer scheduling, without needing a cleared transfer complete flag (TCF).

a. Refer to LPDMA channel x transfer register 2 (LPDMA_CxTR2) for y and z values.

A given LPDMA channel x asserts its clock request in one of the following conditions:

• • if the next transfer to be executed is programmed as conditioned by a trigger (LPDMA_CxTR2.TRIGPOL[1:0] and LPDMA_CxTR2.TRIGM[1:0]), only when the trigger hit occurs.
• • if the next transfer to be executed is not conditioned by a trigger:
  • – if LPDMA_CxTR2.SWREQ = 0, only when the hardware request is asserted by the selected peripheral
  • – if LPDMA_CxTR2.SWREQ = 1 (memory-to-memory, GPIO to/from memory), as soon as the LPDMA is enabled

The LPDMA channel x releases its clock request as soon as all the following conditions are met:

• • The transfer to be executed is completed.
• • The LPDMA channel x is not immediately ready and requested to execute the next transfer.
• • If a channel x interrupt was raised, all the flags of the status register that can cause this interrupt, are cleared by a software agent.

When one channel asserts its clock request, the LPDMA asserts its clock request to the RCC. When none channel asserts its clock request, the LPDMA releases its clock request to the RCC.

18.5 LPDMA in debug mode

When the microcontroller enters debug mode (core halted), any channel x can be individually either continued (default) or suspended, depending on the programmable control bit in the DBGMCU module.

Note: In debug mode, LPDMA_CxSR.SUSPF is not altered by a suspension from the programmable control bit in the DBGMCU module. In this case, LPDMA_CxSR.IDLEF can be checked to know the completion status of the channel suspension.

18.6 LPDMA in low-power modes

Table 153. Effect of low-power modes on LPDMA

1. Refer to Section 18.3.2 to know which Stop mode is supported.

18.7 LPDMA interrupts

There is one LPDMA interrupt line for each channel, and separately for each CPU (if several ones in the devices).

Table 154. LPDMA interrupt requests

A LPDMA channel x event may be:

• • a transfer complete
• • a half-transfer complete
• • a transfer error, due to either:
  • – a data transfer error
  • – an update link error
  • – a user setting error completed suspension
• • a trigger overrun

Note: When a channel x transfer complete event occurs, the output signal lpdma_chx_tc is generated as a high pulse of one clock cycle.

An interrupt is generated following any xx event, provided that both:

• • the corresponding interrupt event xx is enabled (LPDMA_CxCR.xxIE = 1)
• • the corresponding event flag is cleared (LPDMA_CxSR.xxT = 0). This means that, after a previous same xx event occurrence, a software agent must have written 1 into the corresponding xx flag clear control bit (write 1 into LPDMA_CxFR.xxT).

TCF (transfer complete) and HTF (half transfer) events generation is controlled by LPDMA_CxTR2.TCEM[1:0] as follows:

• • A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode LPDMA_CxTR2.TCEM[1:0].
• • A half-transfer event is a half-block transfer. A half-block transfer occurs when half of the source block size bytes (rounded-up integer of LPDMA_CxBR1.BNDT[15:0] / 2) is transferred to the destination.

See LPDMA channel x transfer register 2 (LPDMA_CxTR2) for more details.

A transfer error rises in one of the following situations:

1. • • during a single data transfer from the source or to the destination (DTEF)
   • • during an update of a LPDMA channel register from the programmed LLI in memory (ULEF)
   • • during a tentative execution of a LPDMA channel with an unauthorized setting (USEF)
2. The user must perform a debug session to correct the LPDMA channel programming versus the USEF root causes list (see Section 18.4.16 ).

A trigger overrun is described in Trigger hit memorization and trigger overrun flag generation .

18.8 LPDMA registers

The LPDMA registers must be accessed with an aligned 32-bit word data access.

18.8.1 LPDMA secure configuration register (LPDMA_SECCFGR)

Address offset: 0x000

Reset value: 0x0000 0000

A write access is ignored at bit level if the corresponding channel x is locked (LPDMA_RCFGLOCKR.LOCKx = 1).

A write access to this register must be secure and privileged. A read access is secure or nonsecure, privileged or unprivileged.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This register must be programmed at a bit level, at the initialization/closure of a LPDMA channel (when LPDMA_CxCR.EN = 0), to securely allocate individually any channel x to the secure or nonsecure world.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 SECx : secure state of channel x (x = 3 to 0)

0: nonsecure

1: secure

18.8.2 LPDMA privileged configuration register (LPDMA_PRIVCFGR)

Address offset: 0x004

Reset value: 0x0000 0000

A write access to this register must be privileged. A read access can be privileged or unprivileged, secure or nonsecure.

A write access is ignored at bit level if the corresponding channel x is locked (LPDMA_RCFGLOCKR.LOCKx = 1).

This register can mix secure and nonsecure information. If a channel x is configured as secure (LPDMA_SECCFGR.SECx = 1), the PRIVx bit can be written only by a secure (and privileged) agent.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This register must be programmed at a bit level, at the initialization/closure of a LPDMA channel (LPDMA_CxCR.EN = 0), to individually allocate any channel x to the privileged or unprivileged world.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 PRIVx : privileged state of channel x (x = 3 to 0)

0: unprivileged

1: privileged

18.8.3 LPDMA configuration lock register (LPDMA_RCFGLOCKR)

Address offset: 0x008

Reset value: 0x0000 0000

This register can be written by a software agent with secure privileged attribute in order to individually lock, for example at boot time, the secure privileged attributes of any DMA channel/resource (to lock the setting of LPDMA_SECCFGR, LPDMA_PRIVCFGR for any channel x, for example at boot time).

A read access may be privileged or unprivileged, secure or nonsecure.

Note: If TZEN = 0, this register cannot be written.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 LOCKx : lock the configuration of LPDMA_SECCFGR.SECx, LPDMA_PRIVCFGR.PRIVx until a global DMA reset (x = 3 to 0)

This bit is cleared after reset and, once set, it cannot be reset until a global DMA reset.

0: secure privilege configuration of the channel x is writable.

1: secure privilege configuration of the channel x is not writable.

18.8.4 LPDMA nonsecure masked interrupt status register (LPDMA_MISR)

Address offset: 0x00C

Reset value: 0x0000 0000

This register is a read register.

This is a nonsecure register, containing the masked interrupt status bit MISx for each nonsecure channel x (channel x configured with LPDMA_SECCFGR.SECx = 0). It is a logical OR of all the flags of LPDMA_CxSR, each source flag being enabled by the corresponding interrupt enable bit of LPDMA_CxCR.

Every bit is de-asserted by hardware when writing 1 to the corresponding flag clear bit in LPDMA_CxFCR.

If a channel x is in secure state (LPDMA_SECCFGR.SECx = 1), a read access to the masked interrupt status bit MISx of this channel x returns zero.

This register may mix privileged and unprivileged information, depending on the privileged state of each channel LPDMA_PRIVCFGR.PRIVx. A privileged software can read the full nonsecure interrupt status. An unprivileged software is restricted to read the status of unprivileged (and nonsecure) channel(s), other privileged bit fields returning zero.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 MISx : masked interrupt status of channel x (x = 3 to 0)

0: no interrupt occurred on nonsecure channel x

1: an interrupt occurred on nonsecure channel x

18.8.5 LPDMA secure masked interrupt status register (LPDMA_SMISR)

Address offset: 0x010

Reset value: 0x0000 0000

This is a secure read register, containing the masked interrupt status bit MISx for each secure channel x (LPDMA_SECCFGR.SECx = 1). It is a logical OR of all the LPDMA_CxSR flags, each source flag being enabled by the corresponding LPDMA_CxCR interrupt enable bit.

Every bit is de-asserted by hardware when securely writing 1 to the corresponding LPDMA_CxFCR flag clear bit.

This register does not contain any information about a nonsecure channel.

This register can mix privileged and unprivileged information, depending on the privileged state of each channel LPDMA_PRIVCFGR.PRIVx. A privileged software can read the full secure interrupt status. An unprivileged software is restricted to read the status of unprivileged and secure channels, other privileged bit fields returning zero.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 MISx : masked interrupt status of the secure channel x (x = 3 to 0)

0: no interrupt occurred on the secure channel x

1: an interrupt occurred on the secure channel x

18.8.6 LPDMA channel x linked-list base address register (LPDMA_CxLBAR)

Address offset: 0x050 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register must be written by a privileged software. It is either privileged readable or not, depending on the privileged state of the channel x LPDMA_PRIVCFGR.PRIVx.

This register is either secure or nonsecure depending on the secure state of the channel x (LPDMA_SECCFGR.SECx).

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This channel-based register is the linked-list base address of the memory region, for a given channel x, from which the LLIs describing the programmed sequence of the LPDMA transfers, are conditionally and automatically updated.

This 64-Kbyte aligned channel x linked-list base address is offset by the 16-bit LPDMA_CxLLR register that defines the word-aligned address offset for each LLI.

Bits 31:16 LBA[31:16] : linked-list base address of LPDMA channel x

Bits 15:0 Reserved, must be kept at reset value.

18.8.7 LPDMA channel x flag clear register (LPDMA_CxFCR)

Address offset: 0x05C+ 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This is a write register, secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx) and privileged or unprivileged, depending on the privileged state of the channel x (LPDMA_PRIVCFGR.PRIVx).

Bits 31:15 Reserved, must be kept at reset value.

1. • Bit 14 TOF : trigger overrun flag clear
     • 0: no effect
     • 1: clears the corresponding TOF flag
   • Bit 13 SUSPF : completed suspension flag clear
     • 0: no effect
     • 1: corresponding SUSPF flag cleared
   • Bit 12 USEF : user setting error flag clear
     • 0: no effect
     • 1: corresponding USEF flag cleared
   • Bit 11 ULEF : update link transfer error flag clear
     • 0: no effect
     • 1: corresponding ULEF flag cleared
   • Bit 10 DTEF : data transfer error flag clear
     • 0: no effect
     • 1: corresponding DTEF flag cleared
   • Bit 9 HTF : half-transfer flag clear
     • 0: no effect
     • 1: corresponding HTF flag cleared
   • Bit 8 TCF : transfer complete flag clear
     • 0: no effect
     • 1: corresponding TCF flag cleared
2. Bits 7:0 Reserved, must be kept at reset value.

18.8.8 LPDMA channel x status register (LPDMA_CxSR)

Address offset: 0x060 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0001

This is a read register, reporting the channel status.

This register is secure or nonsecure, depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of the channel (LPDMA_PRIVCFGR.PRIVx).

Bits 31:15 Reserved, must be kept at reset value.

• Bit 14 TOF : trigger overrun flag clear
  • 0: no effect
  • 1: clears the corresponding TOF flag

Bit 13 SUSPF : completed suspension flag
0: no completed suspension event
1: a completed suspension event occurred

Bit 12 USEF : user setting error flag
0: no user setting error event
1: a user setting error event occurred

Bit 11 ULEF : update link transfer error flag
0: no update link transfer error event
1: a master bus error event occurred while updating a linked-list register from memory

Bit 10 DTEF : data transfer error flag
0: no data transfer error event
1: a master bus error event occurred on a data transfer

Bit 9 HTF : half-transfer flag
0: no half-transfer event
1: a half-transfer event occurred
A half-transfer event is a half-block transfer that occurs when half of the bytes of the source block size (rounded-up integer of \( LPDMA\_CxBR1.BNDT[15:0] / 2 \) ) has been transferred to the destination.

Bit 8 TCF : transfer complete flag
0: no transfer complete event
1: a transfer complete event occurred
A transfer complete event is a block transfer complete or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode \( LPDMA\_CxTR2.TCEM[1:0] \) .

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 IDLEF : idle flag
0: channel not in idle state
1: channel in idle state
This idle flag is de-asserted by hardware when the channel is enabled ( \( LPDMA\_CxCR.EN = 1 \) ) with a valid channel configuration (no USEF to be immediately reported).
This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state).

18.8.9 LPDMA channel x control register (LPDMA_CxCR)

Address offset: 0x64 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of the channel x (LPDMA_PRIVCFGR.PRIVx).

This register is used to control a channel (activate, suspend, abort or disable it).

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 PRIO[1:0] : priority level of the channel x LPDMA transfer versus others

00: low priority, low weight

01: low priority, mid weight

10: low priority, high weight

11: high priority

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bits 21:17 Reserved, must be kept at reset value.

Bit 16 LSM : Link step mode

0: channel executed for the full linked-list and completed at the end of the last LLI (LPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0). Then LPDMA_CxBR1.BNDT[15:0] = 0.

1: channel executed once for the current LLI

First the block transfer is executed as defined by the current internal register file until LPDMA_CxBR1.BNDT[15:0] = 0). Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR. Then channel execution is completed.

Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.

Bit 15 Reserved, must be kept at reset value.

Bit 14 TOIE : trigger overrun interrupt enable

0: interrupt disabled

1: interrupt enabled

Bit 13 SUSPIE : completed suspension interrupt enable

0: interrupt disabled

1: interrupt enabled

Bit 12 USEIE : user setting error interrupt enable

0: interrupt disabled

1: interrupt enabled

1. Bit 11 ULEIE : update link transfer error interrupt enable
   0: interrupt disabled
   1: interrupt enabled
2. Bit 10 DTEIE : data transfer error interrupt enable
   0: interrupt disabled
   1: interrupt enabled
3. Bit 9 HTIE : half-transfer complete interrupt enable
   0: interrupt disabled
   1: interrupt enabled
4. Bit 8 TCIE : transfer complete interrupt enable
   0: interrupt disabled
   1: interrupt enabled
5. Bits 7:3 Reserved, must be kept at reset value.
6. Bit 2 SUSP : suspend
   Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else:
   Software must write 1 in order to suspend an active channel (with an ongoing DMA transfer over its master ports).
   The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in Figure 74 .
   0: write: resume channel, read: channel not suspended
   1: write: suspend channel, read: channel suspended.
7. Bit 1 RESET : reset
   This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following:
   - active channel in suspended state (LPDMA_CxSR.SUSPF = 1 and LPDMA_CxSR.IDLEF = LPDMA_CxCR.EN = 1)
   - channel in disabled state (LPDMA_CxSR.IDLEF = 1 and LPDMA_CxCR.EN = 0).
   After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR) before enabling again the channel (see the programming sequence in Figure 75 ).
   0: no channel reset
   1: channel reset
8. Bit 0 EN : enable
   Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else:
   this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, for example: if LSM = 1 at the end of a single execution of the LLI).
   Else, this bit can be asserted by software.
   Writing 0 into this EN bit is ignored.
   0: write: ignored, read: channel disabled
   1: write: enable channel, read: channel enabled

18.8.10 LPDMA channel x transfer register 1 (LPDMA_CxTR1)

Address offset: 0x090 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx) except for secure DSEC and SSEC, privileged or unprivileged, depending on the privileged state of the channel x in LPDMA_PRIVCFGR.PRIVx.

This register controls the transfer of a channel x.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This register must be written when the channel is completed. Then the hardware has deasserted LPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block or LLI or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by LPDMA from the memory if LPDMA_CxLLR.UT1 = 1.

Bit 31 DSEC : security attribute of the LPDMA transfer to the destination

If LPDMA_SECCFGR.SECx = 1 and the access is secure:

0: LPDMA transfer nonsecure

1: LPDMA transfer secure

This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0.

When LPDMA_SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as nonsecure), and the LPDMA transfer to the destination is nonsecure.

Bits 30:20 Reserved, must be kept at reset value.

Bit 19 DINC : destination incrementing single

0: fixed single

1: contiguously incremented single

The destination address, pointed by LPDMA_CxDAR, is kept constant after a single transfer, or is incremented by the offset value corresponding to a contiguous data after a single transfer.

Bit 18 Reserved, must be kept at reset value.

Bits 17:16 DDW_LOG2[1:0] : binary logarithm of the destination data width of a single in bytes

00: byte

01: half-word (2 bytes)

10: word (4 bytes)

11: user setting error reported and no transfer issued

Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued.

A destination single transfer must have an aligned address with its data width (start address LPDMA_CxDAR[2:0] versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and none transfer is issued.

Bit 15 SSEC : security attribute of the LPDMA transfer from the source

If LPDMA_SECCFGR.SECx = 1 and the access is secure:

0: LPDMA transfer nonsecure

1: LPDMA transfer secure

This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx = 1. A secure write is ignored when LPDMA_SECCFGR.SECx = 0.

When LPDMA_SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as nonsecure), and the LPDMA transfer from the source is nonsecure.

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 PAM : padding/alignment mode

If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a single destination transfer is equal to the data width of a single source transfer, this bit is ignored.

Else, in the following enumerated values, the condition PAM_1 is when destination data width is higher than source data width, and the condition PAM_2 is when destination data width is higher than source data width.

Condition: PAM_1

0: source data is transferred as right aligned, padded with 0s up to the destination data width

1: source data is transferred as right aligned, sign extended up to the destination data width

Condition: PAM_2

0: source data is transferred as right aligned, left-truncated down to the destination data width

1: source data is transferred as left-aligned, right-truncated down to the destination data width

Bits 10:4 Reserved, must be kept at reset value.

Bit 3 SINC : source incrementing single

0: fixed single

1: contiguously incremented single

The source address, pointed by LPDMA_CxSAR, is kept constant after a single transfer or is incremented by the offset value corresponding to a contiguous data after a single transfer.

Bit 2 Reserved, must be kept at reset value.

Bits 1:0 SDW_LOG2[1:0] : binary logarithm of the source data width of a single in bytes

00: byte

01: half-word (2 bytes)

10: word (4 bytes)

11: user setting error reported and no transfer issued

Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued.

a source block size must be a multiple of the source data width

(LPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued.

A source single transfer must have an aligned address with its data width (start address LPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.

18.8.11 LPDMA channel x transfer register 2 (LPDMA_CxTR2)

Address offset: 0x094 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (LPDMA_PRIVCFGR.PRIVx).

This register controls the transfer of a channel x.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (the hardware de-asserted LPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block or LLI or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by LPDMA from the memory, if LPDMA_CxLLR.UT2 = 1.

These bits define the transfer granularity for the transfer complete and half-transfer complete events generation.

00: at block level (when LPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.

Note: If the initial LLI ₀ data transfer is null/void (directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half-transfer event is generated.

01: same as 00

10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half-transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer), if any data transfer.

Note: If the initial LLI ₀ data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0] = 0), then the half-transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI ₁ .

11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half-transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address LPDMA_CxLLR.LA[15:2] to zero and clears all the LPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL). If the channel transfer is continuous/infinite, no event is generated.

Bits 29:26 Reserved, must be kept at reset value.

These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0].

00: no trigger (masked trigger event)

01: trigger on the rising edge

10: trigger on the falling edge

11: same as 00

Bits 23:21 Reserved, must be kept at reset value.

These bits select the trigger event input of the LPDMA transfer (as per Section 18.3.5 ), with an active trigger event if TRIGPOL[1:0] = 00.

These bits define the transfer granularity for its conditioning by the trigger.

If the channel x is enabled (LPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 0b00 or 0b11, these TRIGM[1:0] bits are ignored.

Else, a DMA transfer is conditioned by at least one trigger hit:

00: at block level: the first single read of each block transfer is conditioned by one hit trigger.

01: same as 00

10: at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.

11: at programmed single level: each programmed single read is conditioned by one hit trigger.

The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loading with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 0b01 or respectively TRIGPOL[1:0] = 0b10).

The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[4:0] is not modified, and the channel is enabled.

Transferring a next LLI _n+1 that updates the LPDMA_CxTR2 with a new value for any of TRIGSEL[4:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLI _n trigger.

After a first new trigger hit _n+1 is memorized, if another second trigger hit _n+2 is detected and if the hit _n triggered transfer is still not completed, hit _n+2 is lost and not memorized, and a trigger overrun flag is reported (LPDMA_CxSR.TOF = 1), an interrupt is generated if enabled (LPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun.

Bits 13:12 Reserved, must be kept at reset value.

If the channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:

0: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a single level.

1: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 18.3.4 ).

Bit 10 Reserved, must be kept at reset value.

This bit is internally taken into account when LPDMA_CxCR.EN is asserted.

0: no software request. The selected hardware request REQSEL[4:0] is taken into account.

1: software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[4:0] is ignored.

Bits 8:5 Reserved, must be kept at reset value.

These bits are ignored if channel x is activated (LPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 18.3.3 .

Caution: The user must not assign a same input hardware request (same REQSEL[4:0] value) to different active DMA channels (LPDMA_CxCR.EN = 1 and LPDMA_CxTR2.SWREQ = 0 for these channels). DMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting.

18.8.12 LPDMA channel x block register 1 (LPDMA_CxBR1)

Address offset: 0x098 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (LPDMA_PRIVCFGR.PRIVx).

This register controls the transfer of a channel x at a block level.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This register must be written when channel x is completed (then the hardware has de-asserted LPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block, or LLI or full linked-list.

In linked-list mode, during the link transfer:

• • if LPDMA_CxLLR.UB1 = 1, this register is automatically updated by DMA from the next LLI in memory.
• • If LPDMA_CxLLR.UB1 = 0 and if there is at least one linked-list register to be updated from the next LLI in memory, this register is automatically and internally restored with the programmed values for the field BNDT[15:0].
• • If all the update bits LPDMA_CxLLR.Uxx are null and if LPDMA_CxLLR.LA[15:0] # 0, the current LLI is the last one and is continuously executed: this register is automatically and internally restored with the programmed value for BNDT[15:0] after each execution of this final LLI
• • If LPDMA_CxLLR = 0, this register and BNDT[15:0] are kept as null, channel x is completed.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BNDT[15:0] : block number of data bytes to transfer from the source

Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1.

Once the last data transfer is completed (BNDT[15:0] = 0):

• - if LPDMA_CxLLR.UB1 = 1, this field is updated with the LLI in the memory.
• - if LPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this field is internally restored to the programmed value.
• - if all LPDMA_CxLLR.Uxx = 0 and if LPDMA_CxLLR.LA[15:0] = 0, this field is internally restored to the programmed value (infinite/continuous last LLI).
• - if LPDMA_CxLLR = 0, this field is kept as zero following the last LLI data transfer.

Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.

18.8.13 LPDMA channel x source address register (LPDMA_CxSAR)

Address offset: \( 0x09C + 0x80 * x \) (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (LPDMA_PRIVCFGR.PRIVx).

This register configures the source start address of a transfer.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1, and continuously updated by hardware, in order to reflect the address of the next single transfer from the source.

This register must be written when the channel is completed (then the hardware has deasserted LPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block or LLI or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by LPDMA from the memory if LPDMA_CxLLR.USA = 1.

Bits 31:0 SA[31:0] : source address

This field is the pointer to the address from which the next data is read.

During the channel activity, depending on the source addressing mode (LPDMA_CxTR1.SINC), this field is either kept fixed or incremented by the data width (LPDMA_CxTR1.SDW_LOG2[1:0]) after each single source data, reflecting the next address from which data is read.

In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by LPDMA from the memory, provided the LLI is set with LPDMA_CxLLR.USA = 1.

Note: A source address must be aligned with the programmed data width of a source single (SA[32:0] versus LPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.

18.8.14 LPDMA channel x destination address register (LPDMA_CxDAR)

Address offset: 0x0A0 + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (LPDMA_PRIVCFGR.PRIVx).

This register configures the destination start address of a transfer.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1, and continuously updated by hardware, in order to reflect the address of the next single transfer to the destination.

This register must be written when the channel is completed (then the hardware has deasserted LPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block or LLI or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by LPDMA from the memory if LPDMA_CxLLR.UDA = 1.

Bits 31:0 DA[31:0] : destination address

This field is the pointer to the address from which the next data is written.

During the channel activity, depending on the destination addressing mode (LPDMA_CxTR1.DINC), this field is kept fixed or incremented by the data width (LPDMA_CxTR1.DDW_LOG2[1:0]) after each single destination data, reflecting the next address from which data is written.

In linked-list mode, after a LLI data transfer is completed, this register is automatically updated by DMA from the memory, provided the LLI is set with LPDMA_CxLLR.UDA = 1.

Note: A destination address must be aligned with the programmed data width of a destination single (DA[2:0] versus LPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is reported and no transfer is issued.

18.8.15 LPDMA channel x linked-list address register (LPDMA_CxLLR)

Address offset: 0x0CC + 0x80 * x (x = 0 to 3)

Reset value: 0x0000 0000

This register is secure or nonsecure depending on the secure state of channel x (LPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged state of channel x (LPDMA_PRIVCFGR.PRIVx).

This register configures the data structure of the next LLI in the memory and its address pointer. A channel transfer is completed when this register is null.

This register must be written when LPDMA_CxCR.EN = 0.

This register is read-only when LPDMA_CxCR.EN = 1.

This register must be written when the channel is completed (then the hardware has deasserted LPDMA_CxCR.EN). A channel transfer can be completed and programmed at different levels: block or LLI or full linked-list.

In linked-list mode, during the link transfer, this register is automatically updated by LPDMA from the memory if LPDMA_CxLLR.ULL = 1.

Bit 31 UT1 : Update LPDMA_CxTR1 from memory

This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer.

0: no LPDMA_CxTR1 update

1: LPDMA_CxTR1 update

Bit 30 UT2 : Update LPDMA_CxTR2 from memory

This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer.

0: no LPDMA_CxTR2 update

1: LPDMA_CxTR2 update

Bit 29 UB1 : Update LPDMA_CxBR1 from memory

This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer.

0: no LPDMA_CxBR1 update from memory and internally restored to the previous programmed value

1: LPDMA_CxBR1 update

Bit 28 USA : update LPDMA_CxSAR from memory

This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer.

0: no LPDMA_CxSAR update

1: LPDMA_CxSAR update

Bit 27 UDA : Update LPDMA_CxDAR register from memory

This bit is used to control the update of the LPDMA_CxDAR register from the memory during the link transfer.

0: no LPDMA_CxDAR update

1: LPDMA_CxDAR update

Bits 26:17 Reserved, must be kept at reset value.

Bit 16 ULL : Update LPDMA_CxLLR register from memory

This bit is used to control the update of the LPDMA_CxLLR register from the memory during the link transfer.
0: no LPDMA_CxLLR update
1: LPDMA_CxLLR update

Bits 15:2 LA[15:2] : pointer (16-bit low-significant address) to the next linked-list data structure

If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:2] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file.

Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file (LPDMA_CxTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR).

Caution: The user must program this pointer not to exceed the 64-Kbyte addressable space defined by the link base address register LPDMA_CxLBAR. The complete linked-list data structure must be included in the 64-Kbyte addressable space.

Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.

Bits 1:0 Reserved, must be kept at reset value.

18.8.16 LPDMA register map

Table 155. LPDMA register map and reset values

Table 155. LPDMA register map and reset values (continued)

Refer to Section 2.3: Memory organization for the register boundary addresses.