16. Peripherals interconnect matrix

16.1 Interconnect matrix introduction

Several peripherals have direct connections between them. This allows autonomous communication and or synchronization between peripherals, saving CPU resources, thus power supply consumption.

In addition, these hardware connections remove software latency and allow design of predictable system.

Depending on peripherals, these interconnections can operate in various power modes: Run, Sleep, Stop 0, Stop 1, and Stop 2 modes.

16.2 Connection summary

Table 134. Peripherals interconnect matrix ⁽¹⁾ (2)

1. Numbers in this table are links to corresponding subsections of Section 16.3 .

2. “-” means no interconnect.

16.3 Interconnection details

16.3.1 Master to slave interconnection for timers

From timer (TIM1/2/3/4/5/8/15/16/17) to timer (TIM1/2/3/4/5/8/15).

Purpose

Some of the TIMx timers are linked together internally for timer synchronization or chaining.

When one timer is configured in master mode, it can reset, start, stop, or clock the counter of another timer configured in slave mode.

A description of the feature is provided in Section 55.4.23: Timer synchronization .

The synchronization modes are detailed in:

• • Section 54.3.30 for advanced-control timers TIM1/TIM8
• • Section 55.4.22 for general-purpose timers TIM2/TIM3/TIM4/TIM5
• • Section 56.4.23 for the general-purpose timer TIM15

Triggering signals

The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/8) following a configurable timer event. It can be also from signals tim16_oc1 and tim17_oc1 in case of TIM16/17. The input (to slave) is on signals TIMx_ITR0/1/2/3.

The possible master/slave connections are given in:

• • Table 538 for advanced-control timers TIM1/8
• • Table 563 for general-purpose timers TIM2/3/4/5
• • Table 580 for the general-purpose timers TIM15

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 552: Effect of low-power modes on TIM1/TIM8
• • Table 572: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 587: Effect of low-power modes on TIM15/TIM16/TIM17

16.3.2 Triggers to ADCs

From EXTI, timers (TIM1/2/3/4/5/6/8/15/16/17) and LP timers (LPTIM1/ 2/3/4) to ADC1/ADC2

From EXTI, timers (TIM1/2/6/15) and LP timers (LPTIM1/3) to ADC4

Purpose

A conversion, or a sequence of conversions, can be triggered either by software or by an external event (such as timer capture or input pins). For ADC12, if the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events can trigger a conversion with the selected polarity.

More details in:

• • Section 33.4.19: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN[1:0], JEXTSEL, JEXTEN[1:0])
• • EXTEN[1:0] defined in ADC configuration register (ADC_CFGR1)
• • JEXTEN[1:0] defined in ADC injected sequence register (ADC_JSQR)

General-purpose timers (TIM2/3/4/5), basic timer (TIM6), advanced-control timers (TIM1/8) and general-purpose timer (TIM15/16/17) can be used to generate the ADC triggering event through the timer outputs tim_oc and tim_trgo.

Low-power timers (LPTIM1/2/3/4) can be used to generate the ADC triggering event through the LPTIM channels (TIMx synchronization described in Section 54.3.31: ADC triggers for TIM1/8) in addition to the EXTI on channels 11 and 15.

The ADC4 do not have injected channels. The general-purpose timers (TIM2/15), basic timers (TIM6), and advanced-control timers (TIM1) can be used to generate the ADC triggering event through the timer outputs tim_oc and tim_trgo. Low-power timers (LPTIM1/3) can be used to generate the ADC triggering event through the LPTIM channels in addition to EXTI on channel 11 and 15.

Triggering signals

For ADC1/ADC2, the input triggering signals and the description of the interconnection between ADC1/ADC2, and timers, are given in:

• • adc_ext_trgy: Table 307: ADC1/ADC12 external triggers for regular channels
• • adc_jext_trgy: Table 308: ADC1/ADC12 external triggers for injected channels
• • Section 33.4.19: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN[1:0], JEXTSEL, JEXTEN[1:0])
• • Section 33.4.25: Timing diagrams example (single/continuous modes, hardware/software triggers)

For ADC4, the input triggering signals list and the description of the interconnection between ADC4 and timers, are given in:

• • Table 329: ADC interconnection
• • Section 34.4.16: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)
• • Section 34.4.21: Example timing diagrams (single/continuous modes, hardware/software triggers)

Active power mode

This interconnection is active in Run and Sleep modes for all ADCs, and under Stop 0, Stop 1, and Stop 2 modes for ADC4 assuming that its trigger event line is active as well (such as LPTIM). The timers are active in Run and Sleep mode only. The effects of low-power modes are given in:

• • Table 552: Effect of low-power modes on TIM1/TIM8
• • Table 572: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 587: Effect of low-power modes on TIM15/TIM16/TIM17
• • Section 34.5: ADC in low-power modes for ADC4
• • Table 599: STM32U5 series LPTIM features
• • Table 614: Effect of low-power modes on the LPTIM

16.3.3 ADC analog watchdogs as triggers to timers

From ADC1/ADC4 to TIM1/3/8 on STM32U535/345/575/585.

From ADC1/ADC2/ADC4 to TIM1/3/4/8 on STM32U59x/5Ax/5Fx/5Gx.

Purpose

The internal analog watchdog output signals coming from ADC1/ADC2/ADC4, are connected to on-chip timers. ADC1/ADC2/ADC4 can provide trigger event through analog watchdog signals to advanced-control timers (TIM1/3/4/8) in order to reset, start, stop, or clock the counter.

Settings description of the ADC analog watchdog and timer trigger, are provided in:

• • Section 54.3.6: External trigger input for TIM1/8
• • Table 539 for the internal ADC1/ADC2/ADC4 sources connected to TIM1/8 (tim_etr) input multiplexer
• • Table 565 for the internal ADC1/ADC2 sources connected to TIM3/4 (tim_etr) input multiplexer
• • Section 33.4.29 for the ADC1/ADC2/ADC_AWDy_OUT signal output generation
• • Section 34.4.25 for the ADC4/ADC_AWDy_OUT signal output generation

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT, with n being the ADC instance and x = 1, 2, 3 (three watchdogs per ADC). The input (to timer) is on signal TIMx_ETR (external trigger).

Active power mode

ADC1/ADC2 and ADC4 are active in Run and Sleep modes.

The ADC4 conversion is functional and autonomous in Stop 0, Stop 1, and Stop 2 modes. This conversion can generate a wake-up interrupt and desired trigger action on timers.

16.3.4 Triggers to DAC

From timer (TIM1/2/4/5/6/7/8/15), Low-power timers (LPTIM1/3) and EXTI to DAC (DAC1/2)

Purpose

General-purpose timers (TIM2/4/5/15), basic timers (TIM6/7), advanced-control timers (TIM1/8), LP timers (LPTIM1/3) outputs channels (lptim1_ch1 and lptim3_ch1) and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals

The output (from timer) on the TIMx_TRGO signal and from LP timers are directly connected to corresponding DAC inputs.

The selection of input triggers on DAC is provided in:

• • Table 342: DAC interconnection
• • Section 35.4.8: DAC trigger selection

Active power mode

This interconnect is active in Run, Sleep, Stop 0, Stop 1, and Stop 2 modes.

16.3.5 Triggers on MDF1 or ADF1

From EXTI, ADF1, timers (TIM1/3/4/6/7/8/16) and LP timer (LPTIM1), to MDF1

From EXTI and MDF1 to ADF1

Purpose

General-purpose timers (TIM3/4/16), basic timers (TIM6/7), advanced-control timers (TIM1/8), low-power timer (LPTIM1), EXTI (EXTI11/15) and ADF1 can be used to generate a triggering event on MDF1 module and start an ADC conversion. In addition, EXTI15 and MDF1 can trigger ADF1.

A description is given in:

• • Section 39.4.2: MDF pins and internal signals
• • Section 39.4.11: Start-up sequence examples

Triggering signals

The mdf_trgi[13:0] trigger inputs are the triggering input signals. The MDF and ADF trigger inputs connections are detailed in:

• • Table 370: MDF trigger connections
• • Table 391: ADF trigger connections

Active power mode

This interconnection remains active down to Stop 0 and Stop 1 modes for MDF1, and Stop 0, Stop 1, and Stop 2 modes for ADF1, assuming the trigger source remains active.

16.3.6 Timer break from MDF1

From MDF1 to advanced-control timer (TIM1/8)

Purpose

The MDF features an out-of-limit detectors (OLD) and a short circuit detector (SCD) functions. When a short-circuit or open-circuit errors (such as over current or over voltage) is detected an interrupt event or/and a break signal can be generated to TIM1/8.

This behavior is described in:

• • Section 39.4.7: Short-circuit detectors (SCD)
• • Section 39.4.9: Out-of-limit detector (OLD)
• • Section 54.3.18: Using the break function
• • Section 54.3.19: Bidirectional break inputs

Triggering signals

The mdf1_break[0:3] output signals are connected to break1 and break2 inputs signals of TIM1/8. The tables below gives the assignment of break signals:

• • Table 371: MDF break connections
• • Table 541: Timer break interconnect
• • Table 542: Timer break2 interconnect

Active power mode

This interconnection is active under Run and Sleep modes. Refer to:

• • Section 39.4.14: Autonomous mode
• • Table 382: Effect of low-power modes on MDF

16.3.7 Clock sources to timers

From HSE, LSE, LSI, MSIK, HSI and MCO to timers (TIM1/2/3/4/5/8/15/16/17) and LP timers (LPTIM1/2/3)

Purpose

A timer input or timer counter can receive different clock sources and can be used to calibrate internal oscillator on a reference clock for example.

External clocks (HSE, LSE), internal clocks (LSI, MSI, HSI) and microcontroller output clock (MCO) can be used as input to timers:

• • MSIK/HSI are assigned to advanced-control timers TIM1/8 as external trigger signals inputs (tim_etr3/ tim_etr4). MSIK/HSI can be selected as counter clock provided by an external clock source in mode2: external trigger input (tim_etr_in). Inputs assignment and clock selection description are detailed in:
  • – Section 54.3.7: Clock selection for TIM1/8
  • – Table 539: Interconnect to the tim_etr input multiplexer for STM32U535/545/575/585 for TIM1/8
• • MSIK, HSI and LSI are assigned to general purpose timers TIM2/3/4/5 as external inputs signals. MSIK/HSI/LSI can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in). Inputs assignment and clock selection description are detailed in:
  • – Section 55.4.5: Clock selection for TIM2/3/4/5
  • – External clock mode1: Table 559: Interconnect to the tim_ti1 input multiplexer for TIM5, tim_ti1_in1 (LSI) and tim_ti1_in2 (LSE)
  • – External clock mode2: Table 565 , tim_etr3 (MSIK), tim_etr4 (HSI) and tim_etr5 (MSIS) for TIM2/TIM3/TIM4/TIM5
• • LSE, LSI, MSI and HSI are assigned to general purpose timers TIM15/16/17 as external inputs signals. LSE/LSI/MSI/HSI can be selected as counter clock provided by

an external clock source in mode1 (tim_ti1 or tim_ti2 signals). Inputs assignment and clock selection description are detailed in:

• – Table 56.4.6: Clock selection for TIM15/16/17. External clock mode1: external input pin (tim_ti1 or tim_ti2, if available)
• – Table 578: Interconnect to the tim_ti1 input multiplexer , tim_ti1_in1 (LSE-TIM15), tim_ti1_in5(LSE-TIM16/17), tim_ti1_in6 (LSI- TIM16/17), tim_ti1_in7/_8 (MSI-TIM16/17), and tim_ti1_in9 (HSI-TIM16/17)
• • Microcontroller output clock (MCO) is connected as external input to general-purpose timers TIM16/17. This allows the calibration of the HSI16/MSI system clocks (with TIM15/16 and LSE) or LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency. When the low-speed external (LSE) oscillator is used, no additional hardware connections are required. This feature is given in:
  • – Section 11.4.23: Internal/external clock measurement with TIM15/TIM16/TIM17/LPTIM1/LPTIM2
  • – Table 578: Interconnect to the tim_ti1 input multiplexer for TIM15/TIM16/TIM17
• • LSI and LSE can be selected as input capture 2 to LPTIM1 as described in Table 608: LPTIM1 input capture 2 connections .
• • HSI/256 can be selected as input capture 2 to LPTIM2 as described in Table 609: LPTIM2 input capture 2 connections .
• • MSI/1024 and MSI/4 can be selected as input capture 2 to LPTIM3 as described in Table 610: LPTIM3 input capture 2 connections .

Triggering signals

Lptim_ic2_mux1 LPTIM input capture selection can be set in the LPTIM configuration register 2 (LPTIM_CFGR2). For timers, the internal clock signal can be selected as counter clock provided by an external clock source in mode1 (tim_ti1_in) and mode2 (external trigger input tim_etr_in).

Active power mode

This feature is available under Run and Sleep modes.

16.3.8 Triggers to low-power timers

From comparators (COMP1/2), EXTI, TAMP and RTC alarm to LP timers (LPTIM1/2/3/4)

Purpose

LPTIM1/2/3/4 counters may be started either by software or after the detection of an active edge on one of the eight trigger inputs (see Section 58.4.7: Trigger multiplexer ).

GPIO can also be selected as LPTIM input capture selection or LPTIM input selection, according to the LPTIM configuration register 2 (LPTIM_CFGR2).

Triggering signals

This trigger feature is described in Section 58.4.7: Trigger multiplexer and the following sections. The input selection is described in Table 604: LPTIM1/2/3/4 external trigger connections .

Active power mode

This interconnection remains active down to Stop 2 mode.

16.3.9 Blanking sources to comparators

From timers (TIM1/2/3/4/5/8/15/16/17) to comparators (COMP1/2)

Purpose

Advanced-control timers (TIM1/8) and general-purpose timers (TIM2/3/4/5/15/16/17) can be used as blanking window input to COMP1/2.

The blanking function is described in Section 37.4.6: Comparator output-blanking function .

The blanking sources are given in:

• • COMP1 control and status register (COMP1_CSR) , BLANKSEL[4:0]
• • COMP2 control and status register (COMP2_CSR) , BLANKSEL[4:0]

Triggering signals

Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/2.

Active power mode

This feature is available under Run and Sleep modes.

16.3.10 RTC wake-up as inputs to timers

From RTC to timers (TIM5/16/17)

Purpose

RTC wake-up interrupt can be used as input to general-purpose timers (TIM5/16/17) channel 1.

Triggering signals

RTC wake-up signal is connected to tim_ti1_in3 signal as described in Table 559: Interconnect to the tim_ti1 input multiplexer for TIM5.

RTC wake-up signal is connected to tim_ti1_in4 signal as described in Table 578: Interconnect to the tim_ti1 input multiplexer for TIM16/TIM17.

Active power mode

This interconnection is active down to Stop 3 mode. Timers are not active but the count is performed at wake-up.

16.3.11 OTG_FS/OTG_HS SOF as trigger to timers

From OTG_FS/OTG_HS SOF to TIM2

Purpose

The OTG_FS/OTG_HS SOF (start-of-frame) can generate a trigger to the general-purpose timer TIM2. The OTG_FS/OTG_HS connection to TIM2 is described in Table 563: TIMx internal trigger connection .

Triggering signals

The tim_itr11 internal signal is generated by the OTG_FS/OTG_HS SOF.

Active power mode

This interconnection is active in Run and Sleep modes.

16.3.12 Comparators as inputs, trigger or break signals to timers

From comparators to timers (TIM1/2/3/4/5/8/15/16/17)

Purpose

The comparators (COMP1/2) output values can be connected to timers (TIM1/2/3/4/5/8/15/16/17) input captures, TIMx_ETR or timer break signals. The connection to ETR is described in Section 54.3.6: External trigger input .

Comparators (COMP1/2) output values can also generate break input signals for timers (such as TIM1 or TIM8). The sources for break (tim_brk) channel are one of the following:

• • external: connected to one of the TIMx_BKIN pin (as per selection done in the AFIO controller) with polarity selection and optional digital filtering
• • internal: coming from comparators, tim_brk_cmpx input (refer to Section 54.3.2: TIM1/TIM8 pins and internal signals for product specific implementation).

Triggering signals

The tim_etr and tim_brk signals connected TIM1/8 (coming from COMP1/2) are given in:

• • tim_etr ( Table 539: Interconnect to the tim_etr input multiplexer for STM32U535/545/575/585 ): external trigger internal input bus
  These inputs can be used as trigger, external clock or for hardware cycle-by-cycle pulse width control.
• • tim_brk ( Table 541: Timer break interconnect and Table 542: Timer break2 interconnect )
• • Section 54.3.6: External trigger input
• • Section 54.3.18: Using the break function

For TIM2/3/4/5, the sources connected to the tim_ti[1:4] input multiplexers coming from comparators and some other peripherals, are given in:

• • Table 559: Interconnect to the tim_ti1 input multiplexer
• • Table 560: Interconnect to the tim_ti2 input multiplexer
• • Table 562: Interconnect to the tim_ti4 input multiplexer
• • Table 539: Interconnect to the tim_etr input multiplexer for STM32U535/545/575/585

• • Table 540: Interconnect to the tim_etr input multiplex for STM2U59x/5Ax/5Fx/5Gx
• • Table 566: Interconnect to the tim_ocref_clr input multiplexer
• • Section 55.4.22: Timers and external trigger synchronization
• • TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5)

For TIM15/16/17, the sources connected to timers coming from comparators and other peripherals are given in:

• • Table 579: Interconnect to the tim_ti2 input multiplexer
• • Table 581: Timer break interconnect
• • Table 583: Interconnect to the ocref_clr input multiplexer
• • Section 56.4.15: Using the break function
• • Section 56.4.23: External trigger synchronization (TIM15 only)

Active power mode

Run, Sleep, and wake-up capability in Stop 0, Stop 1, and Stop 2 modes for trigger sources. Input and break remain active in same low-power modes as timers activity, on Run and Sleep modes.

16.3.13 System errors as break signals to timers

From system errors to timers (TIM1/8/15/16/17)

Purpose

CSS, CPU lockup, SRAM2/3 ECC double errors, FLASH ECC double-error detection and PVD can generate system errors in the form of timer break toward timers (TIM1/8/15/16/17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

Triggering signals

The possible sources of break are described in:

• • Section 54.3.18: Using the break function for TIM1/8
• • Section 56.4.15: Using the break function for TIM15/16/17
• • Table 543: System break interconnect for TIM1/8
• • Table 582: System break interconnect for TIM15/16/17

Active power mode

Timers are optionally active in Run and Sleep modes. The effects of low-power modes on TIMx are given in:

• • Table 552: Effect of low-power modes on TIM1/TIM8
• • Table 572: Effect of low-power modes on TIM2/TIM3/TIM4/TIM5
• • Table 587: Effect of low-power modes on TIM15/TIM16/TIM17

16.3.14 Timers generating IRTIM signal

From timers (TIM16/17) to IRTIM

The general-purpose timer (TIM16/17) output channels TIMx_OC1, are used to generate the waveform of the infrared signal output.

This functionality is described in Section 60: Infrared interface (IRTIM) .

16.3.15 Triggers for communication peripherals

From LP timers (LPTIM1/2/3), comparators (COMP1/2), GPDMA1 transfer complete, LPDMA1 transfer complete, EXTI, RTC alarm and RTC wake-up to USART1/2/3/6, UART4/5, LPUART1, I2C1/2/3/4/5/6, and SPI1/2/3.

Purpose

LP timer (LPTIM1/3) output channels (lptim1_ch1, lptim1_ch2 and lptim3_ch1), comparator (COMP1/2) output channels (comp1_out and comp2_out), EXTI, RTC alarm and RTC wake-up, can be used as trigger to start a communication on the selected USART, UART, LPUART, I2C, or SPI peripheral.

A GPDMA1 transfer complete can trigger both the GPDMA1 regular or linked-list new transfers and communication on selected communication peripheral.

A LPDMA1 transfer complete can trigger both the LPDMA1 new transfers and the communication on selected peripheral.

Triggering signals

The outputs from triggers are directly connected to peripheral trigger inputs.

The selection of input triggers is detailed in:

• • Table 677: USART interconnection (USART1/2/3/6 and UART4/5)
• • Table 689: LPUART interconnections (LPUART1)
• • Table 657: I2C1, I2C2, I2C4, I2C5, I2C6 interconnection and Table 658: I2C3 interconnection

The outputs (from timer) are directly connected to SPI1/2/3 inputs on signals spi_itrx (x = 6, 7). The selection of input triggers on SPI is provided in:

• • Table 699: SPI interconnection (SPI1 and SPI2)
• • Table 700: SPI interconnection (SPI3)

Active power mode

These interconnections remain active in Run, Sleep, and Stop modes if both source and communication line are autonomous under the mode. Refer to:

• • Section 66.6: USART in low-power modes
• • Section 65.5: I2C in low-power modes
• • Section 68.6: SPI in low-power modes

16.3.16 Triggers to GPDMA/LPDMA

From EXTI, RTC (alarm/wake-up), TAMP (TAMP1/2/3), timers (TIM2/15), LP timers (LPTIM1/3/4), comparators (COMP1/2), LP/GPDMA1 transfer complete (gpdma1_chx_tc/lpdma1_chx_tc), ADC1/4 analog watchdog, and LTDC, DSI, DMA2D, GPU2D, JPEG, to LPDMA1 and GPDMA1

Purpose

A LP/GPDMA trigger can be assigned to a LP/GPDMA channel x. A programmed LP/GPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event. The trigger mode can also be programmed to condition the LLI link transfer. More details are given in the sections below:

• • Section 18.3.5: LPDMA triggers and Section 17.3.5: GPDMA triggers
• • Section 18.4.12: LPDMA triggered transfer and Section 17.4.12: GPDMA triggered transfer
• • LPDMA channel x transfer register 2 (LPDMA_CxTR2) and GPDMA channel x transfer register 2 (GPDMA_CxTR2) for more details on:
  • – Trigger selection TRIGSEL[5:0] field
  • – Trigger mode (LLI) defined by TRIGM[1:0].
  • – Trigger polarity as defined by TRIGPOL[1:0]

Triggering signals

LPDMA trigger mapping is specified in Table 150: Programmed LPDMA1 trigger , according to LPDMA_CxTR2.TRIGSEL[5:0].

GPDMA trigger mapping is specified in Table 139: Programmed GPDMA1 trigger , according to GPDMA_CxTR2.TRIGSEL[5:0].

Active power mode

Assuming sources are active down to Stop modes, this interconnection remains functional in Stop 0 and Stop 1 modes for GPDMA, and Stop 0, Stop 1, and Stop 2 modes for LPDMA.

Refer to:

• • Section 18.6: LPDMA in low-power modes
• • Section 17.6: GPDMA in low-power modes

16.3.17 Internal analog signals to analog peripherals

From internal analog source to ADC (ADC1/2/4), comparators (COMP1/2) and OPAMP (OPAMP1/2)

Purpose

The internal reference voltage ( \( V_{REFINT} \) ), the internal temperature sensor ( \( V_{TS} \) ), and \( V_{BAT} \) monitoring channel are connected to ADC (ADC1/2/4) input channels. In addition, the internal digital core voltage ( \( V_{CORE} \) ) is connected to ADC1/2/4 input channels.

DAC channels (DAC1_OUT/DAC2_OUT) and VREFINT are connected to comparators (COMP1/2).

OPAMP1/2 outputs can be connected to ADC1 or ADC4 input channels through the GPIO. DAC1_OUT1 can be connected to OPAMP1_VINP. DAC1_OUT2 can be connected to OPAMP2_VINP.

Refer to Table 341: DAC internal input/output signals for:

• • dac_out1 analog output DAC channel1, output, for on-chip peripherals
• • dac_out2 analog output DAC channel2, output, for on-chip peripherals

This is according to:

• • Section 33.2 and Section 34.2: ADC main features
• • Section 33.4.11: Channel selection (SQRx, JSQRx)
• • Table 363: Operational amplifier possible connections
• • Section 37.4.2: COMP pins and internal signals

Active power mode

These interconnections remain in Stop modes if the selected peripheral is kept active.
Refer to:

• • Section 34.5: ADC in low-power modes
• • Section 37.5: COMP low-power modes
• • Section 38.4: OPAMP low-power modes

16.3.18 ADC data filtering by the MDF1

From ADC1/ADC2 to MDF1

Purpose

The MDF1 allows the connection of up to two ADCs to the filter path. For each filter, the DATSRC[1:0] field in the MDF digital filter configuration register x (MDF_DFLTxCICR) is used to select either data from the ADCs in:

• • Section 33.4.4: ADC connectivity
• • Table 372: MDF ADC data connections
  • – mdf_adcitf1_dat[15:0] to adc1_dat
  • – mdf_adcitf2_dat[15:0] to adc2_dat
• • Table 306: ADC1/ADC12 interconnection
  • – adc _x _dat[15:0] (x = 1) to mdf1_adc _x _dat[15:0] for STM32U535/545/575/585
  • – adc _x _dat[15:0] (x = 1, 2) mdf1_adc _x _dat[15:0] for STM32U59x/5Ax/5Fx/5Gx
• • Section 39.5: MDF low-power modes
  • – Stop 0 and Stop 1 modes

Active power mode

This feature remains available down to Sleep mode.

16.3.19 Clock source for the DAC sample and hold mode

LSI/LSE to DAC1/2

Purpose

DAC1/2 can run in Stop mode. The sample and hold block and its associated registers use the LSI or LSE clock source (dac_hold_ck) in Stop mode.

Table 341: DAC internal input/output signals:

dac_hold_ck, Input, DAC low-power clock used in sample and hold mode

Active power mode

This feature remains available down to Stop 2 mode.

16.3.20 Triggers from graphic interfaces to timers

From DCMI, LTDC, DSI to timers (TIM2/TIM3/TIM4/TIM5) (for STM32U59x/5Ax/5Fx/5Gx) and GFXTIM (for STM32U5Fx/5Gx)

Purpose

DCMI, LTDC and DSI synchronization signals can be used as triggering event to start the timers.

Triggering signals

The inputs (to DCMI, LTDC, and DSI) are directly connected to the timers (TIM2/3/4/5). External trigger as described in Table 565: Interconnect to the tim_etr input multiplexer for the STM32U59x/5Ax/5Fx/5Gx .

GFXTIM input trigger as described in Table 619: GFXTIM trigger interconnections .

Active power mode

This feature remains available down to Sleep mode. Refer to Section 68.6: SPI in low-power modes .

16.3.21 Internal tamper sources

From internal peripherals, clocks or monitoring to tamper.

Purpose

In order to detect any abnormal activity or tentative to corrupt the device, tampers are introduced and alert the system of such undesired event. Different actions can be taken in consequences.

List of tamper sources can be found in Table 644: TAMP interconnection .

Active power mode

This interconnection is active in all power modes if the tamper source is activated.

16.3.22 Output from tamper to RTC

From TAMP to RTC

Purpose

The RTC can timestamp a tamper event in order to retrieve history in time of such detection. The RTC can also control GPIOs and set a signal based on tamp or alarm status outside the MCU.

Refer to section Section 63.3.3: GPIOs controlled by the RTC and TAMP for more details.

Active power mode

This interconnection remains active in all power modes.

16.3.23 Encryption keys to AES/SAES

From TAMP backup registers, system flash memory to and in between SAES and AES

Purpose

The encryption mechanism requires a hardware key that must be stored in a protected non-volatile memory. Different approaches are implemented in order to load them in a non-readable way. Tamper backup registers or system flash memory can be used to store respectively BHK or RHUK, and to implement a dedicated bus to pass it to the SAES.

Refer to Section 50.4.9: SAES operation with wrapped keys for more details.

The AES encryption mechanism (faster than the SAES) can benefit from the sharing key of the SAES. Refer to Section 49.4.13: AES operation with shared keys for more details.

Active power mode

AES and SAES are operating under Run and Sleep modes.