14. Low-power general-purpose I/Os (LPGPIO)

14.1 Introduction

The low-power general-purpose input/output (LPGPIO) allows the I/O control in Stop mode (down to Stop 2 mode), using DMA in memory-to-memory transfer mode. LPGPIO is designed to be used in conjunction with the GPIO.

14.2 LPGPIO main features

• • 16 I/Os control in low-power modes down to Stop 2 mode
• • Secure clock and reset management
• • Output data from output data register (LPGPIO_ODR)
• • Input data to input data register (LPGPIO_IDR)
• • Bit set and reset register (LPGPIO_BSRR) for bitwise write access to LPGPIO_ODR
• • TrustZone security support

14.3 LPGPIO functional description

14.3.1 LPGPIO and GPIO configuration

The LPGPIO can control in input or output up to 16 I/Os thanks to LPGPIO_Py (y = 0 to 15) pins alternate functions. This control is still functional in Stop 2 mode, thanks to DMA transfers. The I/Os with a LPGPIO function must be configured as LPGPIO alternate function in GPIOx_MODER. Then the I/O value can be read in the LPGPIO input data register, and the I/O can be driven by the LPGPIO output data register or thanks to LPGPIO_BSRR/LPGPIO_BRR registers.

14.3.2 LPGPIO control registers

Each of the 16 I/Os controlled by the LPGPIO can be configured as input or output thanks to LPGPIO_MODER.

14.3.3 LPGPIO I/O data registers

The LPGPIO includes the following 16-bit data registers:

• • LPGPIO_ODR that stores the data to be output (read/write accessible)
• • LPGPIO_IDR that stores the data input through the I/O (read only)

14.3.4 LPGPIO I/O data bitwise handling

The 32-bit LPGPIO_BSRR is implemented to allow bitwise set and reset in LPGPIO_ODR.

Each LPGPIO_ODR bit has the following control bits in LPGPIO_BSRR:

• • LPGPIO_BSRR(i): when writing 1 to it, this bit sets the LPGPIO_ODR(i) bit.
• • LPGPIO_BSRR(i + 16): when writing 1 to it, this bit resets the LPGPIO_ODR(i) bit.

Note: Writing 0 to these bits has no effect on LPGPIO_ODR corresponding bits.

If there is an attempt to set and reset bits of the same index, the set action takes the priority.

Writing LPGPIO_BSRR register does not lock the LPGPIO_ODR bits, that can be anyway accessed directly. LPGPIO_BSRR provides a way to perform atomic bitwise handling.

The 16-bit LPGPIO_BRR allows individual bit reset. It is the same as LPGPIO_BSRR but with minimal pattern preparation:

• • LPGPIO_BRR(i): when writing 1 to it, this bit resets the LPGPIO_ODR(i) bit.

14.3.5 Security protection

The LPGPIO includes a security mechanism, that allows or locks the access to the I/O configuration and data registers. This system is used to protect the I/O against the data corruption or observation.

The security mechanism within the LPGPIO is directly issued from GPIOx_SECCFGR. Therefore, no additional configuration is required.

The LPGPIO security means the following:

• • When the executed code is secure, all bits can be accessed.
• • When the executed code is nonsecure, only the bits concerning the nonsecure I/Os can be accessed.

A nonsecure access to a secure I/O register bit is silent fail:

• • A nonsecure write to a secure I/O register bit is ignored (WI).
• • A nonsecure read to a secure I/O register bit returns 0 (RAZ).
• • No bus error is generated.

14.3.6 Secure clock and reset management

The LPGPIO clock and reset control bits in the RCC are automatically configured as secured as soon as at least one I/O with LPGPIO alternate function is secure (refer to the corresponding I/Os in GPIO_SECCFGR registers).

14.4 LPGPIO registers

This section gives a detailed description of the LPGPIO registers.

The peripheral registers can be written in word, half-word or byte mode.

14.4.1 LPGPIO port mode register (LPGPIO_MODER)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MODEy : Configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.

0: Input mode

1: Output mode

14.4.2 LPGPIO port input data register (LPGPIO_IDR)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDy : Input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.

14.4.3 LPGPIO port output data register (LPGPIO_ODR)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODy : Output data I/O pin y (y = 15 to 0)

These bits can be read and written by software.

Note: For atomic bit set/reset, these OD bits can be individually set and/or reset by writing to the LPGPIO_BSRR or LPGPIO_BRR registers.

14.4.4 LPGPIO port bit set/reset register (LPGPIO_BSRR)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:16 BRy : Reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns zero.

0: No action on the corresponding ODy bit

1: Reset the corresponding ODy bit.

Note: If both BSy and BRy are set, BSy has priority.

Bits 15:0 BSy : Port x set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns zero.

0: No action on the corresponding ODy bit

1: Set the corresponding ODy bit.

14.4.5 LPGPIO port bit reset register (LPGPIO_BRR)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BRy : Reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns zero.

0: No action on the corresponding ODy bit

1: Reset the corresponding ODy bit.

14.4.6 LPGPIO register map

Table 130. LPGPIO register map and reset values