2. Memory and bus architecture

2.1 System architecture

The STM32U5 series architecture relies on an Arm Cortex-M33 core optimized for execution thanks to an instruction cache having a direct access to the embedded flash memory.

This architecture also features a 32-bit multilayer AHB bus matrix that interconnects master and slave as shown in the tables below.

Table 1. Implementation of masters on STM32U5 Series

Table 2. Implementation of slaves on STM32U5 Series

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in the figure below.

Figure 1. System architecture

2.1.1 Fast C-bus

This bus connects the C-bus of the Cortex-M33 core to the internal flash memory and to the bus matrix via the instruction cache. This bus is used for instruction fetch and data access to the internal memories mapped in the code region. This bus targets the internal flash memory and the internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6).

SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6 are accessible on this bus with a continuous mapping.

2.1.2 Slow C-bus

This bus connects the C-bus of the Cortex-M33 core to the bus matrix via the instruction cache. This bus is used for instruction fetch and data access to the external memories mapped in the code region. This bus targets the external memories (FSMC, HSPI1, and OCTOSPIs).

2.1.3 S-bus

This bus connects the system bus of the Cortex-M33 core to the bus matrix. This bus is used by the core to access data located in a peripheral or SRAM area. This bus targets the internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM4, SRAM5, SRAM6, and BKPSRAM), the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the SRD peripherals.

SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6 are accessible on this bus with a continuous mapping.

Note: The bus matrix has a zero latency when accessing SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6.

2.1.4 DCACHE S-bus

This bus connects the system bus of the Cortex-M33 core to the bus matrix via the data cache. This bus is used for instruction fetch and data access to the external memories mapped in the data region. This bus targets the external memories (FSMC, HSPI1, GFXMMU, and OCTOSPIs).

Note: Fetching instructions through this bus is less efficient than fetching instructions through the slow C-bus.

2.1.5 GPDMA-bus

These buses connect the two AHB master interfaces of the GPDMA to the bus matrix. These buses target the internal flash memory, the internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM4, SRAM5, SRAM6, and BKPSRAM), the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals, the SRD peripherals and the external memories through FSMC, HSPI1, or OCTOSPIs.

2.1.6 OTG_HS-bus

This bus connects the OTG_HS master interface to the bus matrix. This bus is used only by the OTG_HS to load/store data from/to the memory. This bus targets the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6) and external memories through FSMC, HSPI1, or OCTOSPIs.

2.1.7 LTDC-bus

This bus connects the LTDC master interface to the bus matrix. This bus is used only to load data from the memory. This bus targets the GFXMMU in addition to the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6) and external memories through FSMC, HSPI1 or OCTOSPIs.

2.1.8 GPU2D-bus

These buses connect the GPU2D master interfaces to the bus matrix. These buses are used only by the GPU2D to load/store data from/to the memory. These buses target the GFXMMU in addition to the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6) and external memories through FSMC, HSPI1, or OCTOSPIs. A 16-Kbyte data cache (DCACHE2) is present on the GPU2D M0 bus in order to improve performances.

2.1.9 GFXMMU-bus

This bus connects the GFXMMU master interface to the bus matrix. This bus is used only by the GFXMMU to load/store data from/to the memory. This bus targets the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6) and external memories through FSMC, HSPI1, or OCTOSPIs. The GFXMMU has also a slave bus connection to be accessed by graphical peripheral master buses.

2.1.10 SDMMC1 and SDMMC2 controllers DMA buses

These buses connect the SDMMC1 and SDMMC2 DMA master interfaces to the bus matrix. These buses are used only by the SDMMC1 and SDMMC2 DMA to load/store data from/to the memory. These buses target the data memories: internal flash memory, internal SRAMs (SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6) and external memories through FSMC, HSPI1, or OCTOSPIs.

2.1.11 Bus matrix

The bus matrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm. This bus matrix features a fast bus multiplexer used to connect each master to a given slave without latency (see Figure 1 ). For the same master, other slaves undergo a latency of at least one cycle at each new access.

2.1.12 AHB/APB bridges

The three AHB/APB bridges provide full synchronous connections between the AHB and the APB buses, allowing flexible selection of the peripheral frequency.

Refer to Section 2.3.2: Memory map and register boundary addresses for the address mapping of the peripherals connected to these bridges.

After each device reset, all peripheral clocks are disabled (except for the internal SRAMs and flash memory interfaces). Before using a peripheral, its clock must be enabled in the RCC_AHBxENR and RCC_APBxENR registers.

Note: When an 8- or 16-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 8- or 16-bit data to feed the 32-bit vector.

2.1.13 SmartRun domain (SRD)

The SRD architecture relies on a DMA allowing autonomous operation during low-power modes down to Stop 2.

This architecture also features a 32-bit AHB bus matrix that interconnects:

• • two masters:
  • – the main AHB bus matrix
  • – LPDMA1 (low-power DMA featuring one master port)
• • two slaves:
  • – AHB3 peripherals including AHB to APB bridge connected to APB3
  • – internal SRAM4

Note: The SRAM4 is the only SRAM that can be accessed by the LPDMA1.

This architecture is shown in the figure below.

Figure 2. SmartRun domain architecture

2.2 Arm TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M mainline extension.

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.

When the TrustZone is enabled, the SAU (security-attribution unit) and IDAU (implementation-defined-attribution unit) define the access permissions based on secure and nonsecure states.

• • SAU: Up to eight SAU configurable regions are available for security attribution.
• • IDAU: provides a first memory partition as nonsecure or nonsecure callable attributes. The IDAU memory map partition is not configurable and fixed by hardware implementation (refer to Figure 3 to Figure 6 in Section 2.3.2: Memory map and register boundary addresses ). It is then combined with the results from the SAU security attribution and the higher security state is selected.

Based on IDAU security attribution, the flash memory, system SRAMs, and peripherals memory space are aliased twice for secure and nonsecure states. The external memories space is not aliased.

The table below shows an example of typical eight SAU regions mapping based on IDAU regions. The user can split and choose the secure, nonsecure or NSC regions for external memories as needed.

Table 3. Example of memory map security attribution versus SAU configuration regions

Table 3. Example of memory map security attribution versus SAU configuration regions

1. NSC = nonsecure callable

2.2.1 Default Arm TrustZone security state

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR, the default system security state is detailed below:

• • CPU:
  • – Cortex-M33 is in secure state after reset. The boot address must be at a secure address.
• • memory map:
  • – SAU is fully secure after reset. Consequently, all memory map is fully secure. Up to height SAU configurable regions are available for security attribution.
• • flash memory:
  • – The flash memory security area is defined by watermark user options.
  • – Flash block-based security attributions are nonsecure after reset.
• • SRAMs:
  • – All SRAMs are secure after reset. MPCBBx (block-based memory protection controller) are secure.
• • external memories:
  • – FSMC, HSPI1 and OCTOSPIs banks are secure after reset. MPCWMx (watermark-based memory protection controller) are secure.
• • peripherals (see Table 4 and Table 5 for a list of securable and TrustZone-aware peripherals)
  • – Securables peripherals are nonsecure after reset.
  • – TrustZone-aware peripherals are nonsecure after reset. Their secure configuration registers are secure.
• • all GPIOs secure after reset
• • interrupts:
  • – NVIC: All interrupts are secure after reset. NVIC is banked for secure and nonsecure state.
  • – TZIC: All illegal access interrupts are disabled after reset (see GTZC TrustZone system architecture ).

2.2.2 Arm TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-aware type as follows:

• • Securable: peripheral protected by an AHB/APB firewall gate that is controlled from TZSC controller to define security properties
• • TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing a specific TrustZone behavior such as a subset of registers being secure.

Refer to GTZC TrustZone system architecture for more details.

The tables below list the securable and TrustZone-aware peripherals within the system.

Table 4. Securable peripherals by TZSC

Table 4. Securable peripherals by TZSC (continued)

Table 4. Securable peripherals by TZSC (continued)

1. ICACHE and DCACHE1 are TrustZone-aware peripherals, regardless if access to their registers is secured by TZSC.

2. Only one COMP on STM32U535/545.

3. FDCAN1 is not present on STM32U5Fx devices.

Table 5. TrustZone aware peripherals

Table 5. TrustZone aware peripherals (continued)

1. Always secure when TZEN = 1.

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.3.2 Memory map and register boundary addresses

Figure 3. Memory map based on IDAU mapping for STM32U535/545

Figure 4. Memory map based on IDAU mapping for STM32U575/585

Figure 5. Memory map based on IDAU mapping for STM32U59x/5Ax

Figure 6. Memory map based on IDAU mapping for STM32U5Fx/5Gx

All memory-map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. The table below gives the boundary addresses of the peripherals available in the devices.

Table 6. Memory map and peripheral register boundary addresses

Table 6. Memory map and peripheral register boundary addresses (continued)

Table 6. Memory map and peripheral register boundary addresses (continued)

Table 6. Memory map and peripheral register boundary addresses (continued)

Table 6. Memory map and peripheral register boundary addresses (continued)

1. 1. Only one COMP in STM32U535/545.
2. 2. No dual ADC mode on STM32U535/545/575/585.
3. 3. MDF features only two filters in STM32U535/545.
4. 4. FDCAN1 is not present on STM32U5Fx devices.

2.3.3 Embedded SRAMs

Table 7. SRAM sizes

These SRAMs can be accessed as bytes, half-words (16 bits), or full words (32 bits). These memories can be addressed both by CPU and DMAs.

The CPU can access the SRAM1, SRAM2, SRAM3, SRAM5, and SRAM6 through the system bus, or through the C-bus depending on the selected address. The CPU can access the SRAM4 and BKPSRAM through the system bus only.

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can be programmed as nonsecure with a block granularity. For more details, refer to Section 5: Global TrustZone controller (GTZC) .

SRAM features are detailed in Section 6.3.1: Internal SRAMs features .

2.3.4 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • the main flash memory block, that contains the application program and user data
• • the information block, that is composed of the following parts:
  • – option bytes for hardware and memory protection user configuration
  • – system memory that contains ST proprietary code
  • – OTP (one-time programmable) area

The flash interface implements instruction access and data access based on the AHB protocol. It also implements the logic necessary to carry out the flash memory operations (program/erase) controlled through the FLASH registers plus security access control features. Refer to Section 7: Embedded flash memory (FLASH) for more details.