RM0456-STM32U5

This reference manual targets application developers. It provides complete information on how to use memory and peripherals of the STM32U5 series microcontrollers.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on the Arm ^®Cortex ^®-Mx cores, refer to the corresponding Arm ^®Technical Reference Manuals available on http://infocenter.arm.com .

STM32U5 series microcontrollers include ST state-of-the-art patented technology.

• STM32U535xx datasheet (DS14217)
• STM32U545xx datasheet (DS14216)
• STM32U535xx and STM32U545xx device errata sheet (ES0587)
• STM32U575xx datasheet (DS13737)
• STM32U585xx datasheet (DS13086)
• STM32U575xx and STM32U585xx device errata sheet (ES0499)
• STM32U59xxx datasheet (DS13633)
• STM32U5Axxx datasheet (DS13543)
• STM32U59xxx and STM32U5Axxx device errata sheet (ES0553)
• STM32U5Fxxx datasheet (DS14395)
• STM32U5Gxxx datasheet (DS14102)
• STM32U5Fxxx and STM32U5Gxxx device errata sheet (ES0595)
• STM32 Cortex ^®-M33 MCUs programming manual (PM0264)

1 Documentation conventions . . . . . 127
- 1.1 General information . . . . . 127
- 1.2 List of abbreviations for registers . . . . . 127
- 1.3 Register reset value . . . . . 128
- 1.4 Glossary . . . . . 128
- 1.5 Availability of peripherals . . . . . 128

2 Memory and bus architecture . . . . . 129
- 2.1 System architecture . . . . . 129
  - 2.1.1 Fast C-bus . . . . . 131
  - 2.1.2 . . . . . Slow C-bus 131
  - 2.1.3 S-bus . . . . . 132
  - 2.1.4 DCACHE S-bus . . . . . 132
  - 2.1.5 GPDMA-bus . . . . . 132
  - 2.1.6 OTG_HS-bus . . . . . 132
  - 2.1.7 LTDC-bus . . . . . 132
  - 2.1.8 GPU2D-bus . . . . . 132
  - 2.1.9 GFXMMU-bus . . . . . 133
  - 2.1.10 SDMMC1 and SDMMC2 controllers DMA buses . . . . . 133
  - 2.1.11 Bus matrix . . . . . 133
  - 2.1.12 AHB/APB bridges . . . . . 133
  - 2.1.13 SmartRun domain (SRD) . . . . . 133
- 2.2 Arm TrustZone security architecture . . . . . 134
  - 2.2.1 Default Arm TrustZone security state . . . . . 135
  - 2.2.2 Arm TrustZone peripheral classification . . . . . 136
- 2.3 Memory organization . . . . . 140
  - 2.3.1 Introduction . . . . . 140
  - 2.3.2 Memory map and register boundary addresses . . . . . 141
  - 2.3.3 Embedded SRAMs . . . . . 149
  - 2.3.4 Flash memory overview . . . . . 150

3 System security . . . . . 151
- 3.1 Key security features . . . . . 151

3.2	Secure install . . . . .	152
3.3	Secure boot . . . . .	152
3.3.1	Unique boot entry and BOOT_LOCK . . . . .	153
3.3.2	Immutable root of trust in system flash memory . . . . .	153
3.4	Secure update . . . . .	153
3.5	Resource isolation using TrustZone . . . . .	154
3.5.1	TrustZone security architecture . . . . .	154
3.5.2	Armv8-M security extension of Cortex-M33 . . . . .	155
3.5.3	Memory and peripheral allocation using IDAU/SAU . . . . .	155
3.5.4	Memory and peripheral allocation using GTZC . . . . .	157
3.5.5	Managing security in TrustZone-aware peripherals . . . . .	161
3.5.6	Activating TrustZone security . . . . .	168
3.5.7	Deactivating TrustZone security . . . . .	169
3.6	Other resource isolations . . . . .	169
3.6.1	Temporal isolation using secure hide protection (HDP) . . . . .	169
3.6.2	RSSLIB functions . . . . .	170
3.6.3	Resource isolation using Cortex privileged mode . . . . .	171
3.7	Secure execution . . . . .	175
3.7.1	Memory protection unit (MPU) . . . . .	175
3.7.2	Embedded flash memory write protection . . . . .	176
3.7.3	Tamper detection and response . . . . .	176
3.8	Secure storage . . . . .	178
3.8.1	Hardware secret key management . . . . .	179
3.8.2	Unique ID . . . . .	180
3.9	Cryptographic engines . . . . .	180
3.9.1	Cryptographic engines features . . . . .	180
3.9.2	Secure AES co-processor (SAES) . . . . .	181
3.9.3	On-the-fly decryption engine (OTFDEC) . . . . .	182
3.10	Product life-cycle . . . . .	182
3.10.1	Life-cycle management with readout protection (RDP) . . . . .	184
3.10.2	Recommended option-byte settings . . . . .	187
3.11	Access controlled debug . . . . .	187
3.11.1	Debug protection with readout protection (RDP) . . . . .	187
3.12	Software intellectual property protection and collaborative development . . . . .	188
3.12.1	Software intellectual property protection with RDP . . . . .	189
3.12.2	Software intellectual property protection with OTFDEC . . . . .	189

- 3.12.3 Other software intellectual property protections . . . . . 191
4 Boot modes . . . . . 192
5 Global TrustZone controller (GTZC) . . . . . 195
- 5.1 GTZC introduction . . . . . 195
- 5.2 GTZC main features . . . . . 195
- 5.3 GTZC implementation . . . . . 197
- 5.4 GTZC functional description . . . . . 200
  - 5.4.1 GTZC block diagram . . . . . 200
  - 5.4.2 Illegal access definition . . . . . 201
  - 5.4.3 TrustZone security controller (TZSC) . . . . . 201
  - 5.4.4 Memory protection controller - block based (MPCBB) . . . . . 203
  - 5.4.5 TrustZone illegal access controller (TZIC) . . . . . 203
  - 5.4.6 Power-on/reset state . . . . . 203
- 5.5 GTZC interrupts . . . . . 204
- 5.6 GTZC1 TZSC registers . . . . . 204
  - 5.6.1 GTZC1 TZSC control register (GTZC1_TZSC_CR) . . . . . 204
  - 5.6.2 GTZC1 TZSC secure configuration register 1 (GTZC1_TZSC_SECCFGR1) . . . . . 205
  - 5.6.3 GTZC1 TZSC secure configuration register 2 (GTZC1_TZSC_SECCFGR2) . . . . . 207
  - 5.6.4 GTZC1 TZSC secure configuration register 3 (GTZC1_TZSC_SECCFGR3) . . . . . 209
  - 5.6.5 GTZC1 TZSC privilege configuration register 1 (GTZC1_TZSC_PRIVCFGR1) . . . . . 212
  - 5.6.6 GTZC1 TZSC privilege configuration register 2 (GTZC1_TZSC_PRIVCFGR2) . . . . . 215
  - 5.6.7 GTZC1 TZSC privilege configuration register 3 (GTZC1_TZSC_PRIVCFGR3) . . . . . 216
  - 5.6.8 GTZC1 TZSC memory x sub-region z watermark configuration register (GTZC1_TZSC_MPCWMxzCFGR) (z = A to B) . . . . . 220
  - 5.6.9 GTZC1 TZSC memory x sub-region A watermark register (GTZC1_TZSC_MPCWMxAR) . . . . . 221
  - 5.6.10 GTZC1 TZSC memory x sub-region B watermark register (GTZC1_TZSC_MPCWMxBR) . . . . . 222
  - 5.6.11 GTZC1 TZSC register map . . . . . 222
- 5.7 GTZC1 TZIC registers . . . . . 225
  - 5.7.1 GTZC1 TZIC interrupt enable register 1 (GTZC1_TZIC_IER1) . . . . . 225

5.7.2	GTZC1 TZIC interrupt enable register 2 (GTZC1_TZIC_IER2) . . . . .	227
5.7.3	GTZC1 TZIC interrupt enable register 3 (GTZC1_TZIC_IER3) . . . . .	229
5.7.4	GTZC1 TZIC interrupt enable register 4 (GTZC1_TZIC_IER4) . . . . .	232
5.7.5	GTZC1 TZIC status register 1 (GTZC1_TZIC_SR1) . . . . .	235
5.7.6	GTZC1 TZIC status register 2 (GTZC1_TZIC_SR2) . . . . .	237
5.7.7	GTZC1 TZIC status register 3 (GTZC1_TZIC_SR3) . . . . .	239
5.7.8	GTZC1 TZIC status register 4 (GTZC1_TZIC_SR4) . . . . .	242
5.7.9	GTZC1 TZIC flag clear register 1 (GTZC1_TZIC_FCR1) . . . . .	245
5.7.10	GTZC1 TZIC flag clear register 2 (GTZC1_TZIC_FCR2) . . . . .	247
5.7.11	GTZC1 TZIC flag clear register 3 (GTZC1_TZIC_FCR3) . . . . .	248
5.7.12	GTZC1 TZIC flag clear register 4 (GTZC1_TZIC_FCR4) . . . . .	252
5.7.13	GTZC1 TZIC register map . . . . .	254
5.8	GTZC1 MPCBBz registers (z = 1, 2, 3, 5, 6) . . . . .	256
5.8.1	GTZC1 SRAMz MPCBB control register (GTZC1_MPCBBz_CR) (z = 1, 2, 3, 5, 6) . . . . .	256
5.8.2	GTZC1 SRAMz MPCBB configuration lock register 1 (GTZC1_MPCBBz_CFGLOCKR1) (z = 1, 2, 3, 5, 6) . . . . .	257
5.8.3	GTZC1 SRAMz MPCBB configuration lock register 2 (GTZC1_MPCBBz_CFGLOCKR2) (z = 1, 2, 3, 5, 6) . . . . .	257
5.8.4	GTZC1 SRAMz MPCBB security configuration for super-block x register (GTZC1_MPCBBz_SECCFGRx) (z = 1, 2, 3, 5, 6) . . . . .	258
5.8.5	GTZC1 SRAMz MPCBB privileged configuration for super-block x register (GTZC1_MPCBBz_PRIVCFGRx) (z = 1, 2, 3, 5, 6) . . . . .	258
5.8.6	GTZC1 MPCBBz register map (z = 1, 2, 3, 5, 6) . . . . .	259
5.9	GTZC2 TZSC registers . . . . .	260
5.9.1	GTZC2 TZSC control register (GTZC2_TZSC_CR) . . . . .	260
5.9.2	GTZC2 TZSC secure configuration register 1 (GTZC2_TZSC_SECCFGR1) . . . . .	260
5.9.3	GTZC2 TZSC privilege configuration register 1 (GTZC2_TZSC_PRIVCFGR1) . . . . .	262
5.9.4	GTZC2 TZSC register map . . . . .	263
5.10	GTZC2 TZIC registers . . . . .	264
5.10.1	GTZC2 TZIC interrupt enable register 1 (GTZC2_TZIC_IER1) . . . . .	264
5.10.2	GTZC2 TZIC interrupt enable register 2 (GTZC2_TZIC_IER2) . . . . .	265
5.10.3	GTZC2 TZIC status register 1 (GTZC2_TZIC_SR1) . . . . .	266
5.10.4	GTZC2 TZIC status register 2 (GTZC2_TZIC_SR2) . . . . .	267
5.10.5	GTZC2 TZIC flag clear register 1 (GTZC2_TZIC_FCR1) . . . . .	269
5.10.6	GTZC2 TZIC flag clear register 2 (GTZC2_TZIC_FCR2) . . . . .	270
5.10.7	GTZC2 TZIC register map . . . . .	271

5.11	GTZC2 MPCBB4 registers . . . . .	272
5.11.1	GTZC2 SRAM4 MPCBB control register (GTZC2_MPCBB4_CR) . . .	272
5.11.2	GTZC2 SRAM4 MPCBB configuration lock register 1 (GTZC2_MPCBB4_CFGLOCKR1) . . . . .	273
5.11.3	GTZC2 SRAM4 MPCBB security configuration for super-block 0 register (GTZC2_MPCBB4_SECCFGGR0) . . . . .	273
5.11.4	GTZC2 SRAM4 MPCBB privileged configuration for super-block 0 register (GTZC2_MPCBB4_PRIVCFGGR0) . . . . .	274
5.11.5	GTZC2 MPCBB4 register map . . . . .	274
6	RAM configuration controller (RAMCFG) . . . . .	276
6.1	RAMCFG introduction . . . . .	276
6.2	RAMCFG main features . . . . .	276
6.3	RAMCFG functional description . . . . .	276
6.3.1	Internal SRAMs features . . . . .	276
6.3.2	Error code correction (SRAM2, SRAM3, BKPSRAM) . . . . .	277
6.3.3	Write protection (SRAM2) . . . . .	280
6.3.4	Read access latency . . . . .	280
6.3.5	Software erase . . . . .	280
6.4	RAMCFG low-power modes . . . . .	281
6.5	RAMCFG interrupts . . . . .	281
6.6	RAMCFG registers . . . . .	282
6.6.1	RAMCFG memory x control register (RAMCFG_MxCR) . . . . .	282
6.6.2	RAMCFG memory x interrupt enable register (RAMCFG_MxIER) . . .	283
6.6.3	RAMCFG memory interrupt status register (RAMCFG_MxISR) . . . . .	283
6.6.4	RAMCFG memory x ECC single error address register (RAMCFG_MxSEAR) . . . . .	284
6.6.5	RAMCFG memory x ECC double error address register (RAMCFG_MxDEAR) . . . . .	285
6.6.6	RAMCFG memory x interrupt clear register x (RAMCFG_MxICR) . . .	285
6.6.7	RAMCFG memory 2 write protection register 1 (RAMCFG_M2WPR1) . . . . .	286
6.6.8	RAMCFG memory 2 write protection register 2 (RAMCFG_M2WPR2) . . . . .	286
6.6.9	RAMCFG memory x ECC key register (RAMCFG_MxECCKEYR) . . .	286
6.6.10	RAMCFG memory x erase key register (RAMCFG_MxERKEYR) . . .	287
6.6.11	RAMCFG register map . . . . .	287
7	Embedded flash memory (FLASH) . . . . .	291

7.1	FLASH introduction . . . . .	291
7.2	FLASH main features . . . . .	291
7.3	FLASH functional description . . . . .	292
7.3.1	Flash memory organization . . . . .	292
7.3.2	Error code correction (ECC) . . . . .	294
7.3.3	Read access latency . . . . .	295
7.3.4	Bank power-down mode . . . . .	297
7.3.5	Flash memory program and erase operations . . . . .	298
7.3.6	Flash main memory erase sequences . . . . .	299
7.3.7	Flash main memory programming sequences . . . . .	300
7.3.8	Flash memory endurance . . . . .	302
7.3.9	Flash memory errors flags . . . . .	302
7.3.10	Read-while-write (RWW) . . . . .	304
7.3.11	Power-down during FLASH programming or erase operation . . . . .	304
7.3.12	Reset during FLASH programming or erase operation . . . . .	304
7.4	FLASH option bytes . . . . .	305
7.4.1	Option bytes description . . . . .	305
7.4.2	Option-byte programming . . . . .	307
7.5	FLASH TrustZone security and privilege protections . . . . .	308
7.5.1	TrustZone security protection . . . . .	308
7.5.2	Watermark-based secure flash memory area protection . . . . .	309
7.5.3	Secure hide protection (HDP) . . . . .	310
7.5.4	Block-based secure flash memory area protection . . . . .	311
7.5.5	Flash security attribute state . . . . .	312
7.5.6	Block-based privileged flash memory area protection . . . . .	312
7.5.7	Flash memory registers privileged and unprivileged modes . . . . .	313
7.5.8	Flash memory bank attributes in case of bank swap . . . . .	313
7.6	FLASH memory protection . . . . .	314
7.6.1	Write protection (WRP) . . . . .	315
7.6.2	Readout protection (RDP) . . . . .	316
7.7	Flash memory and FLASH registers access control . . . . .	325
7.8	FLASH interrupts . . . . .	329
7.9	FLASH registers . . . . .	329
7.9.1	FLASH access control register (FLASH_ACR) . . . . .	329
7.9.2	FLASH nonsecure key register (FLASH_NSKEYR) . . . . .	331
7.9.3	FLASH secure key register (FLASH_SECKEYR) . . . . .	331

7.9.4 FLASH option key register (FLASH_OPTKEYR) . . . . . 332
7.9.5 FLASH bank 1 power-down key register (FLASH_PDKEY1R) . . . . . 332
7.9.6 FLASH bank 2 power-down key register (FLASH_PDKEY2R) . . . . . 333
7.9.7 FLASH nonsecure status register (FLASH_NSSR) . . . . . 333
7.9.8 FLASH secure status register (FLASH_SECSR) . . . . . 335
7.9.9 FLASH nonsecure control register (FLASH_NSCR) . . . . . 336
7.9.10 FLASH secure control register (FLASH_SECCR) . . . . . 338
7.9.11 FLASH ECC register (FLASH_ECCR) . . . . . 340
7.9.12 FLASH operation status register (FLASH_OPSR) . . . . . 341
7.9.13 FLASH option register (FLASH_OPTR) . . . . . 342
7.9.14 FLASH nonsecure boot address 0 register
(FLASH_NSBOOTADD0R) . . . . . 344
7.9.15 FLASH nonsecure boot address 1 register
(FLASH_NSBOOTADD1R) . . . . . 345
7.9.16 FLASH secure boot address 0 register (FLASH_SECBOOTADD0R) . 346
7.9.17 FLASH secure watermark1 register 1 (FLASH_SECWM1R1) . . . . . 347
7.9.18 FLASH secure watermark1 register 2 (FLASH_SECWM1R2) . . . . . 348
7.9.19 FLASH WRP1 area A address register (FLASH_WRP1AR) . . . . . 349
7.9.20 FLASH WRP1 area B address register (FLASH_WRP1BR) . . . . . 350
7.9.21 FLASH secure watermark2 register 1 (FLASH_SECWM2R1) . . . . . 351
7.9.22 FLASH secure watermark2 register 2 (FLASH_SECWM2R2) . . . . . 352
7.9.23 FLASH WPR2 area A address register (FLASH_WRP2AR) . . . . . 353
7.9.24 FLASH WPR2 area B address register (FLASH_WRP2BR) . . . . . 354
7.9.25 FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . . 355
7.9.26 FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . . 355
7.9.27 FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . . 356
7.9.28 FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . . 356
7.9.29 FLASH secure block based bank 1 register x (FLASH_SECB1Rx) . 357
7.9.30 FLASH secure block based bank 2 register x (FLASH_SECB2Rx) . 357
7.9.31 FLASH secure HDP control register (FLASH_SECHDPCR) . . . . . 358
7.9.32 FLASH privilege configuration register (FLASH_PRIVCFGR) . . . . . 358
7.9.33 FLASH privilege block based bank 1 register x
(FLASH_PRIVB1Rx) . . . . . 359
7.9.34 FLASH privilege block based bank 2 register x
(FLASH_PRIVB2Rx) . . . . . 360
7.9.35 FLASH register map . . . . . 360

8 Instruction cache (ICACHE) . . . . . 364

8.1	ICACHE introduction . . . . .	364
8.2	ICACHE main features . . . . .	364
8.3	ICACHE implementation . . . . .	365
8.4	ICACHE functional description . . . . .	366
8.4.1	ICACHE block diagram . . . . .	366
8.4.2	ICACHE reset and clocks . . . . .	367
8.4.3	ICACHE TAG memory . . . . .	367
8.4.4	Direct-mapped ICACHE (1-way cache) . . . . .	368
8.4.5	ICACHE enable . . . . .	369
8.4.6	Cacheable and noncacheable traffic . . . . .	370
8.4.7	Address remapping . . . . .	371
8.4.8	Cacheable accesses . . . . .	373
8.4.9	Dual-master cache . . . . .	374
8.4.10	ICACHE security . . . . .	374
8.4.11	ICACHE maintenance . . . . .	374
8.4.12	ICACHE performance monitoring . . . . .	375
8.4.13	ICACHE boot . . . . .	375
8.5	ICACHE low-power modes . . . . .	375
8.6	ICACHE error management and interrupts . . . . .	376
8.7	ICACHE registers . . . . .	376
8.7.1	ICACHE control register (ICACHE_CR) . . . . .	376
8.7.2	ICACHE status register (ICACHE_SR) . . . . .	377
8.7.3	ICACHE interrupt enable register (ICACHE_IER) . . . . .	378
8.7.4	ICACHE flag clear register (ICACHE_FCR) . . . . .	378
8.7.5	ICACHE hit monitor register (ICACHE_HMONR) . . . . .	379
8.7.6	ICACHE miss monitor register (ICACHE_MMONR) . . . . .	379
8.7.7	ICACHE region x configuration register (ICACHE_CRRx) . . . . .	379
8.7.8	ICACHE register map . . . . .	380
9	Data cache (DCACHE) . . . . .	382
9.1	DCACHE introduction . . . . .	382
9.2	DCACHE main features . . . . .	382
9.3	DCACHE implementation . . . . .	383
9.4	DCACHE functional description . . . . .	384
9.4.1	DCACHE block diagram . . . . .	384
9.4.2	DCACHE reset and clocks . . . . .	385

9.4.3	DCACHE TAG memory . . . . .	385
9.4.4	DCACHE enable . . . . .	387
9.4.5	Cacheable and noncacheable traffic . . . . .	387
9.4.6	Cacheable accesses . . . . .	388
9.4.7	DCACHE security . . . . .	390
9.4.8	DCACHE maintenance . . . . .	390
9.4.9	DCACHE performance monitoring . . . . .	392
9.4.10	DCACHE boot . . . . .	392
9.5	DCACHE low-power modes . . . . .	393
9.6	DCACHE error management and interrupts . . . . .	393
9.7	DCACHE registers . . . . .	394
9.7.1	DCACHE control register (DCACHE_CR) . . . . .	394
9.7.2	DCACHE status register (DCACHE_SR) . . . . .	395
9.7.3	DCACHE interrupt enable register (DCACHE_IER) . . . . .	396
9.7.4	DCACHE flag clear register (DCACHE_FCR) . . . . .	397
9.7.5	DCACHE read-hit monitor register (DCACHE_RHMONR) . . . . .	397
9.7.6	DCACHE read-miss monitor register (DCACHE_RMMONR) . . . . .	398
9.7.7	DCACHE write-hit monitor register (DCACHE_WHMONR) . . . . .	398
9.7.8	DCACHE write-miss monitor register (DCACHE_WMMONR) . . . . .	398
9.7.9	DCACHE command range start address register (DCACHE_CMDRSADRR) . . . . .	399
9.7.10	DCACHE command range end address register (DCACHE_CMDREADRR) . . . . .	399
9.7.11	DCACHE register map . . . . .	399
10	Power control (PWR) . . . . .	401
10.1	PWR introduction . . . . .	401
10.2	PWR main features . . . . .	401
10.3	PWR pins and internal signals . . . . .	401
10.4	PWR power supplies and supply domains . . . . .	404
10.4.1	External power supplies . . . . .	404
10.4.2	Internal regulators . . . . .	406
10.4.3	Power-up and power-down power sequences . . . . .	406
10.4.4	Independent analog peripherals supply . . . . .	406
10.4.5	Independent I/O supply rail . . . . .	407
10.4.6	Independent USB transceivers supply . . . . .	407
10.4.7	Battery backup domain (also known as RTC domain) . . . . .	408

10.5	PWR system supply voltage regulation . . . . .	409
10.5.1	SMPS and LDO embedded regulators . . . . .	409
10.5.2	LDO and SMPS versus reset, voltage scaling, and low-power modes	409
10.5.3	LDO and SMPS step down converter fast startup . . . . .	410
10.5.4	Dynamic voltage scaling management . . . . .	410
10.6	PWR power-supply supervision . . . . .	412
10.6.1	Brownout reset (BOR) . . . . .	412
10.6.2	Programmable voltage detector (PVD) . . . . .	412
10.6.3	Peripheral voltage monitoring (PVM) . . . . .	413
10.6.4	Backup domain voltage and temperature monitoring . . . . .	415
10.7	PWR power management . . . . .	415
10.7.1	Power modes . . . . .	415
10.7.2	Autonomous peripherals and low-power background autonomous mode (LPBAM) 422	422
10.7.3	Run mode . . . . .	424
10.7.4	Low-power modes . . . . .	424
10.7.5	Sleep mode . . . . .	425
10.7.6	Stop 0 mode . . . . .	426
10.7.7	Stop 1 mode . . . . .	429
10.7.8	Stop 2 mode . . . . .	429
10.7.9	Stop 3 mode . . . . .	431
10.7.10	Standby mode . . . . .	434
10.7.11	Shutdown mode . . . . .	436
10.7.12	USB power management in low-power modes (STM32U59x/5Ax/5Fx/5Gx only) . . . . .	438
10.7.13	Power modes output pins . . . . .	439
10.8	PWR security and privileged protection . . . . .	440
10.8.1	PWR security protection . . . . .	440
10.8.2	WR privileged protection . . . . .	441
10.9	PWR interrupts . . . . .	442
10.10	PWR registers . . . . .	443
10.10.1	PWR control register 1 (PWR_CR1) . . . . .	443
10.10.2	PWR control register 2 (PWR_CR2) . . . . .	445
10.10.3	PWR control register 3 (PWR_CR3) . . . . .	449
10.10.4	PWR voltage scaling register (PWR_VOSR) . . . . .	449
10.10.5	PWR supply voltage monitoring control register (PWR_SVMCR) . . . . .	451
10.10.6	PWR wake-up control register 1 (PWR_WUCR1) . . . . .	452

10.10.7	PWR wake-up control register 2 (PWR_WUCR2) . . . . .	453
10.10.8	PWR wake-up control register 3 (PWR_WUCR3) . . . . .	455
10.10.9	PWR backup domain control register 1 (PWR_BDCR1) . . . . .	456
10.10.10	PWR backup domain control register 2 (PWR_BDCR2) . . . . .	457
10.10.11	PWR disable backup domain register (PWR_DBPR) . . . . .	458
10.10.12	PWR UCPD register (PWR_UCPDR) . . . . .	458
10.10.13	PWR security configuration register (PWR_SECCFGR) . . . . .	459
10.10.14	PWR privilege control register (PWR_PRIVCFGR) . . . . .	461
10.10.15	PWR status register (PWR_SR) . . . . .	461
10.10.16	PWR supply voltage monitoring status register (PWR_SVMSR) . . . . .	462
10.10.17	PWR backup domain status register (PWR_BDSR) . . . . .	463
10.10.18	PWR wake-up status register (PWR_WUSR) . . . . .	464
10.10.19	PWR wake-up status clear register (PWR_WUSCR) . . . . .	465
10.10.20	PWR apply pull configuration register (PWR_APCR) . . . . .	466
10.10.21	PWR port A pull-up control register (PWR_PUCRA) . . . . .	466
10.10.22	PWR port A pull-down control register (PWR_PDCRA) . . . . .	467
10.10.23	PWR port B pull-up control register (PWR_PUCRB) . . . . .	468
10.10.24	PWR port B pull-down control register (PWR_PDCRB) . . . . .	468
10.10.25	PWR port C pull-up control register (PWR_PUCRC) . . . . .	469
10.10.26	PWR port C pull-down control register (PWR_PDCRC) . . . . .	469
10.10.27	PWR port D pull-up control register (PWR_PUCRD) . . . . .	470
10.10.28	PWR port D pull-down control register (PWR_PDCRD) . . . . .	470
10.10.29	PWR port E pull-up control register (PWR_PUCRE) . . . . .	471
10.10.30	PWR port E pull-down control register (PWR_PDCRE) . . . . .	471
10.10.31	PWR port F pull-up control register (PWR_PUCRF) . . . . .	472
10.10.32	PWR port F pull-down control register (PWR_PDCRF) . . . . .	472
10.10.33	PWR port G pull-up control register (PWR_PUCRG) . . . . .	473
10.10.34	PWR port G pull-down control register (PWR_PDCRG) . . . . .	473
10.10.35	PWR port H pull-up control register (PWR_PUCRH) . . . . .	474
10.10.36	PWR port H pull-down control register (PWR_PDCRH) . . . . .	474
10.10.37	PWR port I pull-up control register (PWR_PUCRI) . . . . .	475
10.10.38	PWR port I pull-down control register (PWR_PDCRI) . . . . .	475
10.10.39	PWR port J pull-up control register (PWR_PUCRJ) . . . . .	476
10.10.40	PWR port J pull-down control register (PWR_PDCRJ) . . . . .	477
10.10.41	PWR control register 4 (PWR_CR4) . . . . .	477
10.10.42	PWR control register 5 (PWR_CR5) . . . . .	478
10.10.43	PWR register map . . . . .	479

11	Reset and clock control (RCC) . . . . .	483
11.1	RCC introduction . . . . .	483
11.2	RCC pins and internal signals . . . . .	483
11.3	RCC reset functional description . . . . .	483
11.3.1	Power reset . . . . .	483
11.3.2	System reset . . . . .	484
11.3.3	Backup domain reset . . . . .	485
11.4	RCC clock functional description . . . . .	485
11.4.1	HSE clock . . . . .	488
11.4.2	HSI16 clock . . . . .	489
11.4.3	MSI (MSIS and MSIK) clocks . . . . .	489
11.4.4	HSI48 clock . . . . .	492
11.4.5	SHSI clock . . . . .	492
11.4.6	PLL . . . . .	493
11.4.7	LSE clock . . . . .	496
11.4.8	LSI clock . . . . .	497
11.4.9	System clock (SYSCLK) selection . . . . .	497
11.4.10	Clock source frequency versus voltage scaling . . . . .	498
11.4.11	Clock security system (CSS) . . . . .	498
11.4.12	Clock security system on LSE . . . . .	499
11.4.13	ADC and DAC clocks . . . . .	499
11.4.14	RTC and TAMP clock . . . . .	500
11.4.15	Timer clock . . . . .	500
11.4.16	Watchdog clock . . . . .	500
11.4.17	OCTOSPI clock . . . . .	500
11.4.18	HSPI1 clock . . . . .	501
11.4.19	OTG_HS clock . . . . .	501
11.4.20	DSI clock . . . . .	501
11.4.21	LTDC clock . . . . .	501
11.4.22	Clock-out capability . . . . .	501
11.4.23	Internal/external clock measurement with TIM15/TIM16/TIM17/LPTIM1/LPTIM2 502
11.4.24	Peripherals clock gating and autonomous mode . . . . .	503
11.5	RCC security and privilege functional description . . . . .	505
11.5.1	RCC TrustZone security protection modes . . . . .	505
11.5.2	RCC privilege protection modes . . . . .	508

11.6	RCC low-power modes . . . . .	509
11.7	RCC interrupts . . . . .	510
11.8	RCC registers . . . . .	512
11.8.1	RCC clock control register (RCC_CR) . . . . .	512
11.8.2	RCC internal clock sources calibration register 1 (RCC_ICSCR1) . . .	516
11.8.3	RCC internal clock sources calibration register 2 (RCC_ICSCR2) . . .	518
11.8.4	RCC internal clock sources calibration register 3 (RCC_ICSCR3) . . .	519
11.8.5	RCC clock recovery RC register (RCC_CRRRCR) . . . . .	520
11.8.6	RCC clock configuration register 1 (RCC_CFGR1) . . . . .	520
11.8.7	RCC clock configuration register 2 (RCC_CFGR2) . . . . .	522
11.8.8	RCC clock configuration register 3 (RCC_CFGR3) . . . . .	524
11.8.9	RCC PLL1 configuration register (RCC_PLL1CFGR) . . . . .	525
11.8.10	RCC PLL2 configuration register (RCC_PLL2CFGR) . . . . .	527
11.8.11	RCC PLL3 configuration register (RCC_PLL3CFGR) . . . . .	528
11.8.12	RCC PLL1 dividers register (RCC_PLL1DIVR) . . . . .	530
11.8.13	RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .	531
11.8.14	RCC PLL2 dividers configuration register (RCC_PLL2DIVR) . . . . .	532
11.8.15	RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . .	533
11.8.16	RCC PLL3 dividers configuration register (RCC_PLL3DIVR) . . . . .	534
11.8.17	RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . .	535
11.8.18	RCC clock interrupt enable register (RCC_CIER) . . . . .	536
11.8.19	RCC clock interrupt flag register (RCC_CIFR) . . . . .	537
11.8.20	RCC clock interrupt clear register (RCC_CICR) . . . . .	539
11.8.21	RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .	540
11.8.22	RCC AHB2 peripheral reset register 1 (RCC_AHB2RSTR1) . . . . .	542
11.8.23	RCC AHB2 peripheral reset register 2 (RCC_AHB2RSTR2) . . . . .	545
11.8.24	RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .	546
11.8.25	RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .	547
11.8.26	RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .	549
11.8.27	RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	550
11.8.28	RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .	552
11.8.29	RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .	553
11.8.30	RCC AHB2 peripheral clock enable register 1 (RCC_AHB2ENR1) . . .	556
11.8.31	RCC AHB2 peripheral clock enable register 2 (RCC_AHB2ENR2) . . .	560
11.8.32	RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .	561
11.8.33	RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . .	562
11.8.34	RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . .	564

11.8.35	RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	566
11.8.36	RCC APB3 peripheral clock enable register (RCC_APB3ENR) . . . . .	568
11.8.37	RCC AHB1 peripheral clock enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . .	569
11.8.38	RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1 (RCC_AHB2SMENR1) . . . . .	572
11.8.39	RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2 (RCC_AHB2SMENR2) . . . . .	576
11.8.40	RCC AHB3 peripheral clock enable in Sleep and Stop modes register (RCC_AHB3SMENR) . . . . .	577
11.8.41	RCC APB1 peripheral clock enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) . . . . .	579
11.8.42	RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) . . . . .	581
11.8.43	RCC APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) . . . . .	583
11.8.44	RCC APB3 peripheral clock enable in Sleep and Stop modes register (RCC_APB3SMENR) . . . . .	585
11.8.45	RCC SmartRun domain peripheral autonomous mode register (RCC_SRDRAMR) . . . . .	587
11.8.46	RCC peripherals independent clock configuration register 1 (RCC_CCIPR1) . . . . .	589
11.8.47	RCC peripherals independent clock configuration register 2 (RCC_CCIPR2) . . . . .	592
11.8.48	RCC peripherals independent clock configuration register 3 (RCC_CCIPR3) . . . . .	595
11.8.49	RCC backup domain control register (RCC_BDCR) . . . . .	597
11.8.50	RCC control/status register (RCC_CSR) . . . . .	600
11.8.51	RCC secure configuration register (RCC_SECCFGR) . . . . .	602
11.8.52	RCC privilege configuration register (RCC_PRIVCFGR) . . . . .	603
11.8.53	RCC register map . . . . .	604
12	Clock recovery system (CRS) . . . . .	610
12.1	CRS introduction . . . . .	610
12.2	CRS main features . . . . .	610
12.3	CRS implementation . . . . .	610
12.4	CRS functional description . . . . .	611
12.4.1	CRS block diagram . . . . .	611
12.4.2	CRS internal signals . . . . .	611
12.4.3	Synchronization input . . . . .	612

- 12.4.4 Frequency error measurement . . . . . 613
- 12.4.5 Frequency error evaluation and automatic trimming . . . . . 613
- 12.4.6 CRS initialization and configuration . . . . . 614
12.5 CRS in low-power modes . . . . . 615
12.6 CRS interrupts . . . . . 615
12.7 CRS registers . . . . . 616
- 12.7.1 CRS control register (CRS_CR) . . . . . 616
- 12.7.2 CRS configuration register (CRS_CFGR) . . . . . 617
- 12.7.3 CRS interrupt and status register (CRS_ISR) . . . . . 618
- 12.7.4 CRS interrupt flag clear register (CRS_ICR) . . . . . 620
- 12.7.5 CRS register map . . . . . 620

13 General-purpose I/Os (GPIO) . . . . . 622

13.1 Introduction . . . . . 622
13.2 GPIO main features . . . . . 622
13.3 GPIO functional description . . . . . 622
- 13.3.1 General-purpose I/O (GPIO) . . . . . 624
- 13.3.2 I/O pin alternate function multiplexer and mapping . . . . . 625
- 13.3.3 I/O port control registers . . . . . 625
- 13.3.4 I/O port data registers . . . . . 626
- 13.3.5 I/O data bitwise handling . . . . . 626
- 13.3.6 GPIO locking mechanism . . . . . 626
- 13.3.7 I/O alternate function input/output . . . . . 626
- 13.3.8 External interrupt/wake-up lines . . . . . 627
- 13.3.9 Input configuration . . . . . 627
- 13.3.10 Output configuration . . . . . 627
- 13.3.11 Alternate function configuration . . . . . 628
- 13.3.12 Analog configuration . . . . . 629
- 13.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . 629
- 13.3.14 Using the GPIO pins in the RTC supply domain . . . . . 629
- 13.3.15 Using PH3 as GPIO . . . . . 630
- 13.3.16 Using PA11 and PA12 as GPIOs (STM32U59x/5Ax/5Fx/5Gx only) . . . . . 630
- 13.3.17 OPAMPx_VINM dedicated pins . . . . . 630
- 13.3.18 TrustZone security . . . . . 630
- 13.3.19 Privileged and unprivileged modes . . . . . 631
- 13.3.20 High-speed low-voltage mode (HSLV) . . . . . 631

13.3.21	I/O compensation cell .....	632
13.4	GPIO registers .....	633
13.4.1	GPIO port mode register (GPIOx_MODER) (x = A to J) .....	633
13.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A to J) .....	634
13.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A to J) .....	634
13.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to J) .....	635
13.4.5	GPIO port input data register (GPIOx_IDR) (x = A to J) .....	635
13.4.6	GPIO port output data register (GPIOx_ODR) (x = A to J) .....	636
13.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A to J) .....	636
13.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A to J) .....	637
13.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A to J) .....	638
13.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A to J) .....	638
13.4.11	GPIO port bit reset register (GPIOx_BRR) (x = A to J) .....	639
13.4.12	GPIO high-speed low-voltage register (GPIOx_HSLVR) (x = A to J) .....	640
13.4.13	GPIO secure configuration register (GPIOx_SECCFGR) (x = A to J) .....	641
13.4.14	GPIO register map .....	641
14	Low-power general-purpose I/Os (LPGPIO) .....	643
14.1	Introduction .....	643
14.2	LPGPIO main features .....	643
14.3	LPGPIO functional description .....	643
14.3.1	LPGPIO and GPIO configuration .....	643
14.3.2	LPGPIO control registers .....	643
14.3.3	LPGPIO I/O data registers .....	643
14.3.4	LPGPIO I/O data bitwise handling .....	643
14.3.5	Security protection .....	644
14.3.6	Secure clock and reset management .....	644
14.4	LPGPIO registers .....	644
14.4.1	LPGPIO port mode register (LPGPIO_MODER) .....	644
14.4.2	LPGPIO port input data register (LPGPIO_IDR) .....	645
14.4.3	LPGPIO port output data register (LPGPIO_ODR) .....	645
14.4.4	LPGPIO port bit set/reset register (LPGPIO_BSRR) .....	646
14.4.5	LPGPIO port bit reset register (LPGPIO_BRR) .....	646
14.4.6	LPGPIO register map .....	647
15	System configuration controller (SYSCFG) .....	648
15.1	SYSCFG main features .....	648

15.2	SYSCFG functional description . . . . .	648
15.2.1	I/O compensation cell management . . . . .	648
15.2.2	SYSCFG TrustZone security and privilege . . . . .	649
15.2.3	Configuring the OTG_HS PHY (only for STM32U59x/5Ax/5Fx/5Gx) . . . . .	651
15.2.4	Adjusting HSPI supply capacitance (only for STM32U59x/5Ax/5Fx/5Gx) . . . . .	651
15.2.5	Internal SRAMs cacheability by DCACHE2 (only for STM32U59x/5Ax/5Fx/5Gx) . . . . .	651
15.3	SYSCFG registers . . . . .	652
15.3.1	SYSCFG secure configuration register (SYSCFG_SECCFGR) . . . . .	652
15.3.2	SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .	653
15.3.3	SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) . . . . .	655
15.3.4	SYSCFG CPU nonsecure lock register (SYSCFG_CNSLCKR) . . . . .	655
15.3.5	SYSCFG CPU secure lock register (SYSCFG_CSLCKR) . . . . .	656
15.3.6	SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .	657
15.3.7	SYSCFG memory erase status register (SYSCFG_MESR) . . . . .	658
15.3.8	SYSCFG compensation cell control/status register (SYSCFG_CCCSR) . . . . .	659
15.3.9	SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . .	661
15.3.10	SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . .	662
15.3.11	SYSCFG RSS command register (SYSCFG_RSSCMDR) . . . . .	663
15.3.12	SYSCFG OTG_HS PHY register (SYSCFG_OTGHSPHYCR) . . . . .	664
15.3.13	SYSCFG OTG_HS PHY tune register 2 (SYSCFG_OTGHSPHYTUNER2) . . . . .	665
15.3.14	SYSCFG register map . . . . .	666
16	Peripherals interconnect matrix . . . . .	668
16.1	Interconnect matrix introduction . . . . .	668
16.2	Connection summary . . . . .	669
16.3	Interconnection details . . . . .	671
16.3.1	Master to slave interconnection for timers . . . . .	671
16.3.2	Triggers to ADCs . . . . .	671
16.3.3	ADC analog watchdogs as triggers to timers . . . . .	673
16.3.4	Triggers to DAC . . . . .	673
16.3.5	Triggers on MDF1 or ADF1 . . . . .	674
16.3.6	Timer break from MDF1 . . . . .	674
16.3.7	Clock sources to timers . . . . .	675

16.3.8	Triggers to low-power timers . . . . .	676
16.3.9	Blanking sources to comparators . . . . .	677
16.3.10	RTC wake-up as inputs to timers . . . . .	677
16.3.11	OTG_FS/OTG_HS SOF as trigger to timers . . . . .	678
16.3.12	Comparators as inputs, trigger or break signals to timers . . . . .	678
16.3.13	System errors as break signals to timers . . . . .	679
16.3.14	Timers generating IRTIM signal . . . . .	679
16.3.15	Triggers for communication peripherals . . . . .	680
16.3.16	Triggers to GPDMA/LPDMA . . . . .	680
16.3.17	Internal analog signals to analog peripherals . . . . .	681
16.3.18	ADC data filtering by the MDF1 . . . . .	682
16.3.19	Clock source for the DAC sample and hold mode . . . . .	682
16.3.20	Triggers from graphic interfaces to timers . . . . .	683
16.3.21	Internal tamper sources . . . . .	683
16.3.22	Output from tamper to RTC . . . . .	683
16.3.23	Encryption keys to AES/SAES . . . . .	684
17	General purpose direct memory access controller (GPDMA) . . . . .	685
17.1	GPDMA introduction . . . . .	685
17.2	GPDMA main features . . . . .	685
17.3	GPDMA implementation . . . . .	686
17.3.1	GPDMA channels . . . . .	686
17.3.2	GPDMA autonomous mode in low-power modes . . . . .	687
17.3.3	GPDMA requests . . . . .	687
17.3.4	GPDMA block requests . . . . .	691
17.3.5	GPDMA triggers . . . . .	691
17.4	GPDMA functional description . . . . .	694
17.4.1	GPDMA block diagram . . . . .	694
17.4.2	GPDMA channel state and direct programming without any linked-list	694
17.4.3	GPDMA channel suspend and resume . . . . .	695
17.4.4	GPDMA channel abort and restart . . . . .	696
17.4.5	GPDMA linked-list data structure . . . . .	697
17.4.6	Linked-list item transfer execution . . . . .	700
17.4.7	GPDMA channel state and linked-list programming in run-to-completion mode . . . . .	700
17.4.8	GPDMA channel state and linked-list programming in link step mode	704
17.4.9	GPDMA channel state and linked-list programming . . . . .	711

17.4.10	GPDMA FIFO-based transfers . . . . .	713
17.4.11	GPDMA transfer request and arbitration . . . . .	720
17.4.12	GPDMA triggered transfer . . . . .	724
17.4.13	GPDMA circular buffering with linked-list programming . . . . .	725
17.4.14	GPDMA secure/nonsecure channel . . . . .	727
17.4.15	GPDMA privileged/unprivileged channel . . . . .	728
17.4.16	GPDMA error management . . . . .	728
17.4.17	GPDMA autonomous mode . . . . .	730
17.5	GPDMA in debug mode . . . . .	731
17.6	GPDMA in low-power modes . . . . .	731
17.7	GPDMA interrupts . . . . .	732
17.8	GPDMA registers . . . . .	734
17.8.1	GPDMA secure configuration register (GPDMA_SECCFGR) . . . . .	734
17.8.2	GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . .	735
17.8.3	GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . .	735
17.8.4	GPDMA nonsecure masked interrupt status register (GPDMA_MISR) . . . . .	736
17.8.5	GPDMA secure masked interrupt status register (GPDMA_SMISR) . . . . .	737
17.8.6	GPDMA channel x linked-list base address register (GPDMA_CxLBAR) . . . . .	737
17.8.7	GPDMA channel x flag clear register (GPDMA_CxFCR) . . . . .	738
17.8.8	GPDMA channel x status register (GPDMA_CxSR) . . . . .	739
17.8.9	GPDMA channel x control register (GPDMA_CxCGR) . . . . .	740
17.8.10	GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . .	742
17.8.11	GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . .	746
17.8.12	GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . .	750
17.8.13	GPDMA channel x alternate block register 1 (GPDMA_CxBR1) . . . . .	751
17.8.14	GPDMA channel x source address register (GPDMA_CxSAR) . . . . .	754
17.8.15	GPDMA channel x destination address register (GPDMA_CxDAR) . . . . .	756
17.8.16	GPDMA channel x transfer register 3 (GPDMA_CxTR3) . . . . .	757
17.8.17	GPDMA channel x block register 2 (GPDMA_CxBR2) . . . . .	758
17.8.18	GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . . .	759
17.8.19	GPDMA channel x alternate linked-list address register (GPDMA_CxLLR) . . . . .	761
17.8.20	GPDMA register map . . . . .	762
18	Low-power direct memory access controller (LPDMA) . . . . .	765

18.1	LPDMA introduction . . . . .	765
18.2	LPDMA main features . . . . .	765
18.3	LPDMA implementation . . . . .	766
18.3.1	LPDMA channels . . . . .	766
18.3.2	LPDMA autonomous mode in low-power modes . . . . .	767
18.3.3	LPDMA requests . . . . .	767
18.3.4	LPDMA block requests . . . . .	767
18.3.5	LPDMA triggers . . . . .	768
18.4	LPDMA functional description . . . . .	770
18.4.1	LPDMA block diagram . . . . .	770
18.4.2	LPDMA channel state and direct programming without any linked-list . . . . .	770
18.4.3	LPDMA channel suspend and resume . . . . .	771
18.4.4	LPDMA channel abort and restart . . . . .	772
18.4.5	LPDMA linked-list data structure . . . . .	773
18.4.6	Linked-list item transfer execution . . . . .	775
18.4.7	LPDMA channel state and linked-list programming in run-to-completion mode . . . . .	775
18.4.8	LPDMA channel state and linked-list programming in link step mode . . . . .	780
18.4.9	LPDMA channel state and linked-list programming . . . . .	786
18.4.10	LPDMA direct transfers . . . . .	788
18.4.11	LPDMA transfer request and arbitration . . . . .	790
18.4.12	LPDMA triggered transfer . . . . .	794
18.4.13	LPDMA circular buffering with linked-list programming . . . . .	795
18.4.14	LPDMA secure/nonsecure channel . . . . .	797
18.4.15	LPDMA privileged/unprivileged channel . . . . .	798
18.4.16	LPDMA error management . . . . .	799
18.4.17	LPDMA autonomous mode . . . . .	800
18.5	LPDMA in debug mode . . . . .	801
18.6	LPDMA in low-power modes . . . . .	801
18.7	LPDMA interrupts . . . . .	802
18.8	LPDMA registers . . . . .	803
18.8.1	LPDMA secure configuration register (LPDMA_SECCFGR) . . . . .	803
18.8.2	LPDMA privileged configuration register (LPDMA_PRIVCFGR) . . . . .	804
18.8.3	LPDMA configuration lock register (LPDMA_RCFGLOCKR) . . . . .	805
18.8.4	LPDMA nonsecure masked interrupt status register (LPDMA_MISR) . . . . .	805

18.8.5	LPDMA secure masked interrupt status register (LPDMA_SMISR) . . .	806
18.8.6	LPDMA channel x linked-list base address register (LPDMA_CxLBAR) . . . . .	807
18.8.7	LPDMA channel x flag clear register (LPDMA_CxFCR) . . . . .	807
18.8.8	LPDMA channel x status register (LPDMA_CxSR) . . . . .	808
18.8.9	LPDMA channel x control register (LPDMA_CxCR) . . . . .	810
18.8.10	LPDMA channel x transfer register 1 (LPDMA_CxTR1) . . . . .	812
18.8.11	LPDMA channel x transfer register 2 (LPDMA_CxTR2) . . . . .	814
18.8.12	LPDMA channel x block register 1 (LPDMA_CxBR1) . . . . .	817
18.8.13	LPDMA channel x source address register (LPDMA_CxSAR) . . . . .	818
18.8.14	LPDMA channel x destination address register (LPDMA_CxDAR) . . .	819
18.8.15	LPDMA channel x linked-list address register (LPDMA_CxLLR) . . . . .	820
18.8.16	LPDMA register map . . . . .	821
19	Chrom-ART Accelerator controller (DMA2D) . . . . .	823
19.1	DMA2D introduction . . . . .	823
19.2	DMA2D main features . . . . .	823
19.3	DMA2D functional description . . . . .	824
19.3.1	DMA2D block diagram . . . . .	824
19.3.2	DMA2D internal signals . . . . .	825
19.3.3	DMA2D control . . . . .	826
19.3.4	DMA2D foreground and background FIFOs . . . . .	826
19.3.5	DMA2D foreground and background pixel format converter (PFC) . . .	826
19.3.6	DMA2D foreground and background CLUT interface . . . . .	828
19.3.7	DMA2D blender . . . . .	830
19.3.8	DMA2D output PFC . . . . .	830
19.3.9	DMA2D output FIFO . . . . .	830
19.3.10	DMA2D output FIFO byte reordering . . . . .	831
19.3.11	DMA2D AHB master port timer . . . . .	833
19.3.12	DMA2D transactions . . . . .	833
19.3.13	DMA2D configuration . . . . .	833
19.3.14	DMA2D transfer control (start, suspend, abort and completion) . . . . .	837
19.3.15	Watermark . . . . .	837
19.3.16	Error management . . . . .	837
19.3.17	AHB dead time . . . . .	838
19.4	DMA2D interrupts . . . . .	838
19.5	DMA2D registers . . . . .	839

19.5.1	DMA2D control register (DMA2D_CR) . . . . .	839
19.5.2	DMA2D interrupt status register (DMA2D_ISR) . . . . .	840
19.5.3	DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .	841
19.5.4	DMA2D foreground memory address register (DMA2D_FGMAR) . . . . .	842
19.5.5	DMA2D foreground offset register (DMA2D_FGOR) . . . . .	842
19.5.6	DMA2D background memory address register (DMA2D_BGMAR) . . . . .	843
19.5.7	DMA2D background offset register (DMA2D_BGOR) . . . . .	843
19.5.8	DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .	844
19.5.9	DMA2D foreground color register (DMA2D_FGCOLR) . . . . .	845
19.5.10	DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .	846
19.5.11	DMA2D background color register (DMA2D_BGCOLR) . . . . .	848
19.5.12	DMA2D foreground CLUT memory address register (DMA2D_FGCMAR) . . . . .	848
19.5.13	DMA2D background CLUT memory address register (DMA2D_BGCMAR) . . . . .	849
19.5.14	DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .	849
19.5.15	DMA2D output color register (DMA2D_OCOLR) . . . . .	850
19.5.16	DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .	851
19.5.17	DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .	851
19.5.18	DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .	852
19.5.19	DMA2D output memory address register (DMA2D_OMAR) . . . . .	852
19.5.20	DMA2D output offset register (DMA2D_OOR) . . . . .	853
19.5.21	DMA2D number of line register (DMA2D_NLR) . . . . .	853
19.5.22	DMA2D line watermark register (DMA2D_LWR) . . . . .	854
19.5.23	DMA2D AHB master timer configuration register (DMA2D_AMTCR) . . . . .	854
19.5.24	DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .	855
19.5.25	DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .	855
19.5.26	DMA2D register map . . . . .	856
20	Chrom-ART Accelerator controller (DMA2D) . . . . .	858
20.1	DMA2D introduction . . . . .	858
20.2	DMA2D main features . . . . .	858
20.3	DMA2D functional description . . . . .	859
20.3.1	General description . . . . .	859
20.3.2	DMA2D internal signals . . . . .	860
20.3.3	DMA2D control . . . . .	861
20.3.4	DMA2D foreground and background FIFOs . . . . .	861

20.3.5 DMA2D foreground and background PFC . . . . . 861
20.3.6 DMA2D foreground and background CLUT interface . . . . . 863
20.3.7 DMA2D blender . . . . . 865
20.3.8 DMA2D output PFC . . . . . 865
20.3.9 DMA2D output FIFO . . . . . 865
20.3.10 DMA2D output FIFO byte reordering . . . . . 866
20.3.11 DMA2D AHB master port timer . . . . . 868
20.3.12 DMA2D transactions . . . . . 868
20.3.13 DMA2D configuration . . . . . 868
20.3.14 YCbCr support . . . . . 872
20.3.15 DMA2D transfer control (start, suspend, abort, and completion) . . . . . 872
20.3.16 Watermark . . . . . 873
20.3.17 Error management . . . . . 873
20.3.18 AHB dead time . . . . . 873
20.4 DMA2D interrupts . . . . . 873
20.5 DMA2D registers . . . . . 874
- 20.5.1 DMA2D control register (DMA2D_CR) . . . . . 874
- 20.5.2 DMA2D interrupt status register (DMA2D_ISR) . . . . . 876
- 20.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . 876
- 20.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . . . . 877
- 20.5.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . 877
- 20.5.6 DMA2D background memory address register (DMA2D_BGMAR) . . . . . 878
- 20.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . 878
- 20.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 879
- 20.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . 881
- 20.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . . 881
- 20.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . 883
- 20.5.12 DMA2D foreground CLUT memory address register
  (DMA2D_FGCMAR) . . . . . 883
- 20.5.13 DMA2D background CLUT memory address register
  (DMA2D_BGCMAR) . . . . . 884
- 20.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . 884
- 20.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . 885
- 20.5.16 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . 886
- 20.5.17 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . 886
- 20.5.18 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . 887
- 20.5.19 DMA2D output memory address register (DMA2D_OMAR) . . . . . 887

20.5.20	DMA2D output offset register (DMA2D_OOR) . . . . .	888
20.5.21	DMA2D number of line register (DMA2D_NLR) . . . . .	888
20.5.22	DMA2D line watermark register (DMA2D_LWR) . . . . .	889
20.5.23	DMA2D AHB master timer configuration register (DMA2D_AMTCR) . . . . .	889
20.5.24	DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .	890
20.5.25	DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .	890
20.5.26	DMA2D register map . . . . .	891
21	Chrom-GRC (GFXMMU) . . . . .	893
21.1	Introduction . . . . .	893
21.2	GFXMMU main features . . . . .	893
21.3	GFXMMU implementation . . . . .	893
21.4	GFXMMU functional and architectural description . . . . .	894
21.4.1	Virtual memory . . . . .	894
21.4.2	MMU architecture . . . . .	896
21.4.3	Cache and prefetch mechanism . . . . .	899
21.4.4	Address cache . . . . .	901
21.5	GFXMMU interrupts . . . . .	902
21.6	GFXMMU registers . . . . .	903
21.6.1	GFXMMU configuration register (GFXMMU_CR) . . . . .	903
21.6.2	GFXMMU status register (GFXMMU_SR) . . . . .	905
21.6.3	GFXMMU flag clear register (GFXMMU_FCR) . . . . .	905
21.6.4	GFXMMU cache control register (GFXMMU_CCR) . . . . .	906
21.6.5	GFXMMU default value register (GFXMMU_DVR) . . . . .	906
21.6.6	GFXMMU buffer 0 configuration register (GFXMMU_B0CR) . . . . .	907
21.6.7	GFXMMU buffer 1 configuration register (GFXMMU_B1CR) . . . . .	907
21.6.8	GFXMMU buffer 2 configuration register (GFXMMU_B2CR) . . . . .	908
21.6.9	GFXMMU buffer 3 configuration register (GFXMMU_B3CR) . . . . .	908
21.6.10	GFXMMU LUT entry x low (GFXMMU_LUTxL) . . . . .	909
21.6.11	GFXMMU LUT entry x high (GFXMMU_LUTxH) . . . . .	909
21.6.12	GFXMMU register map . . . . .	910
22	Nested vectored interrupt controller (NVIC) . . . . .	912
22.1	NVIC main features . . . . .	912
22.2	SysTick calibration value register . . . . .	912
22.3	Interrupt and exception vectors . . . . .	913

23 Extended interrupts and event controller (EXTI) . . . . . 919

23.1 EXTI main features . . . . . 919

23.2 EXTI block diagram . . . . . 919

23.2.1 EXTI connections between peripherals and CPU . . . . . 921

23.2.2 EXTI interrupt/event mapping . . . . . 921

23.3 EXTI functional description . . . . . 922

23.3.1 EXTI configurable event input wake-up . . . . . 922

23.3.2 EXTI mux selection . . . . . 923

23.4 EXTI functional behavior . . . . . 923

23.5 EXTI event protection . . . . . 924

23.5.1 EXTI security protection . . . . . 925

23.5.2 EXTI privilege protection . . . . . 925

23.6 EXTI registers . . . . . 926

23.6.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . 926

23.6.2 EXTI falling trigger selection register (EXTI_FTSR1) . . . . . 927

23.6.3 EXTI software interrupt event register (EXTI_SWIER1) . . . . . 927

23.6.4 EXTI rising edge pending register (EXTI_RPR1) . . . . . 928

23.6.5 EXTI falling edge pending register (EXTI_FPR1) . . . . . 929

23.6.6 EXTI security configuration register (EXTI_SECCFGR1) . . . . . 929

23.6.7 EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . . 930

23.6.8 EXTI external interrupt selection register (EXTI_EXTICRm) . . . . . 931

23.6.9 EXTI lock register (EXTI_LOCKR) . . . . . 933

23.6.10 EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . . 934

23.6.11 EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . . 934

23.6.12 EXTI register map . . . . . 935

24 Cyclic redundancy check calculation unit (CRC) . . . . . 937

24.1 CRC introduction . . . . . 937

24.2 CRC main features . . . . . 937

24.3 CRC functional description . . . . . 938

24.3.1 CRC block diagram . . . . . 938

24.3.2 CRC internal signals . . . . . 938

24.3.3 CRC operation . . . . . 938

24.4 CRC registers . . . . . 940

24.4.1 CRC data register (CRC_DR) . . . . . 940

24.4.2 CRC independent data register (CRC_IDR) . . . . . 940

24.4.3	CRC control register (CRC_CR) .....	941
24.4.4	CRC initial value (CRC_INIT) .....	942
24.4.5	CRC polynomial (CRC_POL) .....	942
24.4.6	CRC register map .....	943
25	CORDIC coprocessor (CORDIC) .....	944
25.1	CORDIC introduction .....	944
25.2	CORDIC main features .....	944
25.3	CORDIC functional description .....	944
25.3.1	General description .....	944
25.3.2	CORDIC functions .....	944
25.3.3	Fixed point representation .....	951
25.3.4	Scaling factor .....	951
25.3.5	Precision .....	952
25.3.6	Zero-overhead mode .....	955
25.3.7	Polling mode .....	956
25.3.8	Interrupt mode .....	957
25.3.9	DMA mode .....	957
25.4	CORDIC registers .....	958
25.4.1	CORDIC control/status register (CORDIC_CSR) .....	958
25.4.2	CORDIC argument register (CORDIC_WDATA) .....	960
25.4.3	CORDIC result register (CORDIC_RDATA) .....	961
25.4.4	CORDIC register map .....	961
26	Filter math accelerator (FMAC) .....	962
26.1	FMAC introduction .....	962
26.2	FMAC main features .....	962
26.3	FMAC functional description .....	963
26.3.1	General description .....	963
26.3.2	Local memory and buffers .....	964
26.3.3	Input buffers .....	964
26.3.4	Output buffer .....	967
26.3.5	Initialization functions .....	969
26.3.6	Filter functions .....	970
26.3.7	Fixed point representation .....	974
26.3.8	Implementing FIR filters with the FMAC .....	974

26.3.9	Implementing IIR filters with the FMAC . . . . .	976
26.3.10	Examples of filter initialization . . . . .	978
26.3.11	Examples of filter operation . . . . .	979
26.3.12	Filter design tips . . . . .	981
26.4	FMAC registers . . . . .	982
26.4.1	FMAC X1 buffer configuration register (FMAC_X1BUFCFG) . . . . .	982
26.4.2	FMAC X2 buffer configuration register (FMAC_X2BUFCFG) . . . . .	982
26.4.3	FMAC Y buffer configuration register (FMAC_YBUFCFG) . . . . .	983
26.4.4	FMAC parameter register (FMAC_PARAM) . . . . .	984
26.4.5	FMAC control register (FMAC_CR) . . . . .	985
26.4.6	FMAC status register (FMAC_SR) . . . . .	986
26.4.7	FMAC write data register (FMAC_WDATA) . . . . .	987
26.4.8	FMAC read data register (FMAC_RDATA) . . . . .	988
26.4.9	FMAC register map . . . . .	988
27	Flexible static memory controller (FSMC) . . . . .	990
27.1	FMC introduction . . . . .	990
27.2	FMC main features . . . . .	990
27.3	FMC block diagram . . . . .	991
27.4	AHB interface . . . . .	992
27.4.1	Supported memories and transactions . . . . .	992
27.5	External device address mapping . . . . .	993
27.5.1	NOR/PSRAM address mapping . . . . .	994
27.5.2	NAND flash memory address mapping . . . . .	995
27.6	NOR flash/PSRAM controller . . . . .	995
27.6.1	External memory interface signals . . . . .	997
27.6.2	Supported memories and transactions . . . . .	999
27.6.3	General timing rules . . . . .	1000
27.6.4	NOR flash/PSRAM controller asynchronous transactions . . . . .	1000
27.6.5	Synchronous transactions . . . . .	1019
27.6.6	NOR/PSRAM controller registers . . . . .	1026
27.7	NAND flash controller . . . . .	1034
27.7.1	External memory interface signals . . . . .	1034
27.7.2	NAND flash supported memories and transactions . . . . .	1035
27.7.3	Timing diagrams for NAND flash memory . . . . .	1036
27.7.4	NAND flash operations . . . . .	1037

27.7.5	NAND flash prewait functionality . . . . .	1037
27.7.6	Computation of the error correction code (ECC) in NAND flash memory . . . . .	1038
27.7.7	NAND flash controller registers . . . . .	1039
27.7.8	FMC register map . . . . .	1045
28	Octo-SPI interface (OCTOSPI) . . . . .	1047
28.1	OCTOSPI introduction . . . . .	1047
28.2	OCTOSPI main features . . . . .	1047
28.3	OCTOSPI implementation . . . . .	1048
28.4	OCTOSPI functional description . . . . .	1049
28.4.1	OCTOSPI block diagram . . . . .	1049
28.4.2	OCTOSPI pins and internal signals . . . . .	1051
28.4.3	OCTOSPI interface to memory modes . . . . .	1052
28.4.4	OCTOSPI regular-command protocol . . . . .	1053
28.4.5	OCTOSPI regular-command protocol signal interface . . . . .	1056
28.4.6	HyperBus protocol . . . . .	1060
28.4.7	Specific features . . . . .	1063
28.4.8	OCTOSPI operating mode introduction . . . . .	1065
28.4.9	OCTOSPI indirect mode . . . . .	1065
28.4.10	OCTOSPI automatic status-polling mode . . . . .	1067
28.4.11	OCTOSPI memory-mapped mode . . . . .	1068
28.4.12	OCTOSPI configuration introduction . . . . .	1069
28.4.13	OCTOSPI system configuration . . . . .	1069
28.4.14	OCTOSPI device configuration . . . . .	1069
28.4.15	OCTOSPI regular-command mode configuration . . . . .	1072
28.4.16	OCTOSPI HyperBus protocol configuration . . . . .	1074
28.4.17	OCTOSPI error management . . . . .	1075
28.4.18	OCTOSPI BUSY and ABORT . . . . .	1076
28.4.19	OCTOSPI reconfiguration or deactivation . . . . .	1076
28.4.20	NCS behavior . . . . .	1076
28.5	Address alignment and data number . . . . .	1078
28.6	OCTOSPI interrupts . . . . .	1079
28.7	OCTOSPI registers . . . . .	1079
28.7.1	OCTOSPI control register (OCTOSPI_CR) . . . . .	1079
28.7.2	OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . .	1082
28.7.3	OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . .	1084

28.7.4	OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . .	1085
28.7.5	OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . .	1086
28.7.6	OCTOSPI status register (OCTOSPI_SR) . . . . .	1086
28.7.7	OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .	1087
28.7.8	OCTOSPI data length register (OCTOSPI_DLR) . . . . .	1088
28.7.9	OCTOSPI address register (OCTOSPI_AR) . . . . .	1088
28.7.10	OCTOSPI data register (OCTOSPI_DR) . . . . .	1089
28.7.11	OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .	1089
28.7.12	OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .	1090
28.7.13	OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .	1090
28.7.14	OCTOSPI communication configuration register (OCTOSPI_CCR) . . . . .	1091
28.7.15	OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .	1093
28.7.16	OCTOSPI instruction register (OCTOSPI_IR) . . . . .	1093
28.7.17	OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .	1094
28.7.18	OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .	1094
28.7.19	OCTOSPI wrap communication configuration register (OCTOSPI_WPCCR) . . . . .	1095
28.7.20	OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . . . .	1097
28.7.21	OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .	1097
28.7.22	OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .	1098
28.7.23	OCTOSPI write communication configuration register (OCTOSPI_WCCR) . . . . .	1098
28.7.24	OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . .	1100
28.7.25	OCTOSPI write instruction register (OCTOSPI_WIR) . . . . .	1101
28.7.26	OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . .	1101
28.7.27	OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR) . . . . .	1102
28.7.28	OCTOSPI register map . . . . .	1102
29	Octo-SPI I/O manager (OCTOSPIM) . . . . .	1106
29.1	Introduction . . . . .	1106
29.2	OCTOSPIM main features . . . . .	1106
29.3	OCTOSPIM implementation . . . . .	1106
29.4	OCTOSPIM functional description . . . . .	1106
29.4.1	OCTOSPIM block diagram . . . . .	1106
29.4.2	OCTOSPIM input/output pins . . . . .	1107
29.4.3	OCTOSPIM matrix . . . . .	1108
29.4.4	OCTOSPIM multiplexed mode . . . . .	1108

29.5	OCTOSPIM registers . . . . .	1110
29.5.1	OCTOSPIM control register (OCTOSPIM_CR) . . . . .	1110
29.5.2	OCTOSPIM Port n configuration register (OCTOSPIM_PnCR) . . . . .	1110
29.5.3	OCTOSPIM register map . . . . .	1112
30	Hexadeca-SPI interface (HSPI) . . . . .	1113
30.1	HSPI introduction . . . . .	1113
30.2	HSPI main features . . . . .	1113
30.3	HSPI implementation . . . . .	1114
30.4	HSPI functional description . . . . .	1115
30.4.1	HSPI block diagram . . . . .	1115
30.4.2	HSPI pins and internal signals . . . . .	1118
30.4.3	HSPI interface to memory modes . . . . .	1119
30.4.4	HSPI regular-command protocol . . . . .	1119
30.4.5	HSPI regular-command protocol signal interface . . . . .	1123
30.4.6	HyperBus protocol . . . . .	1128
30.4.7	Specific features . . . . .	1133
30.4.8	HSPI operating modes introduction . . . . .	1134
30.4.9	HSPI indirect mode . . . . .	1134
30.4.10	HSPI automatic status-polling mode . . . . .	1136
30.4.11	HSPI memory-mapped mode . . . . .	1137
30.4.12	HSPI configuration introduction . . . . .	1138
30.4.13	HSPI system configuration . . . . .	1138
30.4.14	HSPI device configuration . . . . .	1138
30.4.15	HSPI regular-command mode configuration . . . . .	1141
30.4.16	HSPI HyperBus protocol configuration . . . . .	1143
30.4.17	HSPI error management . . . . .	1144
30.4.18	HSPI high-speed interface and calibration . . . . .	1144
30.4.19	HSPI BUSY and ABORT . . . . .	1145
30.4.20	HSPI reconfiguration or deactivation . . . . .	1146
30.4.21	NCS behavior . . . . .	1146
30.5	Address alignment and data number . . . . .	1148
30.6	HSPI interrupts . . . . .	1149
30.7	HSPI registers . . . . .	1150
30.7.1	HSPI control register (HSPI_CR) . . . . .	1150
30.7.2	HSPI device configuration register 1 (HSPI_DCR1) . . . . .	1153

30.7.3	HSPI device configuration register 2 (HSPI_DCR2) . . . . .	1154
30.7.4	HSPI device configuration register 3 (HSPI_DCR3) . . . . .	1155
30.7.5	HSPI device configuration register 4 (HSPI_DCR4) . . . . .	1156
30.7.6	HSPI status register (HSPI_SR) . . . . .	1156
30.7.7	HSPI flag clear register (HSPI_FCR) . . . . .	1157
30.7.8	HSPI data length register (HSPI_DLR) . . . . .	1158
30.7.9	HSPI address register (HSPI_AR) . . . . .	1158
30.7.10	HSPI data register (HSPI_DR) . . . . .	1159
30.7.11	HSPI polling status mask register (HSPI_PSMKR) . . . . .	1160
30.7.12	HSPI polling status match register (HSPI_PSMAR) . . . . .	1160
30.7.13	HSPI polling interval register (HSPI_PIR) . . . . .	1161
30.7.14	HSPI communication configuration register (HSPI_CCR) . . . . .	1161
30.7.15	HSPI timing configuration register (HSPI_TCR) . . . . .	1163
30.7.16	HSPI instruction register (HSPI_IR) . . . . .	1164
30.7.17	HSPI alternate bytes register (HSPI_ABR) . . . . .	1164
30.7.18	HSPI low-power timeout register (HSPI_LPTR) . . . . .	1164
30.7.19	HSPI wrap communication configuration register (HSPI_WPCCR) . . . . .	1165
30.7.20	HSPI wrap timing configuration register (HSPI_WPTCR) . . . . .	1167
30.7.21	HSPI wrap instruction register (HSPI_WPIR) . . . . .	1168
30.7.22	HSPI wrap alternate byte register (HSPI_WPABR) . . . . .	1168
30.7.23	HSPI write communication configuration register (HSPI_WCCR) . . . . .	1168
30.7.24	HSPI write timing configuration register (HSPI_WTCR) . . . . .	1170
30.7.25	HSPI write instruction register (HSPI_WIR) . . . . .	1171
30.7.26	HSPI write alternate byte register (HSPI_WABR) . . . . .	1171
30.7.27	HSPI HyperBus latency configuration register (HSPI_HLCR) . . . . .	1172
30.7.28	HSPI full-cycle calibration configuration (HSPI_CALFCR) . . . . .	1172
30.7.29	HSPI DLL master calibration configuration (HSPI_CALMR) . . . . .	1173
30.7.30	HSPI DLL slave output calibration configuration (HSPI_CALSOR) . . . . .	1174
30.7.31	HSPI DLL slave input calibration configuration (HSPI_CALSIR) . . . . .	1175
30.7.32	HSPI register map . . . . .	1175
31	Secure digital input/output MultiMediaCard interface (SDMMC) . . .	1179
31.1	SDMMC main features . . . . .	1179
31.2	SDMMC implementation . . . . .	1179
31.3	SDMMC bus topology . . . . .	1180

31.4	SDMMC operation modes . . . . .	1182
31.5	SDMMC functional description . . . . .	1183
31.5.1	SDMMC block diagram . . . . .	1183
31.5.2	SDMMC pins and internal signals . . . . .	1183
31.5.3	General description . . . . .	1184
31.5.4	SDMMC adapter . . . . .	1186
31.5.5	SDMMC AHB slave interface . . . . .	1208
31.5.6	SDMMC AHB master interface . . . . .	1209
31.5.7	AHB and SDMMC_CK clock relation . . . . .	1212
31.6	Card functional description . . . . .	1212
31.6.1	SD I/O mode . . . . .	1212
31.6.2	CMD12 send timing . . . . .	1220
31.6.3	Sleep (CMD5) . . . . .	1224
31.6.4	Interrupt mode (Wait-IRQ) . . . . .	1225
31.6.5	Boot operation . . . . .	1226
31.6.6	Response R1b handling . . . . .	1229
31.6.7	Reset and card cycle power . . . . .	1230
31.7	Hardware flow control . . . . .	1231
31.8	Ultra-high-speed phase I (UHS-I) voltage switch . . . . .	1231
31.9	SDMMC interrupts . . . . .	1235
31.10	SDMMC registers . . . . .	1236
31.10.1	SDMMC power control register (SDMMC_POWER) . . . . .	1236
31.10.2	SDMMC clock control register (SDMMC_CLKCR) . . . . .	1237
31.10.3	SDMMC argument register (SDMMC_ARGR) . . . . .	1239
31.10.4	SDMMC command register (SDMMC_CMDR) . . . . .	1239
31.10.5	SDMMC command response register (SDMMC_RESPCMDR) . . . . .	1241
31.10.6	SDMMC response x register (SDMMC_RESPxR) . . . . .	1242
31.10.7	SDMMC data timer register (SDMMC_DTIMER) . . . . .	1242
31.10.8	SDMMC data length register (SDMMC_DLENR) . . . . .	1243
31.10.9	SDMMC data control register (SDMMC_DCTRL) . . . . .	1244
31.10.10	SDMMC data counter register (SDMMC_DCNTR) . . . . .	1245
31.10.11	SDMMC status register (SDMMC_STAR) . . . . .	1246
31.10.12	SDMMC interrupt clear register (SDMMC_ICR) . . . . .	1249
31.10.13	SDMMC mask register (SDMMC_MASKR) . . . . .	1251
31.10.14	SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .	1254
31.10.15	SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .	1254

31.10.16 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . 1255

31.10.17 SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . . 1256

31.10.18 SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . . 1256

31.10.19 SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . . 1257

31.10.20 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . 1258

31.10.21 SDMMC register map . . . . . 1258

32 Delay block (DLYB) . . . . . 1261

32.1 DLYB introduction . . . . . 1261

32.2 DLYB main features . . . . . 1261

32.3 DLYB implementation . . . . . 1261

32.4 DLYB functional description . . . . . 1261

32.4.1 DLYB diagram . . . . . 1261

32.4.2 DLYB pins and internal signals . . . . . 1262

32.4.3 General description . . . . . 1262

32.4.4 Delay line length configuration procedure . . . . . 1263

32.4.5 Output clock phase configuration procedure . . . . . 1264

32.5 DLYB registers . . . . . 1264

32.5.1 DLYB control register (DLYB_CR) . . . . . 1264

32.5.2 DLYB configuration register (DLYB_CFGR) . . . . . 1265

32.5.3 DLYB register map . . . . . 1265

33 Analog-to-digital converter (ADC12) . . . . . 1266

33.1 ADC introduction . . . . . 1266

33.2 ADC main features . . . . . 1266

33.3 ADC implementation . . . . . 1268

33.4 ADC functional description . . . . . 1270

33.4.1 ADC block diagram . . . . . 1270

33.4.2 ADC pins and internal signals . . . . . 1271

33.4.3 ADC clocks . . . . . 1273

33.4.4 ADC connectivity . . . . . 1275

33.4.5 Slave AHB interface . . . . . 1277

33.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . . 1277

33.4.7 Single-ended and differential input channels . . . . . 1277

33.4.8	Calibration (ADCAL, ADCALLIN, ADC_CALFACT) . . . . .	1278
33.4.9	ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .	1282
33.4.10	Constraints when writing the ADC control bits . . . . .	1283
33.4.11	Channel selection (SQRx, JSQRx) . . . . .	1284
33.4.12	Channel preselection register (ADC_PCSEL) . . . . .	1284
33.4.13	Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .	1284
33.4.14	Single conversion mode (CONT = 0) . . . . .	1286
33.4.15	Continuous conversion mode (CONT = 1) . . . . .	1287
33.4.16	Starting conversions (ADSTART, JADSTART) . . . . .	1288
33.4.17	Timing . . . . .	1289
33.4.18	Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .	1289
33.4.19	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN[1:0], JEXTSEL, JEXTEN[1:0]) . . . . .	1291
33.4.20	Injected channel management . . . . .	1292
33.4.21	Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .	1294
33.4.22	Programmable resolution (RES) - fast conversion mode . . . . .	1295
33.4.23	End of conversion and end of sampling phase (EOC, JEOC, EOSMP) . . . . .	1295
33.4.24	End of conversion sequence (EOS, JEOS) . . . . .	1296
33.4.25	Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .	1296
33.4.26	Data management . . . . .	1298
33.4.27	Managing conversions using the MDF . . . . .	1306
33.4.28	Dynamic low-power features . . . . .	1306
33.4.29	Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AW Dy) . . . . .	1311
33.4.30	Oversampler . . . . .	1315
33.4.31	Dual ADC modes . . . . .	1320
33.4.32	Temperature sensor . . . . .	1336
33.4.33	VBAT supply monitoring . . . . .	1338
33.4.34	Monitoring the internal voltage reference . . . . .	1338
33.5	ADC interrupts . . . . .	1340
33.6	ADC registers (for each ADC) . . . . .	1341
33.6.1	ADC interrupt and status register (ADC_ISR) . . . . .	1341
33.6.2	ADC interrupt enable register (ADC_IER) . . . . .	1343
33.6.3	ADC control register (ADC_CR) . . . . .	1345
33.6.4	ADC configuration register (ADC_CFGR1) . . . . .	1348
33.6.5	ADC configuration register 2 (ADC_CFGR2) . . . . .	1351

33.6.6	ADC sample time register 1 (ADC_SMPR1) . . . . .	1354
33.6.7	ADC sample time register 2 (ADC_SMPR2) . . . . .	1355
33.6.8	ADC channel preselection register (ADC_PCSEL) . . . . .	1355
33.6.9	ADC regular sequence register 1 (ADC_SQR1) . . . . .	1356
33.6.10	ADC regular sequence register 2 (ADC_SQR2) . . . . .	1357
33.6.11	ADC regular sequence register 3 (ADC_SQR3) . . . . .	1358
33.6.12	ADC regular sequence register 4 (ADC_SQR4) . . . . .	1359
33.6.13	ADC regular data register (ADC_DR) . . . . .	1359
33.6.14	ADC injected sequence register (ADC_JSQR) . . . . .	1360
33.6.15	ADC offset y register (ADC_OF Ry) . . . . .	1361
33.6.16	ADC gain compensation register (ADC_GCOMP) . . . . .	1362
33.6.17	ADC injected data register (ADC_JDRy) . . . . .	1363
33.6.18	ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .	1363
33.6.19	ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .	1364
33.6.20	ADC watchdog threshold register 1 (ADC_LTR1) . . . . .	1364
33.6.21	ADC watchdog threshold register 1 (ADC_HTR1) . . . . .	1365
33.6.22	ADC watchdog lower threshold register 2 (ADC_LTR2) . . . . .	1365
33.6.23	ADC watchdog higher threshold register 2 (ADC_HTR2) . . . . .	1366
33.6.24	ADC watchdog lower threshold register 3 (ADC_LTR3) . . . . .	1366
33.6.25	ADC watchdog higher threshold register 3 (ADC_HTR3) . . . . .	1367
33.6.26	ADC differential mode selection register (ADC_DIFSEL) . . . . .	1367
33.6.27	ADC user control register (ADC_CALFACT) . . . . .	1368
33.6.28	ADC calibration factor register (ADC_CALFACT2) . . . . .	1368
33.7	ADC common registers . . . . .	1369
33.7.1	ADC common status register (ADC12_CSR) . . . . .	1369
33.7.2	ADC system control register (ADC12_CCR) . . . . .	1371
33.7.3	ADC common regular data register for dual mode (ADC12_CDR) . . . . .	1374
33.7.4	ADC common regular data register for 32-bit dual mode (ADC12_CDR2) . . . . .	1374
33.8	ADC register map . . . . .	1375
34	Analog-to-digital converter (ADC4) . . . . .	1379
34.1	ADC introduction . . . . .	1379
34.2	ADC main features . . . . .	1379
34.3	ADC implementation . . . . .	1380

34.4	ADC functional description . . . . .	1382
34.4.1	ADC block diagram . . . . .	1382
34.4.2	ADC pins and internal signals . . . . .	1383
34.4.3	ADC voltage regulator (ADVREGEN) . . . . .	1384
34.4.4	Calibration (ADCAL) . . . . .	1384
34.4.5	ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .	1386
34.4.6	ADC clock (PRESC[3:0]) . . . . .	1388
34.4.7	ADC connectivity . . . . .	1390
34.4.8	Configuring the ADC . . . . .	1391
34.4.9	Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .	1391
34.4.10	Programmable sampling time (SMPx[2:0]) . . . . .	1392
34.4.11	Single conversion mode (CONT = 0) . . . . .	1393
34.4.12	Continuous conversion mode (CONT = 1) . . . . .	1393
34.4.13	Starting conversions (ADSTART) . . . . .	1394
34.4.14	Timings . . . . .	1395
34.4.15	Stopping an ongoing conversion (ADSTP) . . . . .	1396
34.4.16	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .	1396
34.4.17	Discontinuous mode (DISCEN) . . . . .	1397
34.4.18	Programmable resolution (RES) - fast conversion mode . . . . .	1397
34.4.19	End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .	1398
34.4.20	End of conversion sequence (EOS flag) . . . . .	1399
34.4.21	Example timing diagrams (single/continuous modes hardware/software triggers) . . . . .	1399
34.4.22	Low-frequency trigger mode . . . . .	1401
34.4.23	Data management . . . . .	1401
34.4.24	Low-power features . . . . .	1405
34.4.25	Analog window watchdog . . . . .	1409
34.4.26	Oversampler . . . . .	1413
34.4.27	Temperature sensor and internal reference voltage . . . . .	1416
34.4.28	Battery voltage monitoring . . . . .	1418
34.4.29	Concurrent operation with another ADC . . . . .	1419
34.5	ADC in low-power modes . . . . .	1419
34.6	ADC interrupts . . . . .	1420
34.7	ADC registers . . . . .	1422
34.7.1	ADC interrupt and status register (ADC_ISR) . . . . .	1422
34.7.2	ADC interrupt enable register (ADC_IER) . . . . .	1423

34.7.3	ADC control register (ADC_CR) .....	1426
34.7.4	ADC configuration register 1 (ADC_CFGR1) .....	1428
34.7.5	ADC configuration register 2 (ADC_CFGR2) .....	1431
34.7.6	ADC sampling time register (ADC_SMPR) .....	1432
34.7.7	ADC watchdog threshold register (ADC_AWD1TR) .....	1433
34.7.8	ADC watchdog threshold register (ADC_AWD2TR) .....	1434
34.7.9	ADC channel selection register [alternate] (ADC_CHSELR) .....	1435
34.7.10	ADC channel selection register [alternate] (ADC_CHSELR) .....	1435
34.7.11	ADC watchdog threshold register (ADC_AWD3TR) .....	1437
34.7.12	ADC data register (ADC_DR) .....	1438
34.7.13	ADC power register (ADC_PRR) .....	1438
34.7.14	ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) ..	1439
34.7.15	ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) ..	1440
34.7.16	ADC Calibration factor (ADC_CALFACT) .....	1440
34.7.17	ADC option register (ADC_OR) .....	1441
34.7.18	ADC common configuration register (ADC_CCR) .....	1441
34.7.19	ADC register map .....	1442
35	Digital-to-analog converter (DAC) .....	1445
35.1	DAC introduction .....	1445
35.2	DAC main features .....	1445
35.3	DAC implementation .....	1446
35.4	DAC functional description .....	1447
35.4.1	DAC block diagram .....	1447
35.4.2	DAC pins and internal signals .....	1448
35.4.3	DAC clocks .....	1449
35.4.4	DAC channel enable .....	1449
35.4.5	DAC data format .....	1450
35.4.6	DAC conversion .....	1451
35.4.7	DAC output voltage .....	1453
35.4.8	DAC trigger selection .....	1453
35.4.9	DMA requests .....	1453
35.4.10	Noise generation .....	1454
35.4.11	Triangle-wave generation .....	1456
35.4.12	DAC channel modes .....	1457
35.4.13	DAC channel buffer calibration .....	1460
35.4.14	DAC channel conversion modes .....	1461

35.4.15	Dual DAC channel conversion modes (if dual channels are available) . . . . .	1462
35.4.16	DAC autonomous mode . . . . .	1466
35.5	DAC in low-power modes . . . . .	1467
35.6	DAC interrupts . . . . .	1467
35.7	DAC registers . . . . .	1468
35.7.1	DAC control register (DAC_CR) . . . . .	1468
35.7.2	DAC software trigger register (DAC_SWTRGR) . . . . .	1471
35.7.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	1472
35.7.4	DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .	1473
35.7.5	DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .	1473
35.7.6	DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .	1474
35.7.7	DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .	1474
35.7.8	DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .	1475
35.7.9	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .	1475
35.7.10	Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .	1476
35.7.11	Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .	1476
35.7.12	DAC channel1 data output register (DAC_DOR1) . . . . .	1477
35.7.13	DAC channel2 data output register (DAC_DOR2) . . . . .	1477
35.7.14	DAC status register (DAC_SR) . . . . .	1478
35.7.15	DAC calibration control register (DAC_CCR) . . . . .	1479
35.7.16	DAC mode control register (DAC_MCR) . . . . .	1480
35.7.17	DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .	1481
35.7.18	DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .	1482
35.7.19	DAC sample and hold time register (DAC_SHHR) . . . . .	1482
35.7.20	DAC sample and hold refresh time register (DAC_SHRR) . . . . .	1483
35.7.21	DAC autonomous mode control register (DAC_AUTOCR) . . . . .	1484
35.7.22	DAC register map . . . . .	1484

36	Voltage reference buffer (VREFBUF) . . . . .	1487
36.1	VREFBUF introduction . . . . .	1487
36.2	VREFBUF implementation . . . . .	1487
36.3	VREFBUF functional description . . . . .	1487
36.4	VREFBUF trimming . . . . .	1488
36.5	VREFBUF registers . . . . .	1489
36.5.1	VREFBUF control and status register (VREFBUF_CSR) . . . . .	1489
36.5.2	VREFBUF calibration control register (VREFBUF_CCR) . . . . .	1490
36.5.3	VREFBUF register map . . . . .	1490
37	Comparator (COMP) . . . . .	1491
37.1	Introduction . . . . .	1491
37.2	COMP main features . . . . .	1491
37.3	COMP implementation . . . . .	1491
37.4	COMP functional description . . . . .	1492
37.4.1	COMP block diagram . . . . .	1492
37.4.2	COMP pins and internal signals . . . . .	1492
37.4.3	Comparator LOCK mechanism . . . . .	1494
37.4.4	Window comparator . . . . .	1494
37.4.5	Hysteresis . . . . .	1495
37.4.6	Comparator output-blanking function . . . . .	1495
37.4.7	COMP power and speed modes . . . . .	1496
37.4.8	Scaler function . . . . .	1496
37.5	COMP low-power modes . . . . .	1497
37.6	COMP interrupts . . . . .	1497
37.7	COMP registers . . . . .	1498
37.7.1	COMP1 control and status register (COMP1_CSR) . . . . .	1498
37.7.2	COMP2 control and status register (COMP2_CSR) . . . . .	1499
37.7.3	COMP register map . . . . .	1501
38	Operational amplifier (OPAMP) . . . . .	1502
38.1	OPAMP introduction . . . . .	1502
38.2	OPAMP main features . . . . .	1502
38.3	OPAMP functional description . . . . .	1502
38.3.1	OPAMP reset and clocks . . . . .	1502

38.3.2	Initial configuration . . . . .	1503
38.3.3	Signal routing . . . . .	1503
38.3.4	OPAMP modes . . . . .	1504
38.3.5	Calibration . . . . .	1507
38.4	OPAMP low-power modes . . . . .	1509
38.5	OPAMP registers . . . . .	1509
38.5.1	OPAMP1 control/status register (OPAMP1_CSR) . . . . .	1509
38.5.2	OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . . . .	1511
38.5.3	OPAMP1 offset trimming register in low-power mode (OPAMP1_LPOTR) . . . . .	1511
38.5.4	OPAMP2 control/status register (OPAMP2_CSR) . . . . .	1512
38.5.5	OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) . . . . .	1513
38.5.6	OPAMP2 offset trimming register in low-power mode (OPAMP2_LPOTR) . . . . .	1514
38.5.7	OPAMP register map . . . . .	1514
39	Multi-function digital filter (MDF) . . . . .	1516
39.1	MDF introduction . . . . .	1516
39.2	MDF main features . . . . .	1517
39.3	MDF implementation . . . . .	1517
39.4	MDF functional description . . . . .	1519
39.4.1	MDF block diagram . . . . .	1519
39.4.2	MDF pins and internal signals . . . . .	1520
39.4.3	Serial input interfaces (SITF) . . . . .	1521
39.4.4	ADC slave interface (ADCITF) . . . . .	1527
39.4.5	Clock generator (CKGEN) . . . . .	1528
39.4.6	Bitstream matrix (BSMX) . . . . .	1530
39.4.7	Short-circuit detectors (SCD) . . . . .	1531
39.4.8	Digital filter processing (DFLT) . . . . .	1533
39.4.9	Out-of-limit detector (OLD) . . . . .	1543
39.4.10	Digital filter acquisition modes . . . . .	1546
39.4.11	Start-up sequence examples . . . . .	1556
39.4.12	Break interface . . . . .	1557
39.4.13	Data transfer to memory . . . . .	1558
39.4.14	Autonomous mode . . . . .	1563
39.4.15	Register protection . . . . .	1564
39.5	MDF low-power modes . . . . .	1565

39.6 MDF interrupts . . . . . 1565
39.7 MDF application informations . . . . . 1567
- 39.7.1 MDF configuration examples for audio capture . . . . . 1567
- 39.7.2 Programming examples . . . . . 1568
- 39.7.3 Connection examples . . . . . 1570
- 39.7.4 Global frequency response . . . . . 1571
- 39.7.5 Total MDF gain . . . . . 1572
39.8 MDF registers . . . . . 1576
- 39.8.1 MDF global control register (MDF_GCR) . . . . . 1576
- 39.8.2 MDF clock generator control register (MDF_CKGCR) . . . . . 1577
- 39.8.3 MDF serial interface control register x (MDF_SITFxCr) . . . . . 1579
- 39.8.4 MDF bitstream matrix control register x (MDF_BSMXxCr) . . . . . 1580
- 39.8.5 MDF digital filter control register x (MDF_DFLTxCr) . . . . . 1581
- 39.8.6 MDF digital filter configuration register x (MDF_DFLTxCICR) . . . . . 1583
- 39.8.7 MDF reshape filter configuration register x (MDF_DFLTxRSFR) . . . . . 1585
- 39.8.8 MDF integrator configuration register x (MDF_DFLTxINTR) . . . . . 1586
- 39.8.9 MDF out-of limit detector control register x (MDF_OLDxCr) . . . . . 1586
- 39.8.10 MDF OLDx low threshold register x (MDF_OLDxTHLR) . . . . . 1588
- 39.8.11 MDF OLDx high threshold register x (MDF_OLDxTHHR) . . . . . 1588
- 39.8.12 MDF delay control register x (MDF_DLYxCr) . . . . . 1589
- 39.8.13 MDF short circuit detector control register x (MDF_SCDxCr) . . . . . 1589
- 39.8.14 MDF DFLT0 interrupt enable register 0 (MDF_DFLT0IER) . . . . . 1590
- 39.8.15 MDF DFLTx interrupt enable register x (MDF_DFLTxIER) . . . . . 1592
- 39.8.16 MDF DFLT0 interrupt status register 0 (MDF_DFLT0ISR) . . . . . 1593
- 39.8.17 MDF DFLTx interrupt status register x (MDF_DFLTxISR) . . . . . 1595
- 39.8.18 MDF offset error compensation control register x (MDF_OECxCr) . . . . . 1596
- 39.8.19 MDF snapshot data register x (MDF_SNPSxDR) . . . . . 1597
- 39.8.20 MDF digital filter data register x (MDF_DFLTxDR) . . . . . 1597
- 39.8.21 MDF register map . . . . . 1598

40 Audio digital filter (ADF) . . . . . 1600
- 40.1 ADF introduction . . . . . 1600
- 40.2 ADF main features . . . . . 1600
- 40.3 ADF implementation . . . . . 1601
- 40.4 ADF functional description . . . . . 1602
  - 40.4.1 ADF block diagram . . . . . 1602

40.4.2	ADF pins and internal signals . . . . .	1602
40.4.3	Serial input interface (SITF) . . . . .	1603
40.4.4	ADC slave interface (ADCITF) . . . . .	1607
40.4.5	Clock generator (CKGEN) . . . . .	1608
40.4.6	Bitstream matrix (BSMX) . . . . .	1610
40.4.7	Digital filter processing (DFLT) . . . . .	1611
40.4.8	Digital filter acquisition modes . . . . .	1621
40.4.9	Start-up sequence examples . . . . .	1629
40.4.10	Sound activity detection (SAD) . . . . .	1630
40.4.11	Data transfer to memory . . . . .	1638
40.4.12	Autonomous mode . . . . .	1641
40.4.13	Register protection . . . . .	1641
40.5	ADF low-power modes . . . . .	1642
40.6	ADF interrupts . . . . .	1642
40.7	ADF application information . . . . .	1644
40.7.1	ADF configuration examples for audio capture . . . . .	1644
40.7.2	Programming examples . . . . .	1645
40.7.3	Connection examples . . . . .	1647
40.7.4	Global frequency response . . . . .	1648
40.7.5	Total ADF gain . . . . .	1649
40.7.6	How to compute SAD thresholds . . . . .	1652
40.8	ADF registers . . . . .	1656
40.8.1	ADF global control register (ADF_GCR) . . . . .	1656
40.8.2	ADF clock generator control register (ADF_CKGCR) . . . . .	1656
40.8.3	ADF serial interface control register 0 (ADF_SITF0CR) . . . . .	1658
40.8.4	ADF bitstream matrix control register 0 (ADF_BSMX0CR) . . . . .	1660
40.8.5	ADF digital filter control register 0 (ADF_DFLT0CR) . . . . .	1660
40.8.6	ADF digital filter configuration register 0 (ADF_DFLT0CICR) . . . . .	1662
40.8.7	ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) . . . . .	1663
40.8.8	ADF delay control register 0 (ADF_DLY0CR) . . . . .	1664
40.8.9	ADF DFLT0 interrupt enable register (ADF_DFLT0IER) . . . . .	1665
40.8.10	ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) . . . . .	1666
40.8.11	ADF SAD control register (ADF_SADCR) . . . . .	1667
40.8.12	ADF SAD configuration register (ADF_SADCFGR) . . . . .	1669
40.8.13	ADF SAD sound level register (ADF_SADSDLVR) . . . . .	1670
40.8.14	ADF SAD ambient noise level register (ADF_SADANLVR) . . . . .	1671
40.8.15	ADF digital filter data register 0 (ADF_DFLT0DR) . . . . .	1671

40.8.16	ADF register map . . . . .	1671
41	Digital camera interface (DCMI) . . . . .	1674
41.1	DCMI introduction . . . . .	1674
41.2	DCMI main features . . . . .	1674
41.3	DCMI functional description . . . . .	1674
41.3.1	DCMI block diagram . . . . .	1675
41.3.2	DCMI pins and internal signals . . . . .	1675
41.3.3	DCMI clocks . . . . .	1676
41.3.4	DCMI DMA interface . . . . .	1676
41.3.5	DCMI physical interface . . . . .	1676
41.3.6	DCMI synchronization . . . . .	1678
41.3.7	DCMI capture modes . . . . .	1680
41.3.8	DCMI crop feature . . . . .	1681
41.3.9	DCMI JPEG format . . . . .	1682
41.3.10	DCMI FIFO . . . . .	1682
41.3.11	DCMI data format description . . . . .	1683
41.4	DCMI interrupts . . . . .	1685
41.5	DCMI registers . . . . .	1685
41.5.1	DCMI control register (DCMI_CR) . . . . .	1685
41.5.2	DCMI status register (DCMI_SR) . . . . .	1688
41.5.3	DCMI raw interrupt status register (DCMI_RIS) . . . . .	1688
41.5.4	DCMI interrupt enable register (DCMI_IER) . . . . .	1689
41.5.5	DCMI masked interrupt status register (DCMI_MIS) . . . . .	1690
41.5.6	DCMI interrupt clear register (DCMI_ICR) . . . . .	1691
41.5.7	DCMI embedded synchronization code register (DCMI_ESCR) . . . . .	1692
41.5.8	DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .	1692
41.5.9	DCMI crop window start (DCMI_CWSTRT) . . . . .	1693
41.5.10	DCMI crop window size (DCMI_CWSIZE) . . . . .	1694
41.5.11	DCMI data register (DCMI_DR) . . . . .	1694
41.5.12	DCMI register map . . . . .	1695
42	Parallel synchronous slave interface (PSSI) . . . . .	1696
42.1	PSSI introduction . . . . .	1696
42.2	PSSI main features . . . . .	1696
42.3	PSSI functional description . . . . .	1696

42.3.1	PSSI block diagram . . . . .	1697
42.3.2	PSSI pins and internal signals . . . . .	1697
42.3.3	PSSI clock . . . . .	1698
42.3.4	PSSI data management . . . . .	1698
42.3.5	PSSI optional control signals . . . . .	1700
42.4	PSSI interrupts . . . . .	1703
42.5	PSSI registers . . . . .	1704
42.5.1	PSSI control register (PSSI_CR) . . . . .	1704
42.5.2	PSSI status register (PSSI_SR) . . . . .	1705
42.5.3	PSSI raw interrupt status register (PSSI_RIS) . . . . .	1706
42.5.4	PSSI interrupt enable register (PSSI_IER) . . . . .	1707
42.5.5	PSSI masked interrupt status register (PSSI_MIS) . . . . .	1707
42.5.6	PSSI interrupt clear register (PSSI_ICR) . . . . .	1708
42.5.7	PSSI data register (PSSI_DR) . . . . .	1708
42.5.8	PSSI register map . . . . .	1709
43	LCD-TFT display controller (LTDC) . . . . .	1710
43.1	Introduction . . . . .	1710
43.2	LTDC main features . . . . .	1710
43.3	LTDC functional description . . . . .	1711
43.3.1	LTDC block diagram . . . . .	1711
43.3.2	LTDC pins and internal signals . . . . .	1711
43.3.3	LTDC reset and clocks . . . . .	1712
43.4	LTDC programmable parameters . . . . .	1714
43.4.1	LTDC global configuration parameters . . . . .	1714
43.4.2	Layer programmable parameters . . . . .	1716
43.5	LTDC interrupts . . . . .	1720
43.6	LTDC programming procedure . . . . .	1721
43.7	LTDC registers . . . . .	1722
43.7.1	LTDC synchronization size configuration register (LTDC_SSCR) . . . . .	1722
43.7.2	LTDC back porch configuration register (LTDC_BPCR) . . . . .	1722
43.7.3	LTDC active width configuration register (LTDC_AWCR) . . . . .	1723
43.7.4	LTDC total width configuration register (LTDC_TWCR) . . . . .	1724
43.7.5	LTDC global control register (LTDC_GCR) . . . . .	1724
43.7.6	LTDC shadow reload configuration register (LTDC_SRCR) . . . . .	1726
43.7.7	LTDC background color configuration register (LTDC_BCCR) . . . . .	1726

43.7.8 LTDC interrupt enable register (LTDC_IER) . . . . . 1727

43.7.9 LTDC interrupt status register (LTDC_ISR) . . . . . 1728

43.7.10 LTDC interrupt clear register (LTDC_ICR) . . . . . 1728

43.7.11 LTDC line interrupt position configuration register (LTDC_LIPCR) . . 1729

43.7.12 LTDC current position status register (LTDC_CPSR) . . . . . 1729

43.7.13 LTDC current display status register (LTDC_CDSR) . . . . . 1730

43.7.14 LTDC layer x control register (LTDC_LxCR) . . . . . 1730

43.7.15 LTDC layer x window horizontal position configuration register
(LTDC_LxWHPER) . . . . . 1731

43.7.16 LTDC layer x window vertical position configuration register
(LTDC_LxWVPER) . . . . . 1732

43.7.17 LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . . 1733

43.7.18 LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . . 1733

43.7.19 LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . . 1734

43.7.20 LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . . 1734

43.7.21 LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . . 1735

43.7.22 LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . . 1736

43.7.23 LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . . 1736

43.7.24 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . . 1737

43.7.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . 1737

43.7.26 LTDC register map . . . . . 1738

44 DSI Host (DSI) . . . . . 1741

44.1 DSI introduction . . . . . 1741

44.2 Standard and references . . . . . 1741

44.3 DSI Host main features . . . . . 1742

44.4 DSI Host functional description . . . . . 1743

44.4.1 General description . . . . . 1743

44.4.2 DSI Host pins and internal signals . . . . . 1743

44.4.3 Supported resolutions and frame rates . . . . . 1744

44.4.4 System level architecture . . . . . 1744

44.5	Functional description: video mode on LTDC interface . . . . .	1747
44.5.1	Video transmission mode . . . . .	1749
44.5.2	Updating the LTDC interface configuration in video mode . . . . .	1750
44.6	Functional description: adapted command mode on LTDC interface . . .	1752
44.7	Functional description: APB register interface . . . . .	1756
44.7.1	Packet transmission using the generic interface . . . . .	1756
44.8	Functional description: timeout counters . . . . .	1760
44.8.1	Contention error detection timeout counters . . . . .	1760
44.8.2	Peripheral response timeout counters . . . . .	1761
44.9	Functional description: transmission of commands . . . . .	1766
44.9.1	Transmission of commands in video mode . . . . .	1766
44.9.2	Transmission of commands in low-power mode . . . . .	1768
44.9.3	Transmission of commands in high-speed . . . . .	1772
44.9.4	Read command transmission . . . . .	1772
44.9.5	Clock lane in low-power mode . . . . .	1773
44.10	Functional description: virtual channels . . . . .	1775
44.11	Functional description: video mode pattern generator . . . . .	1776
44.11.1	Color bar pattern . . . . .	1776
44.11.2	Color coding . . . . .	1778
44.11.3	BER testing pattern . . . . .	1778
44.11.4	Video mode pattern generator resolution . . . . .	1779
44.12	Functional description: D-PHY management . . . . .	1780
44.12.1	D-PHY configuration . . . . .	1780
44.12.2	D-PHY HS2LP and LP2HS durations . . . . .	1780
44.12.3	Special D-PHY operations . . . . .	1781
44.12.4	DSI PLL control . . . . .	1781
44.12.5	D-PHY bias control . . . . .	1782
44.13	Functional description: interrupts and errors . . . . .	1782
44.13.1	DSI Wrapper interrupts . . . . .	1782
44.13.2	DSI Host interrupts and errors . . . . .	1783
44.14	Programing procedure . . . . .	1790
44.14.1	Programing procedure overview . . . . .	1791
44.14.2	Configuring the D-PHY parameters . . . . .	1792
44.14.3	Configuring the DSI Host timing . . . . .	1792
44.14.4	Configuring flow control and DBI interface . . . . .	1793
44.14.5	Configuring the DSI Host LTDC interface . . . . .	1793

44.14.6	Configuring the video mode . . . . .	1794
44.14.7	Configuring the adapted command mode . . . . .	1798
44.14.8	Configuring the video mode pattern generator . . . . .	1798
44.14.9	Managing ULPM . . . . .	1799
44.15	DSI Host registers . . . . .	1802
44.15.1	DSI Host version register (DSI_VR) . . . . .	1802
44.15.2	DSI Host control register (DSI_CR) . . . . .	1802
44.15.3	DSI Host clock control register (DSI_CCR) . . . . .	1802
44.15.4	DSI Host LTDC VCID register (DSI_LVCIDR) . . . . .	1803
44.15.5	DSI Host LTDC color coding register (DSI_LCOLCR) . . . . .	1803
44.15.6	DSI Host LTDC polarity configuration register (DSI_LPCR) . . . . .	1804
44.15.7	DSI Host low-power mode configuration register (DSI_LPMCR) . . . . .	1804
44.15.8	DSI Host protocol configuration register (DSI_PCR) . . . . .	1805
44.15.9	DSI Host generic VCID register (DSI_GVCIDR) . . . . .	1806
44.15.10	DSI Host mode configuration register (DSI_MCR) . . . . .	1806
44.15.11	DSI Host video mode configuration register (DSI_VMCR) . . . . .	1807
44.15.12	DSI Host video packet configuration register (DSI_VPCR) . . . . .	1808
44.15.13	DSI Host video chunks configuration register (DSI_VCCR) . . . . .	1808
44.15.14	DSI Host video null packet configuration register (DSI_VNPCR) . . . . .	1809
44.15.15	DSI Host video HSA configuration register (DSI_VHSACR) . . . . .	1809
44.15.16	DSI Host video HBP configuration register (DSI_VHBPCR) . . . . .	1810
44.15.17	DSI Host video line configuration register (DSI_VLCR) . . . . .	1810
44.15.18	DSI Host video VSA configuration register (DSI_VVSACR) . . . . .	1810
44.15.19	DSI Host video VBP configuration register (DSI_VVBPCR) . . . . .	1811
44.15.20	DSI Host video VFP configuration register (DSI_VVPCR) . . . . .	1811
44.15.21	DSI Host video VA configuration register (DSI_VVACR) . . . . .	1811
44.15.22	DSI Host LTDC command configuration register (DSI_LCCR) . . . . .	1812
44.15.23	DSI Host command mode configuration register (DSI_CMCR) . . . . .	1812
44.15.24	DSI Host generic header configuration register (DSI_GHCR) . . . . .	1814
44.15.25	DSI Host generic payload data register (DSI_GPDR) . . . . .	1814
44.15.26	DSI Host generic packet status register (DSI_GPSR) . . . . .	1815
44.15.27	DSI Host timeout counter configuration register 0 (DSI_TCCR0) . . . . .	1816
44.15.28	DSI Host timeout counter configuration register 1 (DSI_TCCR1) . . . . .	1817
44.15.29	DSI Host timeout counter configuration register 2 (DSI_TCCR2) . . . . .	1817
44.15.30	DSI Host timeout counter configuration register 3 (DSI_TCCR3) . . . . .	1818
44.15.31	DSI Host timeout counter configuration register 4 (DSI_TCCR4) . . . . .	1818
44.15.32	DSI Host timeout counter configuration register 5 (DSI_TCCR5) . . . . .	1819

44.15.33 DSI Host clock lane configuration register (DSI_CLCR) . . . . .	1819
44.15.34 DSI Host clock lane timer configuration register (DSI_CLTCR) . . . . .	1820
44.15.35 DSI Host data lane timer configuration register (DSI_DLTCR) . . . . .	1820
44.15.36 DSI Host PHY control register (DSI_PCTLR) . . . . .	1820
44.15.37 DSI Host PHY configuration register (DSI_PCONFGR) . . . . .	1821
44.15.38 DSI Host PHY ULPS control register (DSI_PUCR) . . . . .	1822
44.15.39 DSI Host PHY TX triggers configuration register (DSI_PTTTCR) . . . . .	1822
44.15.40 DSI Host PHY status register (DSI_PSR) . . . . .	1823
44.15.41 DSI Host interrupt and status register 0 (DSI_ISR0) . . . . .	1823
44.15.42 DSI Host interrupt and status register 1 (DSI_ISR1) . . . . .	1825
44.15.43 DSI Host interrupt enable register 0 (DSI_IER0) . . . . .	1826
44.15.44 DSI Host interrupt enable register 1 (DSI_IER1) . . . . .	1828
44.15.45 DSI Host force interrupt register 0 (DSI_FIR0) . . . . .	1830
44.15.46 DSI Host force interrupt register 1 (DSI_FIR1) . . . . .	1831
44.15.47 DSI Host data lane timer read configuration register (DSI_DLTRCR) . . . . .	1832
44.15.48 DSI Host video shadow control register (DSI_VSCR) . . . . .	1833
44.15.49 DSI Host LTDC current VCID register (DSI_LCVCIDR) . . . . .	1833
44.15.50 DSI Host LTDC current color coding register (DSI_LCCCR) . . . . .	1833
44.15.51 DSI Host low-power mode current configuration register (DSI_LPMCCR) . . . . .	1834
44.15.52 DSI Host video mode current configuration register (DSI_VMCCR) . . . . .	1835
44.15.53 DSI Host video packet current configuration register (DSI_VPCCR) . . . . .	1836
44.15.54 DSI Host video chunks current configuration register (DSI_VCCCR) . . . . .	1836
44.15.55 DSI Host video null packet current configuration register (DSI_VNPCCR) . . . . .	1837
44.15.56 DSI Host video HSA current configuration register (DSI_VHSACCR) . . . . .	1837
44.15.57 DSI Host video HBP current configuration register (DSI_VHBPCCR) . . . . .	1837
44.15.58 DSI Host video line current configuration register (DSI_VLCCR) . . . . .	1838
44.15.59 DSI Host video VSA current configuration register (DSI_VVSACCR) . . . . .	1838
44.15.60 DSI Host video VBP current configuration register (DSI_VVPCCR) . . . . .	1838
44.15.61 DSI Host video VFP current configuration register (DSI_VVFPCCR) . . . . .	1839

- - 44.15.6.2 DSI Host video VA current configuration register (DSI_VVACCR) . . . . . 1839
  - 44.15.6.3 DSI Host FIFO and buffer status register (DSI_FBSR) . . . . . 1840
- 44.16 DSI Wrapper registers . . . . . 1842
  - 44.16.1 DSI Wrapper configuration register (DSI_WCFGR) . . . . . 1842
  - 44.16.2 DSI Wrapper control register (DSI_WCR) . . . . . 1843
  - 44.16.3 DSI Wrapper interrupt enable register (DSI_WIER) . . . . . 1843
  - 44.16.4 DSI Wrapper interrupt and status register (DSI_WISR) . . . . . 1844
  - 44.16.5 DSI Wrapper interrupt flag clear register (DSI_WIFCR) . . . . . 1845
  - 44.16.6 DSI Wrapper PHY configuration register 0 (DSI_WPCR0) . . . . . 1846
  - 44.16.7 DSI Wrapper regulator and PLL control register (DSI_WRPCR) . . . . . 1847
  - 44.16.8 DSI Wrapper PLL tuning register (DSI_WPTR) . . . . . 1848
- 44.17 DSI bias registers . . . . . 1848
  - 44.17.1 DSI bias configuration register (DSI_BCFGR) . . . . . 1848
- 44.18 D-PHY registers . . . . . 1849
  - 44.18.1 DSI D-PHY clock band control register (DSI_DPCBCR) . . . . . 1849
  - 44.18.2 DSI D-PHY clock skew rate control register (DSI_DPCSRCR) . . . . . 1849
  - 44.18.3 DSI D-PHY data lane 0 HS offset control register (DSI_DPDL0HSOCR) . . . . . 1850
  - 44.18.4 DSI D-PHY data lane 0 HS LPX offset control register (DSI_DPDL0LPXOCR) . . . . . 1850
  - 44.18.5 DSI D-PHY data lane 0 band control register (DSI_DPDL0BCR) . . . . . 1851
  - 44.18.6 DSI D-PHY data lane 0 skew rate control register (DSI_DPDL0SRCR) . . . . . 1852
  - 44.18.7 DSI D-PHY data lane 1 HS offset control register (DSI_DPDL1HSOCR) . . . . . 1852
  - 44.18.8 DSI D-PHY data lane 1 HS LPX offset control register (DSI_DPDL1LPXOCR) . . . . . 1853
  - 44.18.9 DSI D-PHY data lane 1 band control register (DSI_DPDL1BCR) . . . . . 1853
  - 44.18.10 DSI D-PHY data lane 1 skew rate control register (DSI_DPDL1SRCR) . . . . . 1854
  - 44.18.11 DSI register map . . . . . 1855
45 Neo-Chrom graphic processor (GPU2D) . . . . . 1861
- 45.1 GPU2D introduction . . . . . 1861
- 45.2 GPU2D main features . . . . . 1861
- 45.3 GPU2D implementation . . . . . 1862
- 45.4 GPU2D general description . . . . . 1863

45.4.1	GPU2D block diagram . . . . .	1863
45.4.2	GPU2D pins and internal signals . . . . .	1863
46	JPEG codec (JPEG) . . . . .	1864
46.1	JPEG introduction . . . . .	1864
46.2	JPEG codec main features . . . . .	1864
46.3	JPEG codec block functional description . . . . .	1865
46.3.1	General description . . . . .	1865
46.3.2	JPEG internal signals . . . . .	1865
46.3.3	JPEG decoding procedure . . . . .	1866
46.3.4	JPEG encoding procedure . . . . .	1868
46.4	JPEG codec interrupts . . . . .	1871
46.5	JPEG codec registers . . . . .	1871
46.5.1	JPEG codec control register (JPEG_CONFR0) . . . . .	1871
46.5.2	JPEG codec configuration register 1 (JPEG_CONFR1) . . . . .	1872
46.5.3	JPEG codec configuration register 2 (JPEG_CONFR2) . . . . .	1873
46.5.4	JPEG codec configuration register 3 (JPEG_CONFR3) . . . . .	1873
46.5.5	JPEG codec configuration register x (JPEG_CONFRx) . . . . .	1874
46.5.6	JPEG control register (JPEG_CR) . . . . .	1875
46.5.7	JPEG status register (JPEG_SR) . . . . .	1876
46.5.8	JPEG clear flag register (JPEG_CFR) . . . . .	1877
46.5.9	JPEG data input register (JPEG_DIR) . . . . .	1878
46.5.10	JPEG data output register (JPEG_DOR) . . . . .	1878
46.5.11	JPEG quantization memory x (JPEG_QMEMx_y) . . . . .	1879
46.5.12	JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .	1879
46.5.13	JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . .	1880
46.5.14	JPEG Huffman base (JPEG_HUFFBASEx) . . . . .	1880
46.5.15	JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . .	1881
46.5.16	JPEG DHT memory (JPEG_DHTMEMx) . . . . .	1882
46.5.17	JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . .	1882
46.5.18	JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . .	1883
46.5.19	JPEG codec register map . . . . .	1884
47	Touch sensing controller (TSC) . . . . .	1886
47.1	TSC introduction . . . . .	1886
47.2	TSC main features . . . . .	1886

47.3 TSC functional description . . . . . 1886
- 47.3.1 TSC block diagram . . . . . 1886
- 47.3.2 Surface charge transfer acquisition overview . . . . . 1887
- 47.3.3 Reset and clocks . . . . . 1890
- 47.3.4 Charge transfer acquisition sequence . . . . . 1890
- 47.3.5 Spread spectrum feature . . . . . 1891
- 47.3.6 Max count error . . . . . 1892
- 47.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . 1892
- 47.3.8 Acquisition mode . . . . . 1893
- 47.3.9 I/O hysteresis and analog switch control . . . . . 1893
47.4 TSC low-power modes . . . . . 1894
47.5 TSC interrupts . . . . . 1894
47.6 TSC registers . . . . . 1894
- 47.6.1 TSC control register (TSC_CR) . . . . . 1894
- 47.6.2 TSC interrupt enable register (TSC_IER) . . . . . 1897
- 47.6.3 TSC interrupt clear register (TSC_ICR) . . . . . 1897
- 47.6.4 TSC interrupt status register (TSC_ISR) . . . . . 1898
- 47.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . 1898
- 47.6.6 TSC I/O analog switch control register
  (TSC_IOASCR) . . . . . 1899
- 47.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . 1899
- 47.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . 1900
- 47.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . 1900
- 47.6.10 TSC I/O group x counter register (TSC_IOGxCR) . . . . . 1901
- 47.6.11 TSC register map . . . . . 1901
48 True random number generator (RNG) . . . . . 1903
- 48.1 RNG introduction . . . . . 1903
- 48.2 RNG main features . . . . . 1903
- 48.3 RNG functional description . . . . . 1904
  - 48.3.1 RNG block diagram . . . . . 1904
  - 48.3.2 RNG internal signals . . . . . 1904
  - 48.3.3 Random number generation . . . . . 1904
  - 48.3.4 RNG initialization . . . . . 1907
  - 48.3.5 RNG operation . . . . . 1908
  - 48.3.6 RNG clocking . . . . . 1910
  - 48.3.7 Error management . . . . . 1910

48.3.8	RNG low-power use . . . . .	1911
48.4	RNG interrupts . . . . .	1912
48.5	RNG processing time . . . . .	1912
48.6	RNG entropy source validation . . . . .	1913
48.6.1	Introduction . . . . .	1913
48.6.2	Validation conditions . . . . .	1913
48.7	RNG registers . . . . .	1914
48.7.1	RNG control register (RNG_CR) . . . . .	1914
48.7.2	RNG status register (RNG_SR) . . . . .	1916
48.7.3	RNG data register (RNG_DR) . . . . .	1917
48.7.4	RNG noise source control register (RNG_NSCR) . . . . .	1918
48.7.5	RNG health test control register (RNG_HTCR) . . . . .	1919
48.7.6	RNG register map . . . . .	1919
49	AES hardware accelerator (AES) . . . . .	1920
49.1	Introduction . . . . .	1920
49.2	AES main features . . . . .	1920
49.3	AES implementation . . . . .	1921
49.4	AES functional description . . . . .	1921
49.4.1	AES block diagram . . . . .	1921
49.4.2	AES internal signals . . . . .	1921
49.4.3	AES cryptographic core . . . . .	1922
49.4.4	AES procedure to perform a cipher operation . . . . .	1927
49.4.5	AES decryption round key preparation . . . . .	1930
49.4.6	AES ciphertext stealing and data padding . . . . .	1930
49.4.7	AES task suspend and resume . . . . .	1931
49.4.8	AES basic chaining modes (ECB, CBC) . . . . .	1931
49.4.9	AES counter (CTR) mode . . . . .	1936
49.4.10	AES Galois/counter mode (GCM) . . . . .	1938
49.4.11	AES Galois message authentication code (GMAC) . . . . .	1943
49.4.12	AES counter with CBC-MAC (CCM) . . . . .	1945
49.4.13	AES operation with shared keys . . . . .	1950
49.4.14	AES data registers and data swapping . . . . .	1951
49.4.15	AES key registers . . . . .	1953
49.4.16	AES initialization vector registers . . . . .	1953
49.4.17	AES DMA interface . . . . .	1954

49.4.18	AES error management . . . . .	1955
49.5	AES interrupts . . . . .	1956
49.6	AES processing latency . . . . .	1957
49.7	AES registers . . . . .	1958
49.7.1	AES control register (AES_CR) . . . . .	1958
49.7.2	AES status register (AES_SR) . . . . .	1960
49.7.3	AES data input register (AES_DINR) . . . . .	1962
49.7.4	AES data output register (AES_DOUTR) . . . . .	1962
49.7.5	AES key register 0 (AES_KEYR0) . . . . .	1963
49.7.6	AES key register 1 (AES_KEYR1) . . . . .	1963
49.7.7	AES key register 2 (AES_KEYR2) . . . . .	1964
49.7.8	AES key register 3 (AES_KEYR3) . . . . .	1964
49.7.9	AES initialization vector register 0 (AES_IVR0) . . . . .	1964
49.7.10	AES initialization vector register 1 (AES_IVR1) . . . . .	1965
49.7.11	AES initialization vector register 2 (AES_IVR2) . . . . .	1965
49.7.12	AES initialization vector register 3 (AES_IVR3) . . . . .	1965
49.7.13	AES key register 4 (AES_KEYR4) . . . . .	1966
49.7.14	AES key register 5 (AES_KEYR5) . . . . .	1966
49.7.15	AES key register 6 (AES_KEYR6) . . . . .	1966
49.7.16	AES key register 7 (AES_KEYR7) . . . . .	1967
49.7.17	AES suspend registers (AES_SUSPxR) . . . . .	1967
49.7.18	AES interrupt enable register (AES_IER) . . . . .	1968
49.7.19	AES interrupt status register (AES_ISR) . . . . .	1968
49.7.20	AES interrupt clear register (AES_ICR) . . . . .	1969
49.7.21	AES register map . . . . .	1970
50	Secure AES coprocessor (SAES) . . . . .	1972
50.1	Introduction . . . . .	1972
50.2	SAES main features . . . . .	1973
50.3	SAES implementation . . . . .	1973
50.4	SAES functional description . . . . .	1974
50.4.1	SAES block diagram . . . . .	1974
50.4.2	SAES internal signals . . . . .	1974
50.4.3	SAES cryptographic core . . . . .	1975
50.4.4	SAES procedure to perform a cipher operation . . . . .	1977
50.4.5	SAES decryption round key preparation . . . . .	1980

50.4.6	SAES ciphertext stealing and data padding . . . . .	1980
50.4.7	SAES task suspend and resume . . . . .	1981
50.4.8	SAES basic chaining modes (ECB, CBC) . . . . .	1981
50.4.9	SAES operation with wrapped keys . . . . .	1986
50.4.10	SAES operation with shared keys . . . . .	1989
50.4.11	SAES data registers and data swapping . . . . .	1991
50.4.12	SAES key registers . . . . .	1993
50.4.13	SAES initialization vector registers . . . . .	1994
50.4.14	SAES DMA interface . . . . .	1995
50.4.15	SAES error management . . . . .	1996
50.5	SAES interrupts . . . . .	1998
50.6	SAES processing latency . . . . .	1999
50.7	SAES registers . . . . .	1999
50.7.1	SAES control register (SAES_CR) . . . . .	1999
50.7.2	SAES status register (SAES_SR) . . . . .	2002
50.7.3	SAES data input register (SAES_DINR) . . . . .	2004
50.7.4	SAES data output register (SAES_DOU TR) . . . . .	2004
50.7.5	SAES key register 0 (SAES_KEYR0) . . . . .	2005
50.7.6	SAES key register 1 (SAES_KEYR1) . . . . .	2005
50.7.7	SAES key register 2 (SAES_KEYR2) . . . . .	2006
50.7.8	SAES key register 3 (SAES_KEYR3) . . . . .	2006
50.7.9	SAES initialization vector register 0 (SAES_IVR0) . . . . .	2006
50.7.10	SAES initialization vector register 1 (SAES_IVR1) . . . . .	2007
50.7.11	SAES initialization vector register 2 (SAES_IVR2) . . . . .	2007
50.7.12	SAES initialization vector register 3 (SAES_IVR3) . . . . .	2007
50.7.13	SAES key register 4 (SAES_KEYR4) . . . . .	2008
50.7.14	SAES key register 5 (SAES_KEYR5) . . . . .	2008
50.7.15	SAES key register 6 (SAES_KEYR6) . . . . .	2008
50.7.16	SAES key register 7 (SAES_KEYR7) . . . . .	2009
50.7.17	SAES interrupt enable register (SAES_IER) . . . . .	2009
50.7.18	SAES interrupt status register (SAES_ISR) . . . . .	2010
50.7.19	SAES interrupt clear register (SAES_ICR) . . . . .	2011
50.7.20	SAES register map . . . . .	2012
51	Hash processor (HASH) . . . . .	2014
51.1	Introduction . . . . .	2014
51.2	HASH main features . . . . .	2014

51.3 HASH implementation . . . . . 2015
51.4 HASH functional description . . . . . 2015
- 51.4.1 HASH block diagram . . . . . 2015
- 51.4.2 HASH internal signals . . . . . 2016
- 51.4.3 About secure hash algorithms . . . . . 2016
- 51.4.4 Message data feeding . . . . . 2016
- 51.4.5 Message digest computing . . . . . 2018
- 51.4.6 Message padding . . . . . 2019
- 51.4.7 HMAC operation . . . . . 2021
- 51.4.8 HASH suspend/resume operations . . . . . 2023
- 51.4.9 HASH DMA interface . . . . . 2025
- 51.4.10 HASH error management . . . . . 2025
- 51.4.11 HASH processing time . . . . . 2025
51.5 HASH interrupts . . . . . 2026
51.6 HASH registers . . . . . 2027
- 51.6.1 HASH control register (HASH_CR) . . . . . 2027
- 51.6.2 HASH data input register (HASH_DIN) . . . . . 2028
- 51.6.3 HASH start register (HASH_STR) . . . . . 2029
- 51.6.4 HASH digest registers . . . . . 2030
- 51.6.5 HASH interrupt enable register (HASH_IMR) . . . . . 2031
- 51.6.6 HASH status register (HASH_SR) . . . . . 2032
- 51.6.7 HASH context swap registers . . . . . 2033
- 51.6.8 HASH register map . . . . . 2034

52 On-the-fly decryption engine (OTFDEC) . . . . . 2036

52.1 OTFDEC introduction . . . . . 2036
52.2 OTFDEC main features . . . . . 2036
52.3 OTFDEC functional description . . . . . 2037
- 52.3.1 OTFDEC block diagram . . . . . 2037
- 52.3.2 OTFDEC internal signals . . . . . 2037
- 52.3.3 OTFDEC on-the-fly decryption . . . . . 2038
- 52.3.4 OTFDEC usage of AES in counter mode decryption . . . . . 2039
- 52.3.5 Flow control management . . . . . 2040
- 52.3.6 OTFDEC error management . . . . . 2040
52.4 OTFDEC interrupts . . . . . 2041
52.5 OTFDEC application information . . . . . 2041

52.5.1	OTFDEC initialization process . . . . .	2041
52.5.2	OTFDEC and power management . . . . .	2043
52.5.3	Encrypting for OTFDEC . . . . .	2043
52.5.4	OTFDEC key CRC source code . . . . .	2044
52.6	OTFDEC registers . . . . .	2045
52.6.1	OTFDEC control register (OTFDEC_CR) . . . . .	2045
52.6.2	OTFDEC privileged access control configuration register (OTFDEC_PRIVCFGGR) . . . . .	2046
52.6.3	OTFDEC region x configuration register (OTFDEC_RxCFGR) . . . . .	2046
52.6.4	OTFDEC region x start address register (OTFDEC_RxSTARTADDR) . . . . .	2048
52.6.5	OTFDEC region x end address register (OTFDEC_RxENDADDR) . . . . .	2048
52.6.6	OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . .	2049
52.6.7	OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . .	2050
52.6.8	OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . .	2050
52.6.9	OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . .	2051
52.6.10	OTFDEC region x key register 2 (OTFDEC_RxKEYR2) . . . . .	2051
52.6.11	OTFDEC region x key register 3 (OTFDEC_RxKEYR3) . . . . .	2052
52.6.12	OTFDEC interrupt status register (OTFDEC_ISR) . . . . .	2052
52.6.13	OTFDEC interrupt clear register (OTFDEC_ICR) . . . . .	2053
52.6.14	OTFDEC interrupt enable register (OTFDEC_IER) . . . . .	2054
52.6.15	OTFDEC register map . . . . .	2055
53	Public key accelerator (PKA) . . . . .	2059
53.1	PKA introduction . . . . .	2059
53.2	PKA main features . . . . .	2059
53.3	PKA functional description . . . . .	2060
53.3.1	PKA block diagram . . . . .	2060
53.3.2	PKA internal signals . . . . .	2060
53.3.3	PKA reset and clocks . . . . .	2060
53.3.4	PKA public key acceleration . . . . .	2061
53.3.5	Typical applications for PKA . . . . .	2063
53.3.6	PKA procedure to perform an operation . . . . .	2065
53.3.7	PKA error management . . . . .	2066
53.4	PKA operating modes . . . . .	2067
53.4.1	Introduction . . . . .	2067
53.4.2	Montgomery parameter computation . . . . .	2068

53.4.3	Modular addition . . . . .	2068
53.4.4	Modular subtraction . . . . .	2069
53.4.5	Modular and Montgomery multiplication . . . . .	2069
53.4.6	Modular exponentiation . . . . .	2070
53.4.7	Modular inversion . . . . .	2072
53.4.8	Modular reduction . . . . .	2072
53.4.9	Arithmetic addition . . . . .	2073
53.4.10	Arithmetic subtraction . . . . .	2073
53.4.11	Arithmetic multiplication . . . . .	2074
53.4.12	Arithmetic comparison . . . . .	2074
53.4.13	RSA CRT exponentiation . . . . .	2074
53.4.14	Point on elliptic curve Fp check . . . . .	2075
53.4.15	ECC Fp scalar multiplication . . . . .	2076
53.4.16	ECDSA sign . . . . .	2077
53.4.17	ECDSA verification . . . . .	2079
53.4.18	ECC complete addition . . . . .	2080
53.4.19	ECC double base ladder . . . . .	2080
53.4.20	ECC projective to affine . . . . .	2081
53.5	Example of configurations and processing times . . . . .	2082
53.5.1	Supported elliptic curves . . . . .	2082
53.5.2	Computation times . . . . .	2084
53.6	PKA interrupts . . . . .	2086
53.7	PKA registers . . . . .	2087
53.7.1	PKA control register (PKA_CR) . . . . .	2087
53.7.2	PKA status register (PKA_SR) . . . . .	2088
53.7.3	PKA clear flag register (PKA_CLRFR) . . . . .	2090
53.7.4	PKA RAM . . . . .	2090
53.7.5	PKA register map . . . . .	2091
54	Advanced-control timers (TIM1/TIM8) . . . . .	2092
54.1	TIM1/TIM8 introduction . . . . .	2092
54.2	TIM1/TIM8 main features . . . . .	2092
54.3	TIM1/TIM8 functional description . . . . .	2093
54.3.1	Block diagram . . . . .	2093
54.3.2	TIM1/TIM8 pins and internal signals . . . . .	2094
54.3.3	Time-base unit . . . . .	2099

54.3.4	Counter modes . . . . .	2101
54.3.5	Repetition counter . . . . .	2113
54.3.6	External trigger input . . . . .	2114
54.3.7	Clock selection . . . . .	2115
54.3.8	Capture/compare channels . . . . .	2119
54.3.9	Input capture mode . . . . .	2122
54.3.10	PWM input mode . . . . .	2123
54.3.11	Forced output mode . . . . .	2124
54.3.12	Output compare mode . . . . .	2124
54.3.13	PWM mode . . . . .	2126
54.3.14	Asymmetric PWM mode . . . . .	2134
54.3.15	Combined PWM mode . . . . .	2135
54.3.16	Combined 3-phase PWM mode . . . . .	2136
54.3.17	Complementary outputs and dead-time insertion . . . . .	2137
54.3.18	Using the break function . . . . .	2140
54.3.19	Bidirectional break inputs . . . . .	2146
54.3.20	Clearing the tim_ocxref signal on an external event . . . . .	2147
54.3.21	6-step PWM generation . . . . .	2149
54.3.22	One-pulse mode . . . . .	2150
54.3.23	Retriggerable One-pulse mode . . . . .	2152
54.3.24	Pulse on compare mode . . . . .	2153
54.3.25	Encoder interface mode . . . . .	2155
54.3.26	Direction bit output . . . . .	2172
54.3.27	UIF bit remapping . . . . .	2173
54.3.28	Timer input XOR function . . . . .	2173
54.3.29	Interfacing with Hall sensors . . . . .	2173
54.3.30	Timer synchronization . . . . .	2175
54.3.31	ADC triggers . . . . .	2180
54.3.32	DMA burst mode . . . . .	2180
54.3.33	TIM1/TIM8 DMA requests . . . . .	2181
54.3.34	Debug mode . . . . .	2181
54.4	TIM1/TIM8 low-power modes . . . . .	2182
54.5	TIM1/TIM8 interrupts . . . . .	2182
54.6	TIM1/TIM8 registers . . . . .	2183
54.6.1	TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .	2183
54.6.2	TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .	2184
54.6.3	TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . .	2188

54.6.4	TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . .	2192
54.6.5	TIMx status register (TIMx_SR)(x = 1, 8) . . . . .	2193
54.6.6	TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .	2196
54.6.7	TIMx capture/compare mode register 1 (TIMx_CCMR1) (x = 1, 8) . . . . .	2197
54.6.8	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) . . . . .	2199
54.6.9	TIMx capture/compare mode register 2 (TIMx_CCMR2) (x = 1, 8) . . . . .	2202
54.6.10	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 1, 8) . . . . .	2203
54.6.11	TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) . . . . .	2206
54.6.12	TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .	2210
54.6.13	TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .	2210
54.6.14	TIMx autoreload register (TIMx_ARR)(x = 1, 8) . . . . .	2211
54.6.15	TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .	2211
54.6.16	TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . .	2212
54.6.17	TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . .	2212
54.6.18	TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . .	2213
54.6.19	TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . .	2214
54.6.20	TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . . . . .	2215
54.6.21	TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . .	2219
54.6.22	TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . .	2220
54.6.23	TIMx capture/compare mode register 3 (TIMx_CCMR3) (x = 1, 8) . . . . .	2221
54.6.24	TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8) . . . . .	2222
54.6.25	TIMx timer encoder control register (TIMx_ECR)(x = 1, 8) . . . . .	2223
54.6.26	TIMx timer input selection register (TIMx_TISEL)(x = 1, 8) . . . . .	2224
54.6.27	TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8) . . . . .	2225
54.6.28	TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8) . . . . .	2228
54.6.29	TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . .	2230
54.6.30	TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . .	2232
54.6.31	TIMx register map . . . . .	2232
55	General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .	2235
55.1	TIM2/TIM3/TIM4/TIM5 introduction . . . . .	2235
55.2	TIM2/TIM3/TIM4/TIM5 main features . . . . .	2235
55.3	TIM2/TIM3/TIM4/TIM5 implementation . . . . .	2236

55.4	TIM2/TIM3/TIM4/TIM5 functional description . . . . .	2237
55.4.1	Block diagram . . . . .	2237
55.4.2	TIM2/TIM3/TIM4/TIM5 pins and internal signals . . . . .	2238
55.4.3	Time-base unit . . . . .	2242
55.4.4	Counter modes . . . . .	2244
55.4.5	Clock selection . . . . .	2256
55.4.6	Capture/compare channels . . . . .	2260
55.4.7	Input capture mode . . . . .	2262
55.4.8	PWM input mode . . . . .	2263
55.4.9	Forced output mode . . . . .	2264
55.4.10	Output compare mode . . . . .	2264
55.4.11	PWM mode . . . . .	2266
55.4.12	Asymmetric PWM mode . . . . .	2274
55.4.13	Combined PWM mode . . . . .	2275
55.4.14	Clearing the tim_ocxref signal on an external event . . . . .	2276
55.4.15	One-pulse mode . . . . .	2278
55.4.16	Retriggerable one-pulse mode . . . . .	2279
55.4.17	Pulse on compare mode . . . . .	2280
55.4.18	Encoder interface mode . . . . .	2282
55.4.19	Direction bit output . . . . .	2300
55.4.20	UIF bit remapping . . . . .	2301
55.4.21	Timer input XOR function . . . . .	2301
55.4.22	Timers and external trigger synchronization . . . . .	2301
55.4.23	Timer synchronization . . . . .	2305
55.4.24	ADC triggers . . . . .	2310
55.4.25	DMA burst mode . . . . .	2311
55.4.26	TIM2/TIM3/TIM4/TIM5 DMA requests . . . . .	2312
55.4.27	Debug mode . . . . .	2312
55.4.28	TIM2/TIM3/TIM4/TIM5 low-power modes . . . . .	2312
55.4.29	TIM2/TIM3/TIM4/TIM5 interrupts . . . . .	2313
55.5	TIM2/TIM3/TIM4/TIM5 registers . . . . .	2314
55.5.1	TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .	2314
55.5.2	TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .	2315
55.5.3	TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .	2317
55.5.4	TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .	2321
55.5.5	TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .	2322
55.5.6	TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .	2324

55.5.7	TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5)	2325
55.5.8	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 2 to 5)	2327
55.5.9	TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5)	2329
55.5.10	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2 to 5)	2330
55.5.11	TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5)	2333
55.5.12	TIMx counter (TIMx_CNT)(x = 2 to 5)	2335
55.5.13	TIMx prescaler (TIMx_PSC)(x = 2 to 5)	2335
55.5.14	TIMx autoreload register (TIMx_ARR)(x = 2 to 5)	2336
55.5.15	TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5)	2336
55.5.16	TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5)	2337
55.5.17	TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5)	2338
55.5.18	TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5)	2339
55.5.19	TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5)	2340
55.5.20	TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5)	2341
55.5.21	TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5)	2342
55.5.22	TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5)	2343
55.5.23	TIMx DMA control register (TIMx_DCR)(x = 2 to 5)	2344
55.5.24	TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5)	2345
55.5.25	TIMx register map	2346
56	General purpose timers (TIM15/TIM16/TIM17)	2349
56.1	TIM15/TIM16/TIM17 introduction	2349
56.2	TIM15 main features	2349
56.3	TIM16/TIM17 main features	2350
56.4	TIM15/TIM16/TIM17 functional description	2351
56.4.1	Block diagram	2351
56.4.2	TIM15/TIM16/TIM17 pins and internal signals	2352
56.4.3	Time-base unit	2355
56.4.4	Counter modes	2357
56.4.5	Repetition counter	2361
56.4.6	Clock selection	2362
56.4.7	Capture/compare channels	2364
56.4.8	Input capture mode	2366
56.4.9	PWM input mode (only for TIM15)	2368
56.4.10	Forced output mode	2369

56.4.11	Output compare mode . . . . .	2369
56.4.12	PWM mode . . . . .	2371
56.4.13	Combined PWM mode (TIM15 only) . . . . .	2376
56.4.14	Complementary outputs and dead-time insertion . . . . .	2377
56.4.15	Using the break function . . . . .	2380
56.4.16	Bidirectional break input . . . . .	2384
56.4.17	Clearing the tim_ocxref signal on an external event . . . . .	2385
56.4.18	6-step PWM generation . . . . .	2386
56.4.19	One-pulse mode . . . . .	2388
56.4.20	Retriggerable one pulse mode (TIM15 only) . . . . .	2389
56.4.21	UIF bit remapping . . . . .	2390
56.4.22	Timer input XOR function (TIM15 only) . . . . .	2390
56.4.23	External trigger synchronization (TIM15 only) . . . . .	2390
56.4.24	Slave mode – combined reset + trigger mode (TIM15 only) . . . . .	2393
56.4.25	Slave mode – combined reset + gated mode (TIM15 only) . . . . .	2393
56.4.26	Timer synchronization (TIM15 only) . . . . .	2394
56.4.27	Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .	2394
56.4.28	ADC triggers (TIM15 only) . . . . .	2394
56.4.29	DMA burst mode . . . . .	2394
56.4.30	TIM15/TIM16/TIM17 DMA requests . . . . .	2395
56.4.31	Debug mode . . . . .	2395
56.5	TIM15/TIM16/TIM17 low-power modes . . . . .	2396
56.6	TIM15/TIM16/TIM17 interrupts . . . . .	2396
56.7	TIM15 registers . . . . .	2396
56.7.1	TIM15 control register 1 (TIM15_CR1) . . . . .	2397
56.7.2	TIM15 control register 2 (TIM15_CR2) . . . . .	2398
56.7.3	TIM15 slave mode control register (TIM15_SMCR) . . . . .	2400
56.7.4	TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .	2402
56.7.5	TIM15 status register (TIM15_SR) . . . . .	2403
56.7.6	TIM15 event generation register (TIM15_EGR) . . . . .	2405
56.7.7	TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .	2406
56.7.8	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	2407
56.7.9	TIM15 capture/compare enable register (TIM15_CCER) . . . . .	2410
56.7.10	TIM15 counter (TIM15_CNT) . . . . .	2413
56.7.11	TIM15 prescaler (TIM15_PSC) . . . . .	2413
56.7.12	TIM15 autoreload register (TIM15_ARR) . . . . .	2414

56.7.13	TIM15 repetition counter register (TIM15_RCR) . . . . .	2414
56.7.14	TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .	2415
56.7.15	TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .	2416
56.7.16	TIM15 break and dead-time register (TIM15_BDTR) . . . . .	2416
56.7.17	TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . .	2419
56.7.18	TIM15 input selection register (TIM15_TISEL) . . . . .	2420
56.7.19	TIM15 alternate function register 1 (TIM15_AF1) . . . . .	2421
56.7.20	TIM15 alternate function register 2 (TIM15_AF2) . . . . .	2423
56.7.21	TIM15 DMA control register (TIM15_DCR) . . . . .	2424
56.7.22	TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .	2425
56.7.23	TIM15 register map . . . . .	2425
56.8	TIM16/TIM17 registers . . . . .	2428
56.8.1	TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .	2428
56.8.2	TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .	2429
56.8.3	TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .	2430
56.8.4	TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .	2431
56.8.5	TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .	2432
56.8.6	TIMx capture/compare mode register 1 (TIMx_CCMR1) (x = 16 to 17) . . . . .	2433
56.8.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) . . . . .	2434
56.8.8	TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .	2436
56.8.9	TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .	2439
56.8.10	TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .	2439
56.8.11	TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .	2440
56.8.12	TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .	2440
56.8.13	TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .	2441
56.8.14	TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .	2442
56.8.15	TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .	2445
56.8.16	TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .	2446
56.8.17	TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .	2446
56.8.18	TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .	2449
56.8.19	TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . .	2449
56.8.20	TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .	2450
56.8.21	TIM16/TIM17 DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .	2451
56.8.22	TIM16/TIM17 register map . . . . .	2452

57	Basic timers (TIM6/TIM7) . . . . .	2454
57.1	TIM6/TIM7 introduction . . . . .	2454
57.2	TIM6/TIM7 main features . . . . .	2454
57.3	TIM6/TIM7 functional description . . . . .	2455
57.3.1	TIM6/TIM7 block diagram . . . . .	2455
57.3.2	TIM6/TIM7 internal signals . . . . .	2455
57.3.3	TIM6/TIM7 clocks . . . . .	2456
57.3.4	Time-base unit . . . . .	2456
57.3.5	Counting mode . . . . .	2458
57.3.6	UIF bit remapping . . . . .	2465
57.3.7	ADC triggers . . . . .	2466
57.3.8	TIM6/TIM7 DMA requests . . . . .	2466
57.3.9	Debug mode . . . . .	2466
57.3.10	TIM6/TIM7 low-power modes . . . . .	2466
57.3.11	TIM6/TIM7 interrupts . . . . .	2466
57.4	TIM6/TIM7 registers . . . . .	2467
57.4.1	TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .	2467
57.4.2	TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .	2469
57.4.3	TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .	2469
57.4.4	TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .	2470
57.4.5	TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .	2470
57.4.6	TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .	2470
57.4.7	TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .	2471
57.4.8	TIMx autoreload register (TIMx_ARR)(x = 6 to 7) . . . . .	2471
57.4.9	TIMx register map . . . . .	2472
58	Low-power timer (LPTIM) . . . . .	2473
58.1	LPTIM introduction . . . . .	2473
58.2	LPTIM main features . . . . .	2473
58.3	LPTIM implementation . . . . .	2474
58.4	LPTIM functional description . . . . .	2475
58.4.1	LPTIM block diagram . . . . .	2475
58.4.2	LPTIM pins and internal signals . . . . .	2476
58.4.3	LPTIM input and trigger mapping . . . . .	2478
58.4.4	LPTIM reset and clocks . . . . .	2479
58.4.5	Glitch filter . . . . .	2480

58.4.6	Prescaler . . . . .	2481
58.4.7	Trigger multiplexer . . . . .	2481
58.4.8	Operating mode . . . . .	2482
58.4.9	Timeout function . . . . .	2484
58.4.10	Waveform generation . . . . .	2484
58.4.11	Register update . . . . .	2485
58.4.12	Counter mode . . . . .	2486
58.4.13	Timer enable . . . . .	2486
58.4.14	Timer counter reset . . . . .	2487
58.4.15	Encoder mode . . . . .	2487
58.4.16	Repetition counter . . . . .	2489
58.4.17	Capture/compare channels . . . . .	2490
58.4.18	Input capture mode . . . . .	2491
58.4.19	PWM mode . . . . .	2493
58.4.20	Autonomous mode . . . . .	2495
58.4.21	DMA requests . . . . .	2496
58.4.22	Debug mode . . . . .	2497
58.5	LPTIM low-power modes . . . . .	2497
58.6	LPTIM interrupts . . . . .	2497
58.7	LPTIM registers . . . . .	2498
58.7.1	LPTIM4 interrupt and status register (LPTIM4_ISR) . . . . .	2499
58.7.2	LPTIMx interrupt and status register [alternate] (LPTIMx_ISR) (x = 1 to 3) . . . . .	2500
58.7.3	LPTIMx interrupt and status register [alternate] (LPTIMx_ISR) (x = 1 to 3) . . . . .	2502
58.7.4	LPTIM4 interrupt clear register (LPTIM4_ICR) . . . . .	2504
58.7.5	LPTIMx interrupt clear register [alternate] (LPTIMx_ICR) (x = 1 to 3) . . . . .	2505
58.7.6	LPTIMx interrupt clear register [alternate] (LPTIMx_ICR) (x = 1 to 3) . . . . .	2506
58.7.7	LPTIM4 interrupt enable register (LPTIM4_DIER) . . . . .	2507
58.7.8	LPTIMx interrupt enable register [alternate] (LPTIMx_DIER) (x = 1 to 3) . . . . .	2509
58.7.9	LPTIMx interrupt enable register [alternate] (LPTIMx_DIER) (x = 1 to 3) . . . . .	2510
58.7.10	LPTIM configuration register (LPTIM_CFGR) . . . . .	2512
58.7.11	LPTIM control register (LPTIM_CR) . . . . .	2515
58.7.12	LPTIM compare register 1 (LPTIM_CCR1) . . . . .	2516

58.7.13	LPTIM autoreload register (LPTIM_ARR) . . . . .	2517
58.7.14	LPTIM counter register (LPTIM_CNT) . . . . .	2517
58.7.15	LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .	2518
58.7.16	LPTIM repetition register (LPTIM_RCR) . . . . .	2519
58.7.17	LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . .	2519
58.7.18	LPTIM compare register 2 (LPTIM_CCR2) . . . . .	2522
58.7.19	LPTIM register map . . . . .	2522
59	Graphic timer (GFXTIM) . . . . .	2525
59.1	GFXTIM introduction . . . . .	2525
59.2	GFXTIM main features . . . . .	2525
59.3	GFXTIM functional description . . . . .	2525
59.3.1	Block diagram . . . . .	2525
59.3.2	GFXTIM pins and internal signals . . . . .	2526
59.3.3	Clock generator . . . . .	2527
59.3.4	Example of clock generator configuration . . . . .	2529
59.3.5	Absolute timers . . . . .	2533
59.3.6	Relative timers . . . . .	2534
59.3.7	Tearing-effect detection . . . . .	2535
59.3.8	Event generator . . . . .	2535
59.3.9	Watchdog timer . . . . .	2536
59.4	GFXTIM interrupts . . . . .	2537
59.5	GFXTIM registers . . . . .	2538
59.5.1	GFXTIM configuration register (GFXTIM_CR) . . . . .	2538
59.5.2	GFXTIM clock generator configuration register (GFXTIM_CGCR) . . . . .	2539
59.5.3	GFXTIM timers configuration register (GFXTIM_TCR) . . . . .	2541
59.5.4	GFXTIM timers disable register (GFXTIM_TDR) . . . . .	2542
59.5.5	GFXTIM events control register (GFXTIM_EVCR) . . . . .	2543
59.5.6	GFXTIM events selection register (GFXTIM_EVSR) . . . . .	2543
59.5.7	GFXTIM watchdog timer configuration register (GFXTIM_WDGTCR) . . . . .	2545
59.5.8	GFXTIM interrupt status register (GFXTIM_ISR) . . . . .	2547
59.5.9	GFXTIM interrupt clear register (GFXTIM_ICR) . . . . .	2548
59.5.10	GFXTIM interrupt enable register (GFXTIM_IER) . . . . .	2550
59.5.11	GFXTIM timers status register (GFXTIM_TSR) . . . . .	2552
59.5.12	GFXTIM line-clock counter reload register (GFXTIM_LCCRR) . . . . .	2553
59.5.13	GFXTIM frame-clock counter reload register (GFXTIM_FCCRR) . . . . .	2553

59.5.14	GFXTIM absolute time register (GFXTIM_ATR) . . . . .	2553
59.5.15	GFXTIM absolute frame counter register (GFXTIM_AFCR) . . . . .	2554
59.5.16	GFXTIM absolute line counter register (GFXTIM_ALCR) . . . . .	2554
59.5.17	GFXTIM absolute frame counter compare 1 register (GFXTIM_AFCC1R) . . . . .	2555
59.5.18	GFXTIM absolute line counter compare 1 register (GFXTIM_ALCC1R) . . . . .	2555
59.5.19	GFXTIM absolute line counter compare 2 register (GFXTIM_ALCC2R) . . . . .	2555
59.5.20	GFXTIM relative frame counter 1 register (GFXTIM_RFC1R) . . . . .	2556
59.5.21	GFXTIM relative frame counter 1 reload register (GFXTIM_RFC1RR) . . . . .	2556
59.5.22	GFXTIM relative frame counter 2 register (GFXTIM_RFC2R) . . . . .	2557
59.5.23	GFXTIM relative frame counter 2 reload register (GFXTIM_RFC2RR) . . . . .	2557
59.5.24	GFXTIM watchdog counter register (GFXTIM_WDGCR) . . . . .	2557
59.5.25	GFXTIM watchdog reload register (GFXTIM_WDGRR) . . . . .	2558
59.5.26	GFXTIM watchdog pre-alarm register (GFXTIM_WDGPAR) . . . . .	2558
59.5.27	GFXTIM register map . . . . .	2558
60	Infrared interface (IRTIM) . . . . .	2561
61	Independent watchdog (IWDG) . . . . .	2562
61.1	IWDG introduction . . . . .	2562
61.2	IWDG main features . . . . .	2562
61.3	IWDG implementation . . . . .	2562
61.4	IWDG functional description . . . . .	2563
61.4.1	IWDG block diagram . . . . .	2563
61.4.2	IWDG internal signals . . . . .	2564
61.4.3	Software and hardware watchdog modes . . . . .	2564
61.4.4	Window option . . . . .	2565
61.4.5	Debug . . . . .	2568
61.4.6	Register access protection . . . . .	2568
61.5	IWDG low power modes . . . . .	2568
61.6	IWDG interrupts . . . . .	2569
61.7	IWDG registers . . . . .	2570
61.7.1	IWDG key register (IWDG_KR) . . . . .	2570
61.7.2	IWDG prescaler register (IWDG_PR) . . . . .	2571

61.7.3	IWDG reload register (IWDG_RLR) . . . . .	2572
61.7.4	IWDG status register (IWDG_SR) . . . . .	2572
61.7.5	IWDG window register (IWDG_WINR) . . . . .	2573
61.7.6	IWDG early wake-up interrupt register (IWDG_EWCR) . . . . .	2574
61.7.7	IWDG register map . . . . .	2575
62	System window watchdog (WWDG) . . . . .	2576
62.1	WWDG introduction . . . . .	2576
62.2	WWDG main features . . . . .	2576
62.3	WWDG implementation . . . . .	2576
62.4	WWDG functional description . . . . .	2577
62.4.1	WWDG block diagram . . . . .	2577
62.4.2	WWDG internal signals . . . . .	2577
62.4.3	Enabling the watchdog . . . . .	2578
62.4.4	Controlling the down-counter . . . . .	2578
62.4.5	How to program the watchdog timeout . . . . .	2578
62.4.6	Debug mode . . . . .	2579
62.5	WWDG interrupts . . . . .	2580
62.6	WWDG registers . . . . .	2580
62.6.1	WWDG control register (WWDG_CR) . . . . .	2580
62.6.2	WWDG configuration register (WWDG_CFR) . . . . .	2581
62.6.3	WWDG status register (WWDG_SR) . . . . .	2582
62.6.4	WWDG register map . . . . .	2582
63	Real-time clock (RTC) . . . . .	2583
63.1	RTC introduction . . . . .	2583
63.2	RTC main features . . . . .	2583
63.3	RTC functional description . . . . .	2584
63.3.1	RTC block diagram . . . . .	2584
63.3.2	RTC pins and internal signals . . . . .	2586
63.3.3	GPIOs controlled by the RTC and TAMP . . . . .	2587
63.3.4	RTC secure protection modes . . . . .	2590
63.3.5	RTC privilege protection modes . . . . .	2591
63.3.6	Clock and prescalers . . . . .	2592
63.3.7	Real-time clock and calendar . . . . .	2594
63.3.8	Calendar ultra-low power mode . . . . .	2594

63.3.9	Programmable alarms . . . . .	2594
63.3.10	Periodic auto-wake-up . . . . .	2595
63.3.11	RTC initialization and configuration . . . . .	2596
63.3.12	Reading the calendar . . . . .	2598
63.3.13	Resetting the RTC . . . . .	2599
63.3.14	RTC synchronization . . . . .	2600
63.3.15	RTC reference clock detection . . . . .	2600
63.3.16	RTC smooth digital calibration . . . . .	2601
63.3.17	Timestamp function . . . . .	2603
63.3.18	Calibration clock output . . . . .	2604
63.3.19	Tamper and alarm output . . . . .	2605
63.4	RTC low-power modes . . . . .	2605
63.5	RTC interrupts . . . . .	2606
63.6	RTC registers . . . . .	2607
63.6.1	RTC time register (RTC_TR) . . . . .	2607
63.6.2	RTC date register (RTC_DR) . . . . .	2608
63.6.3	RTC subsecond register (RTC_SSR) . . . . .	2609
63.6.4	RTC initialization control and status register (RTC_ICSR) . . . . .	2610
63.6.5	RTC prescaler register (RTC_PRER) . . . . .	2612
63.6.6	RTC wake-up timer register (RTC_WUTR) . . . . .	2613
63.6.7	RTC control register (RTC_CR) . . . . .	2613
63.6.8	RTC privilege mode control register (RTC_PRIVCFGR) . . . . .	2617
63.6.9	RTC secure configuration register (RTC_SECCFGR) . . . . .	2619
63.6.10	RTC write protection register (RTC_WPR) . . . . .	2620
63.6.11	RTC calibration register (RTC_CALR) . . . . .	2621
63.6.12	RTC shift control register (RTC_SHIFTR) . . . . .	2622
63.6.13	RTC timestamp time register (RTC_TSTR) . . . . .	2623
63.6.14	RTC timestamp date register (RTC_TSDR) . . . . .	2624
63.6.15	RTC timestamp subsecond register (RTC_TSSSR) . . . . .	2625
63.6.16	RTC alarm A register (RTC_ALRMAR) . . . . .	2625
63.6.17	RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .	2627
63.6.18	RTC alarm B register (RTC_ALRMBR) . . . . .	2628
63.6.19	RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .	2629
63.6.20	RTC status register (RTC_SR) . . . . .	2630
63.6.21	RTC nonsecure masked interrupt status register (RTC_MISR) . . . . .	2632
63.6.22	RTC secure masked interrupt status register (RTC_SMISR) . . . . .	2633
63.6.23	RTC status clear register (RTC_SCR) . . . . .	2634

63.6.24	RTC alarm A binary mode register (RTC_ALRABINR) . . . . .	2635
63.6.25	RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .	2635
63.6.26	RTC register map . . . . .	2637
64	Tamper and backup registers (TAMP) . . . . .	2639
64.1	TAMP introduction . . . . .	2639
64.2	TAMP main features . . . . .	2640
64.3	TAMP implementation . . . . .	2640
64.4	TAMP functional description . . . . .	2641
64.4.1	TAMP block diagram . . . . .	2641
64.4.2	TAMP pins and internal signals . . . . .	2642
64.4.3	GPIOs controlled by the RTC and TAMP . . . . .	2645
64.4.4	TAMP register write protection . . . . .	2645
64.4.5	TAMP secure protection modes . . . . .	2645
64.4.6	Backup registers protection zones . . . . .	2646
64.4.7	TAMP privilege protection modes . . . . .	2646
64.4.8	Boot hardware key (BHK) . . . . .	2647
64.4.9	Tamper detection . . . . .	2647
64.4.10	TAMP backup registers and other device secrets erase . . . . .	2647
64.4.11	Tamper detection configuration and initialization . . . . .	2649
64.5	TAMP low-power modes . . . . .	2656
64.6	TAMP interrupts . . . . .	2656
64.7	TAMP registers . . . . .	2657
64.7.1	TAMP control register 1 (TAMP_CR1) . . . . .	2657
64.7.2	TAMP control register 2 (TAMP_CR2) . . . . .	2659
64.7.3	TAMP control register 3 (TAMP_CR3) . . . . .	2661
64.7.4	TAMP filter control register (TAMP_FLTCR) . . . . .	2662
64.7.5	TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .	2664
64.7.6	TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .	2666
64.7.7	TAMP active tamper output register (TAMP_ATOR) . . . . .	2667
64.7.8	TAMP active tamper control register 2 (TAMP_ATCR2) . . . . .	2668
64.7.9	TAMP secure configuration register (TAMP_SECCFGR) . . . . .	2671
64.7.10	TAMP privilege configuration register (TAMP_PRIVCFGR) . . . . .	2673
64.7.11	TAMP interrupt enable register (TAMP_IER) . . . . .	2674
64.7.12	TAMP status register (TAMP_SR) . . . . .	2676
64.7.13	TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .	2678

64.7.14	TAMP secure masked interrupt status register (TAMP_SMISR) . . . .	2679
64.7.15	TAMP status clear register (TAMP_SCR) . . . . .	2681
64.7.16	TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . .	2683
64.7.17	TAMP erase configuration register (TAMP_ERCFGGR) . . . . .	2683
64.7.18	TAMP backup x register (TAMP_BKPxR) . . . . .	2684
64.7.19	TAMP register map . . . . .	2685
65	Inter-integrated circuit interface (I2C) . . . . .	2687
65.1	I2C introduction . . . . .	2687
65.2	I2C main features . . . . .	2687
65.3	I2C implementation . . . . .	2688
65.4	I2C functional description . . . . .	2689
65.4.1	I2C block diagram . . . . .	2690
65.4.2	I2C pins and internal signals . . . . .	2690
65.4.3	I2C clock requirements . . . . .	2692
65.4.4	I2C mode selection . . . . .	2692
65.4.5	I2C initialization . . . . .	2693
65.4.6	I2C reset . . . . .	2697
65.4.7	I2C data transfer . . . . .	2698
65.4.8	I2C target mode . . . . .	2700
65.4.9	I2C controller mode . . . . .	2709
65.4.10	I2C_TIMINGR register configuration examples . . . . .	2720
65.4.11	SMBus specific features . . . . .	2722
65.4.12	SMBus initialization . . . . .	2724
65.4.13	SMBus I2C_TIMEOUTR register configuration examples . . . . .	2726
65.4.14	SMBus target mode . . . . .	2727
65.4.15	SMBus controller mode . . . . .	2730
65.4.16	Autonomous mode . . . . .	2733
65.4.17	Error conditions . . . . .	2735
65.5	I2C in low-power modes . . . . .	2736
65.6	I2C interrupts . . . . .	2737
65.7	I2C DMA requests . . . . .	2737
65.7.1	Transmission using DMA . . . . .	2737
65.7.2	Reception using DMA . . . . .	2738
65.7.3	Controller event control using DMA . . . . .	2738
65.8	I2C debug modes . . . . .	2739

65.9	I2C registers . . . . .	2739
65.9.1	I2C control register 1 (I2C_CR1) . . . . .	2739
65.9.2	I2C control register 2 (I2C_CR2) . . . . .	2742
65.9.3	I2C own address 1 register (I2C_OAR1) . . . . .	2744
65.9.4	I2C own address 2 register (I2C_OAR2) . . . . .	2744
65.9.5	I2C timing register (I2C_TIMINGR) . . . . .	2745
65.9.6	I2C timeout register (I2C_TIMEOUTR) . . . . .	2746
65.9.7	I2C interrupt and status register (I2C_ISR) . . . . .	2747
65.9.8	I2C interrupt clear register (I2C_ICR) . . . . .	2750
65.9.9	I2C PEC register (I2C_PECR) . . . . .	2751
65.9.10	I2C receive data register (I2C_RXDR) . . . . .	2751
65.9.11	I2C transmit data register (I2C_TXDR) . . . . .	2752
65.9.12	I2C autonomous mode control register (I2C_AUTOCR) . . . . .	2752
65.9.13	I2C register map . . . . .	2754
66	Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .	2756
66.1	USART introduction . . . . .	2756
66.2	USART main features . . . . .	2756
66.3	USART extended features . . . . .	2757
66.4	USART implementation . . . . .	2757
66.5	USART functional description . . . . .	2759
66.5.1	USART block diagram . . . . .	2759
66.5.2	USART pins and internal signals . . . . .	2759
66.5.3	USART clocks . . . . .	2762
66.5.4	USART character description . . . . .	2762
66.5.5	USART FIFOs and thresholds . . . . .	2764
66.5.6	USART transmitter . . . . .	2764
66.5.7	USART receiver . . . . .	2767
66.5.8	USART baud rate generation . . . . .	2774
66.5.9	Tolerance of the USART receiver to clock deviation . . . . .	2776
66.5.10	USART auto baud rate detection . . . . .	2777
66.5.11	USART multiprocessor communication . . . . .	2779
66.5.12	USART Modbus communication . . . . .	2781
66.5.13	USART parity control . . . . .	2782
66.5.14	USART LIN (local interconnection network) mode . . . . .	2783
66.5.15	USART synchronous mode . . . . .	2785

66.5.16	USART single-wire half-duplex communication . . . . .	2789
66.5.17	USART receiver timeout . . . . .	2789
66.5.18	USART smartcard mode . . . . .	2790
66.5.19	USART IrDA SIR ENDEC block . . . . .	2794
66.5.20	Continuous communication using USART and DMA . . . . .	2797
66.5.21	RS232 hardware flow control and RS485 driver enable . . . . .	2799
66.5.22	USART autonomous mode . . . . .	2801
66.6	USART in low-power modes . . . . .	2803
66.7	USART interrupts . . . . .	2804
66.8	USART registers . . . . .	2806
66.8.1	USART control register 1 (USART_CR1) . . . . .	2806
66.8.2	USART control register 1 [alternate] (USART_CR1) . . . . .	2810
66.8.3	USART control register 2 (USART_CR2) . . . . .	2813
66.8.4	USART control register 3 (USART_CR3) . . . . .	2817
66.8.5	USART control register 3 [alternate] (USART_CR3) . . . . .	2821
66.8.6	USART baud rate register (USART_BRR) . . . . .	2824
66.8.7	USART guard time and prescaler register (USART_GTPR) . . . . .	2825
66.8.8	USART receiver timeout register (USART_RTOR) . . . . .	2826
66.8.9	USART request register (USART_RQR) . . . . .	2827
66.8.10	USART interrupt and status register (USART_ISR) . . . . .	2828
66.8.11	USART interrupt and status register [alternate] (USART_ISR) . . . . .	2834
66.8.12	USART interrupt flag clear register (USART_ICR) . . . . .	2839
66.8.13	USART receive data register (USART_RDR) . . . . .	2840
66.8.14	USART transmit data register (USART_TDR) . . . . .	2841
66.8.15	USART prescaler register (USART_PRESC) . . . . .	2841
66.8.16	USART autonomous mode control register (USART_AUTOCR) . . . . .	2842
66.8.17	USART register map . . . . .	2843
67	Low-power universal asynchronous receiver transmitter (LPUART) . . . . .	2845
67.1	LPUART introduction . . . . .	2845
67.2	LPUART main features . . . . .	2845
67.3	LPUART implementation . . . . .	2846
67.4	LPUART functional description . . . . .	2848
67.4.1	LPUART block diagram . . . . .	2848
67.4.2	LPUART pins and internal signals . . . . .	2849

67.4.3	LPUART clocks . . . . .	2851
67.4.4	LPUART character description . . . . .	2851
67.4.5	LPUART FIFOs and thresholds . . . . .	2853
67.4.6	LPUART transmitter . . . . .	2853
67.4.7	LPUART receiver . . . . .	2857
67.4.8	LPUART baud rate generation . . . . .	2861
67.4.9	Tolerance of the LPUART receiver to clock deviation . . . . .	2862
67.4.10	LPUART multiprocessor communication . . . . .	2863
67.4.11	LPUART parity control . . . . .	2865
67.4.12	LPUART single-wire half-duplex communication . . . . .	2866
67.4.13	Continuous communication using DMA and LPUART . . . . .	2866
67.4.14	RS232 hardware flow control and RS485 driver enable . . . . .	2869
67.4.15	LPUART autonomous mode . . . . .	2871
67.5	LPUART in low-power modes . . . . .	2873
67.6	LPUART interrupts . . . . .	2874
67.7	LPUART registers . . . . .	2875
67.7.1	LPUART control register 1 (LPUART_CR1) . . . . .	2875
67.7.2	LPUART control register 1 [alternate] (LPUART_CR1) . . . . .	2878
67.7.3	LPUART control register 2 (LPUART_CR2) . . . . .	2881
67.7.4	LPUART control register 3 (LPUART_CR3) . . . . .	2883
67.7.5	LPUART control register 3 [alternate] (LPUART_CR3) . . . . .	2885
67.7.6	LPUART baud rate register (LPUART_BRR) . . . . .	2887
67.7.7	LPUART request register (LPUART_RQR) . . . . .	2887
67.7.8	LPUART interrupt and status register (LPUART_ISR) . . . . .	2888
67.7.9	LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .	2893
67.7.10	LPUART interrupt flag clear register (LPUART_ICR) . . . . .	2896
67.7.11	LPUART receive data register (LPUART_RDR) . . . . .	2897
67.7.12	LPUART transmit data register (LPUART_TDR) . . . . .	2897
67.7.13	LPUART prescaler register (LPUART_PRESC) . . . . .	2898
67.7.14	LPUART autonomous mode control register (LPUART_AUTOCR) . . . . .	2899
67.7.15	LPUART register map . . . . .	2899
68	Serial peripheral interface (SPI) . . . . .	2902
68.1	SPI introduction . . . . .	2902
68.2	SPI main features . . . . .	2902
68.3	SPI implementation . . . . .	2903

68.4	SPI functional description . . . . .	2904
68.4.1	SPI block diagram . . . . .	2904
68.4.2	SPI pins and internal signals . . . . .	2905
68.4.3	SPI communication general aspects . . . . .	2907
68.4.4	Communications between one master and one slave . . . . .	2907
68.4.5	Standard multislave communication . . . . .	2910
68.4.6	Multimaster communication . . . . .	2911
68.4.7	Slave select (NSS pin) management . . . . .	2912
68.4.8	Ready pin (RDY) management . . . . .	2916
68.4.9	Communication formats . . . . .	2916
68.4.10	Configuring the SPI . . . . .	2918
68.4.11	Enabling the SPI . . . . .	2919
68.4.12	SPI data transmission and reception procedures . . . . .	2920
68.4.13	Disabling the SPI . . . . .	2924
68.4.14	Communication using DMA (direct memory addressing) . . . . .	2925
68.4.15	Autonomous mode . . . . .	2926
68.5	SPI specific modes and control . . . . .	2928
68.5.1	TI mode . . . . .	2928
68.5.2	SPI error flags . . . . .	2929
68.5.3	CRC computation . . . . .	2932
68.6	SPI in low-power modes . . . . .	2933
68.7	SPI interrupts . . . . .	2933
68.8	SPI registers . . . . .	2935
68.8.1	SPI control register 1 (SPI_CR1) . . . . .	2935
68.8.2	SPI control register 2 (SPI_CR2) . . . . .	2937
68.8.3	SPI configuration register 1 (SPI_CFG1) . . . . .	2937
68.8.4	SPI configuration register 2 (SPI_CFG2) . . . . .	2940
68.8.5	SPI interrupt enable register (SPI_IER) . . . . .	2942
68.8.6	SPI status register (SPI_SR) . . . . .	2943
68.8.7	SPI interrupt/status flags clear register (SPI_IFCR) . . . . .	2946
68.8.8	SPI autonomous mode control register (SPI_AUTOCR) . . . . .	2947
68.8.9	SPI transmit data register (SPI_TXDR) . . . . .	2947
68.8.10	SPI receive data register (SPI_RXDR) . . . . .	2948
68.8.11	SPI polynomial register (SPI_CRCPOLY) . . . . .	2948
68.8.12	SPI transmitter CRC register (SPI_TXCRC) . . . . .	2949
68.8.13	SPI receiver CRC register (SPI_RXCRC) . . . . .	2950

68.8.14	SPI underrun data register (SPI_UDRDR) . . . . .	2950
68.8.15	SPI register map . . . . .	2951
69	Serial audio interface (SAI) . . . . .	2952
69.1	SAI introduction . . . . .	2952
69.2	SAI main features . . . . .	2952
69.3	SAI implementation . . . . .	2953
69.4	SAI functional description . . . . .	2954
69.4.1	SAI block diagram . . . . .	2954
69.4.2	SAI pins and internal signals . . . . .	2955
69.4.3	Main SAI modes . . . . .	2956
69.4.4	SAI synchronization mode . . . . .	2957
69.4.5	Audio data size . . . . .	2958
69.4.6	Frame synchronization . . . . .	2958
69.4.7	Slot configuration . . . . .	2961
69.4.8	SAI clock generator . . . . .	2963
69.4.9	Internal FIFOs . . . . .	2966
69.4.10	PDM interface . . . . .	2968
69.4.11	AC'97 link controller . . . . .	2976
69.4.12	SPDIF output . . . . .	2978
69.4.13	Specific features . . . . .	2981
69.4.14	Error flags . . . . .	2985
69.4.15	Disabling the SAI . . . . .	2988
69.4.16	SAI DMA interface . . . . .	2988
69.5	SAI interrupts . . . . .	2989
69.6	SAI registers . . . . .	2991
69.6.1	SAI global configuration register (SAI_GCR) . . . . .	2991
69.6.2	SAI configuration register 1 (SAI_ACR1) . . . . .	2991
69.6.3	SAI configuration register 2 (SAI_ACR2) . . . . .	2994
69.6.4	SAI frame configuration register (SAI_AFRCR) . . . . .	2996
69.6.5	SAI slot register (SAI_ASLOTR) . . . . .	2997
69.6.6	SAI interrupt mask register (SAI_AIM) . . . . .	2998
69.6.7	SAI status register (SAI_ASR) . . . . .	3000
69.6.8	SAI clear flag register (SAI_ACLRFR) . . . . .	3002
69.6.9	SAI data register (SAI_ADR) . . . . .	3003
69.6.10	SAI configuration register 1 (SAI_BCR1) . . . . .	3003

69.6.11 SAI configuration register 2 (SAI_BCR2) . . . . . 3006
69.6.12 SAI frame configuration register (SAI_BFRCR) . . . . . 3008
69.6.13 SAI slot register (SAI_BSLOTR) . . . . . 3009
69.6.14 SAI interrupt mask register (SAI_BIM) . . . . . 3010
69.6.15 SAI status register (SAI_BSR) . . . . . 3011
69.6.16 SAI clear flag register (SAI_BCLRFR) . . . . . 3013
69.6.17 SAI data register (SAI_BDR) . . . . . 3014
69.6.18 SAI PDM control register (SAI_PDMCR) . . . . . 3015
69.6.19 SAI PDM delay register (SAI_PDMDLY) . . . . . 3016
69.6.20 SAI register map . . . . . 3018

70 FD controller area network (FDCAN) . . . . . 3020
70.1 FDCAN introduction . . . . . 3020
70.2 FDCAN main features . . . . . 3022
70.3 FDCAN functional description . . . . . 3023
- 70.3.1 FDCAN block diagram . . . . . 3023
- 70.3.2 FDCAN pins and internal signals . . . . . 3024
- 70.3.3 Bit timing . . . . . 3025
- 70.3.4 Operating modes . . . . . 3026
- 70.3.5 Error management . . . . . 3035
- 70.3.6 Message RAM . . . . . 3036
- 70.3.7 FIFO acknowledge handling . . . . . 3045
- 70.3.8 FDCAN Rx FIFO element . . . . . 3045
- 70.3.9 FDCAN Tx buffer element . . . . . 3047
- 70.3.10 FDCAN Tx event FIFO element . . . . . 3049
- 70.3.11 FDCAN standard message ID filter element . . . . . 3050
- 70.3.12 FDCAN extended message ID filter element . . . . . 3051
70.4 FDCAN registers . . . . . 3053
- 70.4.1 FDCAN core release register (FDCAN_CREL) . . . . . 3053
- 70.4.2 FDCAN endian register (FDCAN_ENDN) . . . . . 3053
- 70.4.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . . 3053
- 70.4.4 FDCAN test register (FDCAN_TEST) . . . . . 3054
- 70.4.5 FDCAN RAM watchdog register (FDCAN_RWD) . . . . . 3055
- 70.4.6 FDCAN CC control register (FDCAN_CCCR) . . . . . 3056
- 70.4.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . . 3057
- 70.4.8 FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . . 3059
- 70.4.9 FDCAN timestamp counter value register (FDCAN_TSCV) . . . . . 3059

70.4.10	FDCAN timeout counter configuration register (FDCAN_TOCC) . . .	3060
70.4.11	FDCAN timeout counter value register (FDCAN_TOCV) . . . . .	3061
70.4.12	FDCAN error counter register (FDCAN_ECR) . . . . .	3061
70.4.13	FDCAN protocol status register (FDCAN_PSR) . . . . .	3062
70.4.14	FDCAN transmitter delay compensation register (FDCAN_TDCR) . .	3064
70.4.15	FDCAN interrupt register (FDCAN_IR) . . . . .	3064
70.4.16	FDCAN interrupt enable register (FDCAN_IE) . . . . .	3067
70.4.17	FDCAN interrupt line select register (FDCAN_ILS) . . . . .	3069
70.4.18	FDCAN interrupt line enable register (FDCAN_ILE) . . . . .	3070
70.4.19	FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .	3070
70.4.20	FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .	3072
70.4.21	FDCAN high-priority message status register (FDCAN_HPMS) . . . .	3072
70.4.22	FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .	3073
70.4.23	CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .	3074
70.4.24	FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .	3074
70.4.25	FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .	3075
70.4.26	FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .	3075
70.4.27	FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .	3076
70.4.28	FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .	3076
70.4.29	FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .	3077
70.4.30	FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . .	3078
70.4.31	FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) .	3078
70.4.32	FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . .	3079
70.4.33	FDCAN Tx buffer transmission interrupt enable register (FDCAN_TXBTIE) . . . . .	3079
70.4.34	FDCAN Tx buffer cancellation finished interrupt enable register (FDCAN_TXBCIE) . . . . .	3080
70.4.35	FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .	3080
70.4.36	FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .	3081
70.4.37	FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .	3081
70.4.38	FDCAN register map . . . . .	3082
71	Universal serial bus full-speed host/device interface (USB) . . . . .	3086
71.1	USB introduction . . . . .	3086
71.2	USB main features . . . . .	3086
71.3	USB implementation . . . . .	3086
71.4	USB functional description . . . . .	3087

- 71.4.1 USB block diagram . . . . . 3087
- 71.4.2 USB pins and internal signals . . . . . 3088
- 71.4.3 USB reset and clocks . . . . . 3088
- 71.4.4 General description and Device mode functionality . . . . . 3088
- 71.4.5 Description of USB blocks used in both Device and Host modes . . . 3089
- 71.4.6 Description of host frame scheduler (HFS) specific to Host mode . . 3090
71.5 Programming considerations for Device and Host modes . . . . . 3091
- 71.5.1 Generic USB Device programming . . . . . 3091
- 71.5.2 System and power-on reset . . . . . 3092
- 71.5.3 Double-buffered endpoints and usage in Device mode . . . . . 3099
- 71.5.4 Double buffered channels: usage in Host mode . . . . . 3101
- 71.5.5 Isochronous transfers in Device mode . . . . . 3102
- 71.5.6 Isochronous transfers in Host mode . . . . . 3103
- 71.5.7 Suspend/resume events . . . . . 3104
71.6 USB registers . . . . . 3107
- 71.6.1 USB control register (USB_CNTR) . . . . . 3108
- 71.6.2 USB interrupt status register (USB_ISTR) . . . . . 3111
- 71.6.3 USB frame number register (USB_FNR) . . . . . 3115
- 71.6.4 USB Device address (USB_DADDR) . . . . . 3115
- 71.6.5 USB LPM control and status register (USB_LPMCSR) . . . . . 3116
- 71.6.6 USB battery charging detector (USB_BCDR) . . . . . 3117
- 71.6.7 USB endpoint/channel n register (USB_CHEPnR) . . . . . 3118
71.7 USBFSRAM registers . . . . . 3127
- 71.7.1 Channel/endpoint transmit buffer descriptor n
  (USB_CHEP_TXRXBD_n) . . . . . 3128
- 71.7.2 Channel/endpoint receive buffer descriptor n [alternate]
  (USB_CHEP_TXRXBD_n) . . . . . 3128
- 71.7.3 Channel/endpoint receive buffer descriptor n
  (USB_CHEP_RXTXBD_n) . . . . . 3130
- 71.7.4 Channel/endpoint transmit buffer descriptor n [alternate]
  (USB_CHEP_RXTXBD_n) . . . . . 3131
- 71.7.5 USBFSRAM register map . . . . . 3132

72 USB on-the-go full-speed (OTG_FS) . . . . . 3133

72.1 Introduction . . . . . 3133
72.2 OTG_FS main features . . . . . 3135
- 72.2.1 General features . . . . . 3135
- 72.2.2 Host-mode features . . . . . 3136

72.2.3	Peripheral-mode features . . . . .	3136
72.3	OTG_FS implementation . . . . .	3137
72.4	OTG_FS functional description . . . . .	3138
72.4.1	OTG_FS block diagram . . . . .	3138
72.4.2	OTG_FS pin and internal signals . . . . .	3138
72.4.3	OTG_FS core . . . . .	3139
72.4.4	Embedded full-speed OTG PHY connected to OTG_FS . . . . .	3139
72.4.5	OTG detections . . . . .	3140
72.5	OTG_FS dual role device (DRD) . . . . .	3140
72.5.1	ID line detection . . . . .	3140
72.5.2	HNP dual role device . . . . .	3141
72.5.3	SRP dual role device . . . . .	3141
72.6	OTG_FS as a USB peripheral . . . . .	3141
72.6.1	SRP-capable peripheral . . . . .	3142
72.6.2	Peripheral states . . . . .	3142
72.6.3	Peripheral endpoints . . . . .	3143
72.7	OTG_FS as a USB host . . . . .	3145
72.7.1	SRP-capable host . . . . .	3146
72.7.2	USB host states . . . . .	3146
72.7.3	Host channels . . . . .	3148
72.7.4	Host scheduler . . . . .	3149
72.8	OTG_FS SOF trigger . . . . .	3150
72.8.1	Host SOFs . . . . .	3150
72.8.2	Peripheral SOFs . . . . .	3150
72.9	OTG_FS low-power modes . . . . .	3151
72.10	OTG_FS dynamic update of the OTG_HFIR register . . . . .	3152
72.11	OTG_FS data FIFOs . . . . .	3152
72.11.1	Peripheral FIFO architecture . . . . .	3153
72.11.2	Host FIFO architecture . . . . .	3154
72.11.3	FIFO RAM allocation . . . . .	3155
72.12	OTG_FS system performance . . . . .	3157
72.13	OTG_FS interrupts . . . . .	3157
72.14	OTG_FS control and status registers . . . . .	3159
72.14.1	CSR memory map . . . . .	3159
72.15	OTG_FS registers . . . . .	3163

72.15.1	OTG control and status register (OTG_GOTGCTL) . . . . .	3164
72.15.2	OTG interrupt register (OTG_GOTGINT) . . . . .	3167
72.15.3	OTG AHB configuration register (OTG_GAHBCFG) . . . . .	3168
72.15.4	OTG USB configuration register (OTG_GUSBCFG) . . . . .	3169
72.15.5	OTG reset register (OTG_GRSTCTL) . . . . .	3170
72.15.6	OTG core interrupt register (OTG_GINTSTS) . . . . .	3172
72.15.7	OTG interrupt mask register (OTG_GINTMSK) . . . . .	3177
72.15.8	OTG receive status debug read register (OTG_GRXSTSR) . . . . .	3179
72.15.9	OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .	3180
72.15.10	OTG status read and pop registers (OTG_GRXSTSP) . . . . .	3181
72.15.11	OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .	3182
72.15.12	OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .	3183
72.15.13	OTG host nonperiodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) . . . . .	3184
72.15.14	OTG nonperiodic transmit FIFO/queue status register (OTG_HNPTXSTS) . . . . .	3185
72.15.15	OTG general core configuration register (OTG_GCCFG) . . . . .	3186
72.15.16	OTG core ID register (OTG_CID) . . . . .	3187
72.15.17	OTG core LPM configuration register (OTG_GLPMCFG) . . . . .	3188
72.15.18	OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) . . . . .	3192
72.15.19	OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) . . . . .	3192
72.15.20	Host-mode registers . . . . .	3193
72.15.21	OTG host configuration register (OTG_HCFG) . . . . .	3193
72.15.22	OTG host frame interval register (OTG_HFIR) . . . . .	3194
72.15.23	OTG host frame number/frame time remaining register (OTG_HFNUM) . . . . .	3195
72.15.24	OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS) . . . . .	3195
72.15.25	OTG host all channels interrupt register (OTG_HAINT) . . . . .	3196
72.15.26	OTG host all channels interrupt mask register (OTG_HAINTMSK) . . . . .	3197
72.15.27	OTG host port control and status register (OTG_HPRT) . . . . .	3197
72.15.28	OTG host channel x characteristics register (OTG_HCCHARx) . . . . .	3200
72.15.29	OTG host channel x interrupt register (OTG_HCINTx) . . . . .	3201
72.15.30	OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .	3202
72.15.31	OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .	3203

72.15.32	Device-mode registers . . . . .	3204
72.15.33	OTG device configuration register (OTG_DCFG) . . . . .	3204
72.15.34	OTG device control register (OTG_DCTL) . . . . .	3206
72.15.35	OTG device status register (OTG_DSTS) . . . . .	3208
72.15.36	OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) . . . . .	3209
72.15.37	OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) . . . . .	3210
72.15.38	OTG device all endpoints interrupt register (OTG_DAINIT) . . . . .	3211
72.15.39	OTG all endpoints interrupt mask register (OTG_DAINMSK) . . . . .	3212
72.15.40	OTG device V _BUSdischarge time register (OTG_DVBUSDIS) . . . . .	3212
72.15.41	OTG device V _BUSpulsing time register (OTG_DVBUSPULSE) . . . . .	3213
72.15.42	OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) . . . . .	3213
72.15.43	OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) . . . . .	3214
72.15.44	OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .	3215
72.15.45	OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .	3218
72.15.46	OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) . . . . .	3219
72.15.47	OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) . . . . .	3220
72.15.48	OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .	3221
72.15.49	OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) . . . . .	3222
72.15.50	OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .	3223
72.15.51	OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . .	3225
72.15.52	OTG device OUT endpoint x control register (OTG_DOEPCTLx) . . . . .	3226
72.15.53	OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) . . . . .	3228
72.15.54	OTG power and clock gating control register (OTG_PCGCCTL) . . . . .	3229
72.15.55	OTG_FS register map . . . . .	3230
72.16	OTG_FS programming model . . . . .	3238
72.16.1	Core initialization . . . . .	3238
72.16.2	Host initialization . . . . .	3239
72.16.3	Device initialization . . . . .	3239

72.16.4	Host programming model .....	3240
72.16.5	Device programming model .....	3261
72.16.6	Worst case response time .....	3282
72.16.7	OTG programming model .....	3284
73	USB on-the-go high-speed (OTG_HS) .....	3290
73.1	OTG_HS introduction .....	3290
73.2	OTG_HS main features .....	3291
73.2.1	General features .....	3291
73.2.2	Host-mode features .....	3292
73.2.3	Peripheral-mode features .....	3292
73.3	OTG_HS implementation .....	3292
73.4	OTG_HS functional description .....	3293
73.4.1	OTG_HS block diagram .....	3293
73.4.2	OTG_HS pin and internal signals .....	3294
73.4.3	OTG_HS core .....	3294
73.4.4	OTG detections .....	3295
73.4.5	High-speed OTG PHY connected to OTG_HS .....	3295
73.4.6	Battery charging detection .....	3295
73.5	OTG_HS dual role device (DRD) .....	3295
73.5.1	ID line detection .....	3296
73.6	OTG_HS as a USB peripheral .....	3296
73.6.1	Peripheral states .....	3297
73.6.2	Peripheral endpoints .....	3298
73.7	OTG_HS as a USB host .....	3300
73.7.1	USB host states .....	3301
73.7.2	Host channels .....	3302
73.7.3	Host scheduler .....	3304
73.8	OTG_HS SOF trigger .....	3305
73.8.1	Host SOFs .....	3305
73.8.2	Peripheral SOFs .....	3305
73.9	OTG_HS low-power modes .....	3306
73.10	OTG_HS Dynamic update of the OTG_HFIR register .....	3307
73.11	OTG_HS data FIFOs .....	3307
73.11.1	Peripheral FIFO architecture .....	3308
73.11.2	Host FIFO architecture .....	3309

73.11.3	FIFO RAM allocation . . . . .	3310
73.12	OTG_HS interrupts . . . . .	3312
73.13	OTG_HS control and status registers . . . . .	3314
73.13.1	CSR memory map . . . . .	3314
73.14	OTG_HS registers . . . . .	3319
73.14.1	OTG control and status register (OTG_GOTGCTL) . . . . .	3319
73.14.2	OTG interrupt register (OTG_GOTGINT) . . . . .	3321
73.14.3	OTG AHB configuration register (OTG_GAHBCFG) . . . . .	3322
73.14.4	OTG USB configuration register (OTG_GUSBCFG) . . . . .	3323
73.14.5	OTG reset register (OTG_GRSTCTL) . . . . .	3325
73.14.6	OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .	3328
73.14.7	OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . .	3332
73.14.8	OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .	3337
73.14.9	OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . .	3338
73.14.10	OTG receive status debug read register [alternate] (OTG_GRXSTSR) . . . . .	3340
73.14.11	OTG receive status debug read register [alternate] (OTG_GRXSTSR) . . . . .	3341
73.14.12	OTG status read and pop registers (OTG_GRXSTSP) . . . . .	3342
73.14.13	OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .	3343
73.14.14	OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .	3344
73.14.15	OTG host non-periodic transmit FIFO size register [alternate] (OTG_HNPTXFSIZ) . . . . .	3345
73.14.16	Endpoint 0 transmit FIFO size [alternate] (OTG_DIEPTXF0) . . . . .	3345
73.14.17	OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) . . . . .	3346
73.14.18	OTG general core configuration register (OTG_GCCFG) . . . . .	3347
73.14.19	OTG core ID register (OTG_CID) . . . . .	3348
73.14.20	OTG core LPM configuration register (OTG_GLPMCFG) . . . . .	3349
73.14.21	OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) . . . . .	3353
73.14.22	OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) . . . . .	3353
73.14.23	Host-mode registers . . . . .	3353
73.14.24	OTG host configuration register (OTG_HCFG) . . . . .	3354
73.14.25	OTG host frame interval register (OTG_HFIR) . . . . .	3354
73.14.26	OTG host frame number/frame time remaining register (OTG_HFNUM) . . . . .	3355

73.14.27	OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS)	3356
73.14.28	OTG host all channels interrupt register (OTG_HAINT)	3357
73.14.29	OTG host all channels interrupt mask register (OTG_HAINTMSK)	3357
73.14.30	OTG host port control and status register (OTG_HPRT)	3358
73.14.31	OTG host channel x characteristics register (OTG_HCCHARx)	3360
73.14.32	OTG host channel x split control register (OTG_HCSPLTx)	3361
73.14.33	OTG host channel x interrupt register (OTG_HCINTx)	3362
73.14.34	OTG host channel x interrupt mask register (OTG_HCINTMSKx)	3363
73.14.35	OTG host channel x transfer size register (OTG_HCTSIZx)	3364
73.14.36	OTG host channel x DMA address register(OTG_HCDMAx)	3365
73.14.37	Device-mode registers	3365
73.14.38	OTG device configuration register (OTG_DCFG)	3365
73.14.39	OTG device control register (OTG_DCTL)	3367
73.14.40	OTG device status register (OTG_DSTS)	3369
73.14.41	OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)	3370
73.14.42	OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK)	3371
73.14.43	OTG device all endpoints interrupt register (OTG_DAININT)	3372
73.14.44	OTG all endpoints interrupt mask register (OTG_DAININTMSK)	3373
73.14.45	OTG device threshold control register (OTG_DTHRCCTL)	3373
73.14.46	OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK)	3374
73.14.47	OTG device IN endpoint x control register [alternate] (OTG_DIEPCTLx)	3375
73.14.48	OTG device IN endpoint x control register [alternate] (OTG_DIEPCTLx)	3377
73.14.49	OTG device IN endpoint x interrupt register (OTG_DIEPINTx)	3379
73.14.50	OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0)	3380
73.14.51	OTG device IN endpoint x DMA address register (OTG_DIEPDMAx)	3381
73.14.52	OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx)	3381
73.14.53	OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx)	3382
73.14.54	OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0)	3382
73.14.55	OTG device OUT endpoint x interrupt register (OTG_DOEPINTx)	3384

73.14.56	OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . .	3386
73.14.57	OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) . . . . .	3387
73.14.58	OTG device OUT endpoint x control register [alternate] (OTG_DOEPCTLx) . . . . .	3387
73.14.59	OTG device OUT endpoint x control register [alternate] (OTG_DOEPCTLx) . . . . .	3389
73.14.60	OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) . . . . .	3391
73.14.61	OTG power and clock gating control register (OTG_PCGCTL) . . . . .	3392
73.14.62	OTG power and clock gating control register 1 (OTG_PCGCTL1) . . . . .	3393
73.14.63	OTG_HS register map . . . . .	3394
73.15	OTG_HS programming model . . . . .	3401
73.15.1	Core initialization . . . . .	3401
73.15.2	Host initialization . . . . .	3402
73.15.3	Device initialization . . . . .	3403
73.15.4	DMA mode . . . . .	3403
73.15.5	Host programming model . . . . .	3403
73.15.6	Device programming model . . . . .	3436
73.15.7	Worst case response time . . . . .	3456
73.15.8	OTG programming model . . . . .	3458
74	USB Type-C ^®/USB Power Delivery interface (UCPD) . . . . .	3459
74.1	UCPD introduction . . . . .	3459
74.2	UCPD main features . . . . .	3459
74.3	UCPD implementation . . . . .	3460
74.4	UCPD functional description . . . . .	3460
74.4.1	UCPD block diagram . . . . .	3461
74.4.2	UCPD reset and clocks . . . . .	3462
74.4.3	Physical layer protocol . . . . .	3463
74.4.4	UCPD BMC transmitter . . . . .	3469
74.4.5	UCPD BMC receiver . . . . .	3471
74.4.6	UCPD Type-C pull-ups (Rp) and pull-downs (Rd) . . . . .	3472
74.4.7	UCPD Type-C voltage monitoring and de-bouncing . . . . .	3473
74.4.8	UCPD fast role swap (FRS) . . . . .	3473
74.4.9	UCPD DMA Interface . . . . .	3473
74.4.10	Wake-up from Stop mode . . . . .	3473

74.5	UCPD programming sequences . . . . .	3474
74.5.1	Initialization phase . . . . .	3474
74.5.2	Type-C state machine handling . . . . .	3474
74.5.3	USB PD transmit . . . . .	3476
74.5.4	USB PD receive . . . . .	3477
74.5.5	UCPD software trimming . . . . .	3478
74.6	UCPD low-power modes . . . . .	3478
74.7	UCPD interrupts . . . . .	3479
74.8	UCPD registers . . . . .	3480
74.8.1	UCPD configuration register 1 (UCPD_CFGR1) . . . . .	3480
74.8.2	UCPD configuration register 2 (UCPD_CFGR2) . . . . .	3482
74.8.3	UCPD configuration register 3 (UCPD_CFGR3) . . . . .	3482
74.8.4	UCPD control register (UCPD_CR) . . . . .	3483
74.8.5	UCPD interrupt mask register (UCPD_IMR) . . . . .	3485
74.8.6	UCPD status register (UCPD_SR) . . . . .	3487
74.8.7	UCPD interrupt clear register (UCPD_ICR) . . . . .	3490
74.8.8	UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . .	3491
74.8.9	UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . .	3491
74.8.10	UCPD Tx data register (UCPD_TXDR) . . . . .	3492
74.8.11	UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . .	3492
74.8.12	UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . .	3493
74.8.13	UCPD receive data register (UCPD_RXDR) . . . . .	3494
74.8.14	UCPD Rx ordered set extension register 1 (UCPD_RX_ORDEXTR1) . . . . .	3494
74.8.15	UCPD Rx ordered set extension register 2 (UCPD_RX_ORDEXTR2) . . . . .	3495
74.8.16	UCPD register map . . . . .	3495
75	Debug support (DBG) . . . . .	3498
75.1	DBG introduction . . . . .	3498
75.2	DBG functional description . . . . .	3499
75.2.1	DBG block diagram . . . . .	3499
75.2.2	DBG pins and internal signals . . . . .	3499
75.2.3	DBG reset and clocks . . . . .	3500
75.2.4	DBG power domains . . . . .	3500
75.2.5	Debug and low-power modes . . . . .	3500
75.2.6	Security . . . . .	3501

75.3	Serial-wire and JTAG debug port (SWJ-DP) . . . . .	3502
75.3.1	JTAG debug port . . . . .	3503
75.3.2	Serial-wire debug port . . . . .	3505
75.3.3	Debug port registers . . . . .	3506
75.3.4	Debug port register map . . . . .	3513
75.4	Access ports . . . . .	3514
75.4.1	Access port registers . . . . .	3514
75.4.2	Access port register map . . . . .	3519
75.5	ROM tables . . . . .	3520
75.5.1	MCU ROM table registers . . . . .	3522
75.5.2	MCU ROM table register map . . . . .	3525
75.5.3	Processor ROM table registers . . . . .	3526
75.5.4	Processor ROM table register map . . . . .	3530
75.6	Data watchpoint and trace unit (DWT) . . . . .	3531
75.6.1	DWT registers . . . . .	3532
75.6.2	DWT register map . . . . .	3545
75.7	Instrumentation trace macrocell (ITM) . . . . .	3547
75.7.1	ITM registers . . . . .	3548
75.7.2	ITM register map . . . . .	3555
75.8	Breakpoint unit (BPU) . . . . .	3556
75.8.1	BPU registers . . . . .	3556
75.8.2	BPU register map . . . . .	3562
75.9	Embedded Trace Macrocell (ETM) . . . . .	3563
75.9.1	ETM registers . . . . .	3563
75.9.2	ETM register map . . . . .	3586
75.10	Trace port interface unit (TPIU) . . . . .	3589
75.10.1	TPIU registers . . . . .	3590
75.10.2	TPIU register map . . . . .	3599
75.11	Cross-trigger interface (CTI) . . . . .	3601
75.11.1	CTI registers . . . . .	3602
75.11.2	CTI register map . . . . .	3612
75.12	Microcontroller debug unit (DBGMCU) . . . . .	3614
75.12.1	Device ID . . . . .	3614
75.12.2	Low-power mode emulation . . . . .	3614
75.12.3	Peripheral clock freeze . . . . .	3614
75.12.4	DBGMCU registers . . . . .	3616

75.12.5	DBGMCU register map . . . . .	3626
75.13	References . . . . .	3629
76	Device electronic signature . . . . .	3630
76.1	Unique device ID register (96 bits) . . . . .	3630
76.2	Flash size data register . . . . .	3631
76.3	Package data register . . . . .	3632
77	Important security notice . . . . .	3633
78	Revision history . . . . .	3634

List of tables

Table 1.	Implementation of masters on STM32U5 Series . . . . .	129
Table 2.	Implementation of slaves on STM32U5 Series. . . . .	130
Table 3.	Example of memory map security attribution versus SAU configuration regions . . . . .	134
Table 4.	Securable peripherals by TZSC . . . . .	136
Table 5.	TrustZone aware peripherals . . . . .	138
Table 6.	Memory map and peripheral register boundary addresses . . . . .	145
Table 7.	SRAM sizes . . . . .	149
Table 8.	Configuring security attributes with IDAU and SAU . . . . .	157
Table 9.	MPCWMx resources. . . . .	159
Table 10.	MPCBBx resources . . . . .	159
Table 11.	DMA channel use (security). . . . .	163
Table 12.	Secure alternate function between peripherals and allocated I/Os . . . . .	166
Table 13.	Nonsecure peripheral functions that are not connected to secure I/Os . . . . .	166
Table 14.	Nonsecure peripheral functions that can be connected to secure I/Os . . . . .	167
Table 15.	TrustZone-aware DBGMCU access management . . . . .	168
Table 16.	DMA channel use (privilege). . . . .	173
Table 17.	Internal tampers in TAMP . . . . .	177
Table 18.	Effect of low-power modes on TAMP . . . . .	178
Table 19.	Accelerated-cryptographic operations . . . . .	181
Table 20.	Main product life-cycle transitions. . . . .	183
Table 21.	Typical product life-cycle phases . . . . .	184
Table 22.	OEM1/2 RDP unlocking methods . . . . .	186
Table 23.	Debug protection with RDP . . . . .	187
Table 24.	Software intellectual property protection with RDP. . . . .	189
Table 25.	Boot modes when TrustZone is disabled (TZEN = 0). . . . .	192
Table 26.	Boot modes when TrustZone is enabled (TZEN = 1) . . . . .	193
Table 27.	Boot space versus RDP protection. . . . .	193
Table 28.	GTZC features . . . . .	197
Table 29.	GTZC1 subblocks address offset . . . . .	198
Table 30.	GTZC2 subblocks address offset . . . . .	198
Table 31.	MPCWM resource assignment . . . . .	198
Table 32.	MPCBB resource assignment for STM32U535/545 . . . . .	199
Table 33.	MPCBB resource assignment for STM32U575/585 . . . . .	199
Table 34.	MPCBB resource assignment for STM32U59x/5Ax . . . . .	199
Table 35.	MPCBB resource assignment for STM32U5Fx/5Gx. . . . .	199
Table 36.	Secure properties of sub-regions A and B . . . . .	202
Table 37.	Privileged properties of sub-regions A and B . . . . .	202
Table 38.	GTZC interrupt request. . . . .	204
Table 39.	GTZC1 TZSC register map and reset values . . . . .	222
Table 40.	GTZC1 TZIC register map and reset values. . . . .	254
Table 41.	GTZC1 MPCBBz register map and reset values (z = 1, 2, 3, 5, 6). . . . .	259
Table 42.	GTZC2 TZSC register map and reset values . . . . .	263
Table 43.	GTZC2 TZIC register map and reset values. . . . .	271
Table 44.	GTZC2 MPCBB4 register map and reset values . . . . .	274
Table 45.	SRAM structure . . . . .	276
Table 46.	Internal SRAMs features. . . . .	277
Table 47.	Number of wait states versus HCLK frequency and voltage range scaling . . . . .	280
Table 48.	Effect of low-power modes on RAMCFG . . . . .	281

Table 49.	RAMCFG interrupt requests . . . . .	281
Table 50.	RAMCFG register map and reset values . . . . .	287
Table 51.	Flash module 512-Kbyte dual-bank organization for STM32U535/545 . . . . .	293
Table 52.	Flash module 2-Mbyte dual-bank organization for STM32U575/585 . . . . .	293
Table 53.	Flash module 4-Mbyte dual-bank organization for STM32U59x/5Ax/5Fx/5Gx . . . . .	294
Table 54.	Number of wait states according to CPU clock (HCLK) frequency (LPM = 0) . . . . .	295
Table 55.	Number of wait states according to CPU clock (HCLK) frequency (LPM = 1) . . . . .	296
Table 56.	Flash operation interrupted by a system reset . . . . .	305
Table 57.	User option-byte organization mapping . . . . .	306
Table 58.	Default secure option bytes after TZEN activation . . . . .	309
Table 59.	Secure watermark-based area . . . . .	309
Table 60.	Secure hide protection . . . . .	311
Table 61.	Secure and HDP protections . . . . .	311
Table 62.	Flash security state . . . . .	312
Table 63.	WRP protection . . . . .	316
Table 64.	Flash memory readout protection status (TZEN = 0) . . . . .	317
Table 65.	Access status versus protection level and execution modes when TZEN = 0 . . . . .	318
Table 66.	Flash memory readout protection status (TZEN = 1) . . . . .	318
Table 67.	Access status versus protection level and execution modes when TZEN = 1 . . . . .	320
Table 68.	Flash memory access versus RDP level when TrustZone is active (TZEN = 1) . . . . .	325
Table 69.	Flash memory access versus RDP level when TrustZone is disabled (TZEN = 0) . . . . .	326
Table 70.	Flash memory mass erase versus RDP level when TrustZone is active (TZEN = 1) . . . . .	326
Table 71.	Flash system memory, OTP and RSS accesses . . . . .	327
Table 72.	Flash registers access . . . . .	327
Table 73.	Flash page access versus privilege mode . . . . .	327
Table 74.	Flash mass erase versus privilege mode . . . . .	328
Table 75.	SECyBBRx registers access when TrustZone is active (TZEN = 1) . . . . .	328
Table 76.	PRIVyBBRx registers access when TrustZone is active (TZEN = 1) . . . . .	328
Table 77.	PRIVyBBRx registers access when TrustZone is disabled (TZEN = 0) . . . . .	328
Table 78.	Flash interrupt requests . . . . .	329
Table 79.	FLASH register map and reset values . . . . .	360
Table 80.	ICACHE features for STM32U535/545/575/585 . . . . .	365
Table 81.	ICACHE features for STM32U59x/5Ax/5Fx/5Gx . . . . .	365
Table 82.	TAG memory dimensioning parameters for n-way set associative operating mode (default) . . . . .	367
Table 83.	TAG memory dimensioning parameters for direct-mapped cache mode . . . . .	369
Table 84.	ICACHE cacheability for AHB transaction . . . . .	370
Table 85.	Memory configurations . . . . .	371
Table 86.	ICACHE remap region size, base address, and remap address . . . . .	372
Table 87.	ICACHE interrupts . . . . .	376
Table 88.	ICACHE register map and reset values . . . . .	380
Table 89.	DCACHE features for STM32U535/545/575/585 . . . . .	383
Table 90.	DCACHE features for STM32U59x/5Ax/5Fx/5Gx . . . . .	383
Table 91.	TAG memory dimensioning parameters . . . . .	386
Table 92.	DCACHE cacheability for AHB transaction . . . . .	388
Table 93.	DCACHE interrupts . . . . .	393
Table 94.	DCACHE register map and reset values . . . . .	399
Table 95.	PWR input/output pins . . . . .	401
Table 97.	PWR wake-up source selection . . . . .	402
Table 96.	PWR internal input/output signals . . . . .	402
Table 98.	PVM features . . . . .	413
Table 99.	Low-power mode summary . . . . .	417

Table 100.	Functionalities depending on the working mode . . . . .	418
Table 101.	Sleep mode . . . . .	426
Table 102.	Stop 0 mode . . . . .	428
Table 103.	Stop 1 mode . . . . .	429
Table 104.	Stop 2 mode . . . . .	431
Table 105.	Stop 3 mode . . . . .	434
Table 106.	Standby mode . . . . .	436
Table 107.	Shutdown mode . . . . .	438
Table 108.	Power modes output states versus MCU power modes . . . . .	439
Table 109.	PWR Security configuration summary . . . . .	440
Table 110.	PWR interrupt requests . . . . .	442
Table 111.	PWR register map and reset values . . . . .	479
Table 112.	RCC input/output signals connected to package pins or balls . . . . .	483
Table 113.	MSIS and MSIK ranges per internal MSIRCs (PLL_mode disabled) . . . . .	490
Table 114.	Bus maximum frequency . . . . .	498
Table 115.	Clock source maximum frequency . . . . .	498
Table 116.	Autonomous peripherals . . . . .	504
Table 117.	RCC security configuration summary . . . . .	506
Table 118.	Interrupt sources and control . . . . .	510
Table 119.	RCC register map and reset values . . . . .	604
Table 120.	CRS features . . . . .	610
Table 121.	CRS internal input/output signals . . . . .	611
Table 122.	CRS interconnection for STM32U535/545/575/585 . . . . .	612
Table 123.	CRS interconnection for STM32U59x/5Ax/5Fx/5Gx . . . . .	612
Table 124.	Effect of low-power modes on CRS . . . . .	615
Table 125.	Interrupt control bits . . . . .	615
Table 126.	CRS register map and reset values . . . . .	620
Table 127.	Port bit configuration . . . . .	623
Table 128.	GPIO secured bits . . . . .	631
Table 129.	GPIO register map and reset values . . . . .	641
Table 130.	LPGPIO register map and reset values . . . . .	647
Table 131.	TrustZone security and privilege register accesses . . . . .	650
Table 132.	BOOSTEN and ANASWVDD set/reset . . . . .	654
Table 133.	SYSCFG register map and reset values . . . . .	666
Table 134.	Peripherals interconnect matrix . . . . .	669
Table 135.	GPDMA1 channel implementation . . . . .	687
Table 136.	GPDMA1 autonomous mode and wake-up in low-power modes . . . . .	687
Table 137.	Programmed GPDMA1 request . . . . .	687
Table 138.	Programmed GPDMA1 request as a block request . . . . .	691
Table 139.	Programmed GPDMA1 trigger . . . . .	691
Table 140.	Programmed GPDMA source/destination burst . . . . .	713
Table 141.	Programmed data handling . . . . .	718
Table 142.	Effect of low-power modes on GPDMA . . . . .	731
Table 143.	GPDMA interrupt requests . . . . .	732
Table 144.	GPDMA register map and reset values . . . . .	762
Table 145.	LPDMA1 channels implementation . . . . .	766
Table 146.	LPDMA1 channels implementation . . . . .	766
Table 147.	LPDMA1 autonomous mode and wake-up in low-power modes . . . . .	767
Table 148.	Programmed LPDMA1 request . . . . .	767
Table 149.	Programmed LPDMA1 request as a block request . . . . .	768
Table 150.	Programmed LPDMA1 trigger . . . . .	768
Table 151.	Programmed LPDMA source/destination single . . . . .	788

Table 152.	Programmed data handling . . . . .	789
Table 153.	Effect of low-power modes on LPDMA . . . . .	801
Table 154.	LPDMA interrupt requests . . . . .	802
Table 155.	LPDMA register map and reset values . . . . .	821
Table 156.	DMA2D internal signals . . . . .	825
Table 157.	DMA2D trigger interconnection . . . . .	825
Table 158.	Supported color mode in input . . . . .	826
Table 159.	Data order in memory . . . . .	827
Table 160.	Alpha mode configuration . . . . .	828
Table 161.	Supported CLUT color mode . . . . .	829
Table 162.	CLUT data order in system memory . . . . .	829
Table 163.	Supported color mode in output . . . . .	830
Table 164.	Data order in memory . . . . .	831
Table 165.	Standard data order in memory . . . . .	831
Table 166.	Output FIFO byte reordering steps . . . . .	832
Table 167.	DMA2D interrupt requests . . . . .	838
Table 168.	DMA2D register map and reset values . . . . .	856
Table 169.	DMA2D internal signals . . . . .	860
Table 170.	DMA2D trigger interconnections . . . . .	860
Table 171.	Supported color mode in input . . . . .	861
Table 172.	Data order in memory . . . . .	862
Table 173.	Alpha mode configuration . . . . .	863
Table 174.	Supported CLUT color mode . . . . .	864
Table 175.	CLUT data order in memory . . . . .	864
Table 176.	Supported color mode in output . . . . .	865
Table 177.	Data order in memory . . . . .	866
Table 178.	Standard data order in memory . . . . .	866
Table 179.	Output FIFO byte reordering steps . . . . .	867
Table 180.	MCU order in memory . . . . .	872
Table 181.	DMA2D interrupt requests . . . . .	873
Table 182.	DMA2D register map and reset values . . . . .	891
Table 183.	GFXMMU implementation . . . . .	893
Table 184.	GFXMMU interrupt requests . . . . .	902
Table 185.	GFXMMU register map and reset values . . . . .	910
Table 186.	STM32U5 series vector table . . . . .	913
Table 187.	EXTI signals . . . . .	920
Table 188.	EVG signals . . . . .	920
Table 189.	EXTI line connections . . . . .	921
Table 190.	Masking functionality . . . . .	923
Table 191.	Register protection overview . . . . .	924
Table 192.	EXTI register map sections . . . . .	926
Table 193.	EXTI register map and reset values . . . . .	935
Table 194.	CRC internal input/output signals . . . . .	938
Table 195.	CRC register map and reset values . . . . .	943
Table 196.	CORDIC functions . . . . .	945
Table 197.	Cosine parameters . . . . .	945
Table 198.	Sine parameters . . . . .	946
Table 199.	Phase parameters . . . . .	946
Table 200.	Modulus parameters . . . . .	947
Table 201.	Arctangent parameters . . . . .	948
Table 202.	Hyperbolic cosine parameters . . . . .	948
Table 203.	Hyperbolic sine parameters . . . . .	949

Table 204.	Hyperbolic arctangent parameters . . . . .	949
Table 205.	Natural logarithm parameters . . . . .	950
Table 206.	Natural log scaling factors and corresponding ranges . . . . .	950
Table 207.	Square root parameters . . . . .	951
Table 208.	Square root scaling factors and corresponding ranges . . . . .	951
Table 209.	Precision vs. number of iterations. . . . .	954
Table 210.	CORDIC register map and reset value . . . . .	961
Table 211.	Valid combinations for read and write methods . . . . .	975
Table 212.	FMAC register map and reset values . . . . .	988
Table 213.	NOR/PSRAM bank selection . . . . .	994
Table 214.	NOR/PSRAM External memory address . . . . .	994
Table 215.	NAND memory mapping and timing registers. . . . .	995
Table 216.	NAND bank selection . . . . .	995
Table 217.	Programmable NOR/PSRAM access parameters . . . . .	996
Table 218.	Non-multiplexed I/O NOR flash memory. . . . .	997
Table 219.	16-bit multiplexed I/O NOR flash memory . . . . .	998
Table 220.	Non-multiplexed I/Os PSRAM/SRAM . . . . .	998
Table 221.	16-Bit multiplexed I/O PSRAM . . . . .	998
Table 222.	NOR flash/PSRAM: example of supported memories and transactions . . . . .	999
Table 223.	FMC_BCRx bitfields (mode 1) . . . . .	1002
Table 224.	FMC_BTRx bitfields (mode 1) . . . . .	1003
Table 225.	FMC_BCRx bitfields (mode A) . . . . .	1005
Table 226.	FMC_BTRx bitfields (mode A) . . . . .	1005
Table 227.	FMC_BWTRx bitfields (mode A) . . . . .	1006
Table 228.	FMC_BCRx bitfields (mode 2/B) . . . . .	1008
Table 229.	FMC_BTRx bitfields (mode 2/B) . . . . .	1008
Table 230.	FMC_BWTRx bitfields (mode 2/B) . . . . .	1009
Table 231.	FMC_BCRx bitfields (mode C) . . . . .	1010
Table 232.	FMC_BTRx bitfields (mode C) . . . . .	1011
Table 233.	FMC_BWTRx bitfields (mode C) . . . . .	1011
Table 234.	FMC_BCRx bitfields (mode D) . . . . .	1013
Table 235.	FMC_BTRx bitfields (mode D) . . . . .	1014
Table 236.	FMC_BWTRx bitfields (mode D) . . . . .	1014
Table 237.	FMC_BCRx bitfields (Muxed mode) . . . . .	1016
Table 238.	FMC_BTRx bitfields (Muxed mode) . . . . .	1017
Table 239.	FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .	1022
Table 240.	FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .	1023
Table 241.	FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .	1024
Table 242.	FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .	1025
Table 243.	Programmable NAND flash access parameters . . . . .	1034
Table 244.	8-bit NAND flash . . . . .	1034
Table 245.	16-bit NAND flash . . . . .	1035
Table 246.	Supported memories and transactions . . . . .	1035
Table 247.	ECC result relevant bits . . . . .	1044
Table 248.	FMC register map and reset values . . . . .	1045
Table 249.	Instances on STM32U5 Series devices . . . . .	1048
Table 250.	OCTOSPI/HSPI implementation. . . . .	1048
Table 251.	OCTOSPI input/output pins (for STM32U5 Series except STM32U535/545 devices) . . . . .	1051
Table 252.	OCTOSPI input/output pins (for STM32U535/545 devices) . . . . .	1052
Table 253.	OCTOSPI internal signals. . . . .	1052

Table 254.	Command/address phase description . . . . .	1061
Table 255.	OctaRAM command address bit assignment (based on 64-Mbyte OctaRAM) . . . . .	1071
Table 256.	Address alignment cases . . . . .	1078
Table 257.	OCTOSPI interrupt requests . . . . .	1079
Table 258.	OCTOSPI register map and reset values . . . . .	1102
Table 259.	OCTOSPIM implementation . . . . .	1106
Table 260.	OCTOSPIM input/output pins . . . . .	1107
Table 261.	OCTOSPIM register map and reset values . . . . .	1112
Table 262.	Instances on STM32U5 series devices . . . . .	1114
Table 263.	HSPI implementation . . . . .	1114
Table 264.	HSPI input/output pins . . . . .	1118
Table 265.	HSPI internal signals . . . . .	1118
Table 266.	Command/address phase description . . . . .	1129
Table 267.	OctaRAM command address bit assignment (based on 64 Mb OctaRAM) . . . . .	1140
Table 268.	Address alignment cases . . . . .	1148
Table 269.	HSPI interrupt requests . . . . .	1149
Table 270.	HSPI register map and reset values . . . . .	1175
Table 271.	SDMMC features . . . . .	1179
Table 272.	SDMMC operation modes SD and SDIO . . . . .	1182
Table 273.	SDMMC operation modes e•MMC . . . . .	1182
Table 274.	SDMMC internal input/output signals . . . . .	1183
Table 275.	SDMMC pins . . . . .	1184
Table 276.	SDMMC Command and data phase selection . . . . .	1185
Table 277.	Command token format . . . . .	1191
Table 278.	Short response with CRC token format . . . . .	1192
Table 279.	Short response without CRC token format . . . . .	1192
Table 280.	Long response with CRC token format . . . . .	1192
Table 281.	Specific Commands overview . . . . .	1193
Table 282.	Command path status flags . . . . .	1194
Table 283.	Command path error handling . . . . .	1194
Table 284.	Data token format . . . . .	1202
Table 285.	Data path status flags and clear bits . . . . .	1202
Table 286.	Data path error handling . . . . .	1204
Table 287.	Data FIFO access . . . . .	1205
Table 288.	Transmit FIFO status flags . . . . .	1206
Table 289.	Receive FIFO status flags . . . . .	1207
Table 290.	AHB and SDMMC_CK clock frequency relation . . . . .	1212
Table 291.	SDIO special operation control . . . . .	1212
Table 292.	4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .	1216
Table 293.	CMD12 use cases . . . . .	1221
Table 294.	SDMMC interrupts . . . . .	1235
Table 295.	Response type and SDMMC_RESPxR registers . . . . .	1242
Table 296.	SDMMC register map . . . . .	1258
Table 297.	STM32U5 series features . . . . .	1261
Table 298.	DLYB internal input/output signals . . . . .	1262
Table 299.	Delay block control . . . . .	1263
Table 300.	DLYB register map and reset values . . . . .	1265
Table 301.	ADC features . . . . .	1268
Table 302.	Memory location of the temperature sensor calibration values . . . . .	1268
Table 303.	Memory location of the internal reference voltage sensor . . . . .	1268

calibration value . . . . .	1269
Table 304. ADC input/output pins . . . . .	1271
Table 305. ADC internal input/output signals . . . . .	1271
Table 306. ADC1/ADC12 interconnection . . . . .	1271
Table 307. ADC1/ADC12 external triggers for regular channels . . . . .	1272
Table 308. ADC1/ADC12 external triggers for injected channels . . . . .	1272
Table 309. Calibration factor index . . . . .	1281
Table 310. Configuring the trigger polarity for regular external triggers . . . . .	1291
Table 311. Configuring the trigger polarity for injected external triggers . . . . .	1291
Table 312. TSAR timings depending on resolution . . . . .	1295
Table 313. Offset computation versus data resolution . . . . .	1299
Table 314. 14-bit data formats . . . . .	1301
Table 315. Numerical examples for 16-bit format . . . . .	1302
Table 316. Analog watchdog channel selection . . . . .	1311
Table 317. Analog watchdog 1,2,3 comparison . . . . .	1312
Table 318. Summary of oversampler operating modes . . . . .	1320
Table 319. ADC interrupts . . . . .	1341
Table 320. DELAY bits versus ADC resolution . . . . .	1373
Table 321. ADC global register map . . . . .	1375
Table 322. ADC register map and reset values for each ADC (offset = 0x00 for master ADC, 0x100 for slave ADC) . . . . .	1375
Table 323. ADC register map and reset values (master and slave ADC common registers) offset = 0x300 . . . . .	1377
Table 324. ADC main features . . . . .	1380
Table 325. Memory location of the temperature sensor calibration values . . . . .	1381
Table 326. Memory location of the internal reference voltage sensor calibration value . . . . .	1381
Table 327. ADC input/output pins . . . . .	1383
Table 328. ADC internal input/output signals . . . . .	1383
Table 329. ADC interconnection . . . . .	1383
Table 330. Latency between trigger and start of conversion . . . . .	1388
Table 331. Configuring the trigger polarity . . . . .	1396
Table 332. t _SARtimings depending on resolution . . . . .	1398
Table 333. Analog watchdog comparison . . . . .	1410
Table 334. Analog watchdog 1 channel selection . . . . .	1410
Table 335. Maximum output results vs N and M. Grayed values indicates truncation . . . . .	1414
Table 336. Effect of low-power modes on the ADC . . . . .	1419
Table 337. ADC wake-up and interrupt requests . . . . .	1421
Table 338. ADC register map and reset values . . . . .	1442
Table 339. DAC features . . . . .	1446
Table 340. DAC input/output pins . . . . .	1448
Table 341. DAC internal input/output signals . . . . .	1448
Table 342. DAC interconnection . . . . .	1449
Table 343. Data format (case of 12-bit data) . . . . .	1451
Table 344. HFSEL description . . . . .	1452
Table 345. Sample and refresh timings . . . . .	1458
Table 346. Channel output modes summary . . . . .	1459
Table 347. Effect of low-power modes on DAC . . . . .	1467
Table 348. DAC interrupts . . . . .	1467
Table 349. DAC register map and reset values . . . . .	1484
Table 350. VREFBUF typical values . . . . .	1487
Table 351. VREF buffer modes . . . . .	1488

Table 352.	VREFBUF register map and reset values . . . . .	1490
Table 353.	COMP features . . . . .	1491
Table 354.	COMP1 non-inverting input assignment . . . . .	1492
Table 355.	COMP1 inverting input assignment . . . . .	1493
Table 356.	COMP2 non-inverting input assignment . . . . .	1493
Table 357.	COMP2 inverting input assignment . . . . .	1493
Table 358.	COMP1 output-blanking PWM assignment . . . . .	1493
Table 359.	COMP2 output-blanking PWM assignment . . . . .	1494
Table 360.	Comparator behavior in the low-power modes . . . . .	1497
Table 361.	Interrupt control bits . . . . .	1498
Table 362.	COMP register map and reset values . . . . .	1501
Table 363.	Operational amplifier possible connections . . . . .	1503
Table 364.	Operating modes and calibration . . . . .	1508
Table 365.	Effect of low-power modes on the OPAMP . . . . .	1509
Table 366.	OPAMP register map and reset values . . . . .	1514
Table 367.	ADF/MDF features . . . . .	1517
Table 368.	MDF external pins . . . . .	1520
Table 369.	MDF internal signals . . . . .	1520
Table 370.	MDF trigger connections . . . . .	1520
Table 371.	MDF break connections . . . . .	1521
Table 372.	MDF ADC data connections . . . . .	1521
Table 373.	Control of the common clock generation . . . . .	1529
Table 374.	Clock constraints with respect to the incoming stream . . . . .	1530
Table 375.	Data size according to CIC order and CIC decimation values . . . . .	1537
Table 376.	Maximum decimation ratio versus order and input data size . . . . .	1538
Table 377.	Possible gain values . . . . .	1539
Table 378.	Recommended maximum gain values versus CIC decimation ratios . . . . .	1541
Table 379.	Most common microphone settings . . . . .	1541
Table 380.	HPF 3 dB cut-off frequencies examples . . . . .	1543
Table 381.	Register protection summary . . . . .	1564
Table 382.	Effect of low-power modes on MDF . . . . .	1565
Table 383.	MDF interrupt requests . . . . .	1567
Table 384.	Examples of MDF settings for microphone capture . . . . .	1568
Table 385.	Programming sequence . . . . .	1568
Table 386.	Output signal levels . . . . .	1575
Table 387.	MDF register map and reset values . . . . .	1598
Table 388.	ADF/MDF features . . . . .	1601
Table 389.	ADF external pins . . . . .	1602
Table 390.	ADF internal signals . . . . .	1602
Table 391.	ADF trigger connections . . . . .	1603
Table 392.	Control of the common clock generation . . . . .	1609
Table 393.	Clock constraints with respect to the incoming stream . . . . .	1610
Table 394.	Data size according to CIC order and CIC decimation values . . . . .	1615
Table 395.	Possible gain values . . . . .	1616
Table 396.	Recommended maximum gain values versus CIC decimation ratios . . . . .	1618
Table 397.	Most common microphone settings . . . . .	1619
Table 398.	HPF 3 dB cut-off frequency examples . . . . .	1621
Table 399.	ANSLP values versus FRSIZE and sampling rates . . . . .	1634
Table 400.	Threshold values according SNTHR . . . . .	1635
Table 401.	Register protection summary . . . . .	1641
Table 402.	Effect of low-power modes on ADF . . . . .	1642

Table 403.	ADF interrupt requests . . . . .	1643
Table 404.	Examples of ADF settings for microphone capture . . . . .	1644
Table 405.	Programming sequence (CIC4) . . . . .	1645
Table 406.	Programming sequence (CIC5) . . . . .	1646
Table 407.	Output signal levels . . . . .	1651
Table 408.	ADF register map and reset values . . . . .	1671
Table 409.	DCMI input/output pins . . . . .	1675
Table 410.	DCMI internal input/output signals . . . . .	1675
Table 411.	Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .	1677
Table 412.	Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .	1677
Table 413.	Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .	1677
Table 414.	Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .	1678
Table 415.	Data storage in monochrome progressive video format . . . . .	1683
Table 416.	Data storage in RGB progressive video format . . . . .	1684
Table 417.	Data storage in YCbCr progressive video format . . . . .	1684
Table 418.	Data storage in YCbCr progressive video format - Y extraction mode . . . . .	1684
Table 419.	DCMI interrupts . . . . .	1685
Table 420.	DCMI register map and reset values . . . . .	1695
Table 421.	PSSI input/output pins . . . . .	1698
Table 422.	PSSI internal input/output signals . . . . .	1698
Table 423.	Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .	1699
Table 424.	Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .	1700
Table 425.	PSSI interrupt requests . . . . .	1703
Table 426.	PSSI register map and reset values . . . . .	1709
Table 427.	LTDC external pins . . . . .	1711
Table 428.	LTDC internal signals . . . . .	1712
Table 429.	LTDC trigger interconnection . . . . .	1712
Table 430.	Clock domain for each register . . . . .	1712
Table 431.	Pixel data mapping versus color format . . . . .	1717
Table 432.	LTDC interrupt requests . . . . .	1721
Table 433.	LTDC register map and reset values . . . . .	1738
Table 434.	DSI pins . . . . .	1743
Table 435.	DSI internal input/output signals . . . . .	1744
Table 436.	Location of color components in the LTDC interface . . . . .	1747
Table 437.	Multiplicity of the payload size in pixels for each data type . . . . .	1748
Table 438.	Contention detection timeout counters configuration . . . . .	1760
Table 439.	List of events of different categories of the RESP_TO counter . . . . .	1761
Table 440.	RESP_TO counter configuration . . . . .	1764
Table 441.	Frame requirement configuration registers . . . . .	1776
Table 442.	RGB components . . . . .	1778
Table 443.	Custom lane configuration . . . . .	1780
Table 444.	HS2LP and LP2HS values vs. band frequency (MHz) . . . . .	1781
Table 445.	DSI Wrapper interrupt requests . . . . .	1782
Table 446.	Error causes and recovery . . . . .	1784
Table 447.	DSI register map and reset values . . . . .	1855
Table 448.	GPU2D implementation . . . . .	1862
Table 449.	GPU2D internal input/output signals . . . . .	1863
Table 450.	GPU2D trigger connections . . . . .	1863
Table 451.	JPEG internal signals . . . . .	1865
Table 452.	JPEG trigger connections . . . . .	1866
Table 453.	JPEG codec interrupt requests . . . . .	1871
Table 454.	JPEG codec register map and reset values . . . . .	1884

Table 455.	Acquisition sequence summary . . . . .	1889
Table 456.	Spread spectrum deviation versus AHB clock frequency . . . . .	1891
Table 457.	I/O state depending on its mode and IODEF bit value . . . . .	1892
Table 458.	Effect of low-power modes on TSC . . . . .	1894
Table 459.	Interrupt control bits . . . . .	1894
Table 460.	TSC register map and reset values . . . . .	1901
Table 461.	RNG internal input/output signals . . . . .	1904
Table 462.	RNG interrupt requests . . . . .	1912
Table 463.	RNG initialization times . . . . .	1913
Table 464.	RNG configurations . . . . .	1913
Table 465.	Configuration selection . . . . .	1914
Table 466.	RNG register map and reset map . . . . .	1919
Table 467.	AES/SAES features . . . . .	1921
Table 468.	AES internal input/output signals . . . . .	1922
Table 469.	CTR mode initialization vector definition . . . . .	1937
Table 470.	GCM last block definition . . . . .	1939
Table 471.	Initialization of AES_IVRx registers in GCM mode . . . . .	1940
Table 472.	Initialization of AES_IVRx registers in CCM mode . . . . .	1947
Table 473.	Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .	1953
Table 474.	AES interrupt requests . . . . .	1957
Table 475.	Processing latency for ECB, CBC and CTR . . . . .	1957
Table 476.	Processing latency for GCM and CCM (in clock cycles) . . . . .	1957
Table 477.	AES register map and reset values . . . . .	1970
Table 478.	AES/SAES features . . . . .	1973
Table 479.	SAES internal input/output signals . . . . .	1974
Table 480.	Key endianness in SAES_KEYRx registers (128- or 256-bit key length) . . . . .	1993
Table 481.	SAES interrupt requests . . . . .	1998
Table 482.	Processing latency for ECB, CBC . . . . .	1999
Table 483.	SAES register map and reset values . . . . .	2012
Table 484.	HASH internal input/output signals . . . . .	2016
Table 485.	Hash processor outputs . . . . .	2019
Table 486.	Processing time (in clock cycle) . . . . .	2025
Table 487.	HASH interrupt requests . . . . .	2026
Table 488.	HASH register map and reset values . . . . .	2034
Table 489.	OTFDEC internal input/output signals . . . . .	2037
Table 490.	OTFDEC interrupt requests . . . . .	2041
Table 491.	OTFDEC register map and reset values . . . . .	2055
Table 492.	Internal input/output signals . . . . .	2060
Table 493.	PKA integer arithmetic functions list . . . . .	2061
Table 494.	PKA prime field (Fp) elliptic curve functions list . . . . .	2062
Table 495.	Example of 'a' curve coefficient for ECC Fp scalar . . . . .	2068
Table 496.	Montgomery parameter computation . . . . .	2068
Table 497.	Modular addition . . . . .	2069
Table 498.	Modular subtraction . . . . .	2069
Table 499.	Montgomery multiplication . . . . .	2070
Table 500.	Modular exponentiation (normal mode) . . . . .	2071
Table 501.	Modular exponentiation (fast mode) . . . . .	2071
Table 502.	Modular exponentiation (protected mode) . . . . .	2072
Table 503.	Modular inversion . . . . .	2072
Table 504.	Modular reduction . . . . .	2073
Table 505.	Arithmetic addition . . . . .	2073
Table 506.	Arithmetic subtraction . . . . .	2073

Table 507.	Arithmetic multiplication . . . . .	2074
Table 508.	Arithmetic comparison . . . . .	2074
Table 509.	CRT exponentiation . . . . .	2075
Table 510.	Point on elliptic curve Fp check . . . . .	2076
Table 511.	ECC Fp scalar multiplication. . . . .	2076
Table 512.	ECDSA sign - Inputs . . . . .	2078
Table 513.	ECDSA sign - Outputs . . . . .	2078
Table 514.	Extended ECDSA sign - additional outputs . . . . .	2079
Table 515.	ECDSA verification - inputs . . . . .	2079
Table 516.	ECDSA verification - outputs . . . . .	2080
Table 517.	ECC complete addition . . . . .	2080
Table 518.	ECC double base ladder. . . . .	2081
Table 519.	ECC projective to affine . . . . .	2082
Table 520.	Family of supported curves for ECC operations . . . . .	2083
Table 521.	Modular exponentiation . . . . .	2084
Table 522.	ECC scalar multiplication . . . . .	2084
Table 523.	ECDSA signature average computation time . . . . .	2085
Table 524.	ECDSA verification average computation times . . . . .	2085
Table 525.	ECC double base ladder average computation times . . . . .	2085
Table 526.	ECC projective to affine average computation times . . . . .	2085
Table 527.	ECC complete addition average computation times . . . . .	2085
Table 528.	Point on elliptic curve Fp check average computation times . . . . .	2085
Table 529.	Montgomery parameters average computation times. . . . .	2086
Table 530.	PKA interrupt requests . . . . .	2086
Table 531.	PKA register map and reset values . . . . .	2091
Table 532.	TIM input/output pins . . . . .	2094
Table 533.	TIM internal input/output signals . . . . .	2094
Table 534.	Interconnect to the tim_ti1 input multiplexer . . . . .	2095
Table 535.	Interconnect to the tim_ti2 input multiplexer . . . . .	2096
Table 536.	Interconnect to the tim_ti3 input multiplexer . . . . .	2096
Table 537.	Interconnect to the tim_ti4 input multiplexer . . . . .	2096
Table 538.	Internal trigger connection . . . . .	2096
Table 539.	Interconnect to the tim_etr input multiplexer for STM32U535/545/575/585 . . . . .	2097
Table 540.	Interconnect to the tim_etr input multiplexer for STM2U59x/5Ax/5Fx/5Gx . . . . .	2097
Table 541.	Timer break interconnect . . . . .	2098
Table 542.	Timer break2 interconnect . . . . .	2098
Table 543.	System break interconnect . . . . .	2099
Table 544.	Interconnect to the ocref_clr input multiplexer . . . . .	2099
Table 545.	CCR and ARR register change dithering pattern . . . . .	2132
Table 546.	CCR register change dithering pattern in center-aligned PWM mode . . . . .	2133
Table 547.	Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .	2145
Table 548.	Break protection disarming conditions . . . . .	2147
Table 549.	Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .	2156
Table 550.	Counting direction versus encoder signals and polarity settings . . . . .	2160
Table 551.	DMA request. . . . .	2181
Table 552.	Effect of low-power modes on TIM1/TIM8 . . . . .	2182
Table 553.	Interrupt requests . . . . .	2182
Table 554.	Output control bits for complementary tim_ocx and tim_ocxn channels with break feature . . . . .	2209
Table 555.	TIMx register map and reset values . . . . .	2232
Table 556.	STM32U5 series general purpose timers . . . . .	2236
Table 557.	TIM input/output pins . . . . .	2238

Table 558.	TIM internal input/output signals . . . . .	2238
Table 559.	Interconnect to the tim_ti1 input multiplexer . . . . .	2239
Table 560.	Interconnect to the tim_ti2 input multiplexer . . . . .	2239
Table 561.	Interconnect to the tim_ti3 input multiplexer . . . . .	2240
Table 562.	Interconnect to the tim_ti4 input multiplexer . . . . .	2240
Table 563.	TIMx internal trigger connection . . . . .	2240
Table 564.	Interconnect to the tim_etr input multiplexer for STM32U535/545/575/585 . . . . .	2241
Table 565.	Interconnect to the tim_etr input multiplexer for the STM32U59x/5Ax/5Fx/5Gx . . . . .	2241
Table 566.	Interconnect to the tim_ocref_clr input multiplexer . . . . .	2242
Table 567.	CCR and ARR register change dithering pattern . . . . .	2273
Table 568.	CCR register change dithering pattern in center-aligned PWM mode . . . . .	2274
Table 569.	Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .	2283
Table 570.	Counting direction versus encoder signals and polarity settings . . . . .	2288
Table 571.	DMA request . . . . .	2312
Table 572.	Effect of low-power modes on TIM2/TIM3/TIM4/TIM5 . . . . .	2312
Table 573.	Interrupt requests . . . . .	2313
Table 574.	Output control bit for standard tim_ocx channels . . . . .	2334
Table 575.	TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .	2346
Table 576.	TIM input/output pins . . . . .	2352
Table 577.	TIM internal input/output signals . . . . .	2353
Table 578.	Interconnect to the tim_ti1 input multiplexer . . . . .	2353
Table 579.	Interconnect to the tim_ti2 input multiplexer . . . . .	2354
Table 580.	TIMx internal trigger connection . . . . .	2354
Table 581.	Timer break interconnect . . . . .	2354
Table 582.	System break interconnect . . . . .	2355
Table 583.	Interconnect to the ocref_clr input multiplexer . . . . .	2355
Table 584.	CCR and ARR register change dithering pattern . . . . .	2375
Table 585.	Break protection disarming conditions . . . . .	2384
Table 586.	DMA request . . . . .	2395
Table 587.	Effect of low-power modes on TIM15/TIM16/TIM17 . . . . .	2396
Table 588.	Interrupt requests . . . . .	2396
Table 589.	Output control bits for complementary tim_ocx and tim_ocxn channels with break feature (TIM15) . . . . .	2412
Table 590.	TIM15 register map and reset values . . . . .	2425
Table 591.	Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .	2438
Table 592.	TIM16/TIM17 register map and reset values . . . . .	2452
Table 593.	TIM internal input/output signals . . . . .	2455
Table 594.	TIMx_ARR register change dithering pattern . . . . .	2465
Table 595.	DMA request . . . . .	2466
Table 596.	Effect of low-power modes on TIM6/TIM7 . . . . .	2466
Table 597.	Interrupt request . . . . .	2466
Table 598.	TIMx register map and reset values . . . . .	2472
Table 599.	STM32U5 series LPTIM features . . . . .	2474
Table 600.	LPTIM1/2/3 input/output pins . . . . .	2476
Table 601.	LPTIM4 input/output pins . . . . .	2476
Table 602.	LPTIM1/2/3 internal signals . . . . .	2477
Table 603.	LPTIM4 internal signals . . . . .	2477
Table 604.	LPTIM1/2/3/4 external trigger connections . . . . .	2478
Table 605.	LPTIM1/2/3/4 input 1 connections . . . . .	2478

Table 606.	LPTIM1/2 input 2 connections . . . . .	2478
Table 607.	LPTIM1/2/3 input capture 1 connections . . . . .	2478
Table 608.	LPTIM1 input capture 2 connections . . . . .	2479
Table 609.	LPTIM2 input capture 2 connections . . . . .	2479
Table 610.	LPTIM3 input capture 2 connections . . . . .	2479
Table 611.	Prescaler division ratios . . . . .	2481
Table 612.	Encoder counting scenarios . . . . .	2488
Table 613.	Input capture Glitch filter latency (in counter step unit). . . . .	2492
Table 614.	Effect of low-power modes on the LPTIM. . . . .	2497
Table 615.	Interrupt events. . . . .	2498
Table 616.	LPTIM register map and reset values. . . . .	2522
Table 617.	GFXTIM input/output pins. . . . .	2526
Table 618.	GFXTIM internal signals . . . . .	2526
Table 619.	GFXTIM trigger interconnections . . . . .	2527
Table 620.	Graphic timer interrupt requests . . . . .	2537
Table 621.	GFXTIM register map and reset values . . . . .	2558
Table 622.	STM32U5 series IWDG features . . . . .	2562
Table 623.	IWDG delays versus actions . . . . .	2564
Table 624.	IWDG internal input/output signals . . . . .	2564
Table 625.	Effect of low power modes on IWDG . . . . .	2568
Table 626.	IWDG interrupt request. . . . .	2570
Table 627.	IWDG register map and reset values . . . . .	2575
Table 628.	WWDG features . . . . .	2576
Table 629.	WWDG internal input/output signals. . . . .	2577
Table 630.	WWDG interrupt requests. . . . .	2580
Table 631.	WWDG register map and reset values . . . . .	2582
Table 632.	RTC input/output pins . . . . .	2586
Table 633.	RTC internal input/output signals . . . . .	2586
Table 634.	RTC interconnection . . . . .	2587
Table 635.	RTC pin PC13 configuration. . . . .	2588
Table 636.	RTC_OUT mapping . . . . .	2590
Table 637.	Effect of low-power modes on RTC . . . . .	2605
Table 638.	RTC pins functionality over modes. . . . .	2605
Table 639.	Nonsecure interrupt requests . . . . .	2606
Table 640.	Secure interrupt requests . . . . .	2606
Table 641.	RTC register map and reset values . . . . .	2637
Table 642.	TAMP input/output pins . . . . .	2642
Table 643.	TAMP internal input/output signals. . . . .	2642
Table 644.	TAMP interconnection . . . . .	2643
Table 645.	Device resource x tamper protection . . . . .	2649
Table 646.	Active tamper output change period. . . . .	2652
Table 647.	Minimum ATPER value. . . . .	2653
Table 648.	Active tamper filtered pulse duration . . . . .	2654
Table 649.	Effect of low-power modes on TAMP . . . . .	2656
Table 650.	TAMP pins functionality over modes . . . . .	2656
Table 651.	Interrupt requests . . . . .	2656
Table 652.	TAMP register map and reset values . . . . .	2685
Table 653.	STM32U535/545/575/585 I2C implementation. . . . .	2688
Table 654.	STM32U59x/5Ax/5Fx/5Gx I2C implementation . . . . .	2688
Table 655.	I2C input/output pins. . . . .	2690
Table 656.	I2C internal input/output signals . . . . .	2691
Table 657.	I2C1, I2C2, I2C4, I2C5, I2C6 interconnection . . . . .	2691

Table 658.	I2C3 interconnection . . . . .	2691
Table 659.	Comparison of analog and digital filters . . . . .	2694
Table 660.	I ²C-bus and SMBus specification data setup and hold times . . . . .	2696
Table 661.	I2C configuration. . . . .	2700
Table 662.	I ²C-bus and SMBus specification clock timings . . . . .	2711
Table 663.	Timing settings for f _I2CCLKof 8 MHz. . . . .	2721
Table 664.	Timing settings for f _I2CCLKof 16 MHz. . . . .	2721
Table 665.	SMBus timeout specifications . . . . .	2723
Table 666.	SMBus with PEC configuration . . . . .	2725
Table 667.	TIMEOUTA[11:0] for maximum t _TIMEOUTof 25 ms. . . . .	2726
Table 668.	TIMEOUTB[11:0] for maximum t _LOW:SEXTand t _LOW:MEXTof 8 ms . . . . .	2726
Table 669.	TIMEOUTA[11:0] for maximum t _IDLEof 50 µs . . . . .	2726
Table 670.	Effect of low-power modes to I2C . . . . .	2736
Table 671.	I2C interrupt requests . . . . .	2737
Table 672.	I2C register map and reset values . . . . .	2754
Table 673.	Instance implementation on STM32U5 series . . . . .	2757
Table 674.	USART/LPUART features . . . . .	2758
Table 675.	USART/UART input/output pins . . . . .	2760
Table 676.	USART internal input/output signals . . . . .	2761
Table 677.	USART interconnection (USART1/2/3/6 and UART4/5). . . . .	2761
Table 678.	Noise detection from sampled data . . . . .	2773
Table 679.	Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .	2777
Table 680.	Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .	2777
Table 681.	USART frame formats . . . . .	2782
Table 682.	Effect of low-power modes on the USART . . . . .	2803
Table 683.	USART interrupt requests. . . . .	2804
Table 684.	USART register map and reset values . . . . .	2843
Table 685.	Instance implementation on STM32U5 series . . . . .	2846
Table 686.	USART/LPUART features . . . . .	2846
Table 687.	LPUART input/output pins . . . . .	2849
Table 688.	LPUART internal input/output signals. . . . .	2849
Table 689.	LPUART interconnections (LPUART1). . . . .	2850
Table 690.	Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .	2861
Table 691.	Tolerance of the LPUART receiver. . . . .	2862
Table 693.	Effect of low-power modes on the LPUART . . . . .	2873
Table 694.	LPUART interrupt requests. . . . .	2874
Table 695.	LPUART register map and reset values . . . . .	2899
Table 696.	SPI features . . . . .	2903
Table 697.	SPI input/output pins. . . . .	2905
Table 698.	SPI internal input/output signals . . . . .	2906
Table 699.	SPI interconnection (SPI1 and SPI2) . . . . .	2906
Table 700.	SPI interconnection (SPI3) . . . . .	2907
Table 701.	Effect of low-power modes on the SPI . . . . .	2933
Table 702.	SPI wake-up and interrupt requests . . . . .	2934
Table 703.	SPI register map and reset values . . . . .	2951
Table 704.	SAI features . . . . .	2953
Table 705.	SAI internal input/output signals . . . . .	2955
Table 706.	SAI input/output pins. . . . .	2955
Table 707.	External synchronization selection . . . . .	2958
Table 708.	MCLK_x activation conditions. . . . .	2963
Table 709.	Clock generator programming examples . . . . .	2966
Table 710.	SAI_A configuration for TDM mode . . . . .	2973

Table 711.	TDM frame configuration examples . . . . .	2975
Table 712.	SOPD pattern . . . . .	2979
Table 713.	Parity bit calculation . . . . .	2979
Table 714.	Audio sampling frequency versus symbol rates . . . . .	2980
Table 715.	SAI interrupt sources . . . . .	2989
Table 716.	SAI register map and reset values . . . . .	3018
Table 717.	CAN subsystem I/O signals . . . . .	3024
Table 718.	CAN subsystem I/O pins. . . . .	3024
Table 719.	DLC coding in FDCAN . . . . .	3028
Table 720.	Possible configurations for frame transmission . . . . .	3042
Table 721.	Rx FIFO element . . . . .	3045
Table 722.	Rx FIFO element description . . . . .	3045
Table 723.	Tx buffer and FIFO element . . . . .	3047
Table 724.	Tx buffer element description . . . . .	3047
Table 725.	Tx event FIFO element. . . . .	3049
Table 726.	Tx event FIFO element description. . . . .	3049
Table 727.	Standard message ID filter element . . . . .	3050
Table 728.	Standard message ID filter element field description . . . . .	3051
Table 729.	Extended message ID filter element. . . . .	3051
Table 730.	Extended message ID filter element field description. . . . .	3052
Table 731.	FDCAN register map and reset values . . . . .	3082
Table 732.	STM32U5 series USB implementation . . . . .	3086
Table 733.	USB input/output pins . . . . .	3088
Table 734.	Double-buffering buffer flag definition. . . . .	3100
Table 735.	Bulk double-buffering memory buffers usage (Device mode). . . . .	3100
Table 736.	Bulk double-buffering memory buffers usage (Host mode) . . . . .	3102
Table 737.	Isochronous memory buffers usage . . . . .	3103
Table 738.	Isochronous memory buffers usage . . . . .	3104
Table 739.	Resume event detection . . . . .	3106
Table 740.	Resume event detection for host . . . . .	3107
Table 741.	Reception status encoding . . . . .	3125
Table 742.	Endpoint/channel type encoding. . . . .	3125
Table 743.	Endpoint/channel kind meaning . . . . .	3125
Table 744.	Transmission status encoding . . . . .	3125
Table 745.	USB register map and reset values . . . . .	3126
Table 746.	Definition of allocated buffer memory . . . . .	3129
Table 747.	USBFSRAM register map and reset values . . . . .	3132
Table 748.	OTG_FS speeds supported . . . . .	3134
Table 749.	OTG_FS implementation . . . . .	3137
Table 750.	OTG_FS input/output pins . . . . .	3138
Table 751.	OTG_FS input/output signals . . . . .	3139
Table 752.	Compatibility of STM32 low power modes with the OTG . . . . .	3151
Table 753.	Core global control and status registers (CSRs). . . . .	3159
Table 754.	Host-mode control and status registers (CSRs) . . . . .	3160
Table 755.	Device-mode control and status registers . . . . .	3161
Table 756.	Data FIFO (DFIFO) access register map . . . . .	3163
Table 757.	Power and clock gating control and status registers . . . . .	3163
Table 758.	TRDT values. . . . .	3170
Table 759.	Minimum duration for soft disconnect. . . . .	3207
Table 760.	OTG_FS register map and reset values . . . . .	3230
Table 761.	OTG_HS speeds supported . . . . .	3291
Table 762.	OTG_HS implementation . . . . .	3292

Table 763.	OTG_HS input/output pins . . . . .	3294
Table 764.	OTG_HS input/output signals . . . . .	3294
Table 765.	Compatibility of STM32 low power modes with the OTG . . . . .	3306
Table 766.	Core global control and status registers (CSRs). . . . .	3314
Table 767.	Host-mode control and status registers (CSRs) . . . . .	3315
Table 768.	Device-mode control and status registers . . . . .	3316
Table 769.	Data FIFO (DFIFO) access register map . . . . .	3318
Table 770.	Power and clock gating control and status registers . . . . .	3319
Table 771.	TRDT values . . . . .	3325
Table 772.	Minimum duration for soft disconnect . . . . .	3368
Table 773.	OTG_HS register map and reset values . . . . .	3394
Table 774.	UCPD implementation . . . . .	3460
Table 775.	UCPD software trim data . . . . .	3460
Table 776.	UCPD signals on pins . . . . .	3461
Table 777.	UCPD internal signals . . . . .	3462
Table 778.	4b5b symbol encoding table . . . . .	3464
Table 779.	Ordered sets . . . . .	3465
Table 780.	Validation of ordered sets . . . . .	3465
Table 781.	Data size . . . . .	3466
Table 782.	Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . .	3474
Table 783.	Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . .	3476
Table 784.	Effect of low power modes on the UCPD . . . . .	3478
Table 785.	UCPD interrupt requests . . . . .	3479
Table 786.	UCPD register map and reset values . . . . .	3495
Table 787.	JTAG/Serial-wire debug port pins . . . . .	3499
Table 788.	Trace port pins . . . . .	3499
Table 789.	Single-wire trace port pins . . . . .	3500
Table 790.	Authentication signal states . . . . .	3501
Table 791.	JTAG-DP data registers . . . . .	3504
Table 792.	Packet request . . . . .	3505
Table 793.	ACK response . . . . .	3506
Table 794.	Data transfer . . . . .	3506
Table 795.	Debug port register map and reset values . . . . .	3513
Table 796.	Access port register map and reset values . . . . .	3519
Table 797.	MCU ROM table . . . . .	3520
Table 798.	Processor ROM table . . . . .	3520
Table 799.	MCU ROM table register map and reset values . . . . .	3525
Table 800.	CPU ROM table register map and reset values . . . . .	3530
Table 801.	DWT register map and reset values . . . . .	3545
Table 802.	ITM register map and reset values . . . . .	3555
Table 803.	BPU register map and reset values . . . . .	3562
Table 804.	ETM register map and reset values . . . . .	3586
Table 805.	TPIU register map and reset values . . . . .	3599
Table 806.	CTI inputs . . . . .	3601
Table 807.	CTI outputs . . . . .	3601
Table 808.	CTI register map and reset values . . . . .	3612
Table 809.	Peripheral clock freeze control bits . . . . .	3614
Table 810.	Peripheral behavior in debug mode . . . . .	3615
Table 811.	Debugger access to freeze register bits . . . . .	3616
Table 812.	DBGMCU register map and reset values . . . . .	3626
Table 813.	Document revision history . . . . .	3634

List of figures

Figure 1.	System architecture . . . . .	131
Figure 2.	SmartRun domain architecture . . . . .	134
Figure 3.	Memory map based on IDAU mapping for STM32U535/545 . . . . .	141
Figure 4.	Memory map based on IDAU mapping for STM32U575/585 . . . . .	142
Figure 5.	Memory map based on IDAU mapping for STM32U59x/5Ax . . . . .	143
Figure 6.	Memory map based on IDAU mapping for STM32U5Fx/5Gx . . . . .	144
Figure 7.	Secure/nonsecure partitioning using TrustZone technology . . . . .	154
Figure 8.	Sharing memory map between CPU in secure and nonsecure state . . . . .	156
Figure 9.	Secure world transition and memory partitioning . . . . .	156
Figure 10.	Global TrustZone framework and TrustZone awareness . . . . .	158
Figure 11.	Flash memory TrustZone protections . . . . .	162
Figure 12.	Flash memory secure HDP area . . . . .	170
Figure 13.	Key management principle . . . . .	179
Figure 14.	Device life-cycle security . . . . .	182
Figure 15.	RDP level transition scheme . . . . .	185
Figure 16.	Collaborative development principle . . . . .	188
Figure 17.	External flash memory protection using SFI . . . . .	190
Figure 18.	GTZC in Armv8-M subsystem block diagram . . . . .	197
Figure 19.	GTZC block diagram . . . . .	200
Figure 20.	Watermark memory protection controller (region x/sub-regions A and B) . . . . .	202
Figure 21.	MPCBB block diagram . . . . .	203
Figure 22.	SRAM1, SRAM2 with ECC and SRAM3 with ECC memory map . . . . .	279
Figure 23.	Flash memory security attributes and protections in case of no bank swap (SWAP_BANK = 0) . . . . .	314
Figure 24.	Flash memory security attributes and protections in case of bank swap (SWAP_BANK = 1) . . . . .	314
Figure 25.	RDP level transition scheme when TrustZone is disabled (TZEN = 0) . . . . .	322
Figure 26.	RDP level transition scheme when TrustZone is enabled (TZEN = 1) . . . . .	323
Figure 27.	ICACHE block diagram . . . . .	366
Figure 28.	ICACHE TAG and data memories functional view . . . . .	368
Figure 29.	ICACHE remapping address mechanism . . . . .	372
Figure 30.	DCACHE block diagram . . . . .	384
Figure 31.	DCACHE TAG and data memories functional view . . . . .	387
Figure 32.	Power supply overview . . . . .	404
Figure 33.	Brownout reset waveform . . . . .	412
Figure 34.	PVD thresholds . . . . .	413
Figure 35.	I/O states in Stop 3 mode . . . . .	433
Figure 36.	I/O states in Standby mode . . . . .	436
Figure 37.	Simplified diagram of the reset circuit . . . . .	484
Figure 38.	Clock tree for STM32U5 series . . . . .	487
Figure 39.	HSE/ LSE clock sources . . . . .	488
Figure 40.	MSI block diagram . . . . .	490
Figure 41.	PLL block diagram . . . . .	493
Figure 42.	PLL initialization flow . . . . .	496
Figure 43.	CRS block diagram . . . . .	611
Figure 44.	CRS counter behavior . . . . .	613
Figure 45.	Structure of three-volt or five-volt tolerant GPIO (TT or FT) . . . . .	623
Figure 46.	Input floating/pull-up/pull-down configurations . . . . .	627

Figure 47.	Output configuration . . . . .	628
Figure 48.	Alternate function configuration . . . . .	628
Figure 49.	High-impedance analog configuration . . . . .	629
Figure 50.	I/O compensation cell block diagram . . . . .	649
Figure 51.	GPDMA block diagram . . . . .	694
Figure 52.	GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0) . . . . .	695
Figure 53.	GPDMA channel suspend and resume sequence . . . . .	696
Figure 54.	GPDMA channel abort and restart sequence . . . . .	697
Figure 55.	Static linked-list data structure (all Uxx = 1) of a linear addressing channel x . . . . .	698
Figure 56.	Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x . . . . .	699
Figure 57.	GPDMA dynamic linked-list data structure of a linear addressing channel x . . . . .	700
Figure 58.	GPDMA dynamic linked-list data structure of a 2D addressing channel x . . . . .	700
Figure 59.	GPDMA channel execution and linked-list programming in run-to-completion mode (GPDMA_CxCRL.SM = 0) . . . . .	702
Figure 60.	Inserting a LLIn with an auxiliary GPDMA channel y . . . . .	704
Figure 61.	GPDMA channel execution and linked-list programming in link step mode (GPDMA_CxCRL.SM = 1) . . . . .	706
Figure 62.	Building LLIn+1: GPDMA dynamic linked-lists in link step mode . . . . .	707
Figure 63.	Replace with a new LLIn' in register file in link step mode . . . . .	708
Figure 64.	Replace with a new LLIn' and LLIn+1' in memory in link step mode (option 1) . . . . .	709
Figure 65.	Replace with a new LLIn' and LLIn+1' in memory in link step mode (option 2) . . . . .	710
Figure 66.	GPDMA channel execution and linked-list programming . . . . .	712
Figure 67.	Programmed 2D addressing . . . . .	715
Figure 68.	GPDMA arbitration policy . . . . .	722
Figure 69.	Trigger hit, memorization, and overrun waveform . . . . .	725
Figure 70.	GPDMA circular buffer programming: update of the memory start address with a linear addressing channel . . . . .	726
Figure 71.	Shared GPDMA channel with circular buffering: update of the memory start address with a linear addressing channel . . . . .	727
Figure 72.	LPDMA block diagram . . . . .	770
Figure 73.	LPDMA channel direct programming without linked-list (LPDMA_CxLLR = 0) . . . . .	771
Figure 74.	LPDMA channel suspend and resume sequence . . . . .	772
Figure 75.	LPDMA channel abort and restart sequence . . . . .	773
Figure 76.	Static linked-list data structure (all Uxx = 1) of channel x . . . . .	774
Figure 77.	LPDMA dynamic linked-list data structure of an addressing channel x . . . . .	775
Figure 78.	LPDMA channel execution and linked-list programming in run-to-completion mode (LPDMA_CxCRL.SM = 0) . . . . .	777
Figure 79.	Inserting a LLIn with an auxiliary LPDMA channel y . . . . .	779
Figure 80.	LPDMA channel execution and linked-list programming in link step mode (LPDMA_CxCRL.SM = 1) . . . . .	781
Figure 81.	Building LLIn+1: LPDMA dynamic linked-lists in link step mode . . . . .	782
Figure 82.	Replace with a new LLIn' in register file in link step mode . . . . .	783
Figure 83.	Replace with a new LLIn' and LLIn+1' in memory in link step mode (option 1) . . . . .	784
Figure 84.	Replace with a new LLIn' and LLIn+1' in memory in link step mode (option 2) . . . . .	785
Figure 85.	LPDMA channel execution and linked-list programming . . . . .	787
Figure 86.	LPDMA arbitration policy . . . . .	791
Figure 87.	Trigger hit, memorization and overrun waveform . . . . .	795
Figure 88.	LPDMA circular buffer programming: update of the memory start address . . . . .	796

Figure 89.	Shared LPDMA channel with circular buffering: update of the memory start address . . . . .	797
Figure 90.	DMA2D block diagram . . . . .	825
Figure 91.	Intel 8080 16-bit mode (RGB565) . . . . .	832
Figure 92.	Intel 8080 18/24-bit mode (RGB888) . . . . .	832
Figure 93.	DMA2D block diagram . . . . .	860
Figure 94.	Intel 8080 16-bit mode (RGB565) . . . . .	867
Figure 95.	Intel 8080 18/24-bit mode (RGB888) . . . . .	867
Figure 96.	GFXMMU block diagram . . . . .	894
Figure 97.	Virtual buffer . . . . .	895
Figure 98.	Virtual buffer and physical buffer memory map . . . . .	896
Figure 99.	MMU block diagram . . . . .	897
Figure 100.	Block validation/comparator implementation . . . . .	898
Figure 101.	EXTI block diagram . . . . .	920
Figure 102.	Configurable event trigger logic CPU wake-up . . . . .	922
Figure 103.	EXTI mux GPIO selection . . . . .	923
Figure 104.	CRC calculation unit block diagram . . . . .	938
Figure 105.	CORDIC convergence for trigonometric functions . . . . .	952
Figure 106.	CORDIC convergence for hyperbolic functions . . . . .	953
Figure 107.	CORDIC convergence for square root . . . . .	954
Figure 108.	Block diagram . . . . .	963
Figure 109.	Input buffer areas . . . . .	965
Figure 110.	Circular input buffer . . . . .	966
Figure 111.	Circular input buffer operation . . . . .	967
Figure 112.	Circular output buffer . . . . .	968
Figure 113.	Circular output buffer operation . . . . .	969
Figure 114.	FIR filter structure . . . . .	971
Figure 115.	IIR filter structure (direct form 1) . . . . .	973
Figure 116.	X1 buffer initialization . . . . .	978
Figure 117.	Filtering example 1 . . . . .	979
Figure 118.	Filtering example 2 . . . . .	980
Figure 119.	FMC block diagram . . . . .	992
Figure 120.	FMC memory banks . . . . .	994
Figure 121.	Mode 1 read access waveforms . . . . .	1001
Figure 122.	Mode 1 write access waveforms . . . . .	1002
Figure 123.	Mode A read access waveforms . . . . .	1004
Figure 124.	Mode A write access waveforms . . . . .	1004
Figure 125.	Mode 2 and mode B read access waveforms . . . . .	1006
Figure 126.	Mode 2 write access waveforms . . . . .	1007
Figure 127.	Mode B write access waveforms . . . . .	1007
Figure 128.	Mode C read access waveforms . . . . .	1009
Figure 129.	Mode C write access waveforms . . . . .	1010
Figure 130.	Mode D read access waveforms . . . . .	1012
Figure 131.	Mode D write access waveforms . . . . .	1013
Figure 132.	Muxed read access waveforms . . . . .	1015
Figure 133.	Muxed write access waveforms . . . . .	1016
Figure 134.	Asynchronous wait during a read access waveforms . . . . .	1018
Figure 135.	Asynchronous wait during a write access waveforms . . . . .	1019
Figure 136.	Wait configuration waveforms . . . . .	1021
Figure 137.	Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .	1022
Figure 138.	Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .	1024
Figure 139.	NAND flash controller waveforms for common memory access . . . . .	1036

Figure 140. Access to non 'CE don't care' NAND-flash. . . . .	1038
Figure 141. OCTOSPI block diagram in octal configuration (for STM32U5 series except STM32U535/545 devices). . . . .	1049
Figure 142. OCTOSPI block diagram in quad configuration (for STM32U5 series except STM32U535/545 devices) . . . . .	1049
Figure 143. OCTOSPI block diagram in dual-quad configuration (for STM32U5 series except STM32U535/545 devices) . . . . .	1050
Figure 144. OCTOSPI block diagram in octal configuration (for STM32U535/545 devices) . . . . .	1050
Figure 145. OCTOSPI block diagram in quad configuration (for STM32U535/545 devices) . . . . .	1051
Figure 146. OCTOSPI block diagram in dual-quad configuration (for STM32U535/545 devices) . . . . .	1051
Figure 147. SDR read command in octal configuration . . . . .	1053
Figure 148. DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .	1056
Figure 149. SDR write command in octo-SPI mode example . . . . .	1058
Figure 150. DTR write in octal-SPI mode (Macronix mode) example . . . . .	1059
Figure 151. Example of HyperBus read operation. . . . .	1060
Figure 152. HyperBus write operation with initial latency . . . . .	1061
Figure 153. HyperBus read operation with additional latency . . . . .	1062
Figure 154. HyperBus write operation with additional latency . . . . .	1062
Figure 155. HyperBus write operation with no latency (register write). . . . .	1063
Figure 156. HyperBus read operation page crossing with latency. . . . .	1063
Figure 157. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .	1070
Figure 158. OctaRAM read operation with reverse data ordering D1/D0 . . . . .	1071
Figure 159. NCS when CKMODE = 0 (T = CLK period) . . . . .	1076
Figure 160. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .	1077
Figure 161. NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .	1077
Figure 162. NCS when CKMODE = 1 with an abort (T = CLK period). . . . .	1077
Figure 163. OCTOSPIM block diagram . . . . .	1107
Figure 164. HSPI block diagram for 16-bit configuration . . . . .	1115
Figure 165. HSPI block diagram for dual-octal configuration . . . . .	1116
Figure 166. HSPI block diagram for octal configuration . . . . .	1116
Figure 167. HSPI block diagram in quad configuration . . . . .	1117
Figure 168. HSPI block diagram for dual-quad configuration . . . . .	1118
Figure 169. SDR read command in 16-bit configuration . . . . .	1120
Figure 170. DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .	1123
Figure 171. SDR write command in octal-SPI mode example. . . . .	1125
Figure 172. DTR write in octal-SPI mode (Macronix mode) example . . . . .	1126
Figure 173. Example of HyperBus read operation (8-bit data mode) . . . . .	1128
Figure 174. HyperBus write operation with initial latency (8-bit data mode) . . . . .	1130
Figure 175. HyperBus read operation with additional latency (8-bit data mode). . . . .	1130
Figure 176. HyperBus write operation with additional latency (8-bit data mode). . . . .	1131
Figure 177. HyperBus write operation with no latency (register write). . . . .	1131
Figure 178. HyperBus read operation page crossing with latency (8-bit data mode) . . . . .	1132
Figure 179. HyperBus write operation with initial latency (16-bit mode) . . . . .	1133
Figure 180. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .	1139
Figure 181. OctaRAM read operation with reverse data ordering D1/D0 . . . . .	1140
Figure 182. NCS when CKMODE = 0 (T = CLK period) . . . . .	1146
Figure 183. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .	1147
Figure 184. NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .	1147
Figure 185. NCS when CKMODE =1 with an abort (T = CLK period). . . . .	1147

Figure 186. SDMMC “no response” and “no data” operations . . . . .	1180
Figure 187. SDMMC (multiple) block read operation . . . . .	1180
Figure 188. SDMMC (multiple) block write operation . . . . .	1181
Figure 189. SDMMC (sequential) stream read operation . . . . .	1181
Figure 190. SDMMC (sequential) stream write operation . . . . .	1181
Figure 191. SDMMC block diagram . . . . .	1183
Figure 192. SDMMC Command and data phase relation . . . . .	1185
Figure 193. Control unit . . . . .	1187
Figure 194. Command/response path . . . . .	1188
Figure 195. Command path state machine (CPSM) . . . . .	1189
Figure 196. Data path . . . . .	1195
Figure 197. DDR mode data packet clocking . . . . .	1196
Figure 198. DDR mode CRC status / boot acknowledgment clocking . . . . .	1196
Figure 199. Data path state machine (DPSM) . . . . .	1197
Figure 200. CLKMUX unit . . . . .	1208
Figure 201. Linked list structures . . . . .	1210
Figure 202. Asynchronous interrupt generation . . . . .	1213
Figure 203. Synchronous interrupt period data read . . . . .	1214
Figure 204. Synchronous interrupt period data write . . . . .	1214
Figure 205. Asynchronous interrupt period data read . . . . .	1215
Figure 206. Asynchronous interrupt period data write . . . . .	1216
Figure 207. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25 . . . . .	1219
Figure 208. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 . . . . .	1219
Figure 209. Read Wait with SDMMC_CK < 50 MHz . . . . .	1220
Figure 210. Read Wait with SDMMC_CK > 50 MHz . . . . .	1220
Figure 211. CMD12 stream timing . . . . .	1223
Figure 212. CMD5 Sleep Awake procedure . . . . .	1225
Figure 213. Normal boot mode operation . . . . .	1227
Figure 214. Alternative boot mode operation . . . . .	1228
Figure 215. Command response R1b busy signaling . . . . .	1229
Figure 216. SDMMC state control . . . . .	1230
Figure 217. Card cycle power / power up diagram . . . . .	1231
Figure 218. CMD11 signal voltage switch sequence . . . . .	1232
Figure 219. Voltage switch transceiver typical application . . . . .	1234
Figure 220. DLYB block diagram . . . . .	1262
Figure 221. ADC block diagram . . . . .	1270
Figure 222. ADC clock scheme . . . . .	1274
Figure 223. ADC1 connectivity . . . . .	1275
Figure 224. ADC2 connectivity (STM32U59x/5Ax/5Fx/5Gx) . . . . .	1276
Figure 225. ADC calibration . . . . .	1279
Figure 226. Enabling/disabling the ADC . . . . .	1283
Figure 227. Bulb mode timing diagram . . . . .	1286
Figure 228. Analog-to-digital conversion time in single conversion . . . . .	1289
Figure 229. Stopping ongoing regular conversions . . . . .	1290
Figure 230. Stopping ongoing regular and injected conversions . . . . .	1290
Figure 231. Triggers are shared between ADC master and ADC slave . . . . .	1292
Figure 232. Injected conversion latency . . . . .	1293
Figure 233. Single conversions of a sequence, software trigger . . . . .	1296
Figure 234. Continuous conversion of a sequence, software trigger . . . . .	1297
Figure 235. Single conversions of a sequence, hardware trigger . . . . .	1297
Figure 236. Continuous conversions of a sequence, hardware trigger . . . . .	1298
Figure 237. Right alignment (offset disabled, unsigned value) . . . . .	1299

Figure 238. Right alignment (offset enabled, signed value) . . . . .	1300
Figure 239. Left alignment (offset disabled, unsigned value) . . . . .	1300
Figure 240. Left alignment (offset enabled, signed value) . . . . .	1301
Figure 241. Example of overrun (OVRMOD = 0). . . . .	1304
Figure 242. Example of overrun (OVRMOD = 1). . . . .	1304
Figure 243. AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .	1308
Figure 244. AUTODLY = 1, regular hardware conversions interrupted by injected conversions (DISCEN = 0; JDISCEN = 0) . . . . .	1308
Figure 245. AUTODLY = 1, regular hardware conversions interrupted by injected conversions. (DISCEN = 1, JDISCEN = 1) . . . . .	1309
Figure 246. AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .	1310
Figure 247. AUTODLY = 1 in auto- injected mode (JAUTO = 1). . . . .	1310
Figure 248. Analog watchdog guarded area . . . . .	1311
Figure 249. ADC _y_AWD _x_OUT signal generation (on all regular channels). . . . .	1313
Figure 250. ADC_AWD _x_OUT signal generation (AWD _xflag not cleared by software) . . . . .	1313
Figure 251. ADC_AWD _x_OUT signal generation (on a single regular channel) . . . . .	1314
Figure 252. ADC_AWD _x_OUT signal generation (on all injected channels) . . . . .	1314
Figure 253. 14-bit result oversampling with 10-bits right shift and rounding . . . . .	1315
Figure 254. Triggered regular oversampling mode (TROVS bit = 1). . . . .	1317
Figure 255. Regular oversampling modes (4x ratio) . . . . .	1318
Figure 256. Regular and injected oversampling modes used simultaneously . . . . .	1318
Figure 257. Triggered regular oversampling with injection . . . . .	1319
Figure 258. Oversampling in auto-injected mode . . . . .	1319
Figure 259. Dual ADC block diagram ⁽¹⁾. . . . .	1322
Figure 260. Injected simultaneous mode on four channels: dual ADC mode . . . . .	1323
Figure 261. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .	1325
Figure 262. Interleaved mode on one channel in continuous conversion mode: dual ADC mode . . . . .	1327
Figure 263. Interleaved mode on one channel in single conversion mode: dual ADC mode . . . . .	1327
Figure 264. Interleaved conversion with injection . . . . .	1328
Figure 265. Alternate trigger: injected group of each ADC . . . . .	1329
Figure 266. Alternate trigger: Four injected channels (each ADC) in discontinuous mode . . . . .	1330
Figure 267. Alternate + regular simultaneous . . . . .	1331
Figure 268. Case of trigger occurring during injected conversion . . . . .	1331
Figure 269. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .	1332
Figure 270. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first . . . . .	1332
Figure 271. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first . . . . .	1332
Figure 272. DMA Requests in regular simultaneous mode when DAMDF[1:0] = 00 . . . . .	1333
Figure 273. DMA requests in regular simultaneous mode when DAMDF[1:0] = 10 . . . . .	1334
Figure 274. DMA requests in interleaved mode when DAMDF[1:0] = 10 . . . . .	1335
Figure 275. Temperature sensor channel block diagram . . . . .	1337
Figure 276. VBAT channel block diagram . . . . .	1338
Figure 277. VREFINT channel block diagram . . . . .	1339
Figure 278. ADC block diagram . . . . .	1382
Figure 279. ADC calibration . . . . .	1385
Figure 280. Calibration factor forcing . . . . .	1386
Figure 281. Enabling/disabling the ADC . . . . .	1387
Figure 282. ADC clock scheme . . . . .	1388
Figure 283. ADC4 connectivity . . . . .	1390
Figure 284. Analog-to-digital conversion time . . . . .	1395
Figure 285. ADC conversion timings . . . . .	1395

Figure 286. Stopping an ongoing conversion . . . . .	1396
Figure 287. Single conversions of a sequence, software trigger . . . . .	1399
Figure 288. Continuous conversion of a sequence, software trigger . . . . .	1400
Figure 289. Single conversions of a sequence, hardware trigger . . . . .	1400
Figure 290. Continuous conversions of a sequence, hardware trigger . . . . .	1401
Figure 291. Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .	1402
Figure 292. Example of overrun (OVR) . . . . .	1403
Figure 293. Wait conversion mode (continuous mode, software trigger) . . . . .	1405
Figure 294. Auto-off mode state diagram . . . . .	1407
Figure 295. ADC behavior with WAIT = 0 and AUTOFF = 1 . . . . .	1407
Figure 296. ADC behavior with WAIT = 1 and AUTOFF = 1 . . . . .	1408
Figure 297. Autonomous mode state diagram . . . . .	1409
Figure 298. Analog watchdog guarded area . . . . .	1410
Figure 299. ADC_AWDx_OUT signal generation . . . . .	1411
Figure 300. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .	1412
Figure 301. ADC_AWDx_OUT signal generation (on a single channel) . . . . .	1412
Figure 302. Analog watchdog threshold update . . . . .	1413
Figure 303. 20-bit to 16-bit result truncation . . . . .	1413
Figure 304. Numerical example with 5-bits shift and rounding . . . . .	1414
Figure 305. Triggered oversampling mode (TOVS bit = 1) . . . . .	1416
Figure 306. Temperature sensor and VREFINT channel block diagram . . . . .	1417
Figure 307. VBAT channel block diagram . . . . .	1419
Figure 308. Dual-channel DAC block diagram . . . . .	1447
Figure 309. Data registers in single DAC channel mode . . . . .	1450
Figure 310. Data registers in dual DAC channel mode . . . . .	1451
Figure 311. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	1452
Figure 312. DAC LFSR register calculation algorithm . . . . .	1455
Figure 313. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .	1455
Figure 314. DAC triangle wave generation . . . . .	1456
Figure 315. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	1456
Figure 316. DAC sample and hold mode phase diagram . . . . .	1459
Figure 317. VREFBUF block diagram . . . . .	1487
Figure 318. Comparator block diagrams . . . . .	1492
Figure 319. Window mode . . . . .	1495
Figure 320. Comparator hysteresis . . . . .	1495
Figure 321. Comparator output blanking . . . . .	1496
Figure 322. Scaler . . . . .	1497
Figure 323. Standalone mode: external gain setting mode . . . . .	1504
Figure 324. Follower configuration . . . . .	1505
Figure 325. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .	1506
Figure 326. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . .	1507
Figure 327. MDF block diagram . . . . .	1519
Figure 328. SITFx overview . . . . .	1523
Figure 329. SPI timing example . . . . .	1524
Figure 330. Manchester timing example (SITFMOD = 11) . . . . .	1526
Figure 331. CKGEN overview . . . . .	1529
Figure 332. BSMX overview . . . . .	1531
Figure 333. SCD functional view . . . . .	1532
Figure 334. SCD timing example . . . . .	1532
Figure 335. DFLT overview . . . . .	1534
Figure 336. Programmable delay . . . . .	1535

Figure 337. CIC3 and CIC5 frequency response with decimation ratio = 32 . . . . .	1537
Figure 338. Reshape filter frequency response normalized (FRS / 2 = 1). . . . .	1542
Figure 339. Out-of-limit detector thresholds. . . . .	1545
Figure 340. Trigger logic for DFLT and CKGEN . . . . .	1547
Figure 341. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . .	1548
Figure 342. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . .	1549
Figure 343. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . .	1550
Figure 344. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . .	1551
Figure 345. Window continuous mode (ACQMOD[2:0] = 100) . . . . .	1552
Figure 346. Snapshot mode example . . . . .	1554
Figure 347. Discard function example . . . . .	1555
Figure 348. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . .	1556
Figure 349. Start sequence with trigger input, in continuous mode, motor configuration . . . . .	1557
Figure 350. Break interface simplified view . . . . .	1558
Figure 351. MDF_DFLTxDATA data format. . . . .	1558
Figure 352. Data resynchronization . . . . .	1559
Figure 353. Data transfer in interleaved-transfer mode . . . . .	1560
Figure 354. Data path for interleaved- and independent-transfer modes . . . . .	1562
Figure 355. Example of overflow and transfer to memory . . . . .	1563
Figure 356. MDF interrupt interface . . . . .	1566
Figure 357. Sensor connection examples . . . . .	1571
Figure 358. Global frequency response . . . . .	1572
Figure 359. Detailed frequency response . . . . .	1572
Figure 360. Simplified DFLT view with gain information . . . . .	1574
Figure 361. ADF block diagram . . . . .	1602
Figure 362. SITF overview. . . . .	1604
Figure 363. SPI timing example . . . . .	1605
Figure 364. Manchester timing example (SITFMOD = 11) . . . . .	1606
Figure 365. CKGEN overview . . . . .	1609
Figure 366. BSMX overview . . . . .	1611
Figure 367. DFLT overview . . . . .	1612
Figure 368. Programmable delay. . . . .	1613
Figure 369. CIC4 and CIC5 frequency response with decimation ratio = 32 or 16 . . . . .	1614
Figure 370. Reshape filter frequency response normalized (FRS / 2 = 1). . . . .	1620
Figure 371. Trigger logic for DFLT and CKGEN . . . . .	1622
Figure 372. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . .	1623
Figure 373. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . .	1624
Figure 374. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . .	1625
Figure 375. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . .	1626
Figure 376. Window continuous mode (ACQMOD[2:0] = 100) . . . . .	1627
Figure 377. Discard function example . . . . .	1629
Figure 378. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . .	1629
Figure 379. SAD block diagram . . . . .	1630
Figure 380. SAD flow diagram. . . . .	1632
Figure 381. SAD timing diagram example . . . . .	1638
Figure 382. ADF_DFLTxDATA data format . . . . .	1638
Figure 383. Data resynchronization . . . . .	1639
Figure 384. Example of overflow and transfer to memory . . . . .	1640
Figure 385. ADF interrupt interface . . . . .	1643
Figure 386. Sensor connection examples . . . . .	1648
Figure 387. Global frequency response. . . . .	1648
Figure 388. Detailed frequency response . . . . .	1649

Figure 389. Simplified DFLT view with gain information . . . . .	1651
Figure 390. SAD example working with SADMOD = 01 . . . . .	1654
Figure 391. SAD example working with SADMOD = 1x . . . . .	1655
Figure 392. DCMI block diagram . . . . .	1675
Figure 393. DCMI signal waveforms . . . . .	1676
Figure 394. Timing diagram . . . . .	1678
Figure 395. Frame capture waveforms in snapshot mode. . . . .	1680
Figure 396. Frame capture waveforms in continuous grab mode . . . . .	1681
Figure 397. Coordinates and size of the window after cropping . . . . .	1681
Figure 398. Data capture waveforms. . . . .	1682
Figure 399. Pixel raster scan order . . . . .	1683
Figure 400. PSSI block diagram . . . . .	1697
Figure 401. Top-level block diagram . . . . .	1697
Figure 402. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .	1701
Figure 403. Data enable waveform diagram in transmit mode (CKPOL=1). . . . .	1701
Figure 404. Ready in receive mode waveform diagram (CKPOL=0). . . . .	1702
Figure 405. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . .	1703
Figure 406. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . .	1703
Figure 407. LTDC block diagram . . . . .	1711
Figure 408. LTDC synchronous timings. . . . .	1714
Figure 409. Layer window programmable parameters . . . . .	1717
Figure 410. Blending two layers with background . . . . .	1719
Figure 411. Interrupt events. . . . .	1721
Figure 412. DSI block diagram . . . . .	1743
Figure 413. DSI Host architecture . . . . .	1745
Figure 414. Flow to update the LTDC interface configuration using shadow registers . . . . .	1750
Figure 415. Immediate update procedure . . . . .	1751
Figure 416. Configuration update during the transmission of a frame. . . . .	1751
Figure 417. Adapted command mode usage flow . . . . .	1753
Figure 418. 24 bpp APB pixel to byte organization . . . . .	1757
Figure 419. 18 bpp APB pixel to byte organization . . . . .	1758
Figure 420. 16 bpp APB pixel to byte organization . . . . .	1758
Figure 421. 12 bpp APB pixel to byte organization . . . . .	1759
Figure 422. 8 bpp APB pixel to byte organization . . . . .	1759
Figure 423. Timing of PRESP_TO after a bus-turn-around. . . . .	1762
Figure 424. Timing of PRESP_TO after a read request (HS or LP). . . . .	1763
Figure 425. Timing of PRESP_TO after a write request (HS or LP) . . . . .	1764
Figure 426. Effect of prep mode at 1 . . . . .	1765
Figure 427. Command transmission periods within the image area . . . . .	1766
Figure 428. Transmission of commands on the last line of a frame. . . . .	1767
Figure 429. LPSIZE for non-burst with sync pulses. . . . .	1768
Figure 430. LPSIZE for burst or non-burst with sync events . . . . .	1768
Figure 431. VLPSIZE for non-burst with sync pulses . . . . .	1770
Figure 432. VLPSIZE for non-burst with sync events . . . . .	1770
Figure 433. VLPSIZE for burst mode. . . . .	1770
Figure 434. Location of LPSIZE and VLPSIZE in the image area . . . . .	1772
Figure 435. Clock lane and data lane in HS . . . . .	1773
Figure 436. Clock lane in HS and data lanes in LP . . . . .	1774
Figure 437. Clock lane and data lane in LP. . . . .	1774
Figure 438. Command transmission by the generic interface . . . . .	1775
Figure 439. Vertical color bar mode. . . . .	1777
Figure 440. Horizontal color bar mode. . . . .	1777

Figure 441. RGB888 BER testing pattern . . . . .	1778
Figure 442. Vertical pattern (103x15) . . . . .	1779
Figure 443. Horizontal pattern (103x15) . . . . .	1779
Figure 444. PLL block diagram . . . . .	1781
Figure 445. Error sources . . . . .	1784
Figure 446. Video packet transmission configuration flow diagram. . . . .	1796
Figure 447. Programming sequence to send a test pattern. . . . .	1798
Figure 448. Frame configuration registers. . . . .	1799
Figure 449. GPU2D block diagram . . . . .	1863
Figure 450. JPEG codec block diagram . . . . .	1865
Figure 451. TSC block diagram . . . . .	1887
Figure 452. Surface charge transfer analog I/O group structure . . . . .	1888
Figure 453. Sampling capacitor voltage variation . . . . .	1889
Figure 454. Charge transfer acquisition sequence . . . . .	1890
Figure 455. Spread spectrum variation principle . . . . .	1891
Figure 456. RNG block diagram . . . . .	1904
Figure 457. NIST SP800-90B entropy source model. . . . .	1905
Figure 458. RNG initialization overview. . . . .	1908
Figure 459. AES block diagram . . . . .	1921
Figure 460. ECB encryption and decryption principle . . . . .	1923
Figure 461. CBC encryption and decryption principle . . . . .	1924
Figure 462. CTR encryption and decryption principle . . . . .	1925
Figure 463. GCM encryption and authentication principle. . . . .	1926
Figure 464. GMAC authentication principle . . . . .	1926
Figure 465. CCM encryption and authentication principle. . . . .	1927
Figure 466. Example of suspend mode management. . . . .	1931
Figure 467. ECB encryption. . . . .	1932
Figure 468. ECB decryption. . . . .	1932
Figure 469. CBC encryption. . . . .	1933
Figure 470. CBC decryption. . . . .	1933
Figure 471. ECB/CBC encryption (Mode 1). . . . .	1934
Figure 472. ECB/CBC decryption (Mode 3). . . . .	1935
Figure 473. Message construction in CTR mode. . . . .	1936
Figure 474. CTR encryption. . . . .	1937
Figure 475. CTR decryption. . . . .	1937
Figure 476. Message construction in GCM . . . . .	1939
Figure 477. GCM authenticated encryption . . . . .	1940
Figure 478. Message construction in GMAC mode . . . . .	1944
Figure 479. GMAC authentication mode . . . . .	1944
Figure 480. Message construction in CCM mode . . . . .	1945
Figure 481. CCM mode authenticated encryption . . . . .	1947
Figure 482. 128-bit block construction with respect to data swap . . . . .	1952
Figure 483. DMA transfer of a 128-bit data block during input phase . . . . .	1954
Figure 484. DMA transfer of a 128-bit data block during output phase . . . . .	1955
Figure 485. SAES block diagram. . . . .	1974
Figure 486. ECB encryption and decryption principle . . . . .	1976
Figure 487. CBC encryption and decryption principle . . . . .	1977
Figure 488. Example of suspend mode management. . . . .	1981
Figure 489. ECB encryption. . . . .	1982
Figure 490. ECB decryption. . . . .	1982
Figure 491. CBC encryption. . . . .	1983
Figure 492. CBC decryption. . . . .	1983

Figure 493. ECB/CBC encryption (Mode 1) . . . . .	1984
Figure 494. ECB/CBC decryption (Mode 3) . . . . .	1985
Figure 495. Operation with wrapped keys . . . . .	1987
Figure 496. Usage of Shared-key mode . . . . .	1989
Figure 497. 128-bit block construction with respect to data swap . . . . .	1992
Figure 498. Key protection mechanisms . . . . .	1994
Figure 499. DMA transfer of a 128-bit data block during input phase . . . . .	1995
Figure 500. DMA transfer of a 128-bit data block during output phase . . . . .	1996
Figure 501. HASH block diagram . . . . .	2015
Figure 502. Message data swapping feature . . . . .	2017
Figure 503. HASH suspend/resume mechanism . . . . .	2023
Figure 504. OTFDEC block diagram . . . . .	2037
Figure 505. Typical OTFDEC use in a SoC . . . . .	2038
Figure 506. AES CTR decryption flow . . . . .	2039
Figure 507. OTFDEC flow control overview (dual burst read request) . . . . .	2040
Figure 508. PKA block diagram . . . . .	2060
Figure 509. Advanced-control timer block diagram . . . . .	2093
Figure 510. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	2100
Figure 511. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	2101
Figure 512. Counter timing diagram, internal clock divided by 1 . . . . .	2102
Figure 513. Counter timing diagram, internal clock divided by 2 . . . . .	2103
Figure 514. Counter timing diagram, internal clock divided by 4 . . . . .	2103
Figure 515. Counter timing diagram, internal clock divided by N . . . . .	2104
Figure 516. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .	2104
Figure 517. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded) . . . . .	2105
Figure 518. Counter timing diagram, internal clock divided by 1 . . . . .	2106
Figure 519. Counter timing diagram, internal clock divided by 2 . . . . .	2107
Figure 520. Counter timing diagram, internal clock divided by 4 . . . . .	2107
Figure 521. Counter timing diagram, internal clock divided by N . . . . .	2108
Figure 522. Counter timing diagram, update event when repetition counter is not used . . . . .	2108
Figure 523. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	2110
Figure 524. Counter timing diagram, internal clock divided by 2 . . . . .	2110
Figure 525. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .	2111
Figure 526. Counter timing diagram, internal clock divided by N . . . . .	2111
Figure 527. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .	2112
Figure 528. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .	2113
Figure 529. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	2114
Figure 531. Control circuit in normal mode, internal clock divided by 1 . . . . .	2116
Figure 532. tim_ti2 external clock connection example . . . . .	2116
Figure 533. Control circuit in external clock mode 1 . . . . .	2117
Figure 534. External trigger input block . . . . .	2118
Figure 535. Control circuit in external clock mode 2 . . . . .	2119
Figure 536. Capture/compare channel (example: channel 1 input stage) . . . . .	2119
Figure 537. Capture/compare channel 1 main circuit . . . . .	2120
Figure 538. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .	2121
Figure 539. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .	2121
Figure 540. PWM input mode timing . . . . .	2124
Figure 541. Output compare mode, toggle on tim_oc1 . . . . .	2126
Figure 542. Edge-aligned PWM waveforms (ARR = 8) . . . . .	2127
Figure 543. Center-aligned PWM waveforms (ARR = 8) . . . . .	2128

Figure 544. Dithering principle . . . . .	2129
Figure 545. Data format and register coding in dithering mode . . . . .	2130
Figure 546. PWM resolution vs frequency . . . . .	2131
Figure 547. PWM dithering pattern . . . . .	2132
Figure 548. Dithering effect on duty cycle in center-aligned PWM mode . . . . .	2133
Figure 549. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	2135
Figure 550. Combined PWM mode on channel 1 and 3 . . . . .	2136
Figure 551. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .	2137
Figure 552. Complementary output with symmetrical dead-time insertion . . . . .	2138
Figure 553. Asymmetrical deadtime . . . . .	2139
Figure 554. Dead-time waveforms with delay greater than the negative pulse . . . . .	2139
Figure 555. Dead-time waveforms with delay greater than the positive pulse . . . . .	2139
Figure 556. Break and Break2 circuitry overview . . . . .	2142
Figure 557. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .	2144
Figure 558. PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .	2145
Figure 559. PWM output state following tim_brk assertion (OSSI = 0) . . . . .	2146
Figure 560. Output redirection (tim_brk2 request not represented) . . . . .	2147
Figure 561. tim_ocref_clr input selection multiplexer . . . . .	2148
Figure 562. Clearing TIMx tim_ocxref . . . . .	2149
Figure 563. 6-step generation, COM example (OSSR = 1) . . . . .	2150
Figure 564. Example of one pulse mode . . . . .	2151
Figure 565. Retriggerable one-pulse mode . . . . .	2152
Figure 566. Pulse generator circuitry . . . . .	2153
Figure 567. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .	2154
Figure 568. Extended pulsewidth in case of concurrent triggers . . . . .	2155
Figure 569. Example of counter operation in encoder interface mode . . . . .	2157
Figure 570. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .	2157
Figure 571. Quadrature encoder counting modes . . . . .	2158
Figure 572. Direction plus clock encoder mode . . . . .	2159
Figure 573. Directional clock encoder mode (CC1P = CC2P = 0) . . . . .	2159
Figure 574. Directional clock encoder mode (CC1P = CC2P = 1) . . . . .	2160
Figure 575. Index gating options . . . . .	2161
Figure 576. Jittered Index signals . . . . .	2161
Figure 577. Index generation for IPOS[1:0] = 11 . . . . .	2162
Figure 578. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .	2162
Figure 579. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .	2163
Figure 580. Counter reading with index gated on channel A and B . . . . .	2163
Figure 581. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . .	2164
Figure 582. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .	2165
Figure 583. Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .	2166
Figure 584. Directional index sensitivity . . . . .	2166
Figure 585. Counter reset as function of FIDX bit setting . . . . .	2167
Figure 586. Index blanking . . . . .	2167
Figure 587. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .	2168
Figure 588. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .	2168
Figure 589. State diagram for quadrature encoded signals . . . . .	2169
Figure 590. Up-counting encoder error detection . . . . .	2170
Figure 591. Down-counting encode error detection . . . . .	2171
Figure 592. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .	2172
Figure 593. Measuring time interval between edges on three signals . . . . .	2173
Figure 594. Example of Hall sensor interface . . . . .	2175
Figure 595. Control circuit in reset mode . . . . .	2176

Figure 596. Control circuit in Gated mode . . . . .	2177
Figure 597. Control circuit in trigger mode . . . . .	2178
Figure 598. Control circuit in external clock mode 2 + trigger mode . . . . .	2179
Figure 599. General-purpose timer block diagram . . . . .	2237
Figure 600. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	2243
Figure 601. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	2244
Figure 602. Counter timing diagram, internal clock divided by 1 . . . . .	2245
Figure 603. Counter timing diagram, internal clock divided by 2 . . . . .	2245
Figure 604. Counter timing diagram, internal clock divided by 4 . . . . .	2246
Figure 605. Counter timing diagram, internal clock divided by N . . . . .	2246
Figure 606. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	2247
Figure 607. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .	2248
Figure 608. Counter timing diagram, internal clock divided by 1 . . . . .	2249
Figure 609. Counter timing diagram, internal clock divided by 2 . . . . .	2250
Figure 610. Counter timing diagram, internal clock divided by 4 . . . . .	2250
Figure 611. Counter timing diagram, internal clock divided by N . . . . .	2251
Figure 612. Counter timing diagram, Update event . . . . .	2251
Figure 613. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	2253
Figure 614. Counter timing diagram, internal clock divided by 2 . . . . .	2253
Figure 615. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .	2254
Figure 616. Counter timing diagram, internal clock divided by N . . . . .	2254
Figure 617. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .	2255
Figure 618. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .	2256
Figure 619. Control circuit in normal mode, internal clock divided by 1 . . . . .	2257
Figure 620. tim_ti2 external clock connection example . . . . .	2257
Figure 621. Control circuit in external clock mode 1 . . . . .	2258
Figure 622. External trigger input block . . . . .	2259
Figure 623. Control circuit in external clock mode 2 . . . . .	2260
Figure 624. Capture/compare channel (example: channel 1 input stage) . . . . .	2260
Figure 625. Capture/compare channel 1 main circuit . . . . .	2261
Figure 626. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .	2261
Figure 627. PWM input mode timing . . . . .	2264
Figure 628. Output compare mode, toggle on tim_oc1 . . . . .	2266
Figure 629. Edge-aligned PWM waveforms (ARR = 8) . . . . .	2267
Figure 630. Center-aligned PWM waveforms (ARR = 8). . . . .	2268
Figure 631. Dithering principle . . . . .	2269
Figure 632. Data format and register coding in dithering mode . . . . .	2270
Figure 633. PWM resolution vs frequency (16-bit mode). . . . .	2271
Figure 634. PWM resolution vs frequency (32-bit mode). . . . .	2271
Figure 635. PWM dithering pattern . . . . .	2272
Figure 636. Dithering effect on duty cycle in center-aligned PWM mode . . . . .	2273
Figure 637. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .	2275
Figure 638. Combined PWM mode on channels 1 and 3 . . . . .	2276
Figure 639. OCREF_CLR input selection multiplexer . . . . .	2277
Figure 640. Clearing TIMx tim_ocxref . . . . .	2277
Figure 641. Example of One-pulse mode . . . . .	2278
Figure 642. Retriggerable one-pulse mode . . . . .	2280
Figure 643. Pulse generator circuitry . . . . .	2281
Figure 644. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .	2281
Figure 645. Extended pulse width in case of concurrent triggers . . . . .	2282
Figure 646. Example of counter operation in encoder interface mode . . . . .	2284
Figure 647. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .	2284

Figure 648. Quadrature encoder counting modes . . . . .	2285
Figure 649. Direction plus clock encoder mode . . . . .	2286
Figure 650. Directional clock encoder mode (CC1P = CC2P = 0) . . . . .	2287
Figure 651. Directional clock encoder mode (CC1P = CC2P = 1) . . . . .	2287
Figure 652. Index gating options . . . . .	2289
Figure 653. Jittered Index signals . . . . .	2289
Figure 654. Index generation for IPOS[1:0] = 11 . . . . .	2290
Figure 655. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .	2290
Figure 656. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .	2291
Figure 657. Counter reading with index gated on channel A and B . . . . .	2291
Figure 658. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . .	2292
Figure 659. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .	2293
Figure 660. Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .	2294
Figure 661. Directional index sensitivity . . . . .	2294
Figure 662. Counter reset as function of FIDX bit setting . . . . .	2295
Figure 663. Index blanking . . . . .	2295
Figure 664. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .	2296
Figure 665. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .	2296
Figure 666. State diagram for quadrature encoded signals . . . . .	2297
Figure 667. Up-counting encoder error detection . . . . .	2298
Figure 668. Down-counting encode error detection . . . . .	2299
Figure 669. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .	2300
Figure 670. Control circuit in reset mode . . . . .	2302
Figure 671. Control circuit in gated mode . . . . .	2303
Figure 672. Control circuit in trigger mode . . . . .	2303
Figure 673. Control circuit in external clock mode 2 + trigger mode . . . . .	2305
Figure 674. Master/Slave timer example . . . . .	2305
Figure 675. Master/slave connection example with 1 channel only timers . . . . .	2306
Figure 676. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .	2307
Figure 677. Gating TIM_slv with Enable of TIM_mstr . . . . .	2308
Figure 678. Triggering TIM_slv with update of TIM_mstr . . . . .	2309
Figure 679. Triggering TIM_slv with Enable of TIM_mstr . . . . .	2309
Figure 680. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input . . . . .	2310
Figure 681. TIM15 block diagram . . . . .	2351
Figure 682. TIM16/TIM17 block diagram . . . . .	2352
Figure 683. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	2356
Figure 684. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	2357
Figure 685. Counter timing diagram, internal clock divided by 1 . . . . .	2358
Figure 686. Counter timing diagram, internal clock divided by 2 . . . . .	2359
Figure 687. Counter timing diagram, internal clock divided by 4 . . . . .	2359
Figure 688. Counter timing diagram, internal clock divided by N . . . . .	2360
Figure 689. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .	2360
Figure 690. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded) . . . . .	2361
Figure 691. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	2362
Figure 692. Control circuit in normal mode, internal clock divided by 1 . . . . .	2363
Figure 693. tim_ti2 external clock connection example . . . . .	2363
Figure 694. Control circuit in external clock mode 1 . . . . .	2364
Figure 695. Capture/compare channel (example: channel 1 input stage) . . . . .	2365
Figure 696. Capture/compare channel 1 main circuit . . . . .	2365
Figure 697. Output stage of capture/compare channel (channel 1) . . . . .	2366

Figure 698. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .	2366
Figure 699. PWM input mode timing . . . . .	2369
Figure 700. Output compare mode, toggle on tim_oc1 . . . . .	2371
Figure 701. Edge-aligned PWM waveforms (ARR = 8) . . . . .	2372
Figure 702. Dithering principle . . . . .	2373
Figure 703. Data format and register coding in dithering mode . . . . .	2373
Figure 704. PWM resolution vs frequency . . . . .	2374
Figure 705. PWM dithering pattern . . . . .	2375
Figure 706. Combined PWM mode on channel 1 and 2 . . . . .	2377
Figure 707. Complementary output with symmetrical dead-time insertion. . . . .	2378
Figure 708. Asymmetrical deadtime . . . . .	2379
Figure 709. Dead-time waveforms with delay greater than the negative pulse. . . . .	2379
Figure 710. Dead-time waveforms with delay greater than the positive pulse. . . . .	2379
Figure 711. Break circuitry overview . . . . .	2381
Figure 712. Output behavior in response to a break event on tim_brk . . . . .	2383
Figure 713. Output redirection . . . . .	2385
Figure 714. tim_ocref_clr input selection multiplexer. . . . .	2386
Figure 715. 6-step generation, COM example (OSSR = 1) . . . . .	2387
Figure 716. Example of one pulse mode. . . . .	2388
Figure 717. Retriggerable one pulse mode . . . . .	2390
Figure 718. Measuring time interval between edges on 2 signals . . . . .	2390
Figure 719. Control circuit in reset mode . . . . .	2391
Figure 720. Control circuit in gated mode . . . . .	2392
Figure 721. Control circuit in trigger mode . . . . .	2393
Figure 722. Basic timer block diagram. . . . .	2455
Figure 723. Control circuit in normal mode, internal clock divided by 1 . . . . .	2456
Figure 724. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	2457
Figure 725. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	2458
Figure 726. Counter timing diagram, internal clock divided by 1 . . . . .	2459
Figure 727. Counter timing diagram, internal clock divided by 2 . . . . .	2459
Figure 728. Counter timing diagram, internal clock divided by 4 . . . . .	2460
Figure 729. Counter timing diagram, internal clock divided by N . . . . .	2460
Figure 730. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	2461
Figure 731. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .	2462
Figure 732. Dithering principle . . . . .	2463
Figure 733. Data format and register coding in dithering mode . . . . .	2463
Figure 734. FCnt resolution vs frequency . . . . .	2464
Figure 735. PWM dithering pattern . . . . .	2464
Figure 736. LPTIM1/2/3 block diagram ⁽¹⁾. . . . .	2475
Figure 737. LPTIM4 block diagram ⁽¹⁾. . . . .	2476
Figure 738. Glitch filter timing diagram . . . . .	2480
Figure 739. LPTIM output waveform, single-counting mode configuration when repetition register content is different than zero (with PRELOAD = 1) . . . . .	2482
Figure 740. LPTIM output waveform, single-counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .	2483
Figure 741. LPTIM output waveform, Continuous counting mode configuration . . . . .	2483
Figure 742. Waveform generation . . . . .	2485
Figure 743. Encoder mode counting sequence . . . . .	2489
Figure 744. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1). . . . .	2490

Figure 745. Capture/compare input stage (channel 1) . . . . .	2491
Figure 746. Capture/compare output stage (channel 1) . . . . .	2491
Figure 747. Edge-aligned PWM mode (PRELOAD = 1) . . . . .	2493
Figure 748. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .	2494
Figure 749. PWM mode with immediate update versus preloaded update . . . . .	2495
Figure 750. GFXTIM block diagram . . . . .	2526
Figure 751. Clock generator . . . . .	2528
Figure 752. Waveforms in standalone . . . . .	2530
Figure 753. Active counters and signals in standalone . . . . .	2530
Figure 754. Waveforms with external HSYNC and VSYNC . . . . .	2530
Figure 755. Waveforms with external HSYNC only . . . . .	2531
Figure 756. Active counters and signals with external HSYNC only . . . . .	2531
Figure 757. Waveforms with external VSYNC only . . . . .	2531
Figure 758. Active counters with external VSYNC only . . . . .	2532
Figure 759. Prescaling when external VSYNC only . . . . .	2532
Figure 760. Waveforms with external CSYNC only . . . . .	2532
Figure 761. Active counters and signals with external CSYNC only . . . . .	2533
Figure 762. Prescaling when external CSYNC only . . . . .	2533
Figure 763. Tearing-effect configurations . . . . .	2535
Figure 764. Watchdog timer . . . . .	2536
Figure 765. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .	2561
Figure 766. Independent watchdog block diagram . . . . .	2563
Figure 767. Reset timing due to timeout . . . . .	2565
Figure 768. Reset timing due to refresh in the not allowed area . . . . .	2566
Figure 769. Changing PR, RL, and performing a refresh ⁽¹⁾. . . . .	2567
Figure 770. Independent watchdog interrupt timing diagram . . . . .	2569
Figure 771. Watchdog block diagram . . . . .	2577
Figure 772. Window watchdog timing diagram . . . . .	2579
Figure 773. RTC block diagram . . . . .	2585
Figure 774. TAMP block diagram . . . . .	2641
Figure 775. Backup registers protection zones . . . . .	2646
Figure 776. Tamper sampling with precharge pulse . . . . .	2651
Figure 777. Low level detection with precharge and filtering . . . . .	2651
Figure 778. Active tamper filtering . . . . .	2653
Figure 779. Block diagram . . . . .	2690
Figure 780. I ²C-bus protocol . . . . .	2693
Figure 781. Setup and hold timings . . . . .	2695
Figure 782. I2C initialization flow . . . . .	2697
Figure 783. Data reception . . . . .	2698
Figure 784. Data transmission . . . . .	2699
Figure 785. Target initialization flow . . . . .	2702
Figure 786. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .	2704
Figure 787. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .	2705
Figure 788. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .	2706
Figure 789. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .	2707
Figure 790. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .	2708
Figure 791. Transfer bus diagrams for I2C target receiver (mandatory events only) . . . . .	2708
Figure 792. Controller clock generation . . . . .	2710
Figure 793. Controller initialization flow . . . . .	2712
Figure 794. 10-bit address read access with HEAD10R = 0 . . . . .	2712
Figure 795. 10-bit address read access with HEAD10R = 1 . . . . .	2713

Figure 796.	Transfer sequence flow for I2C controller transmitter, $N \leq 255$ bytes.	2714
Figure 797.	Transfer sequence flow for I2C controller transmitter, $$ N > 255 $$ bytes.	2715
Figure 798.	Transfer bus diagrams for I2C controller transmitter (mandatory events only)	2716
Figure 799.	Transfer sequence flow for I2C controller receiver, $N \leq 255$ bytes	2718
Figure 800.	Transfer sequence flow for I2C controller receiver, $$ N > 255 $$ bytes.	2719
Figure 801.	Transfer bus diagrams for I2C controller receiver (mandatory events only)	2720
Figure 802.	Timeout intervals for $t_{LOW:SEXT}$ , $t_{LOW:MEXT}$	2724
Figure 803.	Transfer sequence flow for SMBus target transmitter N bytes + PEC	2727
Figure 804.	Transfer bus diagram for SMBus target transmitter (SBC = 1).	2728
Figure 805.	Transfer sequence flow for SMBus target receiver N bytes + PEC	2729
Figure 806.	Bus transfer diagrams for SMBus target receiver (SBC = 1)	2730
Figure 807.	Bus transfer diagrams for SMBus controller transmitter	2731
Figure 808.	Bus transfer diagrams for SMBus controller receiver	2733
Figure 809.	USART block diagram	2759
Figure 810.	Word length programming	2763
Figure 811.	Configurable stop bits	2765
Figure 812.	TC/TXE behavior when transmitting	2767
Figure 813.	Start bit detection when oversampling by 16 or 8.	2768
Figure 814.	usart_ker_ck clock divider block diagram	2771
Figure 815.	Data sampling when oversampling by 16	2772
Figure 816.	Data sampling when oversampling by 8	2773
Figure 817.	Mute mode using Idle line detection	2780
Figure 818.	Mute mode using address mark detection	2781
Figure 819.	Break detection in LIN mode (11-bit break length - LBDL bit is set)	2784
Figure 820.	Break detection in LIN mode vs. Framing error detection.	2785
Figure 821.	USART example of synchronous master transmission.	2786
Figure 822.	USART data clock timing diagram in synchronous master mode (M bits = 00)	2786
Figure 823.	USART data clock timing diagram in synchronous master mode (M bits = 01)	2787
Figure 824.	USART data clock timing diagram in synchronous slave mode (M bits = 00)	2788
Figure 825.	ISO 7816-3 asynchronous protocol	2790
Figure 826.	Parity error detection using the 1.5 stop bits	2792
Figure 827.	IrDA SIR ENDEC block diagram.	2796
Figure 828.	IrDA data modulation (3/16) - normal mode	2796
Figure 829.	Transmission using DMA	2798
Figure 830.	Reception using DMA	2799
Figure 831.	Hardware flow control between two USARTs.	2799
Figure 832.	RS232 RTS flow control	2800
Figure 833.	RS232 CTS flow control	2801
Figure 834.	LPUART block diagram	2848
Figure 835.	LPUART word length programming	2852
Figure 836.	Configurable stop bits	2854
Figure 837.	TC/TXE behavior when transmitting	2856
Figure 838.	lpuart_ker_ck clock divider block diagram	2860
Figure 839.	Mute mode using Idle line detection	2864
Figure 840.	Mute mode using address mark detection	2865
Figure 841.	Transmission using DMA	2867
Figure 842.	Reception using DMA	2868

Figure 843. Hardware flow control between two LPUARTs . . . . .	2869
Figure 844. RS232 RTS flow control . . . . .	2869
Figure 845. RS232 CTS flow control . . . . .	2870
Figure 846. SPI block diagram . . . . .	2904
Figure 847. Full-duplex single master/ single slave application . . . . .	2908
Figure 848. Half-duplex single master/ single slave application . . . . .	2909
Figure 849. Simplex single master / single slave application (master in transmit-only / slave in receive-only mode) . . . . .	2910
Figure 850. Master and three independent slaves connected in star topology . . . . .	2911
Figure 851. Multimaster application . . . . .	2912
Figure 852. Scheme of NSS control logic . . . . .	2914
Figure 853. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .	2914
Figure 854. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . .	2915
Figure 855. Data clock timing diagram . . . . .	2917
Figure 856. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .	2918
Figure 857. TI mode transfer . . . . .	2928
Figure 858. Optional configurations of the slave behavior when an underrun condition is detected . . . . .	2930
Figure 859. SAI functional block diagram . . . . .	2954
Figure 860. Audio frame . . . . .	2958
Figure 861. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .	2960
Figure 862. FS role is start of frame (FSDEF = 0) . . . . .	2961
Figure 863. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .	2962
Figure 864. First bit offset . . . . .	2962
Figure 865. Audio block clock generator overview . . . . .	2964
Figure 866. PDM typical connection and timing . . . . .	2968
Figure 867. Detailed PDM interface block diagram . . . . .	2969
Figure 868. Start-up sequence . . . . .	2970
Figure 869. SAI_ADR format in TDM mode, 32-bit slot width . . . . .	2971
Figure 870. SAI_ADR format in TDM mode, 16-bit slot width . . . . .	2972
Figure 871. SAI_ADR format in TDM mode, 8-bit slot width . . . . .	2973
Figure 872. AC'97 audio frame . . . . .	2976
Figure 873. Example of typical AC'97 configuration on devices featuring at least two embedded SAIs (three external AC'97 decoders) . . . . .	2977
Figure 874. SPDIF format . . . . .	2978
Figure 875. SAI_xDR register ordering . . . . .	2979
Figure 876. Data companding hardware in an audio block in the SAI . . . . .	2982
Figure 877. Tristate strategy on SD output line on an inactive slot . . . . .	2984
Figure 878. Tristate on output data line in a protocol like I2S . . . . .	2985
Figure 879. Overrun detection error . . . . .	2986
Figure 880. FIFO underrun event . . . . .	2986
Figure 881. CAN subsystem . . . . .	3021
Figure 882. FDCAN block diagram . . . . .	3023
Figure 883. Bit timing . . . . .	3025
Figure 884. Transceiver delay measurement . . . . .	3030
Figure 885. Pin control in bus monitoring mode . . . . .	3031
Figure 886. Pin control in loop-back mode . . . . .	3034
Figure 887. CAN error state diagram . . . . .	3035
Figure 888. Message RAM configuration . . . . .	3036
Figure 889. Standard message ID filter path . . . . .	3039
Figure 890. Extended message ID filter path . . . . .	3040
Figure 891. USB peripheral block diagram . . . . .	3087
Figure 892. Packet buffer areas with examples of buffer description table locations . . . . .	3094

Figure 893. OTG_FS full-speed block diagram . . . . .	3138
Figure 894. OTG_FS A-B device connection. . . . .	3140
Figure 895. OTG_FS peripheral-only connection . . . . .	3142
Figure 896. OTG_FS host-only connection . . . . .	3146
Figure 897. SOF connectivity (SOF trigger output to TIM and ITRx connection). . . . .	3150
Figure 898. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .	3152
Figure 899. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .	3153
Figure 900. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .	3154
Figure 901. Interrupt hierarchy. . . . .	3158
Figure 902. Transmit FIFO write task . . . . .	3241
Figure 903. Receive FIFO read task . . . . .	3242
Figure 904. Normal bulk/control OUT/SETUP . . . . .	3243
Figure 905. Bulk/control IN transactions . . . . .	3247
Figure 906. Normal interrupt OUT . . . . .	3250
Figure 907. Normal interrupt IN . . . . .	3255
Figure 908. Isochronous OUT transactions . . . . .	3257
Figure 909. Isochronous IN transactions . . . . .	3260
Figure 910. Receive FIFO packet read . . . . .	3264
Figure 911. Processing a SETUP packet . . . . .	3266
Figure 912. Bulk OUT transaction . . . . .	3273
Figure 913. TRDT max timing case . . . . .	3283
Figure 914. A-device SRP . . . . .	3284
Figure 915. B-device SRP . . . . .	3285
Figure 916. A-device HNP . . . . .	3286
Figure 917. B-device HNP . . . . .	3288
Figure 918. OTG_HS high-speed block diagram. . . . .	3293
Figure 919. OTG_HS A-B device connection . . . . .	3295
Figure 920. OTG_HS peripheral-only connection . . . . .	3297
Figure 921. OTG_HS host-only connection . . . . .	3301
Figure 922. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .	3305
Figure 923. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .	3307
Figure 924. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .	3308
Figure 925. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .	3309
Figure 926. Interrupt hierarchy. . . . .	3313
Figure 927. Transmit FIFO write task . . . . .	3406
Figure 928. Receive FIFO read task . . . . .	3407
Figure 929. Normal bulk/control OUT/SETUP . . . . .	3408
Figure 930. Bulk/control IN transactions . . . . .	3412
Figure 931. Normal interrupt OUT . . . . .	3415
Figure 932. Normal interrupt IN . . . . .	3420
Figure 933. Isochronous OUT transactions . . . . .	3422
Figure 934. Isochronous IN transactions . . . . .	3425
Figure 935. Normal bulk/control OUT/SETUP transactions - DMA . . . . .	3427
Figure 936. Normal bulk/control IN transaction - DMA. . . . .	3429
Figure 937. Normal interrupt OUT transactions - DMA mode . . . . .	3430
Figure 938. Normal interrupt IN transactions - DMA mode . . . . .	3431
Figure 939. Normal isochronous OUT transaction - DMA mode . . . . .	3432
Figure 940. Normal isochronous IN transactions - DMA mode . . . . .	3433
Figure 941. Receive FIFO packet read . . . . .	3439
Figure 942. Processing a SETUP packet . . . . .	3441
Figure 943. Bulk OUT transaction . . . . .	3448
Figure 944. TRDT max timing case . . . . .	3457

Figure 945. UCPD block diagram . . . . .	3461
Figure 946. Clock division and timing elements. . . . .	3463
Figure 947. K-code transmission . . . . .	3465
Figure 948. Transmit order for various sizes of data . . . . .	3466
Figure 949. Packet format . . . . .	3467
Figure 950. Line format of Hard Reset. . . . .	3467
Figure 951. Line format of Cable Reset. . . . .	3468
Figure 952. BIST test data frame. . . . .	3469
Figure 953. BIST Carrier Mode 2 frame. . . . .	3469
Figure 954. UCPD BMC transmitter architecture. . . . .	3470
Figure 955. UCPD BMC receiver architecture . . . . .	3471
Figure 956. Block diagram of debug support infrastructure. . . . .	3499
Figure 957. JTAG TAP state machine . . . . .	3503
Figure 958. CoreSight topology . . . . .	3521
Figure 959. Trace port interface unit (TPIU) . . . . .	3590
Figure 960. Embedded cross trigger . . . . .	3601

RM0456-STM32U5

Contents

List of tables

List of figures

Chapters

RM0456-STM32U5

Related documents

Contents

List of tables

List of figures

Chapters