67. Revision history

Section 12: System configuration controller (SYSCFG)
Added Section 12.3.1: Analog switch configuration management , Section 12.3.2: I2C Fm+ configuration , Section 12.3.4: Management of external interrupt line connections to GPIOs and Section 12.3.5: I/O speed in low-voltage mode . SYSCFG peripheral mode configuration register (SYSCFG_PMCR) :
Updated reset value.
Updated PBxFMP and I2CxFMP descriptions

Section 38: True random number generator (RNG)
Corrected section numbering.
Section 43: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Removed all information related to BDTR register, MOE and OSSSI bits. Updated Figure 404: Output stage of Capture/Compare channel (channel 1) .

Section 45: General-purpose timers (TIM15/TIM16/TIM17)
Changed COMDE of TIMx_DIER for TIM16/17 to reserved.

Section 52: Inter-integrated circuit (I2C) interface
Swapped I2C_SDA and I2C_SCL definition in Table 371: I2C input/output pins .

Changed document classification to public.
Added support for STM32H7B0 value line.
Updated Figure 1: System architecture for STM32H7A3/7B3/7B0xx devices , Table 7: Register boundary addresses . Updated USART3 pins and added FDCAN1 in Section : Embedded bootloader .

Section 4: Embedded flash memory (FLASH)
Whole section updated to support STM32H7B0 and STM32H7A3xG. Specified that the Secure access mode is available only on STM32H7B0 and STM32H7B3 devices.
In Table 26: Effect of low-power modes on the embedded flash memory , added VSO0 in the list of voltage ranges applicable for Run mode.
Updated Figure 8: Embedded flash memory usage . Section : Adjusting programming timing constraints : added note related to WRHIGHFREQ modification during Flash memory programming/erasing.
Updated BOR option byte default value when the devices are delivered by STMicroelectronics in Section 4.4.5: Description of user and system option bytes .
Section 4.4.6: Description of data protection option bytes
Secure DTCM size (ST_RAM_SIZE):

• – Removed Secure DTCM size (ST_RAM_SIZE) from Section : Changing user option bytes .
• – Changed Default factory value to 11 in Table 21: Option byte organization .
• – Updated ST_RAM_SIZE description and added ST_RAM_SIZE to the values programmed in the data protection option bytes in Section 4.4.6: Description of data protection option bytes .

Updated Table 16: FLASH recommended number of wait states and programming delay .

Section : Definitions of RDP global protection level : updated description of RDP level 1 to 0 regression and RDP level 2. Section : RDP protection transitions : user Flash memory can be partially or mass erased when doing a level regression from RDP level 1 to 0.

In Section 4.9.8: FLASH option status register (FLASH_OPTSR_CUR) and Section 4.9.9: FLASH option status register (FLASH_OPTSR_PRG) :

• – Added note related to the availability of the whole DTCM RAM regardless of ST_RAM_SIZE configuration of FLASH_OPTSR_CUR/PRG.
• – Updated BOV_LEV 00 configuration in FLASH_OPTSR_CUR/PRG.

Restored Section 4.9.17: FLASH register boot address (FLASH_BOOT_CURR) and Section 4.9.18: FLASH register boot address (FLASH_BOOT_PRGR) register descriptions and renamed BOOT_CM_ADD01/ into BOOT_ADD0/1 in the whole document.

Section 5: Secure memory management (SMM) (former Secure internal Flash memory)
Added STM32H7B0 devices and specified that the Secure access mode is not available on STM32H7A3.
Changed SIFM domain from D1 to CD in Section 5.1: Introduction .
Added note related to HDP in Table 29: List of preferred terms .
Updated Figure 15: Flash memory areas and services in Standard and Secure access modes and Removed note related to secure user area.
Updated Section 5.4.2: Secure area exiting service .
Added Section 5.4.3: OTFDEC encryption service .

Section 6: Power control (PWR)

Added PDV_IN to Figure 18: Power control block diagram , and Table 32: PWR input/output signals connected to package pins or balls .

Replaced RC48 by HSI48 in Figure 19: Power supply overview .

In Section 6.4.5: Backup domain , removed PC1 from the list of functions available in VBAT mode when the VDD supply is absent and a supply is present on VBAT.

Replaced PDR by POR/PDR in Section 6.5.1: Power-on reset (POR)/power-down reset (PDR) .

Removed reference to VBOR0 for BOR off in Section 6.5.2: Brownout reset (BOR) .

Updated Section 6.5.5: Battery voltage thresholds and Section 6.7.7: DStop and DStop2 modes .

Added GFXSO bit (position 25) and update FLPS bit description in Section 6.8.1: PWR control register 1 (PWR_CR1) .

Changed VBATH/L bits to reserved in Section 6.8.3: PWR control register 2 (PWR_CR2) .

Section 7: Low-power SRD domain application example

Replaced LINUART1 by LPUART1.

Updated Figure 41: Timing diagram of SRD SRAM-to-LPUART1 transfer with BDMA2 and SRD domain in Autonomous mode .

Updated Section : EXTI programming .

Updated DMAMUX2_C0CR value for DMAMUX2_SYNC0 in Table 48: BDMA2 and DMAMUX2 initialization sequence (DMAMUX2_INIT) .

Renamed Table 50 into “LPUART1 start programming.”

Section 8: Reset and clock control (RCC)

Replace rc48_ck by hsi48_ck in Figure 47: Top-level clock tree and Figure 61: Kernel clock distribution for USB (2) . Updated Figure 48: HSE/LSE clock source and Figure 55: Kernel clock distribution for SAIs, DFSDMs and SPDIFRX .

Updated maximum VCO range in Figure 52: PLL block diagram , PLL3VCOSEL, PLL2VCOSEL and PLL1VCOSEL of RCC PLLs configuration register (RCC_PLL_CFGGR) , in DIVN1/2/3[8:0] of RCC PLL1 dividers configuration register (RCC_PLL1DIVR) / RCC PLL2 dividers configuration register (RCC_PLL2DIVR) / RCC PLL3 dividers configuration register (RCC_PLL3DIVR) and FRACN1/2/3[12:0] of RCC PLL1 fractional divider register (RCC_PLL1FRACR) / RCC PLL2 fractional divider register (RCC_PLL2FRACR) / RCC PLL3 fractional divider register (RCC_PLL3FRACR) .

Changed sys_ck_cpu and sys_ck_bus max frequency to 280 MHz in Figure 54: Core and bus clock generation .

In Table 58: Kernel clock distribution overview , updated DAC1. removed note 6 and changed DFSDM to DFSDM2 in note 7 related to SPI6 maximum frequency.

Updated Figure 62: Kernel clock distribution for ADCs, SWPMI, RNG and FDCANs .

Updated CPUCKRDY bit description in RCC source control register (RCC_CR) .

Updated TIMPRE bit description in RCC clock configuration register (RCC_CFGGR) .

Replaced DCMIRST by DCMI_PSSIRST in RCC AHB2 peripheral reset register (RCC_AHB2RSTR) , DCMIEN by DCMI_PSSIEEN in RCC AHB2 clock register (RCC_AHB2ENR) , DCMILPEN by DCMI_PSSILPEN in RCC AHB2 sleep clock register (RCC_AHB2LPENR) and TMPSENLPEN by DTSLPEN in RCC APB4 sleep clock register (RCC_APB4LPENR) .

Section 8: Reset and clock control (RCC) (continued)

Replaced TMPSENSRST by DTSRST in RCC APB4 peripheral reset register (RCC_APB4RSTR) , TMPSENSAMEN by DTSAMEN in RCC SmartRun domain Autonomous mode register (RCC_SRDAMR) and TMPSENSEN by DTSEN in RCC APB4 clock register (RCC_APB4ENR) .

Section 9: Clock recovery system (CRS)

Added Section 9.3: CRS implementation .

Updated Section 9.8.1: CRS control register (CRS_CR) and Table 68: CRS register map and reset values .

Section 12: System configuration controller (SYSCFG)

Added Section 12.3.1: Analog switch configuration management , Section 12.3.2: I2C Fm+ configuration , Section 12.3.4: Management of external interrupt line connections to GPIOs and Section 12.3.5: I/O speed in low-voltage mode .

Updated reset value and PBxFMP and I2CxFMP descriptions in SYSCFG peripheral mode configuration register (SYSCFG_PMCR) .

Renamed SYSCFG_BRK_LOCKUPR into SYSCFG_CFGR.

Section 13: Block interconnect

Renamed DCMI to DCMI_PSSI in Table 81: DMAMUX1, DMA1, DMA2 and BDMA1 connections .

Section 14: MDMA controller (MDMA)

Updated number of hardware trigger sources in Section 14.2: MDMA main features .

Updated Figure 82: MDMA block diagram .

Section 16: Basic direct memory access controller (BDMA)

Added “Channel state and disabling channel” sub-part in Section 16.4.5: BDMA channels .

Section 19: Nested vectored interrupt controller (NVIC)

Replaced DCMI by DCMI/PSSI and added cpu_fpu_it (position 81) in Table 123: NVIC .

Section 20: Extended interrupt and event controller (EXTI)

Removed HSEM and Cortex-M7 SEV interrupts in Table 126: EXTI Event input mapping .

Section 23: Flexible memory controller (FMC)

Replaced BCH8 by Hamming in Section 23.8.6: Computation of the error correction code (ECC) in NAND flash memory

Updated Figure 119: Mode D write access waveforms .

Replaced FMC_CLK by fmc_ker_ck in the formulas of Section : Wait management .

Section 24: Octo-SPI interface (OCTOSPI)

Section 24.4.11: OCTOSPI memory-mapped mode: removed timeout from the list of events triggering BUSY fall; removed mention that Memory-mapped write operations are not supported on memories without write strobe or in Dual-quad mode in Section : Memory-mapped mode configuration .

Updated Section : Sending the instruction only once (SIOO) .

Updated WRAP support subsection in Section 24.4.7: Specific features .

Updated ABORT, EN and FTHRES[4:0] descriptions in Section 24.7.1: OCTOSPI control register (OCTOSPI_CR) , DLYBYP bit in Section 24.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1) and FLEVEL description in Section 24.7.6: OCTOSPI status register (OCTOSPI_SR) .

Section 25: OCTOSPI I/O manager (OCTOSPIM)

Updated Section 25.4.4: OCTOSPIM multiplexed mode .

Section 27: Analog-to-digital converters (ADC)

Removed VREF+ and VREF- ranges and added adc_sclk in Table 191: ADC input/output pins .

Added reference to LDORDY bit in the whole section.

Added LDO voltage regulator and replaced SMPPLUS control by Extended sample time option (SMPPLUS control) in Section 27.3: ADC implementation .

Added adc_sclk in Figure 157: ADC block diagram .

Updated Section 27.4.3: ADC clocks . Renamed adc_ker_ck into adc_ker_ck_inputs.

Updated Section : BOOST control .

Changed BOOSTE bit register to PWR_CR1 in Section : I/O analog switch voltage booster .

Updated Figure 159: ADC1 connectivity and Figure 160: ADC2 connectivity . Changed TIMx_CCy into TIMx_OCy and all source names put in low-case in Section 27.4.19: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) .

Updated Section : Single ADC operating modes support when oversampling to remove the mention that the offset correction is not supported in oversampling mode.

Updated ADC input channel to which VBAT supply is connected in Section 27.4.34: VBAT supply monitoring .

Updated RES[2:0] bitfield definition in Section 27.6.4: ADC configuration register (ADC_CFGR) .

Updated LSHIFT[3:0] “Shift left 14-bits” configuration in Section 27.6.5: ADC configuration register 2 (ADC_CFGR2) register.

Updated Section 27.6.26: ADC calibration factors register (ADC_CALFACT) register. Renamed VSENSEEN into TSEN in Section 27.7.2: ADC x common control register (ADCx_CCR) (x=1/2).

Replaced adc_hclk by adc_hclk in CKMODE[1:0] bitfield definition of Section 27.7.2: ADC x common control register (ADCx_CCR) (x=1/2).

Section 28: Digital temperature sensor (DTS)
Changed title to “Digital temperature sensor”.
Removed all information related to quick measurement mode.
Removed EN pin and Q_MEAS_opt from Figure 227: Temperature sensor functional block diagram .
Updated Table 212: Trigger configuration .
Updated formulas to calculate the temperature in Section 28.3.7: Temperature measurement principles .
Removed startup time value from Section 28.3.10: On-off control and ready flag
Updated bitfield descriptions in Section 28.6.5: Temperature sensor data register (DTS_DR) .
Removed TS1_EN and updated TS1_INTRIG_SEL[3:0] to replace the list of triggers by a reference to Table Trigger configuration in Section 28.6.1: Temperature sensor configuration register 1 (DTS_CFGR1) .
Changed DTS_OR bitfield names to uppercase (TS_opn into TS_OPn).

Section 29: Digital-to-analog converter (DAC)
Updated Section 29.3: DAC implementation . Renamed internal signals:
Replaced sample and hold clock by dac_hold_ck.
Changed dac_chx_trg[0:15] into dac_chx_trg[1:15].
Updated TSELx bitfield description in DAC_CR register to add the correspondence between TSELx configurations and dac_chx_trgy.
Updated Figure 231: Dual-channel DAC block diagram . Updated Section 29.3: DAC implementation .
Added Table 219: DAC1 interconnection and Table 220: DAC2 interconnection in Section 29.4.2: DAC pins and internal signals and replaced ck_lsi by lsi_ck. Updated Figure 234: Timing diagram for conversion with trigger disabled TEN = 0 . Updated Section : Sample and hold mode to indicate that the lsi_ck/lse_ck (when available) must not be stopped when Sample and hold mode enabled.
Removed Trigger selection tables from Section 29.4.7: DAC trigger selection . Updated supply voltages in Section 29.4.12: DAC channel buffer calibration .
Updated CStop mode description for DAC2 in Section 29.5: DAC in low-power modes .
Updated Section 29.6: DAC interrupts .

Section 33: Digital filter for sigma delta modulators (DFSDM)
Updated Section 33.7: DFSDM channel y registers (y=0..7) .
Updated Section 33.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR) .
Updated Section 33.8: DFSDM filter x module registers (x=0..7) .

Section 30: Voltage reference buffer (VREFBUF)
Updated supported voltages in Section 30.2: VREFBUF functional description .

Section 34: Digital camera interface (DCMI)
Updated pin names in Section 34.3: DCMI functional description .

Section 38: True random number generator (RNG)

Updated Section 38.1: Introduction and Section 38.2: RNG main features .

Updated Figure 282: RNG block diagram and Table 281: RNG internal input/output signals .

Updated Section 38.4: RNG interrupts .

Renamed NISTN by NISTC.

Updated Section 38.3.3: Random number generation and Figure 283: NIST SP800-90B entropy source model .

Updated note in Section 38.3.5: RNG operation .

Updated Section 38.4: RNG interrupts , Section 38.5: RNG processing time , and Section 38.6: RNG entropy source validation and in particular Table 283: RNG configurations and Section 38.6.3: Data collection .

Updated Section 38.7.3: RNG data register (RNG_DR) .

Added note in Section 38.7.4: RNG health test control register (RNG_HTCR) .

Section 39: Cryptographic processor (CRYP)

Updated number of clock cycles for TDES in Section 39.2: CRYP main features .

Updated Table 293: Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3).

Updated Section 39.4.17: CRYP key registers .

Section 39.5: CRYP interrupts : removed CRYP interrupt mapping diagram and updated Table 298: CRYP interrupt requests .

Section 39.6: CRYP processing time : updated Table 299: Processing latency for ECB, CBC and CTR and Table 300: Processing time (in clock cycle) for GCM and CCM per 128-bit block .

Section 40: Hash processor (HASH)

Removed MDMA feature.

Message size changed to 264-1 in Section 40.1: Introduction and Section 40.4.3: About secure hash algorithms .

Added Section 40.3: HASH implementation .

Simplified Figure 309: HASH block diagram and renamed hash_in_dma internal signal into hash_dma.

Updated Figure 310: Message data swapping feature .

Updated Section 40.4.8: HASH suspend/resume operations .

Renamed the HASH_HRx registers located at address offset 0x0C into HASH_HRAx.

Specified value returned by reading HASH data input register (HASH_DIN) .

Updated ALGO description in HASH control register (HASH_CR) .

Section 41: On-The-Fly decryption engine - AXI (OTFDEC)

Modified Figure 313: Typical OTFDEC usage in the device .

Replaced "Flash memory" with "external read-only memory" and of "SPI NOR Controller" with "external memory controller" in the whole document.

Modified Section 41.5.3: Encrypting for OTFDEC .

Section 42: Advanced-control timers (TIM1/TIM8)
Updated Figure 317: Advanced-control timer block diagram .
Updated Section 42.3.3: Repetition counter .
Updated Section 42.3.16: Using the break function and Figure 360: Break and Break2 circuitry overview . Updated Section 42.3.29: Debug mode
Updated Section 42.4.2: TIMx control register 2 (TIMx_CR2)(x = 1, 8) .
Aligned TS[2:0] field in Section 42.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . Updated Section 42.4.5: TIMx status register (TIMx_SR)(x = 1, 8) , Section 42.4.6: TIMx event generation register (TIMx_EGR)(x = 1, 8) . Updated Table 315: TIM1 register map and reset values and Table 316: TIM8 register map and reset values .

Section 43: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Updated Figure 377: General-purpose timer block diagram . Updated Section : External clock source mode 2 .
Updated Figure 404: Output stage of Capture/Compare channel (channel 1) .
Updated Section 43.4.2: TIMx control register 2 (TIMx_CR2)(x = 2 to 5) , Section 43.4.5: TIMx status register (TIMx_SR)(x = 2 to 5) , Section 43.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) , Section 43.4.12: TIMx counter (TIMx_CNT)(x = 2 to 5) and Table 320: TIM2/TIM3/TIM4/TIM5 register map and reset values .

Section 44: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 427: General-purpose timer block diagram (TIM12) .
Updated Figure 441: Capture/compare channel 1 main circuit and Figure 442: Output stage of capture/compare channel (channel 1)
Updated Section 44.4.2: TIM12 control register 2 (TIM12_CR2) , Section 44.4.5: TIM12 status register (TIM12_SR) and Section 44.4.6: TIM12 event generation register (TIM12_EGR) . Updated OC1FE description in Section 44.4.7: TIM12 capture/compare mode register 1 (TIM12_CCMR1) and Section 44.5.5: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 13 to 14) .

Section 45: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 453: TIM15 block diagram and Figure 454: TIM16/TIM17 block diagram and Figure 468: Capture/compare channel 1 main circuit .
Updated source for break channels in Section 45.4.13: Using the break function .
Updated Figure 478: Break circuitry overview .
Updated Section 45.5.2: TIM15 control register 2 (TIM15_CR2) , Section 45.5.5: TIM15 status register (TIM15_SR) , Section 45.5.9: TIM15 capture/compare enable register (TIM15_CCER) , Section 45.6.2: TIMx control register 2 (TIMx_CR2)(x = 16 to 17) , Section 45.6.4: TIMx status register (TIMx_SR)(x = 16 to 17) , Section 45.6.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) and Section 45.6.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) .
Replaced DT[7:0] by DTG[7:0] in Table 329: TIM15 register map and reset values and Table 331: TIM16/TIM17 register map and reset values . Updated OC1FE description in Section 45.5.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and Section 45.6.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) .

Section 47: Low-power timer (LPTIM)
Updated Section 47.4.5: Glitch filter .

Section 51: Tamper and backup registers (TAMP)
Updated Figure 510: TAMP block diagram . Updated Table 363: TAMP internal input/output signals and Table 364: TAMP interconnection . Updated Section : TAMP backup registers .
Added: Table 367: TAMP pins functionality over modes .

Section 52: Inter-integrated circuit (I2C) interface
Updated Section 52.3: I2C implementation . Updated Section 52.6: I2C interrupts
Updated Section 52.7.2: I2C control register 2 (I2C_CR2) , Section 52.7.3: I2C own address 1 register (I2C_OAR1) and Section 52.7.8: I2C interrupt clear register (I2C_ICR) .

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Updated Section 53.5.4: USART FIFOs and thresholds .
Changed USART_TDR into USART_RDR in Figure 563: Reception using DMA .
Updated RTO bitfield description in Section 53.8.7: USART receiver timeout register (USART_RTOR) register.
Changed reset value for FIFO enabled and disabled of Section 53.8.9: USART interrupt and status register (USART_ISR) and Table 397: USART register map and reset values .
Changed reset value of USART receive data register (USART_RDR) and USART transmit data register (USART_TDR) .
Changed reset value for FIFO enabled and disabled of Section 54.7.9: LPUART interrupt flag clear register (LPUART_ICR) and Table 407: LPUART register map and reset values .

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Added Section 54.3: LPUART implementation .
Changed LPUART_TDR into LPUART_RDR in Figure 577: Reception using DMA .
Updated Section 54.4.4: LPUART FIFOs and thresholds .

Section 55: Serial peripheral interface (SPI)
Updated Table 408: STM32H7A3/7B3/7B0xx SPI features .
Updated note below Figure 587: Master and three independent slaves at star topology .
Updated Figure 599: Waveform examples .
Updated Section 55.11.1: SPI/I2S control register 1 (SPI_CR1) .
Updated CRCSIZE[4:0] description in Section 55.11.3: SPI configuration register 1 (SPI_CFG1) .

Section 58: Single wire protocol master interface (SWPMI)
Updated Table 436: SWPMI input/output signals connected to package pins or balls .
Replaced SWPSCR of RCC_D2CCIP1R by SWPSEL of RCC_CDCCIP1R in Section 58.3.1: SWPMI block diagram .

Section 56: Serial audio interface (SAI)
Added Section 56.3: SAI implementation .
Number of Dn and CKn lines made generic in Figure 618: SAI functional block diagram .
Added note to indicate that all Dn and CKn might not be available on all SAI instances below Figure 618: SAI functional block diagram , Table 418: SAI input/output pins .
Updated Figure 627: Start-up sequence and added note related to the fact that Fs and Fsck_x formulas are valid only if NODIV = 1.

Section 60: Secure digital input/output MultiMediaCard interface (SDMMC)
Added Section 60.2: SDMMC implementation .

Section 61: Controller area network with flexible data rate (FDCAN)
Updated Section 61.1: Introduction , Section 61.2: FDCAN main features . Added Section 61.3: FDCAN implementation . Added Table 475: CAN triggers .
Updated Figure 705: FDCAN block diagram to remove FDCAN1/2_T/RXFD_MODE signals.
Updated Section : Acceptance filter , Section 61.4.4: Bit timing , Section 61.4.5: Clock calibration on CAN , Section 61.4.6: Application , and Section : Timing of interface signals .
Updated Table 495: Standard message ID filter element , Table 497: Extended message ID filter element , Table 500: Trigger memory element description , Figure 710: Standard message ID filter path and Figure 711: Extended message ID filter path .
Updated Table 495: Standard message ID filter element , Table 497: Extended message ID filter element , Table 500: Trigger memory element description .
Updated Section 61.5.6: FDCAN CC control register (FDCAN_CCCR) , Section 61.5.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) , Section 61.5.12: FDCAN error counter register (FDCAN_ECR) , Section 61.5.15: FDCAN interrupt register (FDCAN_IR) , Section 61.5.15: FDCAN interrupt register (FDCAN_IR) , Section 61.5.18: FDCAN interrupt line enable register (FDCAN_ILE) , Section 61.5.21: FDCAN extended ID filter configuration register (FDCAN_XIDFC) , Section 61.5.37: FDCAN Tx buffer request pending register (FDCAN_TXBRP) , Section 61.6.6: FDCAN TT operation control register (FDCAN_TTOCN) and Section 61.6.18: FDCAN TT trigger select register (FDCAN_TTTS) .
Updated Table 502: FDCAN TT register map and reset values and Table 503: CCU register map and reset values .

Section 62: USB on-the-go high-speed (OTG_HS)

Updated Section 62.2.1: General features .

Updated Section 62.14.2: OTG interrupt register (OTG_GOTGINT) , Section 62.14.5: OTG reset register (OTG_GRSTCTL) , Section 62.14.6: OTG core interrupt register (OTG_GINTSTS) , Section 62.14.18: OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) , Section 62.14.22: OTG host frame interval register (OTG_HFIR) , Section 62.14.33: OTG host channel x transfer size register (OTG_HCTSIZx) , Section 62.14.39: OTG device configuration register (OTG_DCFG) , Section 62.14.40: OTG device control register (OTG_DCTL) , Section 62.14.41: OTG device status register (OTG_DSTS) , Section 62.14.42: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) , Section 62.14.43: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) , Section 62.14.54: OTG device IN endpoint x control register (OTG_DIEPCTLx) , Section 62.14.61: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) .

Updated Section 62.15.3: Device initialization and Section 62.15.6: Device programming model .

Updated Section 62.10: OTG_HS Dynamic update of the OTG_HFIR register .

Section 64: Debug infrastructure

Updated ETM CoreSight device architecture register (M7_ETM_DEVARCH) . Added revision Z and Y in DBGMCU identity code register (DBGMCU_IDC) .

Section 2: Memory and bus architecture
Updated Table 8: Boot modes for BOOT = 1.

Section 4: Embedded flash memory (FLASH)
Changed max voltage to 2.7 V for VDDIO_HSLV and VDDMMC_HSLV in Section 4.4.5: Description of user and system option bytes , Section 4.9.8: FLASH option status register (FLASH_OPTSR_CUR) and Section 4.9.9: FLASH option status register (FLASH_OPTSR_PRG) .
Renamed VDD_HSLV into VDDIO_HSLV in Table 21: Option byte organization .

Section 6: Power control (PWR)
In the whole chapter, replaced 'voltage regulator' by 'LDO voltage regulator'. Updated Figure 18: Power control block diagram and Figure 19: Power supply overview .
Updated Figure 20: System supply configurations for packages with SMPS to restrict it to devices with SMPS, added note 1 below figure; added Figure 21: System supply configurations for packages without SMPS .
Grouped description of regulators and regulator operating modes under Section 6.4.3: Voltage regulators .
Modified Section 6.4.4: PWR external supply . Updated Section 6.5.5: Battery voltage thresholds .
Section 6.6: Power management:

• – Updated introduction
• – Reworked Section 6.6.1: System operating modes .
• – Updated Figure 34: VCORE voltage scaling versus system power modes .
• – Updated Section 6.6.3: Power control modes including Figure 35: Power-control modes detailed state diagram
• – Updated Table 34: Supply configuration control and Table 35: Operating mode summary . Replaced Run or Stop by SDRun or SDStop in Table 36: PDDS_SRD and RETDS_CD low-power mode control .

Section 6.7: Low-power modes:

• – Updated introduction.
• – Updated Section 6.7.2: Controlling peripheral clocks , Section 6.7.3: Entering low-power modes , Section 6.7.4: Exiting from low-power modes .
• – Renamed section Section 6.7.5 into System Run and CSleep modes and updated the whole section.
• – Suppressed Section CStop mode as well as DStop and DStop2 section.
• – Added Section 6.7.6: System Autonomous mode .
• – Updated Section 6.7.7: Stop mode and updated Table 46: GPIO state according to CPU and domain state .
• – Updated pin assignment for NDSTOP2 in Table 45: Overview of low-power mode monitoring pins .

Updated MONEN bit description in PWR control register 2 (PWR_CR2) .
Updated PDDS_SRD and RETDS_CD bit description in PWR CPU control register (PWR_CPUCR) .

Section 7: Low-power SRD domain application example

Changed section title.

Updated Figure 40: EXTI, RCC and PWR interconnections .

Updated Section 7.2.2: Block interactions , Section 7.3.1: Memory retention , Section 7.3.2: Memory-to-peripheral transfer using LPUART1 interface and Section 7.3.3: Overall description of the low-power application example based on LPUART1 transmission .

Section 8: Reset and clock control (RCC)

Changed SWP into SWPMI and IOMNGR into OCTOSPIM in the whole section including in the corresponding register bit names.

Renamed all HDMICECxxx bit registers into CECxxx. Changed the following internal clock signal names:

• – pclk into rcc_pclk1 and APB clock by rcc_pclk2.
• – KCK_FMC into fmc_ker_ck.
• – ADCx_CK
  • – into adc_ker_ck.
• – UCLK
  • – into usart_ker_ck
• – clk_cec into cec_ker_ck
• – I2CCLK into i2c_ker_ck
• – SPDIFRX_CLK into spdifrx_ker_ck
• – com_clk into spi_ker_ck
• – clk_lpt into lptim_ker_ck
• – fdcan_ck into fdcan_ker_ck
• – SWPCLK into swpmi_ker_ck
• – SAI_CK_A/B into sai_a_ker_ck/sai_b_ker_ck.

Updated Figure 55: Kernel clock distribution for SAIs, DFSDMs and SPDIFRX , Figure 56: Kernel clock distribution for SPIs and SPI/I2S , Figure 57: Kernel clock distribution for I2Cs , Figure 58: Kernel clock distribution for UARTs, USARTs and LPUART1 , Figure 59: Kernel clock distribution for LTDC , Figure 60: Kernel clock distribution for SDMMC, OCTOSPI and FMC , Figure 61: Kernel clock distribution for USB (2) , Figure 62: Kernel clock distribution for ADCs, SWPMI, RNG and FDCANs and Figure 63: Kernel clock distribution for LPTIMs and HDMI-CEC (2) .

Updated Section : Restart from system Stop and Section : Restart from system Autonomous mode with CPU domain in DStop/DStop2 .

Updated Section 8.5.9: General clock concept overview . Added Autonomous state in Table 59: System states overview

Updated LTDCEN bit description in RCC APB3 clock register (RCC_APB3ENR) .

Section 12: System configuration controller (SYSCFG)

Changed maximum voltage to 2.7 V in Section 12.3.5: I/O speed in low-voltage mode . Replaced VDD_HSLV by VDIOD_HSLV and changed 2.5 V to 2.7 V for all HSLVx bits in SYSCFG compensation cell control/status register (SYSCFG_CCCSR) .

Section 15: Direct memory access controller (DMA)

Changed bit 20 of DMA stream x configuration register (DMA_SxCR) from Reserved to TRBUFF.

Section 21: Chrom-GRC (GFXMMU)
Updated Section 21.3.1: Virtual memory .

Section 35: Parallel synchronous slave interface (PSSI)
Updated Figure 269: PSSI block diagram and Figure 270: Top-level block diagram .

Section 23: Flexible memory controller (FMC)
Updated Section : General transaction rules to clarify the behavior of the FMC when AXI transaction data size is different from the device data width and add the case of unaligned addresses.

Section 24: Octo-SPI interface (OCTOSPI)
Updated Section 24.3: OCTOSPI implementation .
Updated EN bit description in Section 24.7.1: OCTOSPI control register (OCTOSPI_CR) .

Section 27: Analog-to-digital converters (ADC)
Updated Section : ADC overrun (OVR, OVRMOD) . Added case of FIFO overflow in Section : Managing conversions without using the DMA and without overrun .
Suppressed asynchronous clock delay calibration capability and well as ADC_CALCLKR register.

Section 36: LCD-TFT display controller (LTDC)
Updated Figure 276: LTDC block diagram .
Added Section 36.3.2: LTDC pins and internal signals . Updated Figure 278: Layer window programmable parameters .

Section 39: Cryptographic processor (CRYP)
Removed reference to STM32 cryptographic library from Section 39.1: Introduction .
Support for single and burst transfers updated in Section 39.2: CRYP main features .
Added Section 39.3: CRYP implementation .
Extended the following sections to DES and TDES: Section : DES/TDES keying and chaining modes and transfer size in Table 296: Cryptographic processor configuration for memory-to-peripheral DMA transfers , Table 297: Cryptographic processor configuration for peripheral-to-memory DMA transfers .
Updated Section 39.5: CRYP interrupts , CRYP_K0LR/K0RR, CRYP_K1LR/K1RR, CRYP_K2LR/K2RR and CRYP_K3LR/K3RR registers.

Section 40: Hash processor (HASH)
Updated hash computation sequence in Section 40.4.5: Message digest computing .
Updated HMAC processing sequence in Section : HMAC processing .
Updated LKEY bit description and changed INIT bit to “rw” in HASH_CR.

Section 42: Advanced-control timers (TIM1/TIM8)
Updated Figure 346: Capture/compare channel 1 main circuit .
Replaced ECC error by Double ECC error when applicable, including in Figure 360: Break and Break2 circuitry overview .
Updated Section 42.4.1: TIMx control register 1 (TIMx_CR1)(x = 1, 8) , Section 42.4.2: TIMx control register 2 (TIMx_CR2)(x = 1, 8) , Section 42.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) , Section 42.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) and Section 42.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) . Updated Table 314: Output control bits for complementary OCx and OCxN channels with break feature . Updated Section 42.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) .
Updated BKINP in Section 42.4.26: TIM1 alternate function option register 1 (TIM1_AF1) , BK2INP in Section 42.4.27: TIM1 Alternate function register 2 (TIM1_AF2) , and BKCMP1P/BKCMP2P bit in Section 42.4.28: TIM8 Alternate function option register 1 (TIM8_AF1) .

Section 43: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Updated Figure 377: General-purpose timer block diagram , Figure 403: Capture/Compare channel 1 main circuit and Figure 404: Output stage of Capture/Compare channel (channel 1) .
Updated Section 43.3.19: Timer synchronization .
Added Figure 421: Master/slave connection example with 1 channel only timers .
Updated Section 43.4.2: TIMx control register 2 (TIMx_CR2)(x = 2 to 5) , Section 43.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) and Section 43.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) . Updated Table 319: Output control bit for standard OCx channels .

Section 44: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 428: General-purpose timer block diagram (TIM13/TIM14) . Updated Figure 441: Capture/compare channel 1 main circuit .
Updated Figure 442: Output stage of capture/compare channel (channel 1) . updated Section 44.3.6: PWM input mode (only for TIM12) .
updated Section 44.3.12: Retriggerable one pulse mode (TIM12 only) title.
Added Section 44.3.18: Using timer output as trigger for other timers (TIM13/TIM14) .
Updated Section 44.4.2: TIM12 control register 2 (TIM12_CR2) .
Updated Section 44.4.8: TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) .
Updated Table 322: Output control bit for standard OCx channels . Updated Section 44.5.6: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 13 to 14) .
Updated Table 324: Output control bit for standard OCx channels .
Updated Section 44.5.5: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 13 to 14) .

Section 45: General-purpose timers (TIM15/TIM16/TIM17)

Updated Figure 454: TIM16/TIM17 block diagram , Figure 468: Capture/compare channel 1 main circuit , Figure 469: Output stage of capture/compare channel (channel 1) , Figure 470: Output stage of capture/compare channel (channel 2 for TIM15) .

Updated Section 45.4.7: PWM input mode (only for TIM15) .

Updated Section 45.4.17: Retriggerable one pulse mode (TIM15 only) title.

Updated Table 328: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) .

Added Section 45.4.24: Using timer output as trigger for other timers (TIM16/TIM17) .

Updated Section 45.4.24: Using timer output as trigger for other timers (TIM16/TIM17) , Section 45.4.24: Using timer output as trigger for other timers (TIM16/TIM17) and Table 331: TIM16/TIM17 register map and reset values .

Section 47: Low-power timer (LPTIM)

Updated Section 47.7.4: LPTIM configuration register (LPTIM_CFGR) .

Section 51: Tamper and backup registers (TAMP)

Updated Table 367: TAMP pins functionality over modes .

Section 55: Serial peripheral interface (SPI)

Updated Section 55.2: SPI main features , Section 55.3: SPI implementation and Section 55.4.2: SPI signals .

Updated Section 55.4.5: Standard multislave communication , Section 55.4.5: Standard multislave communication , Section 55.4.7: Slave select (SS) pin management , Section 55.4.8: Communication formats , Section 55.4.9: Configuration of SPI , Section 55.4.10: Procedure for enabling SPI and Section 55.4.11: SPI data transmission and reception procedures .

Updated Figure 595: Packing data in FIFO for transmission and reception

Updated Section 55.5.1: TI mode , Section 55.5.2: SPI error flags and Section 55.5.3: CRC computation .

Updated Section 55.10: I2S wakeup and interrupts .

Updated Section 55.11.1: SPI/I2S control register 1 (SPI_CR1) , Section 55.11.3: SPI configuration register 1 (SPI_CFG1) , Section 55.11.4: SPI configuration register 2 (SPI_CFG2) , Section 55.11.6: SPI/I2S status register (SPI_SR) , Section 55.11.8: SPI/I2S transmit data register (SPI_TXDR) , Section 55.11.8: SPI/I2S transmit data register (SPI_TXDR) , Section 55.11.10: SPI polynomial register (SPI_CRCPOLY) , Section 55.11.11: SPI transmitter CRC register (SPI_TXCRC) .

Updated Section 55.11.12: SPI receiver CRC register (SPI_RXCRC) and Section 55.11.13: SPI underrun data register (SPI_UDRDR) .

Section 58: Single wire protocol master interface (SWPMI)

Modified name of bit and register to select SWPMI in note below Figure 658: SWPMI block diagram .

Section 62: USB on-the-go high-speed (OTG_HS)

Updated Section 62.2.1: General features , Section 62.3: OTG_HS implementation and Section 62.4.3: OTG_HS core .

Updated Section 62.4.4: Embedded full-speed OTG PHY connected to OTG_HS .

Added Section 62.4.5: OTG detections .

Added/updated Figure 722: OTG_HS A-B device connection and Figure 723: OTG_HS peripheral-only connection .

Section 64: Debug infrastructure

Removed revision Y and added revision X in DBGMCU identity code register (DBGMCU_IDC) .

Section 2: Memory and bus architecture
Updated Section : Embedded bootloader .

Section 4: Embedded flash memory (FLASH)
Removed seven wait states from Table 16: FLASH recommended number of wait states and programming delay .

Section 6: Power control (PWR)
Updated Figure 20: System supply configurations for packages with SMPS .

Section 10: Hardware semaphore (HSEM)
Modified Table 69: HSEM internal input/output signals .
Updated Section 10.3.3: HSEM lock procedures, Section 10.3.4: HSEM write/read/read lock register address, Section 10.3.5: HSEM unlock procedures, Section 10.3.6: HSEM MASTERID semaphore clear and Section 10.3.7: HSEM interrupts .

Section 18: Chrom-ART Accelerator controller (DMA2D)
Updated Table 110: DMA2D internal input/output signals .

Section 24: Octo-SPI interface (OCTOSPI)
Extended CSHT timeout is not supported.
Updated all block diagrams. Renamed nCS and CS pin names into NCS, and nCLK into NCLK. Renamed DDR into DTR.
Renamed Status-polling into Automatic status-polling. Add Section 24.5: Address alignment and data number .
Renamed FSEL bit into MSEL and DQM bit into DMM in OCTOSPI_CR register.

Section 26: Delay block (DLYB)
Updated Section 26.3.4: Delay line length configuration procedure and Section 26.3.5: Output clock phase configuration procedure .

Section 39: Cryptographic processor (CRYP)
Updated Figure 286: AES-ECB mode overview, Figure 287: AES-CBC mode overview, Figure 288: AES-CTR mode overview, Figure 289: AES-GCM mode overview, Figure 290: AES-GMAC mode overview, Figure 291: AES-CCM mode overview, Figure 301: Message construction for the Counter mode, Figure 304: Message construction for the Galois/counter mode, Figure 305: Message construction for the Galois Message Authentication Code mode .
Updated Table 286: Counter mode initialization vector, Table 288: GCM mode IV registers initialization, Table 289: CCM mode IV registers initialization .
Updated Section 39.4.16: CRYP data registers and data swapping, Section 39.4.17: CRYP key registers, Section 39.4.18: CRYP initialization vector registers and Section 39.6: CRYP processing time .
Updated all CRYP_KxLR/RR and CRYP_IVxLR/RR register descriptions.

Section 55: Serial peripheral interface (SPI)
Updated Section 55.2: SPI main features , Table 408: STM32H7A3/7B3/7B0xx SPI features and Section 55.4.2: SPI signals .
Updated Section 55.4.5: Standard multislave communication , Section 55.4.7: Slave select (SS) pin management , Section 55.4.8: Communication formats , Section 55.4.9: Configuration of SPI , Section 55.4.10: Procedure for enabling SPI and Section 55.4.11: SPI data transmission and reception procedures .
Modified Figure 595: Packing data in FIFO for transmission and reception .
Updated Section 55.5.1: TI mode , Section 55.5.2: SPI error flags and Section 55.5.3: CRC computation .
Updated Section 55.7: SPI wakeup and interrupts .
Updated Section 55.11.1: SPI/I2S control register 1 (SPI_CR1) , Section 55.11.3: SPI configuration register 1 (SPI_CFG1) , Section 55.11.4: SPI configuration register 2 (SPI_CFG2) , Section 55.11.6: SPI/I2S status register (SPI_SR) , Section 55.11.8: SPI/I2S transmit data register (SPI_TXDR) , Section 55.11.9: SPI/I2S receive data register (SPI_RXDR) , Section 55.11.10: SPI polynomial register (SPI_CRCPOLY) , Section 55.11.11: SPI transmitter CRC register (SPI_TXCRC) , Section 55.11.12: SPI receiver CRC register (SPI_RXCRC) , Section 55.11.13: SPI underrun data register (SPI_UDRDR) , and Section 55.12: SPI register map and reset values .

Section 60: Secure digital input/output MultiMediaCard interface (SDMMC)
Updated Section : Data path and Section : Data FIFO

Section 61: Controller area network with flexible data rate (FDCAN)
Updated Section 61.5.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) .
Added Section 61.5.47: FDCAN register map and Section 61.6.19: FDCAN TT register map .

Section 62: USB on-the-go high-speed (OTG_HS)
Restored ODDFRM bit in OTG_HCCHARx registers.

Section 64: Debug infrastructure
Updated Section 64.5.1: System ROM tables .
Changed TDESIGNER[11:0] to TDESIGNER[10:0] in DP_TARGETSEL Debug port target identification register (DP_TARGETSEL) .
Updated IDCODE in Table 530: JTAG-DP data registers .
Updated reset value and revision in Access port identification register (AP_IDR) .
Updated Table 533: System ROM table 1 and Table 534: System ROM table 2 .
Modified Figure 768: APB-D CoreSight component topology .
Updated SYSROM CoreSight peripheral identity register 0 (SYSROM_PIDR0) and SYSROM CoreSight peripheral identity register 1 (SYSROM_PIDR1) . Added Table 536: System ROM table 2 register map and reset values .
Updated CTI CoreSight peripheral identity register 2 (CTI_PIDR2) and CSTF CoreSight peripheral identity register 2 (CSTF_PIDR2) .
Updated ETF RAM size register (ETF_RSZ) and ETF CoreSight peripheral identity register 2 (ETF_PIDR2) .

Section 64: Debug infrastructure (continued)

Updated TPIU supported port size register (TPIU_SUPPSIZE) , TPIU formatter and flush status register (TPIU_FFSR) and TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . Updated SWO CoreSight peripheral identity register 2 (SWO_PIDR2) . Updated DBGMCU configuration register (DBGMCU_CR) . Modified Table 547: Cortex-M7 CPU ROM table and Figure 772: Cortex-M7 CoreSight Topology . Updated CPU ROM CoreSight peripheral identity register 4 (M7_CPUROM_PIDR4) , CPU ROM CoreSight peripheral identity register 0 (M7_CPUROM_PIDR0) , CPU ROM CoreSight peripheral identity register 1 (M7_CPUROM_PIDR1) and PPB ROM CoreSight peripheral identity register 0 (M7_PPBROM_PIDR0) . Updated DWT CoreSight peripheral identity register 1 (M7_DWT_PIDR1) and DWT CoreSight peripheral identity register 2 (M7_DWT_PIDR2) . Updated ITM CoreSight peripheral identity register 2 (M7_ITM_PIDR2) . Updated FPB CoreSight peripheral identity register 0 (M7_FPB_PIDR0) and FPB CoreSight peripheral identity register 2 (M7_FPB_PIDR2) . Updated ETM CoreSight peripheral identity register 2 (M7_ETM_PIDR2) .

Added errata sheet in the list of reference documents as well as mention that patents apply to the microcontrollers on document cover page.

Section 4: Embedded flash memory (FLASH)

Section : Erase operation overview : removed mention that bank 2 can be erased by ST secure firmware; added note related to the case where data cache is enabled after erase operations.

Changed reset value of FLASH_OPTSR bit 26 and 28 to X in Table 21: Option byte organization .

Added note providing non-secure Flash area start address in SEC_AREA_END1 of Section 4.9.13: FLASH secure address for bank 1 (FLASH_SCAR_CUR1) . Added formula to deduce bank 1/2 fail address from FAIL_ECC_ADDR1/2 in Section 4.9.23: FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) and Section 4.9.39: FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) , respectively.

Section 6: Power control (PWR)

Moved LSI from Backup to VDD domain in Figure 19: Power supply overview .

Section 8: Reset and clock control (RCC)

Updated Figure 50: HSI calibration flow and Figure 55: Kernel clock distribution for SAIs, DFSDMs and SPDIFRX .

Section 11: General-purpose I/Os (GPIO)

Changed default configuration at reset from 00 to 11 in Section 11.4.1: GPIO port mode register (GPIOx_MODER) (x =A to K).

Section 24: Octo-SPI interface (OCTOSPI)

Renamed MSEL bit into FSEL in Updated Section 24.7.1: OCTOSPI control register (OCTOSPI_CR) .

Section 25: OCTOSPI I/O manager (OCTOSPIM)
Added Table 184: OCTOSPIM implementation . Updated Section 25.4.4: OCTOSPIM multiplexed mode .

Section 28: Digital temperature sensor (DTS)
Changed definition of TS1_T0[1:0]=01 in Section 28.6.2: Temperature sensor T0 value register 1 (DTS_T0VALR1) .

Section 29: Digital-to-analog converter (DAC)
Updated transfer function formula in Section 29.4.13: Dual DAC channel conversion modes (if dual channels are available) .

Section 38: True random number generator (RNG)
Updated Section 38.5: RNG processing time .

Section 47: Low-power timer (LPTIM)
Updated Section 47.2: LPTIM main features and Section 47.4.4: LPTIM reset and clocks .
Added note to Section 47.4.7: Trigger multiplexer .

Section 50: Real-time clock (RTC)
Updated Section 50.3.13: RTC smooth digital calibration .
Updated Section 50.6.4: RTC initialization control and status register (RTC_ICSR) and Section 50.6.20: RTC status clear register (RTC_SCR)

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Renamed SCLK pin to CK in the whole document.
Added wakeup from Stop in Section 53.2: USART main features . Added Section 53.6: USART in low-power modes .
Updated Section 53.7: USART interrupts .
Updated ADD[7:0] bitfield descriptions in Section 53.8.3: USART control register 2 (USART_CR2) .
Updated ABRREQ bit description in Section 53.8.8: USART request register (USART_RQR) .
Updated ABRE and EOBF bit descriptions of Section 53.8.9: USART interrupt and status register (USART_ISR) .

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Renamed SCLK pin to CK in the whole document.
Updated Table 401: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz .
Added Section 54.5: LPUART in low-power modes . Updated Section 54.6: LPUART interrupts .
Updated ADD[7:0] bitfield descriptions in Section 54.7.3: LPUART control register 2 (LPUART_CR2) .
Updated ABRE bit descriptions of Section 54.7.7: LPUART interrupt and status register (LPUART_ISR) .

Section 56: Serial audio interface (SAI)
Added reference to implementation section in Section 56.4.10: PDM interface .
In Section 56.4.12: SPDIF output , replaced FSAI_CK_x by FsaI_x_ker_ck in the bit rate formula; added note 2 in Table 423: TDM frame configuration examples .
Added note related to bitfield usage depending on Dx line availability in Section 56.6.19: SAI PDM delay register (SAI_PDMPLY) .

Section 57: SPDIF receiver interface (SPDIFRX)
Added note in about RCC capabilities in Table 432: Minimum spdifrx_ker_ck frequency versus audio sampling rate .

Section 62: USB on-the-go high-speed (OTG_HS)
Updated access types for:
REMWAKE + BESL[3:0] in Section 62.14.17: OTG core LPM configuration register (OTG_GLPMCFG) ,
STALL in Section 62.14.64: OTG device OUT endpoint x control register (OTG_DOEPCTLx) and
RXDPID(r) / TUPCNT[1:0] in Section 62.14.66: OTG power and clock gating control register (OTG_PCGCCTL) .

Section 2: Memory and bus architecture
Added Table 6: Memory map and default device memory area attributes in Section 2.3.2: Memory map and register boundary addresses .

Section 4: Embedded flash memory (FLASH)
Updated Table 26: Effect of low-power modes on the embedded flash memory .

Section 6: Power control (PWR)
Updated Section : Startup with V _CORE provided from an external supply (Bypass) and added Section : How to exit from Run* mode .
Modified PWR SmartRun domain control register (PWR_SRDCR) reset value.

Section 17: DMA request multiplexer (DMAMUX)
Updated Table 102: DMAMUX1: assignment of trigger inputs to resources and Table 103: DMAMUX1: assignment of synchronization inputs to resources .

Section 22: Cyclic redundancy check calculation unit (CRC)
Renamed GPDR bits names to IDR bits in CRC independent data register (CRC_IDR) .

Section 24: Octo-SPI interface (OCTOSPI)
Updated Figure 136: OCTOSPI block diagram in octal configuration , Figure 137: OCTOSPI block diagram in quad configuration and Figure 138: OCTOSPI block diagram in dual-quad configuration .
Updated Section 24.4.4: OCTOSPI regular-command protocol , Section 24.4.6: HyperBus protocol , Section : Memory-mapped mode configuration and Section 24.4.20: NCS behavior .
Updated description of FRCK in OCTOSPI device configuration register 1 (OCTOSPI_DCR1) and REFRESH[31:0] in OCTOSPI device configuration register 4 (OCTOSPI_DCR4) .

Section 25: OCTOSPI I/O manager (OCTOSPIM)
Renamed OCTOSPIn_nCS signal into OCTOSPIn_NCS in the whole section. Updated Figure 155: OCTOSPIM block diagram , Section 25.1: Introduction , Section 25.2: OCTOSPIM main features , Section 25.3: OCTOSPIM implementation , Section 25.4.3: OCTOSPIM matrix and Section 25.4.4: OCTOSPIM multiplexed mode .

Section 27: Analog-to-digital converters (ADC)
Remove ADC supply requirements from Table 191: ADC input/output pins . Added Section : Constraints between ADC clocks .
Replaced ADCx_CCR by ADCx_CDR in Section : Regular simultaneous mode with independent injected .
Updated Figure 190: Example of overrun (OVRMOD = 0) , Figure 196: AUTDLY=1 in auto- injected mode (JAUTO=1) , Figure 205: Regular and injected oversampling modes used simultaneously , and Figure 206: Triggered regular oversampling with injection .
Update maximum junction temperature to 125 °C in Section 27.4.33: Temperature sensor . Section 27.4.33: Temperature sensor , updated temperature calculation formula in Section : Reading the temperature .

Section 28: Digital temperature sensor (DTS)
Modified Figure 227: Temperature sensor functional block diagram .
Updated signal names to which ts1_trg0 to 3 are connected in Table 212: Trigger configuration .
Updated TS1_LITTHD[15:0] bitfield description in Temperature sensor interrupt threshold register 1 (DTS_ITR1) .

Section 29: Digital-to-analog converter (DAC)
Added VREF+ pin availability in Table 29.2: DAC main features .

Section 30: Voltage reference buffer (VREFBUF)
Updated Section 30.2: VREFBUF functional description .

Section 33: Digital filter for sigma delta modulators (DFSDM)
Updated Table 247: DFSDM triggers connection .

Section 38: True random number generator (RNG)
Modified step 3 of Section : Health checks . Updated Table 283: RNG configurations .

Section 42: Advanced-control timers (TIM1/TIM8)
Updated Figure 340: Control circuit in normal mode, internal clock divided by 1 . Added Note in Section 42.3.16: Using the break function .
Updated OC1PE in Section 42.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .

Section 43: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Renamed DBGMCU into DBG in Section 43.3.21: Debug mode .
Added Note to CC4DE bitfield in Section 43.4.4: TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) .

Section 44: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 439: Control circuit in external clock mode 1 .
Updated OC1PE in Section 44.4.8: TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) and Section 44.5.6: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 13 to 14).

Section 45: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 464: Control circuit in normal mode, internal clock divided by 1 .
Added Note in Section 45.4.13: Using the break function . Added Section 45.4.15: 6-step PWM generation .
Updated Section 45.5.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and Section 45.6.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17).

Section 52: Inter-integrated circuit (I2C) interface
Updated Figure 523: Transfer bus diagrams for I2C slave receiver (mandatory events only) .

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Replaced nCTS and nRTS by CTS and RTS in the whole section.

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Replaced nCTS and nRTS by CTS and RTS in the whole section.

Section 57: SPDIF receiver interface (SPDIFRX)
Updated Section 57.3: SPDIFRX functional description including Figure 640: SPDIFRX block diagram , Figure 645: SPDIFRX decoder , and Figure 646: Noise filtering and edge detection . Modified SPDIFRX control register (SPDIFRX_CR) .

Section 61: Controller area network with flexible data rate (FDCAN)
Replaced Host with user throughout the whole document.
Updated Section : Operating conditions , Section : Clock calibration bypassed , Section : Software calibration , Section : Clock calibration active and Calibration configuration register (FDCAN_CCU_CCFG) .

Section 62: USB on-the-go high-speed (OTG_HS)
Removed Table TRDT values for FS mode (not supported).

Section 2: Memory and bus architecture
Updated Table 6: Memory map and default device memory area attributes .

Section 5: Secure memory management (SMM)
Added introduction to RSSS in Section 5.4: Root secure services (RSS) .

Section 6: Power control (PWR)
Added note to bits 7 to 0 of PWR control register 3 (PWR_CR3) .
Added note to bits 15:14 of PWR SmartRun domain control register (PWR_SRDCR) .

Section 24: Octo-SPI interface (OCTOSPI)
Added new note after Figure 141 , Figure 142 , and Figure 143 . Updated Quad-SPI mode , and Octal-SPI mode .
Updated note at the beginning of Section 24.4.11: OCTOSPI memory-mapped mode .
Updated Table 181: Address alignment cases .
Updated DEVSIZE description in OCTOSPI device configuration register 1 (OCTOSPI_DCR1) and REFRESH description in OCTOSPI device configuration register 4 (OCTOSPI_DCR4) .

Section 2: Memory and bus architecture
In Section 2.6: Boot configuration , updated system bootloader address in Table 8: Boot modes .

Section 8: Reset and clock control (RCC)
Updated debug clock and signals in Figure 47: Top-level clock tree .
Renamed traceclk into traceportclk in SW[2:0] of RCC clock configuration register (RCC_CFGR) .

Section 18: Chrom-Art Accelerator controller (DMA2D)
Updated maximum number of color formats to 12 in Section 18.2: DMA2D main features . Updated Section 18.3.1: General description .
Updated list of DMA2D modes in Section 18.3.13: DMA2D configuration . Modified DMA2D output color register (DMA2D_OCOLR) and added alternate descriptions.

Section 21: Chrom-GRC (GFXMMU)
Updated Section : Master accessing the GFXMMU .

Section 25: OCTOSPI I/O manager (OCTOSPIM)
Added Section 25.4.2: OCTOSPIM input/output pins .

Section 27: Analog-to-digital converters (ADC)
Updated formula to calculate the temperature in Section : Reading the temperature .

Section 37: JPEG codec (JPEG)
Added JPEG Huffman min x [alternate] (JPEG_HUFFMINx_y)

Section 39: Cryptographic processor (CRYP)
Added GCM/CCM hardware padding capability in Section : Appending data using the CPU in Polling mode , Section : Appending data using the CPU in Interrupt mode and Section : Appending data using the DMA , as well as NPBLB[3:0] bitfield in CRYP control register (CRYP_CR) .
Updated step 1 of the key preparation sequence in Section 39.4.7: Preparing the CRYP AES key for decryption .
Updated KERF description in Section 39.7.2: CRYP status register (CRYP_SR) .
Updated Section 39.7.5: CRYP DMA control register (CRYP_DMACR) , Section 39.7.8: CRYP masked interrupt status register (CRYP_MISR) .
Renamed IV bitfields of CRYP initialization vector register 0L (CRYP_IV0LR) / CRYP initialization vector register 0R (CRYP_IV0RR) and CRYP initialization vector register 1L (CRYP_IV1LR) / CRYP initialization vector register 1R (CRYP_IV1RR) to IV1. In the whole document, renamed CRPY_IVxR and CRPY_IVxL into CRPY_IVxRR and CRPY_IVxLR, respectively.

Section 38: True random number generator (RNG)
Updated Section 38.5: RNG processing time .
Modified CONFIGLOCK bit description in RNG control register (RNG_CR) .

Section 51: Tamper and backup registers (TAMP)
Updated Section 51.6.1: TAMP control register 1 (TAMP_CR1) .

Section 52: Inter-integrated circuit (I2C) interface
Updated Hardware transfer management .
Updated Figure 523: Transfer bus diagrams for I2C slave receiver (mandatory events only) , Figure 520: Transfer bus diagrams for I2C slave transmitter (mandatory events only) , Figure 530: Transfer bus diagrams for I2C master transmitter (mandatory events only) , and Figure 533: Transfer bus diagrams for I2C master receiver (mandatory events only) .

Section 57: SPDIF receiver interface (SPDIFRX)
Updated Section 57.3: SPDIFRX functional description .

Section 60: Secure digital input/output MultiMediaCard interface (SDMMC) Updated Section : Data FIFO , Section : Stream operation and CMD12 , Section : Block operation and CMD12 , Section : Normal boot operation , and Section : Alternative boot operation .
Added footnote to Table 448: SDMMC operation modes e•MMC .

Section 64: Debug infrastructure
Renamed TRACECK into TRACECLK in Figure 762: Block diagram of debug infrastructure , Figure 763: Power domains of debug infrastructure , Figure 64.5.5: Trace port interface unit (TPIU) and TRACECLKEN bit description of DBGMCU configuration register (DBGMCU_CR) . Updated Section : Clock domains .
Replaced TRACECLKIN by TRACEPORTCK in TPIU test pattern repeat counter register (TPIU_TPRCR) , TPIU device configuration register (TPIU_DEVID) and SWO device configuration register (SWO_DEVID) .
Changed TRACEPORTCK division factor to PRESCALER+1 in PRESCALER[12:0] of SWO current output divisor register (SWO_CODR) . Added Section 66: Important security notice .

Section 3: RAM ECC monitoring (RAMECC)
Added note referring to AN5342 in Section 3.1: Introduction .

Section 4: Embedded flash memory (FLASH)
Corrected number of wait states corresponding to LATENCY = 0111 in FLASH access control register (FLASH_ACR) .

Section 5: Secure memory management (SMM)
In Section 5.5.2: Setting secure user memory areas , replaced exitAndInitializeSecureAreas service by resetAndInitializeSecureAreas .

Section 8: Reset and clock control (RCC)
In RCC PLLs clock source selection register (RCC_PLLCKSELR) removed indication of default value after reset for DIVM3[5:0] = 000000.

Section 9: Clock recovery system (CRS)
Updated Figure 68: CRS block diagram . Updated CRS control register (CRS_CR) .

Section 21: Chrom-GRC (GFXMMU)
Updated Section : Block offset address calculation within the buffer .

Section 23: Flexible memory controller (FMC)
SDRAM Timing registers for SDRAM memory bank x (FMC_SDTRx) : corrected formula in TWR[3:0] bitfield, updated number of SDRAM clock cycles in COUNT bitfield.
Updated SRAM/NOR-flash chip-select control registers for bank x (FMC_BCRx) and Common memory space timing register (FMC_PMEM) address offset.

Section 24: Octo-SPI interface (OCTOSPI)
Updated Section 24.1: Introduction and Section 24.3: OCTOSPI implementation ; added Section 24.4.2: OCTOSPI pins and internal signals . Updated Section : Instruction phase .
Updated Section 24.4.5: OCTOSPI regular-command protocol signal interface .
In Section : Wrap support , added note related to the interruption of wrap operations by refresh.
Updated Section : Triggering the start of a transfer in HyperBus protocol and Section 24.4.10: OCTOSPI automatic status-polling mode . In Section 24.4.11: OCTOSPI memory-mapped mode , added note concerning flash memory programming using the memory-mapped write.
Updated Section 24.4.14: OCTOSPI device configuration , removed section Automatic status-polling mode configuration (HyperBus) , updated Section : Memory-mapped mode configuration (HyperBus) , Section 24.4.17: OCTOSPI error management , Section 24.4.18: OCTOSPI BUSY and ABORT , and Table 181: Address alignment cases .
Updated OCTOSPI address register (OCTOSPI_AR) and OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR) .

Section 27: Analog-to-digital converters (ADC)
Updated Section : I/O analog switch voltage booster .
Changed JQSR into JSQR in Figure 170: Example of JSQR queue of context (sequence change) , Figure 171: Example of JSQR queue of context (trigger change) , Figure 172: Example of JSQR queue of context with overflow before conversion , Figure 173: Example of JSQR queue of context with overflow during conversion , Figure 174: Example of JSQR queue of context with empty queue (case JQM=0) and Figure 175: Example of JSQR queue of context with empty queue (case JQM=1) .

Section 28: Digital temperature sensor (DTS)
Updated Figure 227: Temperature sensor functional block diagram to make it generic for ts1_trgx internal signals.
Removed typ. frequency from Section 28.3.7: Temperature measurement principles .
Updated TS1_SMP_TIME[3:0] description in Temperature sensor configuration register 1 (DTS_CFGR1) .

Section 29: Digital-to-analog converter (DAC)
In Figure 231: Dual-channel DAC block diagram , changed OTRIMx[5:0] into OTRIMx[4:0] (5 trimming bits only).

Section 35: Parallel synchronous slave interface (PSSI)
Updated Section 35.2: PSSI main features , Figure 269: PSSI block diagram , Figure 270: Top-level block diagram , and Table 265: PSSI input/output pins .

Section 37: JPEG codec (JPEG)
Updated JPEG Huffman min x (JPEG_HUFFMINx_y) , and JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) ,

Section 42: Advanced-control timers (TIM1/TIM8)
Updated Section 42.3.18: Clearing the OCxREF signal on an external event . Updated second bullet in Section 42.3.22: Encoder interface mode .
Updated Figure 368: Retriggerable one pulse mode .
Updated OC1M[3:0] in TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .
Replaced BKIN by BRK in BKE bit description in TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) .

Section 43: General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Updated title of Figure 390: Counter timing diagram, Update event .
Updated Section 43.3.12: Clearing the OCxREF signal on an external event . Updated Figure 413: Retriggerable one-pulse mode..
Updated OC1M[3:0] in TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) .

Section 44: General-purpose timers (TIM12/TIM13/TIM14)
Updated Figure 448: Retriggerable one pulse mode .
Updated OC1M[3:0] in TIM12 capture/compare mode register 1 [alternate] (TIM12_CCMR1) and TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 13 to 14).

Section 45: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 483: Retriggerable one pulse mode .
Updated OC1M[3:0] in TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17).

Section 48: System window watchdog (WWDG)
Updated Section 48.4: WWDG interrupts .
Modified EWI bit description in WWDG configuration register (WWDG_CFR) .

Section 47: Low-power timer (LPTIM)
Updated Section 47.7: LPTIM registers introduction .

Section 52: Inter-integrated circuit (I2C) interface
Updated Section : I2C timings .
Removed note related to from I2C timeout register (I2C_TIMEOUTR) and I2C interrupt and status register (I2C_ISR) , I2C interrupt clear register (I2C_ICR) and I2C PEC register (I2C_PECR) .

Section 55: Serial peripheral interface (SPI)
Added note on 24- and 32-bit data width availability in Section 55.2: SPI main features , Section 55.8: I2S main features , Section 55.9.5: Supported audio protocols , below Figure 600: Master I2S Philips protocol waveforms (16/32-bit full accuracy) , Figure 601: I2S Philips standard waveforms , Figure 602: Master MSB Justified 16-bit or 32-bit full-accuracy length , Figure 603: Master MSB justified 16 or 24-bit data length , Figure 604: Slave MSB justified , Figure 605: LSB justified 16 or 24-bit data length , Figure 607: Master PCM standard waveforms (16 or 24-bit data length) , and Section 55.9.10: Internal FIFOs .
Updated MCK description in Section 55.8: I2S main features and Section 55.9.2: Pin sharing with SPI function .
Updated Table 410: Bitfields usable in PCM/I2S mode .
Updated Figure 599: Waveform examples and added note below figure.
Updated Figure 608: Slave PCM waveforms and added note on 24- and 32-bit data width availability below the figure.
Updated note related to AFCNTR bit in Section : Control of the I/Os
Updated Section 55.9.7: Startup sequence , Section 55.9.9: Clock generator , Section 55.9.12: Handling of underrun situation , and Section 55.9.13: Handling of overrun situation .
Suppressed section Master I2S MSB Aligned, full-duplex . Updated Slave I2S Philips standard, receive procedure.
Updated CSUSP bit of SPI/I2S control register 1 (SPI_CR1) ; UDR bit of SPI/I2S status register (SPI_SR) ; WSINV, CHLEN and DATLEN[1:0] of SPI/I2S configuration register (SPI_I2SCFGR) .

Section 56: Serial audio interface (SAI)
Updated and swapped notes 1 and 2 below Figure 626: Detailed PDM interface block diagram and changed note (1) to (2).

Section 61: Controller area network with flexible data rate (FDCAN)
Updated FDCAN data bit timing and prescaler register (FDCAN_DBTP) .

Section 4: Embedded flash memory (FLASH)
Updated the PRG and CUR values in Table 20: Flash register map vs swapping option .

Section 9: Clock recovery system (CRS)
Updated the shutdown mode in Section 9.6: CRS low-power modes .

Section 23: Flexible memory controller (FMC)
Updated the address offset in FMC_BTRx, FMC_BWTRx and FMC_BSCRx.

Section 24: Octo-SPI interface (OCTOSPI)
General update of this section.

Section 27: Analog-to-digital converters (ADC)
Updated Section 27.4.10: Constraints when writing the ADC control bits

Section 34: Digital camera interface (DCMI)
Updated limitation information.

Section 45: General-purpose timers (TIM15/TIM16/TIM17)
Updated Section 45.5.3: TIM15 slave mode control register (TIM15_SMCR) . Replaced BKDFBK1E by BKDF1BK1E in Section 45.6.17: TIM16 alternate function register 1 (TIM16_AF1) .
Updated Section 45.4.13: Using the break function

Section 49: Independent watchdog (IWDG)
Updated Figure 508: Independent watchdog block diagram . Updated Section 49.4.4: IWDG status register (IWDG_SR) .

Section 50: Real-time clock (RTC)
Updated the note in Section 51.6.8: TAMP status register (TAMP_SR) .
Added a note in Section 51.6.9: TAMP masked interrupt status register (TAMP_MISR) .
Updated Section 50.3.4: Clock and prescalers .

Section 52: Inter-integrated circuit (I2C) interface
Updated Section 52.7.2: I2C control register 2 (I2C_CR2) , Section 52.7.6: I2C timeout register (I2C_TIMEOUTR) , Section 52.7.7: I2C interrupt and status register (I2C_ISR) , Section 52.7.8: I2C interrupt clear register (I2C_ICR) , and Section 52.7.9: I2C PEC register (I2C_PECR) .

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Added tables Section Table 389.: USART/UART input/output pins , and Section Table 390.: USART internal input/output signals .
Added a note relating to prescaler support to PRESCALER[3:0] of USART_PRESC.

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Updated tables Section Table 399.: LPUART input/output pins and Section Table 400.: LPUART internal input/output signals .
Added a note relating to prescaler support to PRESCALER[3:0] of LPUART_PRESC.
Removed CK and NSS signals from Figure 542: USART block diagram .

Section 55: Serial peripheral interface (SPI)
Updated the Rx/Tx FIFO feature in Section 55.2: SPI main features
Updated Section 55.5.3: CRC computation
Changed FTHVL into FTHLV in Figure 598: Low-power mode application example .

Section 56: Serial audio interface (SAI)
Reorganized register sections by address offset.

Section 61: Controller area network with flexible data rate (FDCAN)
Updated Figure 706: Transceiver delay measurement .

Section 64: Debug infrastructure
Updated the M7_FPB_CTRL and M7_FPB_COMPx registers, and removed the M7_FPB_REMAP register in Section 64.6.4: Cortex-M7 breakpoint unit (FPB) .
Updated Table 553: Cortex-M7 FPB register map and reset values .

Minor terminology updates were applied to this document.

Section 1: Documentation conventions
Added Section 1.3: Register reset value .

Section 2: Memory and bus architecture
Updated AXI interconnect - INI x AHB functionality modification register (AXI_INIx_FN_MOD_AHB) .

Section 4: Embedded flash memory (FLASH)
Added special region (read-only area and OTP area) in Table 14: Flash memory organization (STM32H7B0 devices) and Table 15: Flash memory organization (STM32H7A3xG devices) .
Step 1 is not more optional for Flash sector erase sequence , Standard flash bank erase sequence , Flash bank erase with automatic protection-removal sequence , and Flash mass erase sequence .
Updated Table 27: Flash interrupt request

Section 6: Power control (PWR)
Updated PWR wake-up clear register (PWR_WKUPCR) and PWR wake-up flag register (PWR_WKUPFR) .

Section 8: Reset and clock control (RCC)
Updated register offset for RCC_RSR to RCC_APB4LPENR registers.
Removed reference to debug mode in LSEBYP bit description of RCC Backup domain control register (RCC_BDCR) .

Section 9: Clock recovery system (CRS)
Updated Section 9.1: CRS introduction , Section 9.2: CRS main features , and Figure 68: CRS block diagram .
Updated Table 65: CRS internal input/output signals . Moved Table 66: CRS interconnection to Section 9.4.2: CRS internal signals and title updated.
Updated Section 9.4.3: Synchronization input and SYNCSRC[1:0] description in CRS configuration register (CRS_CFGR) .
Updated CRS control register (CRS_CR) reset value.

Section 11: General-purpose I/Os (GPIO)
Updated section Peripheral alternate function in Section 11.3.2: I/O pin alternate function multiplexer and mapping .

Section 15: Direct memory access controller (DMA)
Replaced DMIE by DMEIE in Section 15.3.20: Error management .

Section 23: Flexible memory controller (FMC)
Updated Figure 123: Asynchronous wait during a write access waveforms , Figure 124: Wait configuration waveforms , Figure 125: Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) , Figure 126: Synchronous multiplexed write mode waveforms - PSRAM (CRAM) , Figure 129: Burst write SDRAM access waveforms , Figure 130: Burst read SDRAM access , Figure 131: Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) , Figure 132: Read access crossing row boundary , and Figure 135: Power-down mode .
Added timing symbol names in SDRAM Timing registers for SDRAM memory bank x (FMC_SDTRx) .
Changed the bitfields CTB1, CTB2, and MODE[2:0] to "w" instead of "rw" in SDRAM Command mode register (FMC_SDCMR) .

Section 24: Octo-SPI interface (OCTOSPI)
Updated Section 24.4.11: OCTOSPI memory-mapped mode and Section : Memory types .
Updated FRCK bit description of OCTOSPI device configuration register 1 (OCTOSPI_DCR1) .

Section 27: Analog-to-digital converters (ADC)
Replaced SQRx and JSQRx by ADC_SQRY and ADC_JSQR registers, when referring to these registers. Replaced JSQRI and SQRI registers by JSQi and SQi bits, when referring to the bits.
Updated Figure 165: Analog-to-digital conversion time and Figure 215: Alternate trigger: 4 injected channels (each ADC) in discontinuous mode .

Section 29: Digital-to-analog converter (DAC)
Changed DHRx and DORx into DAC_DHRx and DAC_DORx when referring to registers.
Updated user trimming calibration procedure in Section 29.4.12: DAC channel buffer calibration .
Replaced dac_pclk by bus clock in Figure 238: DAC conversion (SW trigger enabled) with triangle wave generation .
Added Section 29.4.13: DAC channel conversion modes .
Updated Section 29.4.12: DAC channel buffer calibration .
Updated WAVE1 and WAVE2 bitfield descriptions in DAC control register (DAC_CR) .
Updated THOLD2[9:0] description in DAC sample and hold time register (DAC_SHHR) and TREFRESH2[7:0] description in DAC sample and hold refresh time register (DAC_SHRR) .

Section 38: True random number generator (RNG)
Updated Section : Noise source error detection .
Updated Section 38.5: RNG processing time .
Updated Table 286: RNG configurations and Table 285: RNG interrupt requests .

Section 40: Hash processor (HASH)
Moved HASH processing time to Section 40.4: HASH functional description .

Section 49: Independent watchdog (IWDG)
Updated Section 49.3.4: Hardware watchdog and Section 49.3.6: Register access protection .

Section 50: Real-time clock (RTC)
Updated Section : TAMPALRM output .

Section 51: Tamper and backup registers (TAMP)
Updated Table 370: Effect of low-power modes on TAMP .

Section 52: Inter-integrated circuit interface (I2C)
Minor improvement of the whole section.
Changed master and slave to controller and target, respectively.
Added Section 52.7: I2C DMA requests and Section 52.8: I2C debug modes .

Section 53: Universal synchronous/asynchronous receiver transmitter (USART/UART)
Updated CK description in Section : Description of USART input/output signals .
Updated Figure 546: Start bit detection when oversampling by 16 or 8 , Figure 562: Transmission using DMA , and Figure 563: Reception using DMA .

Section 54: Low-power universal asynchronous receiver transmitter (LPUART)
Updated Figure 576: Transmission using DMA and Figure 577: Reception using DMA .

Section 56: Serial audio interface (SAI)
Updated Section 56.4.2: SAI pins and internal signals , Section : Configuring and enabling SAI modes , Section 56.4.10: PDM interface .
Modified MUTEVAL bit descriptions in SAI configuration register 2 (SAI_ACR2) and SAI configuration register 2 (SAI_BCR2)

Section 61: Controller area network with flexible data rate (FDCAN)
Updated Table 477: CAN subsystem I/O signals .
Added Section 61.4.2: Error management .
Updated Section : Dedicated Tx buffers , Section : Tx FIFO , Section : Tx queue
Replaced EFT[1:0] by EFT[1:0] in Table 501: Extended message ID filter element .

Section 62: USB on-the-go high-speed (OTG_HS)
Updated Section 62.7: OTG_HS as a USB host .

Section 65: Device electronic signature
Updated Section 65.1: Unique device ID register (96 bits) .

SMM:
Added Section 5.4.1: Version service .
Updated Section 5.4.2: Secure area setting service .
Updated Section 5.4.3: Secure area exiting service .

CRS:
Updated Section 9.7.1: CRS control register (CRS_CR) .

GPIO:
Added note to Section 11.3.11: I/O compensation cell .

CRC:
Updated Section 22.3.3: CRC operation .

OCTOSPI:
Updated Section 24.3: OCTOSPI implementation .
Updated Section : Dual-SPI mode .
Updated Section 24.4.11: OCTOSPI memory-mapped mode .
Updated Section 24.4.17: OCTOSPI error management .
Updated Table 184: Address alignment cases .
Updated Section 24.7.1: OCTOSPI control register (OCTOSPI_CR) .
Updated Section 24.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1) .
Updated Section 24.7.6: OCTOSPI status register (OCTOSPI_SR) .
Updated Section 24.7.7: OCTOSPI flag clear register (OCTOSPI_FCR) .
Updated Section 24.7.27: OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR) .

ADC:
Updated Section 27.4.8: Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) .
Updated Section 27.6.4: ADC configuration register (ADC_CFGGR) .
Updated Section 27.7.2: ADC x common control register (ADCx_CCR) (x=1/2) .

DAC:
Updated Section 29.4.6: DAC output voltage .
Updated Section : Sample and hold mode .
Updated Section 29.4.13: DAC channel conversion modes .

CRYP:
Updated Section : Appending data using the DMA .

I2C:
Updated Figure 521: Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 .
Updated Section 52.9.4: I2C own address 2 register (I2C_OAR2) .

SPI:
Whole section edited.

SDMMC:
Updated Section 60.8: Ultra-high-speed phase I (UHS-I) voltage switch .

FDCAN:
Updated Table 477: CAN subsystem I/O signals .
Updated Figure 704: CAN subsystem .
Updated Figure 705: FDCAN block diagram .
Updated Section 61.4.2: Error management .
Updated Section : Operating conditions .
Updated Section 61.5.3: FDCAN data bit timing and prescaler register (FDCAN_DBTP) .
Updated Section 61.5.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) .
Updated Section 61.5.17: FDCAN interrupt line select register (FDCAN_ILS) .