20. Extended interrupt and event controller (EXTI)

The Extended Interrupt and event controller (EXTI) manages wakeup through configurable and direct event inputs. It provides wakeup requests to the power controller (PWR), and generates interrupt requests to the CPU NVIC and to the SRD domain DMAMUX2, and events to the CPU event input.

The EXTI wakeup requests allow the system to be woken up from Stop mode, and the CPU to be woken up from CStop mode.

In addition, both the interrupt request and event request generation can be used in Run mode.

20.1 EXTI main features

The EXTI main features are the following:

• • All event inputs allow the CPU to wake up and to generate a CPU interrupt and/or a CPU event
• • Some event inputs allow the user to wake up the SRD domain for Autonomous run mode and generate an interrupt to the SRD domain, i.e. the DMAMUX2

The asynchronous event inputs are classified in two groups:

• • Configurable events (signals from I/Os or peripherals able to generate a pulse), that have the following features:
  • – Selectable active trigger edge
  • – Interrupt pending status register bit
  • – Individual Interrupt and event generation mask
  • – Software trigger capability
  • – Configurable system SRD domain wakeup events.

They have an SRD pending mask and a status register, and may have an SRD interrupt signal.

• • Direct events (interrupt and wakeup sources from other peripherals, requiring to be cleared in the peripheral)

Direct events feature:

• – Fixed rising edge active trigger
• – No interrupt pending status register bit in the EXTI (the interrupt pending status is provided by the peripheral generating the event)
• – Individual interrupt and event generation mask
• – No software trigger capability
• – Direct system SRD domain wakeup events have an SRD pending mask and status register, and may have an SRD interrupt signal

20.2 EXTI block diagram

As shown in Figure 95 , the EXTI consists of a register block accessed via an APB interface, an event input trigger block, and a masking block.

The register block contains all EXTI registers.

The event input trigger block provides event input edge triggering logic.

The masking block provides the event input distribution to the different wakeup, interrupt and event outputs, as well as their masking.

Figure 95. EXTI block diagram

20.2.1 EXTI connections between peripherals, CPU and SRD domain

The peripherals able to generate wakeup events when the system is in Stop mode or the CPU is in CStop mode are connected to an EXTI configurable event input or direct event input:

• • Peripheral signals that generate a pulse are connected to an EXTI configurable event input. For these events, the EXTI provides a CPU status pending bit that has to be cleared.
• • Peripheral interrupt and wakeup sources that have to be cleared in the peripheral are connected to an EXTI direct event input. There is no CPU status pending bit within the EXTI. The Interrupt or Wakeup is cleared by the CPU in the peripheral.

The event inputs able to wakeup SRD for Autonomous run mode are provided with an SRD domain pending request function, that has to be cleared. This clearing request is taken care of by the signal selected by the pending clear selection.

The CPU interrupts are connected to their respective CPU NVIC. Similarly, the CPU event is connected to the CPU rxe input.

The EXTI wakeup signals are connected to the PWR block. They are used to wake up the SRD domain and/or the CPU.

The SRD domain interrupts allow the system to trigger events for SRD domain Autonomous run operations.

20.3 EXTI functional description

Different logic implementations can be used, depending on the EXTI event input type and wakeup target(s). The applicable features are controlled from register bits:

• Active trigger edge enable, by EXTI rising trigger selection register (EXTI_RTSR1) , EXTI rising trigger selection register (EXTI_RTSR2) , EXTI rising trigger selection register (EXTI_RTSR3) , and EXTI falling trigger selection register (EXTI_FTSR1) , EXTI falling trigger selection register (EXTI_FTSR2) , EXTI falling trigger selection register (EXTI_FTSR3)
• Software trigger, by EXTI software interrupt event register (EXTI_SWIER1) , EXTI software interrupt event register (EXTI_SWIER2) , EXTI software interrupt event register (EXTI_SWIER3)
• CPU Interrupt enable, by EXTI interrupt mask register (EXTI_CPUIMR1) , EXTI interrupt mask register (EXTI_CPUIMR2) , EXTI interrupt mask register (EXTI_CPUIMR3)
• CPU Event enable, by EXTI event mask register (EXTI_CPUEMR1) , EXTI event mask register (EXTI_CPUEMR2) , EXTI event mask register (EXTI_CPUEMR3)
• SRD domain wakeup pending, by EXTI SRD pending mask register (EXTI_SRDPMR1) , EXTI SRD pending mask register (EXTI_SRDPMR2) , EXTI SRD pending mask register (EXTI_SRDPMR3)

Table 126. EXTI event input configurations and register control ⁽¹⁾

1. X indicates that the functionality is available.

2. Waking up SRD domain for Autonomous run mode and/or CPU.

20.3.1 EXTI configurable event input CPU wakeup

Figure 97 provides a detailed representation of the logic associated to the configurable event inputs that always wake up the CPU.

Figure 96. Configurable event triggering logic CPU wakeup

The software interrupt event register allows the system to trigger configurable events by software, writing the EXTI software interrupt event register (EXTI_SWIER1) , the EXTI software interrupt event register (EXTI_SWIER2) , or the EXTI software interrupt event register (EXTI_SWIER3) register bit.

The rising edge EXTI rising trigger selection register (EXTI_RTSR1) , EXTI rising trigger selection register (EXTI_RTSR2) , EXTI rising trigger selection register (EXTI_RTSR3) , and falling edge EXTI falling trigger selection register (EXTI_FTSR1) , EXTI falling trigger selection register (EXTI_FTSR2) , EXTI falling trigger selection register (EXTI_FTSR3) selection registers allow the system to enable and select the configurable event active trigger edge or both edges.

The devices feature dedicated interrupt mask registers, namely EXTI interrupt mask register (EXTI_CPUIMR1) and EXTI interrupt mask register (EXTI_CPUIMR2) , EXTI interrupt mask register (EXTI_CPUIMR3) , and EXTI pending register (EXTI_CPUPR1) , EXTI pending register (EXTI_CPUPR2) , EXTI pending register (EXTI_CPUPR3) for configurable events pending request registers. The CPU pending register is only set for an unmasked CPU interrupt. Each event provides a individual CPU interrupt to the CPU NVIC. The configurable event interrupts need to be acknowledged by software in the EXTI_CPUPR register.

The devices feature dedicated event mask registers, i.e. EXTI event mask register (EXTI_C1EMR1) , EXTI event mask register (EXTI_C1EMR2) , and EXTI event mask register (EXTI_C1EMR3) . The enabled event then generates an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The CPU pending register (EXTI_CPUPR) is not set for an unmasked CPU event.

When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the CPU clock is woken up before the asynchronous edge detection circuit is reset.

Note: A detected configurable event, enabled by the CPU, is only cleared when the CPU wakes up.

20.3.2 EXTI configurable event input Any wakeup

Figure 97 provides a detailed description of the logic associated to the configurable event inputs that can wake up SRD domain for Autonomous run mode and/or CPU (“Any” target). It provides the same functionality as the configurable event input CPU wakeup, with additional functionality to wake up the SRD domain independently.

When all CPU interrupts and CPU events are disabled, the asynchronous edge detection circuit is reset by the SRD domain clocked delay and rising edge detect pulse generator. This guarantees that the SRD domain clock is woken up before the asynchronous edge detection circuit is reset.

Table 127. Configurable event input asynchronous edge detector reset

Figure 97. Configurable event triggering logic Any wakeup

The event triggering logic for “Any” target has additional SRD pending mask register EXTI SRD pending mask register (EXTI_SRDPMR1) , EXTI SRD pending mask register (EXTI_SRDPMR2) , EXTI SRD pending mask register (EXTI_SRDPMR3) and SRD pending request logic. The SRD pending request logic is only set for unmasked SRD pending events. The SRD pending request logic keeps the SRD domain in Run mode until the SRD pending request logic is cleared by the selected SRD domain pendclear source.

20.3.3 EXTI direct event input CPU wakeup

Figure 98 provides a detailed description of the logic associated with the direct event inputs that wake up the CPU.

Direct events only provide CPU interrupt enable and CPU event enable functionality.

Figure 98. Direct event triggering logic CPU wakeup

1. 1. The CPU interrupt for asynchronous direct event inputs (peripheral wakeup signals) is synchronized with the CPU clock. The synchronous direct event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt without resynchronization.

20.3.4 EXTI direct event input Any wakeup

Figure 99 provides a detailed description of the logic associated to the direct event inputs that wake up SRD domain for Autonomous run mode and/or CPU, (“Any” target). It provides the same functionality as the direct event input CPU wakeup, plus additional functionality to wakeup the SRD domain independently.

Figure 99. Direct event triggering logic Any wakeup

1. 1. The CPU interrupt and SRD domain interrupt for asynchronous direct event inputs (peripheral wakeup signals) are synchronized with the CPU clock and the SRD domain clock, respectively. The synchronous direct event inputs (peripheral interrupt signals), after the asynchronous edge detection, are directly sent to the CPU interrupt and the SRD domain interrupt without resynchronization in the EXTI.

20.3.5 EXTI SRD pending request clear selection

The SRD pending request logic of the event inputs that are able to wake up SRD domain for Autonomous run mode can be cleared by the selected SRD pendclear source.

For each SRD pending request, an SRD domain pendclear source can be selected from four different inputs.

Figure 100 provides a detailed description of the SRD pendclear source selection logic.

Figure 100. SRD domain pending request clear logic

The SRD pending request clear selection registers EXTI SRD pending clear selection register low (EXTI_SRDPCR1L) , EXTI SRD pending clear selection register high (EXTI_SRDPCR1H) , EXTI SRD pending clear selection register low (EXTI_SRDPCR2L) , EXTI SRD pending clear selection register high (EXTI_SRDPCR2H) and EXTI SRD pending clear selection register high (EXTI_SRDPCR3H) allow the system to select the source to reset the SRD pending request.

20.4 EXTI event input mapping

For the sixteen GPIO event inputs, the associated GPIO pin has to be selected in the SYSCFG_EXTICRn register. The same pin from each GPIO maps to the corresponding EXTI event input.

The wakeup capabilities of each event input are detailed in Table 128 . An event input can wake up the CPU, and in the case of “Any” can also wake up SRD domain for Autonomous run mode.

The EXTI event inputs that are connected to the CPU NVIC are indicated in the Connection to NVIC column. For the EXTI events that do not have a connection to the NVIC, the peripheral interrupt is directly connected to the NVIC in parallel with the connection to the EXTI.

All EXTI event inputs are OR-ed together and connected to the CPU event input (rxev).

Table 128. EXTI Event input mapping

Table 128. EXTI Event input mapping (continued)

Table 128. EXTI Event input mapping (continued)

1. 1. PVD and AVD signals are OR-ed together on the same EXTI event input.
2. 2. RTC Tamper, RTC timestamp and RCC LSECSS signals are OR-ed together on the same EXTI event input.
3. 3. Not available on CPU NVIC, to be used for system wakeup only or CPU event input (rxev).
4. 4. Signals of WKUP1 to WKUP6 correspond to WKUPn pin+1.
5. 5. Available on CPU NVIC directly from the peripheral.

20.5 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral that generating the event. The configurable events are enabled by enabling at least one of the trigger edges.

In Stop mode, an event always wakes up the SRD domain.

In system Run and Stop modes, an event always generates an associated SRD domain interrupt. An event only wakes up the CPU when the event associated CPU interrupt is unmasked and/or the CPU event is unmasked.

Table 129. Masking functionality

1. 1. Only for event inputs that allow the system to wake up SRD domain for Autonomous run mode (Any target).
2. 2. For event inputs that always wake up the CPU.

For configurable event inputs, an event request is generated when the enabled edge(s) is/are detected on the event input. When the associated CPU interrupt is unmasked, the corresponding pending PRx bit in EXTI_CPUPR is set and the CPU interrupt signal is activated. EXTI_CPUPR PRx pending bit must be cleared by software by programming it to 1. This clears the CPU interrupt.

For direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit. When the associated CPU interrupt is unmasked, the corresponding CPU interrupt signal is activated.

The CPU event has to be unmasked to generate an event. When the enabled edge(s) is/are detected on the event input, a CPU event pulse is generated. There is no CPU event pending bit.

Both a CPU interrupt and a CPU event may be enabled on the same event input. They both trigger the same event input condition(s).

For configurable event inputs, an event input request can be generated by software by writing 1 in the software interrupt/event register EXTI_SWIER.

Whenever an event input is enabled and a CPU interrupt and/or CPU event is unmasked, the event input also generates an SRD domain wakeup next to the CPU wakeup.

Some event inputs can wake up the SRD domain Autonomous run mode. In this case the CPU interrupt and CPU event are masked, preventing the CPU to be woken up. Two SRD domain Autonomous run mode wakeup mechanisms are supported:

• • SRD domain wakeup without pending (EXTI_SRDPMR = 0)
  • – On a configurable event input, this mechanism wakes up SRD domain and automatically clears the SRD domain wakeup signal after the delay + rising edge detect pulse generator.
  • – On a direct event input, this mechanism wakes up SRD domain and clears the SRD domain wakeup signal after the direct event input signal is cleared.
• • SRD domain wakeup with pending (EXTI_SRDPMR = 1)
  • – On a configurable event input, this mechanism wakes up SRD domain and clears the SRD domain wakeup signal after the delay + rising edge detect pulse generator and when the SRD pending request is cleared.
  • – On a direct event input, this mechanism wakes up SRD domain and clears the SRD domain wakeup signal after the direct event input signal is cleared and when the SRD pending request is cleared.

20.5.1 EXTI CPU interrupt procedure

1. 1. Unmask the event input interrupt by setting the corresponding mask bits in the EXTI_CPUIMR register.
2. 2. For configurable event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
3. 3. Enable the associated interrupt source in the CPU NVIC or use the SEVONPEND, so that an interrupt coming from the CPU interrupt signal can be detected by the CPU after a WFI/WFE instruction.

For configurable event inputs, the associated EXTI pending bit needs to be cleared.

20.5.2 EXTI CPU event procedure

1. 1. Unmask the event input by setting the corresponding mask bits of the EXTI_CPEUMR register.
2. 2. For configurable event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
3. 3. The CPU event signal is detected by the CPU after a WFE instruction.

For configurable event inputs, there is no EXTI pending bit to clear.

20.5.3 EXTI CPU wakeup procedure

1. 1. Unmask the event input by setting at least one of the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers. The CPU wakeup is generated at the same time as the unmasked CPU interrupt and/or CPU event.
2. 2. For configurable event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
3. 3. Direct events automatically generate a CPU wakeup.

20.5.4 EXTI SRD domain wakeup for Autonomous run mode procedure

1. 1. Mask the event input for waking up the CPU by clearing both the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers.
2. 2. For configurable event inputs, enable the event input by setting either one or both the corresponding trigger edge enable bits in EXTI_RTSR and EXTI_FTSR registers.
3. 3. Direct events automatically generate an SRD domain wakeup.
4. 4. Select the SRD domain wakeup mechanism in EXTI_SRDPMR.
   • – When SRD domain wakeup without pending (EXTI_PMR = 0) is selected, the Wakeup is automatically cleared following the clearing of the event input.
   • – When SRD domain wakeup with pending (EXTI_PMR = 1) is selected, the Wakeup needs to be cleared by a selected SRD domain pendclear source.
     A pending SRD domain wakeup signal can also be cleared by firmware by clearing the associated EXTI_SRDPMR register bit.
5. 5. An SRD domain interrupt is generated after the SRD domain wakeup:
   • – Configurable event inputs generate a pulse on SRD domain interrupt.
   • – Direct event inputs activate the SRD domain interrupt until the event input is cleared in the peripheral.

20.5.5 EXTI software interrupt/event trigger procedure

Any of the configurable event inputs can be triggered from the software interrupt/event register (the associated CPU interrupt and/or CPU event shall be enabled by their respective procedure). Follow the steps below:

1. 1. Enable the event input by setting at least one of the corresponding edge trigger bits in the EXTI_RTSR and/or EXTI_FTSR registers.
2. 2. Unmask the software interrupt/event trigger by setting at least one of the corresponding mask bits in the EXTI_CPUIMR and/or EXTI_CPUEMR registers.
3. 3. Trigger the software interrupt/event by writing 1 to the corresponding bit in the EXTI_SWIER register.
4. 4. The event input can be disabled by clearing the EXTI_RTSR and EXTI_FTSR register bits.

Note: An edge on the configurable event input also triggers an interrupt/event.

A software trigger can be used to set the SRD pending request logic, keeping the SRD domain in Run until the SRD pending request logic is cleared.

20.6 EXTI registers

EXTI registers can only be accessed in 32-bit (word) mode. Byte or half-word formats are not allowed.

20.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 TR[21:0] : Rising trigger event configuration bit of configurable event input x (x= 21 to 0)

• 0: Rising trigger disabled (for event and Interrupt) for input line
• 1: Rising trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

20.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 TR[21:0] : Falling trigger event configuration bit of configurable event input x (x= 21 to 0)

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a falling edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same Configurable event input. In this case, both edges generate a trigger.

20.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 SWIER[21:0] : Software interrupt on line x (x = 21 to 0)

This bitfield always returns 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x.

This bit is automatically cleared by hardware.

20.6.4 EXTI SRD pending mask register (EXTI_SRDPMR1)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 MR25 : SRD pending mask on event input x (x =25)

0: SRD pending request from line x is masked. Writing this bit to 0 also clears the SRD Pending request.

1: SRD pending request from line x is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

Bits 24:22 Reserved, must be kept at reset value.

Bits 21:19 MR[21:19] : SRD pending mask on event input x (x = 21 to 19)

0: SRD pending request from line x is masked. Writing this bit to 0 also clears the SRD pending request.

1: SRD pending request from line x is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

Bits 18:16 Reserved, must be kept at reset value.

Bits 15:0 MR[15:0] : SRD pending mask on event input x (x = 15 to 0)

0: SRD pending request from line x is masked. Writing this bit to 0 also clears the SRD pending request.

1: SRD pending request from line x is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

20.6.5 EXTI SRD pending clear selection register low (EXTI_SRDPCR1L)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:0 PCS[15:0][1:0] : SRD pending request clear input signal selection on event input x = truncate (n/2)

00: DMA channel 6 event selected as SRD domain pendclear source

01: DMA channel 7 event selected as SRD domain pendclear source

10: LPTIM2 out selected as SRD domain pendclear source

11: LPTIM3 out selected as SRD domain pendclear source

20.6.6 EXTI SRD pending clear selection register high (EXTI_SRDPCR1H)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 PCS25[1:0] : SRD pending request clear input signal selection on Event input x = truncate \( ((n+32)/2) \)

• 00: DMA channel 6 event selected as SRD domain pendclear source
• 01: DMA channel 7 event selected as SRD domain pendclear source
• 10: LPTIM2 out selected as SRD domain pendclear source
• 11: LPTIM3 out selected as SRD domain pendclear source

Bits 17:12 Reserved, must be kept at reset value.

Bits 11:6 PCS[21:19][1:0] : SRD pending request clear input signal selection on Event input x = truncate \( ((n+32)/2) \)

• 00: DMA channel 6 event selected as SRD domain pendclear source
• 01: DMA channel 7 event selected as SRD domain pendclear source
• 10: LPTIM2 out selected as SRD domain pendclear source
• 11: LPTIM3 out selected as SRD domain pendclear source

Bits 5:0 Reserved, must be kept at reset value.

20.6.7 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TR51 : Rising trigger event configuration bit of configurable event input x+32 (x = 51)

0: Rising trigger disabled (for event and Interrupt) for input line

1: Rising trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bit 18 Reserved, must be kept at reset value.

Bit 17 TR49 : Rising trigger event configuration bit of configurable event input x+32 (x = 49)

0: Rising trigger disabled (for event and Interrupt) for input line

1: Rising trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bits 16:0 Reserved, must be kept at reset value.

20.6.8 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TR51 : Falling trigger event configuration bit of configurable event input x+32 (x = 51)

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bit 18 Reserved, must be kept at reset value.

Bit 17 TR49 : Falling trigger event configuration bit of configurable event input x+32 (x = 49)

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bits 16:0 Reserved, must be kept at reset value.

20.6.9 EXTI software interrupt event register (EXTI_SWIER2)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 SWIER51 : Software interrupt on line x+32 (x = 51)

This bit always returns 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is automatically cleared by hardware.

Bit 18 Reserved, must be kept at reset value.

Bit 17 SWIER49 : Software interrupt on line x+32 (x = 49)

This bit always returns 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is automatically cleared by hardware.

Bits 16:0 Reserved, must be kept at reset value.

20.6.10 EXTI SRD pending mask register (EXTI_SRDPMR2)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:16 MR[51:48] : SRD pending mask on event input x+32 (x = 51 to 48)

0: SRD pending request from line x+32 is masked. Writing this bit to 0 also clears the SRD pending request.

1: SRD pending request from line x+32 is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MR41 : SRD pending mask on event input x+32 (x = 41)

0: SRD pending request from Line x+32 is masked. Writing this bit to 0 also clears the SRD Pending request.

1: SRD pending request from Line x+32 is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

Bits 8:4 Reserved, must be kept at reset value.

Bits 3:2 MR[35:34] : SRD Pending Mask on Event input x+32 (x = 35 to 34)

0: SRD pending request from Line x+32 is masked. Writing this bit to 0 also clears the SRD Pending request.

1: SRD pending request from Line x+32 is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

Bits 1:0 Reserved, must be kept at reset value.

20.6.11 EXTI SRD pending clear selection register low (EXTI_SRDPCLR2L)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 PCS41[1:0] : SRD Pending request clear input signal selection on Event input x = truncate \( ((n+64)/2) \)

• 00: DMA ch6 event selected as SRD domain pendclear source
• 01: DMA ch7 event selected as SRD domain pendclear source
• 10: LPTIM2 out selected as SRD domain pendclear source
• 11: LPTIM3 out selected as SRD domain pendclear source

Bits 17:8 Reserved, must be kept at reset value.

Bits 7:4 PCS[35:34][1:0] : SRD Pending request clear input signal selection on Event input x= truncate \( ((n+64)/2) \)

• 00: DMA ch6 event selected as SRD domain pendclear source
• 01: DMA ch7 event selected as SRD domain pendclear source
• 10: LPTIM2 out selected as SRD domain pendclear source
• 11: LPTIM3 out selected as SRD domain pendclear source

Bits 3:0 Reserved, must be kept at reset value.

20.6.12 EXTI SRD pending clear selection register high (EXTI_SRDPCTR2H)

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PCS[51:48][1:0] : SRD Pending request clear input signal selection on Event input x= truncate \( ((n+96)/2) \)

• 00: DMA ch6 event selected as SRD domain pendclear source
• 01: DMA ch7 event selected as SRD domain pendclear source
• 10: LPTIM2 out selected as SRD domain pendclear source
• 11: LPTIM3 out selected as SRD domain pendclear source

20.6.13 EXTI rising trigger selection register (EXTI_RTSR3)

Address offset: 0x40

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 TR85 : Rising trigger event configuration bit of configurable event input x+64 (x = 85)

0: Rising trigger disabled (for event and Interrupt) for input line

1: Rising trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 TR82 : Rising trigger event configuration bit of configurable event input x+64 (x = 82)

0: Rising trigger disabled (for event and Interrupt) for input line

1: Rising trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bits 17:0 Reserved, must be kept at reset value.

20.6.14 EXTI falling trigger selection register (EXTI_FTSR3)

Address offset: 0x44

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 TR[85] : Falling trigger event configuration bit of configurable event input x+64 (x = 85)

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 TR82 : Falling trigger event configuration bit of configurable event input x+64 (x = 82)

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line

Note: The configurable event inputs are edge triggered, no glitch must be generated on these inputs.

If a rising edge on the configurable event input occurs while writing to the register, the associated pending bit is not set.

Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

Bits 17:0 Reserved, must be kept at reset value.

20.6.15 EXTI software interrupt event register (EXTI_SWIER3)

Address offset: 0x48

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 SWIER85 : Software interrupt on line x+64 (x = 85)

This bitfield always returns 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is automatically cleared by hardware.

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 SWIER82 : Software interrupt on line x+64 (x = 82)

This bitfield always returns 0 when read.

0: Writing 0 has no effect.

1: Writing a 1 to this bit will trigger an event on line x. This bit is automatically cleared by hardware.

Bits 17:0 Reserved, must be kept at reset value.

20.6.16 EXTI SRD pending mask register (EXTI_SRDPMR3)

Address offset: 0x4C

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 MR88 : SRD pending mask on event input x+64 (x = 88)

0: SRD pending request from Line x+64 is masked. Writing this bit to 0 also clears the SRD pending request.

1: SRD Pending request from Line x+64 is unmasked. When triggered, the SRD domain pending signal keeps SRD domain wakeup active until cleared.

Bits 23:0 Reserved, must be kept at reset value.

20.6.17 EXTI SRD pending clear selection register high (EXTI_SRDPCR3H)

Address offset: 0x54

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:16 PCS88[1:0] : SRD pending request clear input signal selection on event input x= truncate \( ((n+160)/2) \)

00: DMA channel 6 event selected as SRD domain pendclear source

01: DMA channel 7 event selected as SRD domain pendclear source

10: LPTIM2 out selected as SRD domain pendclear source

11: LPTIM3 out selected as SRD domain pendclear source

Bits 15:0 Reserved, must be kept at reset value.

20.6.18 EXTI interrupt mask register (EXTI_CPUIMR1)

Address offset: 0x80

Reset value: 0xFFC0 0000

Bits 31:22 MR[31:22] : CPU interrupt mask on direct event input x (x = 31 to 22)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bits 21:0 MR[21:0] : CPU interrupt mask on configurable event input x (x = 21 to 0)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

20.6.19 EXTI event mask register (EXTI_CPUEMR1)

Address offset: 0x84

Reset value: 0x0000 0000

Bits 31:0 MR[31:0] : CPU event mask on event input x (x = 31 to 0)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

20.6.20 EXTI pending register (EXTI_CPUPR1)

Address offset: 0x88

Reset value: undefined

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:0 PR[21:0] : Configurable event inputs x Pending bit (x = 21 to 0)

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event is detected on the external interrupt line. This bit is cleared by writing 1 to the bit or by changing the edge detector sensitivity.

20.6.21 EXTI interrupt mask register (EXTI_CPUIMR2)

Address offset: 0x90

Reset value: 0xFFFF5 FFFF

Bits 31:20 MR[63:52] : CPU interrupt mask on direct event input x+32 (x = 63 to 52)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bit 19 MR51 : CPU interrupt mask on configurable event input x+32 (x = 51)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

Bit 18 MR50 : CPU Interrupt mask on direct Event input x+32 (x = 50)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bit 17 MR[49] : CPU interrupt mask on configurable event input x+32 (x = 49)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

Bits 16:15 MR[48:47] : CPU interrupt mask on direct event input x+32 (x = 47 to 46)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bits 14:12 Reserved, must be kept at reset value.

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bits 11:0 MR[43:32] : CPU Interrupt mask on direct event input x+32 (x = 43 to 32)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

20.6.22 EXTI event mask register (EXTI_CPUEMR2)

Address offset: 0x94

Reset value: 0x0000 0000

Bits 31:15 MR[63:47] CPU event mask on event input x+32 (x = 63 to 47)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

Bits 14:12 Reserved, must be kept at reset value.

Bits 11:0 MR[43:32] : CPU event mask on event input x+32 (x = 43 to 32)

0: Event request from Line x is masked

1: Event request from Line x is unmasked

20.6.23 EXTI pending register (EXTI_CPUPR2)

Address offset: 0x98

Reset value: undefined

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 PR51 : Configurable event inputs x+32 pending bit (x = 51)

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event is detected on the external interrupt line. This bit is cleared by writing a 1 to the bit or by changing the edge detector sensitivity.

Bit 18 Reserved, must be kept at reset value.

Bit 17 PR49 : Configurable event inputs x+32 pending bit (x = 49)

0: No trigger request occurred

1: selected trigger request occurred

This bit is set when the selected edge event is detected on the external interrupt line. This bit is cleared by writing a 1 to the bit or by changing the edge detector sensitivity.

Bits 16:0 Reserved, must be kept at reset value.

20.6.24 EXTI interrupt mask register (EXTI_CPUIMR3)

Address offset: 0xA0

Reset value: 0x018B FFFF

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:23 MR[88:87] : CPU interrupt mask on direct event input x+64 (x =88, 87)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bit 22 Reserved, must be kept at reset value.

Bit 21 MR[85] : CPU interrupt mask on configurable event input x+64 (x = 85)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

Bits 20:19 Reserved, must be kept at reset value.

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bit 18 MR82 : CPU interrupt mask on configurable event input x+64 (x =82)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for configurable event inputs is set to 0 in order to disable the interrupt by default.

Bit 17 Reserved, must be kept at reset value.

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bit 16 MR[80] : CPU interrupt mask on direct event input x+64 (x = 80)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bits 15:14 Reserved, must be kept at reset value.

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bit 13 MR[77] : CPU interrupt mask on direct event input x+64 (x = 77)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bits 12:11 Reserved, must be kept at reset value.

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

Bits 12:0 MR[74:54] : CPU interrupt mask on direct event input x+64 (x = 74 to 54)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is unmasked

Note: The reset value for direct event inputs is set to 1 in order to enable the interrupt by default.

20.6.25 EXTI event mask register (EXTI_CPUEMR3)

Address offset: 0xA4

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:23 MR[88:87] : CPU event mask on event input x+64 (x = 88, 87)

• 0: Event request from Line x is masked
• 1: Event request from Line x is unmasked

Bit 22 Reserved, must be kept at reset value.

Bit 21 MR85 : CPU event mask on event input x+64 (x = 85)

• 0: Event request from Line x is masked
• 1: Event request from Line x is unmasked

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 MR82 : CPU event mask on event input x+64 (x = 82)

• 0: Event request from Line x is masked
• 1: Event request from Line x is unmasked

Bit 17 Reserved, must be kept at reset value.

Bit 16 MR[80] : CPU event mask on event input x+64 (x = 80)

• 0: Event request from Line x is masked
• 1: Event request from Line x is unmasked

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 MR77 : CPU event mask on event input x+64 (x = 77)

• 0: Event request from Line x is masked
• 1: Event request from Line x is unmasked

Bits 12:11 Reserved, must be kept at reset value.

Bits 10:0 MR[74:64] : CPU event mask on event input x+64 (x = 74 to 64)

• 0: Event request from Line x is masked
• 1: Event request from Line x is unmasked

20.6.26 EXTI pending register (EXTI_CPUPR3)

Address offset: 0xA8

Reset value: undefined

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 PR[85] : Configurable event inputs x+64 pending bit (x = 85)

• 0: No trigger request occurred
• 1: selected trigger request occurred

This bit is set when the selected edge event is detected on the external interrupt line. This bit is cleared by writing 1 to the bit or by changing the edge detector sensitivity.

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 PR82 : Configurable event inputs x+64 pending bit (x = 82)

• 0: No trigger request occurred
• 1: selected trigger request occurred

This bit is set when the selected edge event is detected on the external interrupt line. This bit is cleared by writing 1 to the bit or by changing the edge detector sensitivity.

Bits 17:0 Reserved, must be kept at reset value.

20.6.27 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 130. Asynchronous interrupt/event controller register map and reset values

Table 130. Asynchronous interrupt/event controller register map and reset values (continued)

Table 130. Asynchronous interrupt/event controller register map and reset values (continued)

Refer to Section 2.3 on page 131 for the register boundary addresses.