7. Low-power SRD domain application example

This section describes, through an example, how to use the SRD domain to implement low-power applications.

7.1 Introduction

The first part of the description explains how the EXTI, RCC and PWR blocks interact with each other and with the other system blocks. A detailed explanation on how the DMAMUX2 can be used to free the CPU is also provided.

The second part explains how to use the Autonomous mode to perform simple data transfers through an example of LPUART1 transmission.

Register programming is detailed only for the blocks related to the Autonomous mode.

7.2 EXTI, RCC and PWR interconnections

Figure 40 shows the main EXTI, RCC and PWR interconnections.

Figure 40. EXTI, RCC and PWR interconnections

7.2.1 Interrupts and wake-up

Three kinds of signals are exchanged between the peripherals. They can be used to wake up the system from Stop mode:

• • Wake-up events (or asynchronous interrupts)

Some peripherals can generate interrupt events, even if their bus interface clock is not present. These interrupt events are called wake-up events (or asynchronous interrupts).

Example: i2c1_wkup, usart1_wkup and lptim1_wkup.

• • Signals

Some peripherals generate a pulse instead of an interrupt signal. These pulses are called signals.

Examples: lptim2_out and lptim3_out.

• • Interrupts

Contrary to signals, the interrupts should be cleared by a CPU or any other bus master, either by clearing the corresponding event bit in the peripheral register or by updating the FIFO interrupt level.

All the interrupts associated to system peripherals are directly connected to the NVIC, except for the peripherals which are able to wake up the system from Stop mode or the CPU from CStop. In this latter case, the interrupts, signals or wake-up events are connected to the NVIC via the EXTI.

Example: spi1_it, tim1_brk_it and tim1_upd_it.

The interrupt and wake-up sources that require to be cleared in the peripheral itself are connected to EXTI Direct Event inputs. The EXTI does not manage any CPU status pending bit.

The peripherals signals are connected to EXTI Configurable Event inputs. These EXTI inputs provide a CPU status pending bit which needs to be cleared by the application.

7.2.2 Block interactions

Interaction between EXTI and PWR blocks

The EXTI delivers wake-up requests signals ( exti_cd_wkup , exti_srd_wkup ) to the PWR controller. These signals are activated according to the state of the interrupts, signals or wake-up events connected to the EXTI. These wake-up requests are used by the PWR controller to supply the domain who needs to handle the activated wake-up event generated by the peripherals.

Interaction between PWR and RCC blocks

The PWR block controls the V _CORE supply according to the system operating mode (CRun, CSleep or CStop). For DStop2 (Retention mode), the PWR controller also controls the power switch (ePOD) that cuts the supply of part of the CD domain.

The RCC block controls the clock generation in accordance with the system operating mode. It is also responsible for reset generation.

To synchronize the system mode transitions, the RCC block is tightly coupled with the PWR controller:

• • The RCC informs the PWR controller when peripherals located in the CD or SRD domain are allocated by the CPU ( c_per_alloc_cd ).
• • The RCC also warns the PWR block when a domain clock is activated/deactivated. These signals are used in case of domain transition from DRun to DStop, DStop2 and Standby. In this case, the PWR controller waits until the domain clock has been gated, before switching down this domain.
• • Similarly, the PWR controller informs the RCC about the V _CORE supply status of each domain ( pwr_srd_wkup and pwr_cd_wkup ). This information is used by the RCC when a domain transition from DStop or DStop2 to DRun occurs.

Interaction between EXTI and SRD domain

All the wake-up event inputs received by the EXTI from the peripherals located in SRD domain can be used to perform operations in Autonomous mode without activating the CPU.

The EXTI SRD_PenClear[3:0] inputs received from the SRD domain are used to acknowledge the ongoing wake-up requests generated by peripherals located in the SRD domain. The SRD_PenClear[3:0] inputs allow switching the system SRD domain from Run to Stop mode.

7.2.3 Role of DMAMUX2 in SRD domain

The DMAMUX2 implemented in the SRD domain allows chaining BDMA2 transfers. BDMA2 requests are synchronized thanks to trigger events ( dmamux2_evttx ) which can be generated when the expected amount of data has been transferred.

These events can also trigger DMAMUX2 request generators ( REQ_GEN[3:0] ), and thus chain several BDMA2 transfers. In fact REQ_GEN[3:0] can be triggered indirectly by all the wake-up events generated by all SRD domain peripherals.

Like LPTIM3 and LPTIM2 outputs, dmamux2_evt7 and dmamux2_evt6 events are connected to the EXTI. They can be used to switch the SRD domain from DRun to DStop or DStop2 mode when the task requested by the wake-up event is complete.

7.3 Low-power application example based on LPUART1 transmission

This section illustrates, through an example, the benefit of the SRD domain usage on power consumption. To help the user program the device, only the key register settings are given herein.

Refer to Sections Reset and clock control (RCC) and Power control (PWR) for additional details.

7.3.1 Memory retention

The SRD domain features 32 Kbytes of SRAM (SRD SRAM). When the CD domain is in DStop or DStop2 mode while the system is in Run mode, data can be transferred between this RAM area and to/from a peripheral located in the SRD domain.

DStop2 and DStop are very similar from user point of view. In DStop2 mode the asynchronous logic is switched off while RAM and register contents are maintained. This allows further leakage current consumption reduction compared to DStop mode. When exiting DStop2, the CPU domain resumes normal execution at the cost of a slightly higher startup time.

In DStop/DStop2 modes, all the CD domain clocks are OFF but data are retained. The power consumption in DStop/DStop2 mode can be further optimized by choosing to shut off some SRAMs with the consequence to lose their content (see Section 6: Power control (PWR) ).

Note: SRD SRAM remains available as long as the system is not in Standby mode.
If the system is in Standby mode, it is still possible to use the BKUP_SRAM. However, its size is limited to 4 Kbytes.

7.3.2 Memory-to-peripheral transfer using LPUART1 interface

Example description

Figure 41 shows the proposed implementation. At a regular time interval given by LPTIM2, the CPU wakes up from CStop mode (which domain is in DStop/DStop2). When the CPU is in Run mode, it prepares the data to be transmitted via LPUART1, transfers them to SRD SRAM, and goes back to CStop. The SRD domain is configured to perform data transfers via LPUART1 and go back to Stop mode when the transfer is complete.

The LPTIM2 interface is used to wake up the system from Stop at regular time intervals. the CPU must then perform the following operations:

1. 1. Recover the application from the system Stop mode (RECO).
2. 2. Process the new data to be sent via LPUART1 (PROC).
3. 3. Transfer the data into SRD SRAM (XFER).
4. 4. Configure the DMAMUX2, the BDMA2, the LPUART1, and the RCC (CFG).
5. 5. Configure the EXTI (CFG).
6. 6. Configure the PWR block to allow the CD domain to go to DStop/DStop2 mode.
7. 7. Set the CPU to Stop mode.

The SRD domain executes the following tasks in Autonomous mode:

1. 1. Transfer the data from SRD SRAM to LPUART1, using BDMA2.
2. 2. When the LPUART1 interface indicates that the last byte has been transferred, the SRD domain is switched to Stop mode.

Figure 41. Timing diagram of SRD SRAM-to-LPUART1 transfer with BDMA2 and SRD domain in Autonomous mode

Note: The RUN_SRD bit can be used to force the SRD domain to remain in Run mode when the CD domain enters DStop or DStop2 mode.

If the CPU is not running, the SRD domain is not able to switch on its own from Run to Stop mode.

The proposed solution is explained in details in the following sections. It consists in setting a wake-up event for the SRD domain before the CD domain enters DStop/DStop2 mode. In this way the SRD domain remains in run mode and enters Stop mode only when this request is cleared.

RCC programming

Before entering Autonomous mode (CD domain in DStop/DStop2 mode with SRD domain in Run mode), the RCC must be programmed to request the needed clocks to remain enabled. In this example, they are required for the SRD SRAM, BDMA2/DMAMUX2, LPTIM2, GPIOs and LPUART1

LPUART1 can use its own APB clock as kernel clock. Since the system will not enter Stop mode before LPUART1 has completed data transfer, PLLx can be used to provide clocks to the peripherals.

PWR programming

In this example, the PWR block must be programmed in order to:

• • allow the CD domain to enter DStop/Dstop2 mode when the data transfer is complete,
• • define the working voltage according to system modes.

Note: SRD domain could enter Standby as well, but in this case the LPTIM2 could not be used to wake up the system and the AWU should be used instead. In addition, everything must be reprogrammed when the system wakes up.

EXTI programming

The EXTI block must be configured to provide the following services:

• • Keep SRD domain running when CD domain is in DStop/DStop2. This will be done by a software event.
• • Set the device to Stop mode when the data transfer via LPUART1 is complete.
• • Wake up the product from Stop when LPTIM2 time interval has elapsed.

The EXTI block is configured once before performing the first data transfer. For incoming data transfers, the programmed configuration remains unchanged; only some events need to be triggered or acknowledged.

Note: The CPU uses the event input number 0 to generate a software event. LPTIM2 wake-up signal is connected to event input number 48 (direct event input).

All other event inputs must be disabled: EXTI_RTSRx_TRy = '0' and EXTI_FTSRx_TRy = '0'.

To generate a wake-up event for SRD domain, the CPU must write SWIER0 bit of EXTI_SWIER1 to '1'.

BDMA2 and DMAMUX2 programming

Two BDMA2 channels are required to execute data transfers via LPUART1.

• • A BDMA2 channel, such as channel 0, is used to transfer data from SRD SRAM to LPUART1, using the TXE flag.
• • The second BDMA2 channel role is to switch the SRD domain to Stop mode. For that purpose, DMAMUX2 request generator channel 0 (REQ_GEN0) and DMAMUX2 channel 7 synchronization block (SYNC7) are used in conjunction with BDMA2 channel 7.

BDMA2 channel 0 does not use DMAMUX2 trigger capabilities. Refer to Table 48 for initialization details.

BDMA2 channel 7 uses REQ_GEN0 to generate BDMA2 requests. The generation of BDMA2 requests is triggered by the LPUART1 transmit interrupt ( lpuart1_tx_it ). The LPUART1 interface generates lpuart1_tx_it interrupt when the transmit complete event is detected. The BDMA2 then clears the pending interrupt by performing a write operation to the LPUART1.

The SYNC7 block is programmed in Free-running mode. It generates a pulse on its dmamux2_evt7 output when the BDMA2 request generated by the REQ_GEN0 is complete. dmamux2_evt7 signal is used by the EXTI to switch back the SRD domain to Stop mode.

Figure 42 shows the active signal paths via DMAMUX2. The grayed blocks represent the unused paths.

Figure 42. BDMA2 and DMAMUX2 interconnection

Table 48 explain how to program BDMA2 and DMAMUX2 key functions. The way errors are handled is not described.

Table 48. BDMA2 and DMAMUX2 initialization sequence (DMAMUX2_INIT)

Table 48. BDMA2 and DMAMUX2 initialization sequence (DMAMUX2_INIT) (continued)

LPTIM2 programming

When LPTIM2 wake-up event occurs, the CPU reboots and SRD domain mode is also set to Run mode.

An interrupt issued by LPTIM2 is pending on the CPU NVIC. LPTIM2 interrupt handler must acknowledge this LPTIM2 interrupt by writing ARRMCF bit in LPTIM2_ICR register to '1' (LPTIM2_Ack).

LPUART programming

In the use-case described herein, the capability of the LPUART1 to request the kernel clock according to some events is not used.

LPUART1 is programmed so that it generates a BDMA request when its TX-FIFO is not full.

LPUART1 also generates an interrupt when the TX-FIFO and its transmit shift register are empty. This interrupt is used to switch the SRD domain to Stop mode.

Table 49 gives the key settings concerning the handling of Stop mode for LPUART1.

Respect the sequence described in Table 50 to enable LPUART1.

7.3.3 Overall description of the low-power application example based on LPUART1 transmission

After a Power-on reset, the CPU perform the following operations:

1. 1. Boot sequence (not described here).
2. 2. Full initialization of RCC, PWR, EXTI, LPUART1, GPIOs, LPTIM2, DMAMUX2, BDMA2 and NVIC.
   Only the relevant steps of RCC, EXTI, PWR, LPUART1, BDMA2 and DMAMUX2 initialization related to the Autonomous mode are described herein. Refer to the previous sections for additional details.
3. 3. The CPU processes the data to be transferred and copies them to SRD SRAM.
4. 4. The CPU generates a wake-up event (EXTI_Event) to maintain SRD in Run mode when CD enters DStop/DStop2.
5. 5. The CPU enables the BDMA2 to start LPUART transmission and goes to CStop mode. As it is allowed to do so, CD domain enters DStop/DStop2 while SRD remains in Run mode. The data stored in SRD SRAM are retained while the CD domain is in DStop/DStop2 mode.
6. 6. As soon as the BDMA2 is enabled, it serves the request from LPUART1 in order to fill its TX-FIFO. In parallel, serial data transmission can start.
7. 7. When the expected amount of data has been transmitted (NDT bits of BDMA_CNDTR0 set to 0), the BDMA2 no longer provides data to the LPUART1. The LPUART1 generates an interrupt when the TX-FIFO and the transmit buffer are empty.
8. 8. This interrupt triggers DMAMUX2 REQ_GEN0, thus activating a data transfer via BDMA2 channel 7 (BDMA_Ch7). This transfer clears LPUART1 TC flag, and the lpuart1_tx_it is reset to '0'.
9. 9. The end of this transfer triggers a dmamux2_evt7 signal which is used to clear the wake-up request generated by the CPU.
10. 10. As a consequence, the SRD domain (i.e. the system) enters Stop mode and the system clock is gated. LPTIM2 still operates since it uses ck_lsi clock.

1. 11. LPTIM2 lptim2_wkup interrupt wakes up the system. The device exits from Stop mode with the HSI clock. The CPU must restore the proper clock configuration during the warm re-boot sequence and perform the following tasks:
   1. a) Acknowledge LPTIM2 wake-up interrupt,
   2. b) Process the next data block and transfers them to SRD SRAM,
   3. c) Generate again a wake-up event for SRD domain,
   4. d) Start the BDMA2.
   5. e) Go back to CStop mode.

Note: The CPU does not need to initialize BDMA2, DMAMUX2 and LPUART1 again.

Figure 43. Timing diagram of LPUART1 transmission with SRD domain in Autonomous mode

7.3.4 Alternate implementations

More power efficient implementations are also possible. As an example the system clock can be stopped once the data have been transferred to LPUART1 TX-FIFO, instead of remaining activated during the whole transmission as in the example presented above. In this case, the LPUART1 must use ck_hsi or ck_csi as kernel clock when the system switches from Run to Stop mode. LPUART1 must be programmed to wake up SRD domain when its TX-FIFO is almost empty. This asynchronous interrupt can be used as trigger by the REQ_GENx of the DMAMUX2, which will perform a given number (e.g. 14) of data transfers to LPUART1_TDR and then switch back the SRD domain to Stop mode. This implementation is possible because the LPUART1 can request the kernel clock as long as the TX-FIFO and transmit buffer are not empty.

Further power consumption reduction during DStop/DStop2 mode can be achieved by shutting off the SRAMs located in the CD domain. Their content is then lost (see Section 6: Power control (PWR) for more details).

7.4 Other low-power applications

Other peripherals located in SRD domain, such as I2C4, SPI6/I2S6, DFSDM2 or DAC2, can be used to implement low-power applications.