2. Memory and bus architecture

2.1 System architecture

An AXI bus matrix, two AHB bus matrices and bus bridges allow interconnecting bus masters with bus slaves, as illustrated in Table 2 and Figure 1 .

Table 2. Bus-master-to-bus-slave interconnect

Table 2. Bus-master-to-bus-slave interconnect (continued)

1. 1. Bold font type denotes 64-bit bus, plain type denotes 32-bit bus.
2. 2. Table cells indicate access and usage, path and type:
   Access possibility and usage:
   "X" = access possible, "-" = access not possible, shading = access useful/usable.
3. 3. Bank 1 is limited to 128 Kbytes on STM32H7B3/B0 devices.
4. 4. OTFDEC2 is available only on STM32H7B0 and STM32H7B3 devices.

Figure 1. System architecture for STM32H7A3/7B3/7B0xx devices

MSV46123V4

1. 1. Bank 1 is limited to 128 Kbytes on STM32H7B0 devices. STM32H7A3xG and STM32H7A3xI/7B3xx devices feature two banks of 512 Kbytes and 1 Mbyte each, respectively.
2. 2. OTFDEC1 and OTFDEC2 are available only on STM32H7B0 and STM32H7B3 devices.

2.1.1 Bus matrices

AXI bus matrix in CD domain

The CD domain multi AXI bus matrix ensures and arbitrates concurrent accesses from multiple masters to multiple slaves. This allows efficient simultaneous operation of high-speed peripherals.

The arbitration uses a round-robin algorithm with QoS capability.

Refer to Section 2.2: AXI interconnect matrix (AXIM) for more information on AXI interconnect.

AHB bus matrices in CD domain

The AHB bus matrices in CD domain ensure and arbitrate concurrent accesses from multiple masters to multiple slaves. This allows efficient simultaneous operation of high-speed peripherals.

The arbitration uses a round-robin algorithm.

2.1.2 TCM buses

The DTCM and ITCM (data and instruction tightly coupled RAMs) are connected through dedicated TCM buses directly to the Cortex-M7 core. The MDMA controller can access the DTCM and ITCM through AHBS, a specific CPU slave AHB. The ITCM is accessed by Cortex-M7 at CPU clock speed, with zero wait states.

2.1.3 Bus-to-bus bridges

To allow peripherals with different types of buses to communicate together, there is a number of bus-to-bus bridges in the system.

The AHB/APB bridges allow connecting peripherals on APB1 and APB2 to AHB1. Other bridges in the CD domain and in the SRD domain allow connecting APB3 to AHB3 and APB4 to AHB4, respectively. These AHB/APB bridges provide full synchronous interfacing, which allows the APB peripherals to operate with clocks independent of AHB that they connect to.

The AHB/APB bridges also allow APB1 and APB2 peripherals to connect to DMA1 and DMA2 peripheral buses, respectively, without transiting through AHB1.

The AHB/APB bridges convert 8-bit / 16-bit APB data to 32-bit AHB data, by replicating it to the three upper bytes / the upper half-word of the 32-bit word.

The AXI bus matrix incorporates AHB/AXI bus bridge functionality on its slave bus interfaces. The AXI/AHB bus bridges on its master interfaces marked as 32-bit in Figure 1 are outside the matrix.

The Cortex-M7 CPU provides AHB/TCM-bus (ITCM and DTCM buses) translation from its AHBS slave AHB, allowing the MDMA controller to access the ITCM and DTCM.

2.1.4 Domain and inter-domain buses

AXI to CD AHB

A 32-bit bus connects the AXI bus matrix to the AHB bus matrix. It allows AXI bus master to access resources (bus slaves) inside the CD domain.

CD AHB to AXI bus

A 32-bit bus connects the AHB bus matrix to the AXI bus matrix. It allows AHB bus masters to access resources (bus slaves) inside the CD domain and indirectly via the CD-to-SRD AHB in the SRD domain.

AXI to SRD AHB

This 32-bit bus connects the CD domain to the SRD domain AHB bus matrix. It allows bus masters in the CD domain to access resources (bus slaves) in the SRD domain.

CD AHB to SRD AHB

This 32-bit bus connects the CD domain to the SRD domain AHB bus matrix. It allows bus masters in the CD domain to access resources (bus slaves) in the SRD domain.

2.1.5 CPU buses

Cortex ^® -M7 AXIM bus

The Cortex ^® -M7 CPU uses the 64-bit AXIM bus to access all memories (excluding ITCM, and DTCM) and AHB3, AHB4, APB3 and APB4 peripherals (excluding AHB1, APB1 and APB2 peripherals).

The AXIM bus connects the CPU to the AXI bus matrix in the CD domain.

Cortex ^® -M7 ITCM bus

The Cortex ^® -M7 CPU uses the 64-bit ITCM bus for fetching instructions from and accessing data in the ITCM.

Cortex ^® -M7 DTCM bus

The Cortex ^® -M7 CPU uses the 2x32-bit DTCM bus for accessing data in the DTCM. The 2x32-bit DTCM bus allows load/load and load/store instruction pairs to be dual-issued on the DTCM memory. It can also fetch instructions.

Cortex ^® -M7 AHBS bus

The Cortex ^® -M7 CPU uses the 32-bit AHBS slave bus to allow the MDMA controller to access the ITCM and the DTCM.

Cortex ^® -M7 AHBP bus

The Cortex ^® -M7 CPU uses the 32-bit AHBP bus for accessing AHB1, AHB2, APB1 and APB2 peripherals via the AHB bus matrix in the CD domain.

2.1.6 Bus master peripherals

SDMMC1

The SDMMC1 uses a 32-bit bus, connected to the AXI bus matrix, through which it can access internal AXI SRAM and flash memories, and external memories through the OCTOSPI1/2 controllers and the FMC.

SDMMC2

The SDMMC2 uses a 32-bit bus, connected to the AHB bus matrix in CD domain. Through the system bus matrices, it can access the internal AXI SRAM1, AXI SRAM2, AXI SRAM3, AHB SRAM1, AHB SRAM2 and flash memories, and external memories through the OCTOSPI1/2 controllers and the FMC.

MDMA controller

The MDMA controller has two bus masters: an AXI 64-bit bus, connected to the AXI bus matrix and an AHB 32-bit bus connected to the Cortex-M7 AHBS slave bus.

The MDMA is optimized for DMA data transfers between memories since it supports linked list transfers that allow performing a chained list of transfers without the need for CPU intervention. Through the system bus matrices and the Cortex-M7 AHBS slave bus, the MDMA can access all internal and external memories through the OCTOSPI1/2 controllers and the FMC.

DMA1 and DMA2 controllers

The DMA1 and DMA2 controllers have two 32-bit buses - memory bus and peripheral bus, connected to the AHB bus matrix in CD domain.

The memory bus allows DMA data transfers between memories. Through the system bus matrices, the memory bus can access external memories through the OCTOSPI1/2 controllers and the FMC and all internal memories except ITCM and DTCM.

The peripheral bus allows DMA data transfers between two peripherals, between two memories or between a peripheral and a memory. Through the system bus matrices, the peripheral bus can access external memories through the OCTOSPI controller and the FMC, all AHB and APB peripherals and all internal memories except ITCM and DTCM. A direct access to APB1 and APB2 is available, without passing through AHB1. Direct path to APB1 and APB2 bridges allows reducing the bandwidth usage on AHB1 bus by improving data treatment efficiency for APB and AHB peripherals.

BDMA1 controller

The BDMA1 controller is connected to the AHB bus matrix in the CD domain. It is dedicated to the DFSDM1 which is connected to the APB2 bus. The BDMA1 allows DMA data transfers between the DFSDM and AHB SRAM or AHB1, APB1 and APB2 peripherals.

BDMA2 controller

The BDMA2 controller uses a 32-bit bus, connected to the AHB bus matrix in SRD domain, for DMA data transfers between two peripherals, between two memories or between a peripheral and a memory. BDMA2 transfers are limited to the SRD domain resources. It can access the internal SRD SRAM, backup SRAM, and AHB4 and APB4 peripherals through the AHB bus matrix in the SRD domain.

Chrom-Art Accelerator (DMA2D)

The DMA2D graphics accelerator uses a 64-bit bus, connected to the AXI bus matrix. Through the system bus matrices, internal AXI SRAM1, AXI SRAM2, AXI SRAM3, AHB SRAM1, AHB SRAM2 and flash memories, and external memories through the OCTOSPI1/2 controllers and the FMC.

LCD-TFT controller (LTDC)

The LCD-TFT display controller, LTDC, uses a 64-bit bus, connected to the AXI bus matrix, through which it can access internal AXI SRAM1, AXI SRAM2, AXI SRAM3 and flash memories, and external memories through the OCTOSPI1/2 controllers and the FMC.

OTG_HS peripheral

The OTG_HS peripheral uses a 32-bit bus, connected to the AHB bus matrix in the CD domain. Through the system bus matrix, it can access all internal memories except ITCM and DTCM, and external memories through the OCTOSPI1/2 controllers and the FMC.

2.1.7 Clocks to functional blocks

Upon reset, clocks to blocks such as peripherals and some memories are disabled (except for the SRAM, DTCM, ITCM and flash memory). To operate a block with no clock upon reset, the software must first enable its clock through RCC_AHBxENR or RCC_APBxENR register, respectively.

2.2 AXI interconnect matrix (AXIM)

2.2.1 AXI introduction

The AXI (advanced extensible interface) interconnect is based on the Arm® CoreLink™ NIC-400 Network Interconnect. The interconnect has seven initiator ports, or ASIBs (AMBA slave interface blocks), and ten target ports, or AMIBs (AMBA master interface blocks). The ASIBs are connected to the AMIBs via an AXI switch matrix.

Each ASIB is a slave on an AXI bus or AHB (advanced high-performance bus). Similarly, each AMIB is a master on an AXI or AHB bus. Where an ASIB or AMIB is connected to an AHB, it converts between the AHB and the AXI protocol.

The AXI interconnect includes a GPV (global programmer view) which contains registers for configuring certain parameters, such as the QoS (quality of service) level at each ASIB.

Any accesses to unallocated address space are handled by the default slave, which generates the return signals. This ensures that such transactions complete and do not block the issuing master and ASIB.

2.2.2 AXI interconnect main features

• • 64-bit AXI bus switch matrix with seven ASIBs and ten AMIBs, in CD domain
• • AHB/AXI bridge function built into the ASIBs
• • concurrent connectivity of multiple ASIBs to multiple AMIBs
• • programmable traffic priority management (QoS - quality of service)
• • software-configurable via GPV

2.2.3 AXI interconnect functional description

Block diagram

The AXI interconnect is shown in Figure 2 .

Figure 2. AXI interconnect

MSV50670V1.

ASIB configuration

Table 3 summarizes the characteristics of the ASIBs.

Table 3. ASIB configuration

AMIB configuration

Table 4 summarizes the characteristics of the AMIBs.

Table 4. AMIB configuration

1. Conversion to AHB protocol is done via an AXI/AHB bridge sitting between AXI interconnect and the connected slave.

Quality of service (QoS)

The AXI switch matrix uses a priority-based arbitration when two ASIB simultaneously attempt to access the same AMIB. Each ASIB has programmable read channel and write channel priorities, known as QoS, from 0 to 15, such that the higher the value, the higher the priority. The read channel QoS value is programmed in the AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS) , and the write channel in the AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS) . The default QoS value for all channels is 0 (lowest priority).

If two coincident transactions arrive at the same AMIB, the higher priority transaction passes before the lower priority. If the two transactions have the same QoS value, then a least-recently-used (LRU) priority scheme is adopted.

The QoS values should be programmed according to the latency requirements for the application. Setting a higher priority for an ASIB ensures a lower latency for transactions initiated by the associated bus master. This can be useful for real-time-constrained tasks, such as graphics processing (LTDC, DMA2D). Assigning a high priority to masters that can make many and frequent accesses to the same slave (such as the Cortex-M7 CPU) can block access to that slave by other lower-priority masters.

Global programmer view (GPV)

The GPV contains configuration registers for the AXI interconnect (see Section 2.2.4 ). These registers are only accessible by the Cortex-M7 CPU.

2.2.4 AXI interconnect registers

AXI interconnect - peripheral ID4 register (AXI_PERIPH_ID_4)

Address offset: 0x1FD0

Reset value: 0x0000 0004

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 4KCOUNT[3:0] : Register file size

0x0: N/A

Bits 3:0 JEP106CON[3:0] : JEP106 continuation code

0x4: Arm ^®

AXI interconnect - peripheral ID0 register (AXI_PERIPH_ID_0)

Address offset: 0x1FE0

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PARTNUM[7:0] : Peripheral part number bits 0 to 7
0x00: Part number = 0x400

AXI interconnect - peripheral ID1 register (AXI_PERIPH_ID_1)

Address offset: 0x1FE4

Reset value: 0x0000 00B4

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 JEP106ID[3:0] : JEP106 identity bits 0 to 3
0xB: Arm® JEDEC code

Bits 3:0 PARTNUM[11:8] : Peripheral part number bits 8 to 11
0x4: Part number = 0x400

AXI interconnect - peripheral ID2 register (AXI_PERIPH_ID_2)

Address offset: 0x1FE8

Reset value: 0x0000 002B

Bits 7:4 REVISION[3:0] : Peripheral revision number
0x2: r0p2

Bit 3 JEDEC : JEP106 code flag
0x1: JEDEC allocated code

Bits 2:0 JEP106ID[6:4] : JEP106 Identity bits 4 to 6
0x3: Arm® JEDEC code

Address offset: 0x1FEC

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

0: None

0: None

Address offset: 0x1FF0

Reset value: 0x0000 000D

Bits 31:8 Reserved, must be kept at reset value.

0xD: Common ID value

AXI interconnect - component ID1 register (AXI_COMP_ID_1)

Address offset: 0x1FF4

Reset value: 0x0000 00F0

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 CLASS[3:0] : Component class

0xF: Generic IP component class

Bits 3:0 PREAMBLE[11:8] : Preamble bits 8 to 11

0x0: Common ID value

AXI interconnect - component ID2 register (AXI_COMP_ID_2)

Address offset: 0x1FF8

Reset value: 0x0000 0005

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[19:12] : Preamble bits 12 to 19

0x05: Common ID value

AXI interconnect - component ID3 register (AXI_COMP_ID_3)

Address offset: 0x1FFC

Reset value: 0x0000 00B1

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[27:20] : Preamble bits 20 to 27

0xB1: Common ID value

AXI interconnect - TARG x bus matrix issuing functionality register (AXI_TARGx_FN_MOD_ISS_BM)

Address offset: 0x1008 + 0x1000 * x, (x = 1 to 10)

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE : Switch matrix write issuing override for target

0: Default issuing capability

1: Set switch matrix write issuing capability to 1 (see Table 4: AMIB configuration )

Bit 0 READ_ISS_OVERRIDE : Switch matrix read issuing override for target

0: Default issuing capability

1: Set switch matrix read issuing capability to 1 (see Table 4: AMIB configuration )

AXI interconnect - TARG x bus matrix functionality 2 register (AXI_TARGx_FN_MOD2)

Address offset: 0x1024 + 0x1000 * x, (x = 1, 2, 7 to 10)

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BYPASS_MERGE : Disable packing of beats to match the output data width. Unaligned transactions are not realigned to the input data word boundary.

0: Normal operation

1: Disable packing

AXI interconnect - TARG x long burst functionality modification register (AXI_TARGx_FN_MOD_LB)

Address offset: 0x102C + 0x1000 * x, (x = 1, 2, 10)

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 FN_MOD_LB : Controls burst breaking of long bursts

0: Long bursts can not be generated at the output of the ASIB

1: Long bursts can be generated at the output of the ASIB

AXI interconnect - TARG x issuing functionality modification register
(AXI_TARGx_FN_MOD)

Address offset: \( 0x1108 + 0x1000 * x \) , ( \( x = 1, 2, 7 \) to \( 10 \) )

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE : Override AMIB write issuing capability

0: Default issuing capability

1: Force issuing capability to 1 (see Table 4: AMIB configuration )

Bit 0 READ_ISS_OVERRIDE : Override AMIB read issuing capability

0: Default issuing capability

1: Force issuing capability to 1 (see Table 4: AMIB configuration )

AXI interconnect - INI x functionality modification 2 register
(AXI_INIx_FN_MOD2)

Address offset: \( 0x41024 + 0x1000 * x \) , ( \( x = 1, 3, 7 \) )

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BYPASS_MERGE : Disables alteration of transactions by the up-sizer unless required by the protocol

0: Normal operation

1: Transactions pass through unaltered where allowed

AXI interconnect - INI x AHB functionality modification register (AXI_INIx_FN_MOD_AHB)

Address offset: 0x41028 + 0x1000 * x, (x = 1, 3, 7)

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WR_INC_OVERRIDE : Converts all AHB-Lite read transactions to a series of single beat AXI transactions; each AHB-Lite write beat is acknowledged with the AXI buffered write response.

• 0: Override disabled
• 1: Override enabled

Bit 0 RD_INC_OVERRIDE : Converts all AHB-Lite write transactions to a series of single beat AXI transactions

• 0: Override disabled
• 1: Override enabled

AXI interconnect - INI x read QoS register (AXI_INIx_READ_QOS)

Address offset: 0x41100 + 0x1000 * x, (x = 1 to 7)

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 AR_QOS[3:0] : Read channel QoS setting

• 0x0: Lowest priority
• 0xF: Highest priority

AXI interconnect - INI x write QoS register (AXI_INIx_WRITE_QOS)

Address offset: \( 0x41104 + 0x1000 * x \) , ( \( x = 1 \) to \( 7 \) )

Reset value: \( 0x0000\ 0000 \)

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 AW_QOS[3:0] : Write channel QoS setting

0x0: Lowest priority

0xF: Highest priority

AXI interconnect - INI x issuing functionality modification register (AXI_INIx_FN_MOD)

Address offset: \( 0x41108 + 0x1000 * x \) , ( \( x = 1 \) to \( 7 \) )

Reset value: \( 0x0000\ 0000 \)

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 WRITE_ISS_OVERRIDE : Override ASIB write issuing capability

0: Normal issuing capability

1: Force issuing capability to 1

Bit 0 READ_ISS_OVERRIDE : Override ASIB read issuing capability

0: Normal issuing capability

1: Force issuing capability to 1

2.2.5 AXI interconnect register map

Table 5. AXI interconnect register map and reset values

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Table 5. AXI interconnect register map and reset values (continued)

Refer to Section 2.3 on page 131 for the register boundary addresses.

2.3 Memory organization

2.3.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

2.3.2 Memory map and register boundary addresses

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following tables.

Table 6. Memory map and default device memory area attributes

Table 6. Memory map and default device memory area attributes (continued)