RM0455-STM32H7A3-7B3-7B0

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32H7A3/7B3 and STM32H7B0 microcontroller memory and peripherals.

The STM32H7A3/7B3 and STM32H7B0 are microcontrollers with different memory sizes, packages and peripherals.

The devices include ST state-of-the-art patented technology.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M7 with FPU cores, please refer to the corresponding Arm Technical Reference Manuals .

Contents

3.3RAMECC functional description . . . . .141
3.3.1RAMECC block diagram . . . . .141
3.3.2RAMECC internal signals . . . . .143
3.3.3RAMECC monitor mapping . . . . .143
3.4RAMECC registers . . . . .144
3.4.1RAMECC interrupt enable register (RAMECC_IER) . . . . .144
3.4.2RAMECC monitor x configuration register (RAMECC_MxCR) . . . . .145
3.4.3RAMECC monitor x status register (RAMECC_MxSR) . . . . .145
3.4.4RAMECC monitor x failing address register (RAMECC_MxFAR) . . . . .146
3.4.5RAMECC monitor x failing data low register (RAMECC_MxFDRL) . . . . .146
3.4.6RAMECC monitor x failing data high register (RAMECC_MxFDRH) . . . . .147
3.4.7RAMECC monitor x failing ECC error code register
RAMECC_MxFECR) . . . . .		147
3.4.8RAMECC register map . . . . .148
4Embedded flash memory (FLASH) . . . . .149
4.1Introduction . . . . .149
4.2FLASH main features . . . . .149
4.3FLASH functional description . . . . .150
4.3.1FLASH block diagram . . . . .150
4.3.2FLASH internal signals . . . . .151
4.3.3FLASH architecture and integration in the system . . . . .151
4.3.4Flash memory architecture and usage . . . . .153
4.3.5FLASH system performance enhancements . . . . .158
4.3.6FLASH data protection schemes . . . . .158
4.3.7Overview of FLASH operations . . . . .159
4.3.8FLASH read operations . . . . .160
4.3.9FLASH program operations . . . . .164
4.3.10FLASH erase operations . . . . .168
4.3.11FLASH parallel operations . . . . .171
4.3.12Flash memory error protections . . . . .171
4.3.13FLASH one-time programmable area . . . . .173
4.3.14FLASH read-only area . . . . .174
4.3.15Flash bank and register swapping (STM32H7A3/7B3 only) . . . . .175
4.3.16FLASH reset and clocks . . . . .179
4.4FLASH option bytes . . . . .179
4.4.1About option bytes . . . . .179
4.4.2Option byte loading . . . . .180
4.4.3Option byte modification . . . . .180
4.4.4Option bytes overview . . . . .182
4.4.5Description of user and system option bytes . . . . .186
4.4.6Description of data protection option bytes . . . . .187
4.4.7Description of boot address option bytes . . . . .188
4.5FLASH protection mechanisms . . . . .188
4.5.1FLASH configuration protection . . . . .188
4.5.2Write protection . . . . .190
4.5.3Readout protection (RDP) . . . . .191
4.5.4Proprietary code readout protection (PCROP) . . . . .195
4.5.5Secure access mode (STM32H7B0 and STM32H7B3 only) . . . . .196
4.6FLASH low-power modes . . . . .198
4.6.1Introduction . . . . .198
4.6.2Managing the FLASH domain switching to DStop or Standby . . . . .198
4.7FLASH error management . . . . .199
4.7.1Introduction . . . . .199
4.7.2Write protection error (WRPERR) . . . . .199
4.7.3Programming sequence error (PGSERR) . . . . .200
4.7.4Strobe error (STRBERR) . . . . .201
4.7.5Inconsistency error (INCERR) . . . . .201
4.7.6Error correction code error (SNECCERR/DBECCERR) . . . . .202
4.7.7Read protection error (RDPERR) . . . . .202
4.7.8Read secure error (RDSERR) . . . . .203
4.7.9CRC read error (CRCRDERR) . . . . .203
4.7.10Option byte change error (OPTCHANGEERR) . . . . .204
4.7.11Miscellaneous HardFault errors . . . . .204
4.8FLASH interrupts . . . . .204
4.9FLASH registers . . . . .207
4.9.1FLASH access control register (FLASH_ACR) . . . . .207
4.9.2FLASH key register for bank 1 (FLASH_KEYR1) . . . . .207
4.9.3FLASH option key register (FLASH_OPTKEYR) . . . . .208
4.9.4FLASH control register for bank 1 (FLASH_CR1) . . . . .208
4.9.5FLASH status register for bank 1 (FLASH_SR1) . . . . .212
4.9.6FLASH clear control register for bank 1 (FLASH_CCR1) . . . . .215
4.9.7FLASH option control register (FLASH_OPTCR) . . . . .216
4.9.8FLASH option status register (FLASH_OPTSR_CUR) . . . . .217
4.9.9FLASH option status register (FLASH_OPTSR_PRG) . . . . .220
4.9.10FLASH option clear control register (FLASH_OPTCCR) . . . . .222
4.9.11FLASH protection address for bank 1 (FLASH_PRAR_CUR1) . . . . .223
4.9.12FLASH protection address for bank 1 (FLASH_PRAR_PRG1) . . . . .223
4.9.13FLASH secure address for bank 1 (FLASH_SCAR_CUR1) . . . . .224
4.9.14FLASH secure address for bank 1 (FLASH_SCAR_PRG1) . . . . .225
4.9.15FLASH write sector group protection for bank 1
(FLASH_WPSGN_CUR1R) . . . . .		225
4.9.16FLASH write sector group protection for bank 1
(FLASH_WPSGN_PRG1R) . . . . .		226
4.9.17FLASH register boot address (FLASH_BOOT_CURR) . . . . .227
4.9.18FLASH register boot address FLASH_BOOT_PRGR) . . . . .227
4.9.19FLASH CRC control register for bank 1 (FLASH_CRCCR1) . . . . .228
4.9.20FLASH CRC start address register for bank 1
(FLASH_CRCSADD1R) . . . . .		229
4.9.21FLASH CRC end address register for bank 1
(FLASH_CRCEADD1R) . . . . .		230
4.9.22FLASH CRC data register (FLASH_CRCDATAR) . . . . .230
4.9.23FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) . . . . .231
4.9.24FLASH OTP block lock (FLASH_OTPBL_CUR) . . . . .231
4.9.25FLASH OTP block lock (FLASH_OTPBL_PRG) . . . . .232
4.9.26FLASH key register for bank 2 (FLASH_KEYR2) . . . . .232
4.9.27FLASH control register for bank 2 (FLASH_CR2) . . . . .233
4.9.28FLASH status register for bank 2 (FLASH_SR2) . . . . .237
4.9.29FLASH clear control register for bank 2 (FLASH_CCR2) . . . . .240
4.9.30FLASH protection address for bank 2 (FLASH_PRAR_CUR2) . . . . .241
4.9.31FLASH protection address for bank 2 (FLASH_PRAR_PRG2) . . . . .241
4.9.32FLASH secure address for bank 2 (FLASH_SCAR_CUR2) . . . . .242
4.9.33FLASH secure address for bank 2 (FLASH_SCAR_PRG2) . . . . .243
4.9.34FLASH write sector group protection for bank 2
(FLASH_WPSGN_CUR2R) . . . . .		244
4.9.35FLASH write sector group protection for bank 2
(FLASH_WPSGN_PRG2R) . . . . .		244
4.9.36FLASH CRC control register for bank 2 (FLASH_CRCCR2) . . . . .245
4.9.37FLASH CRC start address register for bank 2
(FLASH_CRCSADD2R) . . . . .		246
4.9.38FLASH CRC end address register for bank 2
(FLASH_CRCEADD2R) . . . . .		247

4.9.39 FLASH ECC fail address for bank 2 (FLASH_ECC_FA2R) . . . . . 247

4.9.40 FLASH register map and reset values . . . . . 248

5 Secure memory management (SMM) . . . . . 254

5.1 SMM introduction . . . . . 254

5.2 Glossary . . . . . 254

5.3 Secure access mode . . . . . 255

5.3.1 Associated features . . . . . 256

5.3.2 Boot state machine . . . . . 256

5.3.3 Secure access mode configuration . . . . . 257

5.4 Root secure services (RSS) . . . . . 258

5.4.1 Version service . . . . . 258

5.4.2 Secure area setting service . . . . . 258

5.4.3 Secure area exiting service . . . . . 259

5.4.4 OTFDEC encryption service . . . . . 260

5.5 Secure user software . . . . . 260

5.5.1 Access rules . . . . . 260

5.5.2 Setting secure user memory areas . . . . . 260

5.6 Summary of flash protection mechanisms . . . . . 261

6 Power control (PWR) . . . . . 262

6.1 Introduction . . . . . 262

6.2 PWR main features . . . . . 262

6.3 PWR block diagram . . . . . 263

6.4 Power supplies . . . . . 265

6.4.1 System supply startup . . . . . 271

6.4.2 Core domain . . . . . 275

6.4.3 Voltage regulators . . . . . 275

6.4.4 PWR external supply . . . . . 277

6.4.5 Backup domain . . . . . 277

6.4.6 VBAT battery charging . . . . . 279

6.4.7 Analog supply . . . . . 279

6.4.8 USB regulator . . . . . 280

6.5 Power supply supervision . . . . . 281

6.5.1 Power-on reset (POR)/power-down reset (PDR) . . . . . 281

6.5.2 Brownout reset (BOR) . . . . . 282

6.5.3Programmable voltage detector (PVD) . . . . .283
6.5.4Analog voltage detector (AVD) . . . . .284
6.5.5Battery voltage thresholds . . . . .285
6.5.6Temperature thresholds . . . . .286
6.5.7V CORE maximum voltage level detector . . . . .286
6.6Power management . . . . .287
6.6.1System operating modes . . . . .289
6.6.2Voltage scaling . . . . .292
6.6.3Power control modes . . . . .293
6.6.4Power management examples . . . . .295
6.7Low-power modes . . . . .303
6.7.1Slowing down system clocks . . . . .303
6.7.2Controlling peripheral clocks . . . . .303
6.7.3Entering low-power modes . . . . .303
6.7.4Exiting from low-power modes . . . . .304
6.7.5System Run and CSleep modes . . . . .305
6.7.6System Autonomous mode . . . . .305
6.7.7Stop mode . . . . .307
6.7.8Standby mode . . . . .310
6.7.9Monitoring low-power modes . . . . .312
6.8PWR registers . . . . .313
6.8.1PWR control register 1 (PWR_CR1) . . . . .313
6.8.2PWR control status register 1 (PWR_CSR1) . . . . .315
6.8.3PWR control register 2 (PWR_CR2) . . . . .317
6.8.4PWR control register 3 (PWR_CR3) . . . . .318
6.8.5PWR CPU control register (PWR_CPUCR) . . . . .320
6.8.6PWR SmartRun domain control register (PWR_SRDCR) . . . . .321
6.8.7PWR wake-up clear register (PWR_WKUPCR) . . . . .322
6.8.8PWR wake-up flag register (PWR_WKUPFR) . . . . .322
6.8.9PWR wake-up enable and polarity register (PWR_WKUPEPR) . . . . .323
6.8.10PWR register map . . . . .324
7Low-power SRD domain application example . . . . .325
7.1Introduction . . . . .325
7.2EXTI, RCC and PWR interconnections . . . . .325
7.2.1Interrupts and wake-up . . . . .327
7.2.2Block interactions . . . . .327

8 Reset and clock control (RCC) . . . . . 337

8.7.1RCC source control register (RCC_CR) . . . . .388
8.7.2RCC HSI calibration register (RCC_HSICFGR) . . . . .392
8.7.3RCC clock recovery RC register (RCC_CRRRCR) . . . . .392
8.7.4RCC CSI calibration register (RCC_CSICFGR) . . . . .393
8.7.5RCC clock configuration register (RCC_CFGR) . . . . .394
8.7.6RCC CPU domain clock configuration register 1 (RCC_CDCFGR1) . . . . .396
8.7.7RCC CPU domain clock configuration register 2 (RCC_CDCFGR2) . . . . .398
8.7.8RCC SmartRun domain clock configuration register
(RCC_SRDCFGR) . . . . .		398
8.7.9RCC PLLs clock source selection register (RCC_PLLCKSELR) . . . . .399
8.7.10RCC PLLs configuration register (RCC_PLLCFGR) . . . . .401
8.7.11RCC PLL1 dividers configuration register (RCC_PLL1DIVR) . . . . .403
8.7.12RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .405
8.7.13RCC PLL2 dividers configuration register (RCC_PLL2DIVR) . . . . .405
8.7.14RCC PLL2 fractional divider register (RCC_PLL2FRACR) . . . . .407
8.7.15RCC PLL3 dividers configuration register (RCC_PLL3DIVR) . . . . .407
8.7.16RCC PLL3 fractional divider register (RCC_PLL3FRACR) . . . . .409
8.7.17RCC CPU domain kernel clock configuration register
(RCC_CDCCIPR) . . . . .		409
8.7.18RCC CPU domain kernel clock configuration register
(RCC_CDCCIP1R) . . . . .		410
8.7.19RCC CPU domain kernel clock configuration register
(RCC_CDCCIP2R) . . . . .		413
8.7.20RCC SmartRun domain kernel clock configuration register
(RCC_SRDCCIPR) . . . . .		415
8.7.21RCC clock source interrupt enable register (RCC_CIER) . . . . .417
8.7.22RCC clock source interrupt flag register (RCC_CIFR) . . . . .418
8.7.23RCC clock source interrupt clear register (RCC_CICR) . . . . .420
8.7.24RCC Backup domain control register (RCC_BDCR) . . . . .422
8.7.25RCC clock control and status register (RCC_CSR) . . . . .424
8.7.26RCC AHB3 reset register (RCC_AHB3RSTR) . . . . .424
8.7.27RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .426
8.7.28RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .427
8.7.29RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .428
8.7.30RCC APB3 peripheral reset register (RCC_APB3RSTR) . . . . .430
8.7.31RCC APB1 peripheral reset register (RCC_APB1LRSTR) . . . . .430
8.7.32RCC APB1 peripheral reset register (RCC_APB1HRSTR) . . . . .433
8.7.33RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .434
8.7.34RCC APB4 peripheral reset register (RCC_APB4RSTR) . . . . .436
8.7.35RCC SmartRun domain Autonomous mode register
(RCC_SRDRAMR) . . . . .		438
8.7.36RCC AXI clocks gating enable register (RCC_CKGAENR) . . . . .441
8.7.37RCC reset status register (RCC_RSR) . . . . .444
8.7.38RCC AHB3 clock register (RCC_AHB3ENR) . . . . .446
8.7.39RCC AHB1 clock register (RCC_AHB1ENR) . . . . .447
8.7.40RCC AHB2 clock register (RCC_AHB2ENR) . . . . .449
8.7.41RCC AHB4 Clock Register (RCC_AHB4ENR) . . . . .450
8.7.42RCC APB3 clock register (RCC_APB3ENR) . . . . .452
8.7.43RCC APB1 clock register (RCC_APB1LENR) . . . . .453
8.7.44RCC APB1 clock register (RCC_APB1HENR) . . . . .456
8.7.45RCC APB2 clock register (RCC_APB2ENR) . . . . .457
8.7.46RCC APB4 clock register (RCC_APB4ENR) . . . . .459
8.7.47RCC AHB3 sleep clock register (RCC_AHB3LPENR) . . . . .461
8.7.48RCC AHB1 sleep clock register (RCC_AHB1LPENR) . . . . .464
8.7.49RCC AHB2 sleep clock register (RCC_AHB2LPENR) . . . . .465
8.7.50RCC AHB4 sleep clock register (RCC_AHB4LPENR) . . . . .466
8.7.51RCC APB3 sleep clock register (RCC_APB3LPENR) . . . . .468
8.7.52RCC APB1 low-sleep clock register (RCC_APB1LLPENR) . . . . .469
8.7.53RCC APB1 high-sleep clock register (RCC_APB1HLPENR) . . . . .472
8.7.54RCC APB2 sleep clock register (RCC_APB2LPENR) . . . . .473
8.7.55RCC APB4 sleep clock register (RCC_APB4LPENR) . . . . .475
8.8RCC register map . . . . .477
9Clock recovery system (CRS) . . . . .484
9.1CRS introduction . . . . .484
9.2CRS main features . . . . .484
9.3CRS implementation . . . . .484
9.4CRS functional description . . . . .485
9.4.1CRS block diagram . . . . .485
9.4.2CRS internal signals . . . . .485
9.4.3Synchronization input . . . . .486
9.4.4Frequency error measurement . . . . .486
9.4.5Frequency error evaluation and automatic trimming . . . . .487
9.4.6CRS initialization and configuration . . . . .488
9.5CRS in low-power modes . . . . .489
9.6CRS interrupts . . . . .489
9.7CRS registers . . . . .489
9.7.1CRS control register (CRS_CR) . . . . .489
9.7.2CRS configuration register (CRS_CFGR) . . . . .491
9.7.3CRS interrupt and status register (CRS_ISR) . . . . .492
9.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .494
9.7.5CRS register map . . . . .494
10Hardware semaphore (HSEM) . . . . .496
10.1HSEM introduction . . . . .496
10.2HSEM main features . . . . .496
10.3Functional description . . . . .497
10.3.1HSEM block diagram . . . . .497
10.3.2HSEM internal signals . . . . .497
10.3.3HSEM lock procedures . . . . .497
10.3.4HSEM write/read/read lock register address . . . . .499
10.3.5HSEM unlock procedures . . . . .499
10.3.6HSEM MASTERID semaphore clear . . . . .500
10.3.7HSEM interrupts . . . . .500
10.3.8AHB bus master ID verification . . . . .502
10.4HSEM registers . . . . .503
10.4.1HSEM register semaphore x (HSEM_Rx) . . . . .503
10.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .504
10.4.3HSEM interrupt enable register (HSEM_IER) . . . . .505
10.4.4HSEM interrupt clear register (HSEM_ICR) . . . . .505
10.4.5HSEM interrupt status register (HSEM_ISR) . . . . .505
10.4.6HSEM interrupt status register (HSEM_MISR) . . . . .506
10.4.7HSEM clear register (HSEM_CR) . . . . .506
10.4.8HSEM clear semaphore key register (HSEM_KEYR) . . . . .507
10.4.9HSEM register map . . . . .508
11General-purpose I/Os (GPIO) . . . . .509
11.1Introduction . . . . .509
11.2GPIO main features . . . . .509
11.3GPIO functional description . . . . .509
11.3.1General-purpose I/O (GPIO) . . . . .512
12.3SYSCFG functional description . . . . .529
12.3.1Analog switch configuration management . . . . .529
12.3.2I2C Fm+ configuration . . . . .529
12.3.3Timer break input lockup management . . . . .530
12.3.4Management of external interrupt line connections to GPIOs . . . . .530
12.3.5I/O speed in low-voltage mode . . . . .530
12.3.6I/O compensation cell management . . . . .530
12.4SYSCFG registers . . . . .531
12.4.1SYSCFG peripheral mode configuration register (SYSCFG_PMCR) . . . . .531
12.4.2SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		533
12.4.3SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		534
12.4.4SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		535
12.4.5SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		536
12.4.6SYSCFG timer break lockup register
(SYSCFG_CFGR) . . . . .		536
12.4.7SYSCFG compensation cell control/status register
(SYSCFG_CCCSR) . . . . .		538
12.4.8SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . .539
12.4.9SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . .540
12.4.10SYSCFG register maps . . . . .541
13Block interconnect . . . . .542
13.1Peripheral interconnect . . . . .542
13.1.1Introduction . . . . .542
13.1.2Connection overview . . . . .542
13.2Wakeup from low-power modes . . . . .555
13.3DMA . . . . .560
13.3.1MDMA (CD domain) . . . . .561
13.3.2DMAMUX1, DMA1, DMA2 and BDMA1 (CD domain) . . . . .563
13.3.3DMAMUX2, BDMA2 (SRD domain) . . . . .568
14MDMA controller (MDMA) . . . . .571
14.1MDMA introduction . . . . .571
14.2MDMA main features . . . . .571
14.3MDMA functional description . . . . .573
14.3.1MDMA block diagram . . . . .573
14.3.2MDMA internal signals . . . . .573
14.3.3MDMA overview . . . . .573
14.3.4MDMA channel . . . . .575
14.3.5Source, destination and transfer modes . . . . .575
14.3.6Pointer update . . . . .575
14.3.7MDMA buffer transfer . . . . .576
14.3.8Request arbitration . . . . .577
14.3.9FIFO . . . . .577
14.3.10Block transfer . . . . .577
14.3.11Block repeat mode . . . . .578
14.3.12Linked-list mode . . . . .578
14.3.13MDMA transfer completion . . . . .578
14.3.14MDMA transfer suspension . . . . .578
14.3.15Error management . . . . .579
14.4MDMA interrupts . . . . .579
14.5MDMA registers . . . . .580
14.5.1MDMA global interrupt status register (MDMA_GISR0) . . . . .580
14.5.2MDMA channel x interrupt status register (MDMA_CxISR) . . . . .580
14.5.3MDMA channel x interrupt flag clear register (MDMA_CxIFCR) . . . . .582
14.5.4MDMA channel x error status register (MDMA_CxESR) . . . . .582
14.5.5MDMA channel x control register (MDMA_CxCR) . . . . .583
14.5.6MDMA channel x transfer configuration register (MDMA_CxTCR) . . . . .585
14.5.7MDMA channel x block number of data register (MDMA_CxBNDTR) . . . . .589
14.5.8MDMA channel x source address register (MDMA_CxSAR) . . . . .590
14.5.9MDMA channel x destination address register (MDMA_CxDAR) . . . . .591
14.5.10MDMA channel x block repeat address update register
(MDMA_CxBRUR) . . . . .		591
14.5.11MDMA channel x link address register (MDMA_CxLAR) . . . . .592
14.5.12MDMA channel x trigger and bus selection register
(MDMA_CxTBR) . . . . .		593
14.5.13MDMA channel x mask address register (MDMA_CxMAR) . . . . .594
14.5.14MDMA channel x mask data register (MDMA_CxMDR) . . . . .594
14.5.15MDMA register map . . . . .595
15Direct memory access controller (DMA) . . . . .596
15.1DMA introduction . . . . .596
15.2DMA main features . . . . .596
15.3DMA functional description . . . . .598
15.3.1DMA block diagram . . . . .598
15.3.2DMA internal signals . . . . .598
15.3.3DMA overview . . . . .598
15.3.4DMA transactions . . . . .599
15.3.5DMA request mapping . . . . .599
15.3.6Arbiter . . . . .600
15.3.7DMA streams . . . . .600
15.3.8Source, destination and transfer modes . . . . .600
15.3.9Pointer incrementation . . . . .604
15.3.10Circular mode . . . . .605
15.3.11Double-buffer mode . . . . .605
15.3.12Programmable data width, packing/unpacking, endianness . . . . .606
15.3.13Single and burst transfers . . . . .607
15.3.14FIFO . . . . .608
15.3.15DMA transfer completion . . . . .611
15.3.16DMA transfer suspension . . . . .612
15.3.17Flow controller . . . . .613
15.3.18Summary of the possible DMA configurations . . . . .614
15.3.19Stream configuration procedure . . . . .614
15.3.20Error management . . . . .615
15.4DMA interrupts . . . . .616
15.5DMA registers . . . . .617
15.5.1DMA low interrupt status register (DMA_LISR) . . . . .617
15.5.2DMA high interrupt status register (DMA_HISR) . . . . .618
15.5.3DMA low interrupt flag clear register (DMA_LIFCR) . . . . .618
15.5.4DMA high interrupt flag clear register (DMA_HIFCR) . . . . .619
15.5.5DMA stream x configuration register (DMA_SxCR) . . . . .620
15.5.6DMA stream x number of data register (DMA_SxNDTR) . . . . .623
15.5.7DMA stream x peripheral address register (DMA_SxPAR) . . . . .623
15.5.8DMA stream x memory 0 address register
(DMA_SxM0AR) . . . . .		624
15.5.9DMA stream x memory 1 address register
(DMA_SxM1AR) . . . . .		624
15.5.10DMA stream x FIFO control register (DMA_SxFCR) . . . . .625
15.5.11DMA register map .....626
16Basic direct memory access controller (BDMA) .....630
16.1Introduction .....630
16.2BDMA main features .....630
16.3BDMA implementation .....631
16.3.1BDMA1 and BDMA2 .....631
16.3.2BDMA request mapping .....631
16.4BDMA functional description .....632
16.4.1BDMA block diagram .....632
16.4.2BDMA pins and internal signals .....634
16.4.3BDMA transfers .....634
16.4.4BDMA arbitration .....635
16.4.5BDMA channels .....635
16.4.6BDMA data width, alignment and endianness .....640
16.4.7BDMA error management .....641
16.5BDMA interrupts .....642
16.6BDMA registers .....642
16.6.1BDMA interrupt status register (BDMA_ISR) .....642
16.6.2BDMA interrupt flag clear register (BDMA_IFCR) .....645
16.6.3BDMA channel x configuration register (BDMA_CCRx) .....646
16.6.4BDMA channel x number of data to transfer register
(BDMA_CNDTRx) .....		650
16.6.5BDMA channel x peripheral address register (BDMA_CPARx) .....650
16.6.6BDMA channel x memory 0 address register (BDMA_CM0ARx) .....651
16.6.7BDMA channel x memory 1 address register (BDMA_CM1ARx) .....652
16.6.8BDMA register map .....652
17DMA request multiplexer (DMAMUX) .....655
17.1Introduction .....655
17.2DMAMUX main features .....656
17.3DMAMUX implementation .....656
17.3.1DMAMUX1 and DMAMUX2 instantiation .....656
17.3.2DMAMUX1 mapping .....656
17.3.3DMAMUX2 mapping .....658
17.4DMAMUX functional description .....661
17.4.1DMAMUX block diagram . . . . .661
17.4.2DMAMUX signals . . . . .662
17.4.3DMAMUX channels . . . . .662
17.4.4DMAMUX request line multiplexer . . . . .662
17.4.5DMAMUX request generator . . . . .665
17.5DMAMUX interrupts . . . . .666
17.6DMAMUX registers . . . . .667
17.6.1DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR) . . . . .667
17.6.2DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR) . . . . .668
17.6.3DMAMUX1 request line multiplexer interrupt channel status register (DMAMUX1_CSR) . . . . .669
17.6.4DMAMUX2 request line multiplexer interrupt channel status register (DMAMUX2_CSR) . . . . .669
17.6.5DMAMUX1 request line multiplexer interrupt clear flag register (DMAMUX1_CFR) . . . . .670
17.6.6DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) . . . . .670
17.6.7DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) . . . . .671
17.6.8DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR) . . . . .671
17.6.9DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR) . . . . .673
17.6.10DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR) . . . . .673
17.6.11DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR) . . . . .674
17.6.12DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR) . . . . .674
17.6.13DMAMUX register map . . . . .675
18Chrom-ART Accelerator controller (DMA2D) . . . . .679
18.1DMA2D introduction . . . . .679
18.2DMA2D main features . . . . .679
18.3DMA2D functional description . . . . .680
18.3.1General description . . . . .680
18.3.2DMA2D internal signals . . . . .681
18.3.3DMA2D control . . . . .681
18.3.4DMA2D foreground and background FIFOs . . . . .682
18.3.5DMA2D foreground and background PFC . . . . .682
18.3.6DMA2D foreground and background CLUT interface . . . . .684
18.3.7DMA2D blender . . . . .685
18.3.8DMA2D output PFC . . . . .685
18.3.9DMA2D output FIFO . . . . .686
18.3.10DMA2D output FIFO byte reordering . . . . .687
18.3.11DMA2D AXI master port timer . . . . .688
18.3.12DMA2D transactions . . . . .688
18.3.13DMA2D configuration . . . . .689
18.3.14YCbCr support . . . . .693
18.3.15DMA2D transfer control (start, suspend, abort, and completion) . . . . .693
18.3.16Watermark . . . . .693
18.3.17Error management . . . . .693
18.3.18AXI dead time . . . . .694
18.4DMA2D interrupts . . . . .694
18.5DMA2D registers . . . . .695
18.5.1DMA2D control register (DMA2D_CR) . . . . .695
18.5.2DMA2D interrupt status register (DMA2D_ISR) . . . . .696
18.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .697
18.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . . . .698
18.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .698
18.5.6DMA2D background memory address register (DMA2D_BGMAR) . . . . .699
18.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .699
18.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .700
18.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .701
18.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .702
18.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .703
18.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		704
18.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		704
18.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .705
18.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .706
18.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .706
18.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .707
18.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .707
18.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .708
18.5.20DMA2D output offset register (DMA2D_OOR) . . . . .708
18.5.21DMA2D number of line register (DMA2D_NLR) . . . . .709
18.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .709
18.5.23DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . .710
18.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .710
18.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .711
18.5.26DMA2D register map . . . . .711
19Nested vectored interrupt controller (NVIC) . . . . .713
19.1NVIC features . . . . .713
19.1.1SysTick calibration value register . . . . .713
19.1.2Interrupt and exception vectors . . . . .713
20Extended interrupt and event controller (EXTI) . . . . .722
20.1EXTI main features . . . . .722
20.2EXTI block diagram . . . . .723
20.2.1EXTI connections between peripherals, CPU and SRD domain . . . . .723
20.3EXTI functional description . . . . .724
20.3.1EXTI configurable event input CPU wakeup . . . . .725
20.3.2EXTI configurable event input Any wakeup . . . . .726
20.3.3EXTI direct event input CPU wakeup . . . . .728
20.3.4EXTI direct event input Any wakeup . . . . .729
20.3.5EXTI SRD pending request clear selection . . . . .730
20.4EXTI event input mapping . . . . .730
20.5EXTI functional behavior . . . . .733
20.5.1EXTI CPU interrupt procedure . . . . .734
20.5.2EXTI CPU event procedure . . . . .734
20.5.3EXTI CPU wakeup procedure . . . . .735
20.5.4EXTI SRD domain wakeup for Autonomous run mode procedure . . . . .735
20.5.5EXTI software interrupt/event trigger procedure . . . . .735
20.6EXTI registers . . . . .736
20.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .736
20.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .736
20.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .737
20.6.4EXTI SRD pending mask register (EXTI_SRDPMR1) . . . . .737
20.6.5EXTI SRD pending clear selection register low (EXTI_SRDPCR1L)738
20.6.6EXTI SRD pending clear selection register high (EXTI_SRDPCR1H)739
20.6.7EXTI rising trigger selection register (EXTI_RTSR2)739
20.6.8EXTI falling trigger selection register (EXTI_FTSR2)740
20.6.9EXTI software interrupt event register (EXTI_SWIER2)741
20.6.10EXTI SRD pending mask register (EXTI_SRDPMR2)742
20.6.11EXTI SRD pending clear selection register low (EXTI_SRDPCR2L)742
20.6.12EXTI SRD pending clear selection register high (EXTI_SRDPCR2H)743
20.6.13EXTI rising trigger selection register (EXTI_RTSR3)744
20.6.14EXTI falling trigger selection register (EXTI_FTSR3)744
20.6.15EXTI software interrupt event register (EXTI_SWIER3)745
20.6.16EXTI SRD pending mask register (EXTI_SRDPMR3)746
20.6.17EXTI SRD pending clear selection register high (EXTI_SRDPCR3H)746
20.6.18EXTI interrupt mask register (EXTI_CPUIMR1)747
20.6.19EXTI event mask register (EXTI_CPUEMR1)747
20.6.20EXTI pending register (EXTI_CPUPR1)748
20.6.21EXTI interrupt mask register (EXTI_CPUIMR2)748
20.6.22EXTI event mask register (EXTI_CPUEMR2)749
20.6.23EXTI pending register (EXTI_CPUPR2)750
20.6.24EXTI interrupt mask register (EXTI_CPUIMR3)750
20.6.25EXTI event mask register (EXTI_CPUEMR3)752
20.6.26EXTI pending register (EXTI_CPUPR3)753
20.6.27EXTI register map753
21Chrom-GRC (GFXMMU)756
21.1Introduction756
21.2GFXMMU main features756
21.3GFXMMU functional and architectural description757
21.3.1Virtual memory757
21.3.2MMU architecture759
21.3.3Cache and prefetch mechanism762
21.4GFXMMU interrupts765
21.5GFXMMU registers766
21.5.1GFXMMU configuration register (GFXMMU_CR)766
21.5.2GFXMMU status register (GFXMMU_SR)767
21.5.3GFXMMU flag clear register (GFXMMU_FCR)768
21.5.4GFXMMU cache control register (GFXMMU_CCR)769
21.5.5GFXMMU default value register (GFXMMU_DVR) . . . . .769
21.5.6GFXMMU buffer 0 configuration register (GFXMMU_B0CR) . . . . .770
21.5.7GFXMMU buffer 1 configuration register (GFXMMU_B1CR) . . . . .770
21.5.8GFXMMU buffer 2 configuration register (GFXMMU_B2CR) . . . . .771
21.5.9GFXMMU buffer 3 configuration register (GFXMMU_B3CR) . . . . .771
21.5.10GFXMMU LUT entry x low (GFXMMU_LUTxL) . . . . .772
21.5.11GFXMMU LUT entry x high (GFXMMU_LUTxH) . . . . .772
21.5.12GFXMMU register map . . . . .773
22Cyclic redundancy check calculation unit (CRC) . . . . .774
22.1CRC introduction . . . . .774
22.2CRC main features . . . . .774
22.3CRC functional description . . . . .775
22.3.1CRC block diagram . . . . .775
22.3.2CRC internal signals . . . . .775
22.3.3CRC operation . . . . .775
22.4CRC registers . . . . .777
22.4.1CRC data register (CRC_DR) . . . . .777
22.4.2CRC independent data register (CRC_IDR) . . . . .777
22.4.3CRC control register (CRC_CR) . . . . .778
22.4.4CRC initial value (CRC_INIT) . . . . .779
22.4.5CRC polynomial (CRC_POL) . . . . .779
22.4.6CRC register map . . . . .780
23Flexible memory controller (FMC) . . . . .781
23.1FMC main features . . . . .781
23.2FMC block diagram . . . . .782
23.3FMC internal signals . . . . .784
23.4AHB interface . . . . .784
23.5AXI interface . . . . .784
23.5.1Supported memories and transactions . . . . .785
23.6External device address mapping . . . . .786
23.6.1NOR/PSRAM address mapping . . . . .787
23.6.2NAND flash memory address mapping . . . . .787
23.6.3SDRAM address mapping . . . . .788
23.7NOR flash/PSRAM controller . . . . .792
23.7.1External memory interface signals . . . . .793
23.7.2Supported memories and transactions . . . . .795
23.7.3General timing rules . . . . .796
23.7.4NOR flash/PSRAM controller asynchronous transactions . . . . .797
23.7.5Synchronous transactions . . . . .816
23.7.6NOR/PSRAM controller registers . . . . .822
23.8NAND flash controller . . . . .831
23.8.1External memory interface signals . . . . .831
23.8.2NAND flash supported memories and transactions . . . . .832
23.8.3Timing diagrams for NAND flash memories . . . . .833
23.8.4NAND flash operations . . . . .834
23.8.5NAND flash prewait feature . . . . .835
23.8.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		836
23.8.7NAND flash controller registers . . . . .837
23.9SDRAM controller . . . . .843
23.9.1SDRAM controller main features . . . . .843
23.9.2SDRAM External memory interface signals . . . . .843
23.9.3SDRAM controller functional description . . . . .844
23.9.4Low-power modes . . . . .851
23.9.5SDRAM controller registers . . . . .853
23.9.6FMC register map . . . . .860
24Octo-SPI interface (OCTOSPI) . . . . .863
24.1OCTOSPI introduction . . . . .863
24.2OCTOSPI main features . . . . .863
24.3OCTOSPI implementation . . . . .864
24.4OCTOSPI functional description . . . . .865
24.4.1OCTOSPI block diagram . . . . .865
24.4.2OCTOSPI pins and internal signals . . . . .866
24.4.3OCTOSPI interface to memory modes . . . . .867
24.4.4OCTOSPI regular-command protocol . . . . .867
24.4.5OCTOSPI regular-command protocol signal interface . . . . .871
24.4.6HyperBus protocol . . . . .874
24.4.7Specific features . . . . .878
24.4.8OCTOSPI operating mode introduction . . . . .880
24.4.9OCTOSPI indirect mode . . . . .880
24.4.10OCTOSPI automatic status-polling mode . . . . .882
24.4.11OCTOSPI memory-mapped mode . . . . .883
24.4.12OCTOSPI configuration introduction . . . . .884
24.4.13OCTOSPI system configuration . . . . .884
24.4.14OCTOSPI device configuration . . . . .884
24.4.15OCTOSPI regular-command mode configuration . . . . .887
24.4.16OCTOSPI HyperBus protocol configuration . . . . .889
24.4.17OCTOSPI error management . . . . .890
24.4.18OCTOSPI BUSY and ABORT . . . . .891
24.4.19OCTOSPI reconfiguration or deactivation . . . . .891
24.4.20NCS behavior . . . . .891
24.5Address alignment and data number . . . . .893
24.6OCTOSPI interrupts . . . . .894
24.7OCTOSPI registers . . . . .894
24.7.1OCTOSPI control register (OCTOSPI_CR) . . . . .894
24.7.2OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . .897
24.7.3OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . .899
24.7.4OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . .900
24.7.5OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . .901
24.7.6OCTOSPI status register (OCTOSPI_SR) . . . . .901
24.7.7OCTOSPI flag clear register (OCTOSPI_FCR) . . . . .902
24.7.8OCTOSPI data length register (OCTOSPI_DLR) . . . . .903
24.7.9OCTOSPI address register (OCTOSPI_AR) . . . . .903
24.7.10OCTOSPI data register (OCTOSPI_DR) . . . . .904
24.7.11OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . .904
24.7.12OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . .905
24.7.13OCTOSPI polling interval register (OCTOSPI_PIR) . . . . .905
24.7.14OCTOSPI communication configuration register (OCTOSPI_CCR) . . . . .906
24.7.15OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . .908
24.7.16OCTOSPI instruction register (OCTOSPI_IR) . . . . .908
24.7.17OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . .909
24.7.18OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . .909
24.7.19OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . .		910
24.7.20OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . . . .912
24.7.21OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . .912
24.7.22OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . .913

24.7.23 OCTOSPI write communication configuration register (OCTOSPI_WCCR) . . . . . 913

24.7.24 OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . . 915

24.7.25 OCTOSPI write instruction register (OCTOSPI_WIR) . . . . . 916

24.7.26 OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . . 916

24.7.27 OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR) . . . . . 917

24.7.28 OCTOSPI register map . . . . . 917

25 Octo-SPI I/O manager (OCTOSPIM) . . . . . 921

25.1 Introduction . . . . . 921

25.2 OCTOSPIM main features . . . . . 921

25.3 OCTOSPIM implementation . . . . . 921

25.4 OCTOSPIM functional description . . . . . 921

25.4.1 OCTOSPIM block diagram . . . . . 921

25.4.2 OCTOSPIM input/output pins . . . . . 922

25.4.3 OCTOSPIM matrix . . . . . 923

25.4.4 OCTOSPIM multiplexed mode . . . . . 923

25.5 OCTOSPIM registers . . . . . 925

25.5.1 OCTOSPIM control register (OCTOSPIM_CR) . . . . . 925

25.5.2 OCTOSPIM Port n configuration register (OCTOSPIM_PnCR) . . . . . 925

25.5.3 OCTOSPIM register map . . . . . 927

26 Delay block (DLYB) . . . . . 928

26.1 DLYB introduction . . . . . 928

26.2 DLYB main features . . . . . 928

26.3 DLYB functional description . . . . . 928

26.3.1 DLYB diagram . . . . . 928

26.3.2 DLYB pins and internal signals . . . . . 929

26.3.3 General description . . . . . 929

26.3.4 Delay line length configuration procedure . . . . . 930

26.3.5 Output clock phase configuration procedure . . . . . 930

26.4 DLYB registers . . . . . 931

26.4.1 DLYB control register (DLYB_CR) . . . . . 931

26.4.2 DLYB configuration register (DLYB_CFGR) . . . . . 932

26.4.3 DLYB register map . . . . . 932

27Analog-to-digital converters (ADC) . . . . .933
27.1ADC introduction . . . . .933
27.2ADC main features . . . . .934
27.3ADC implementation . . . . .935
27.4ADC functional description . . . . .936
27.4.1ADC block diagram . . . . .936
27.4.2ADC pins and internal signals . . . . .937
27.4.3ADC clocks . . . . .938
27.4.4ADC1/2 connectivity . . . . .940
27.4.5Slave AHB interface . . . . .942
27.4.6ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .942
27.4.7Single-ended and differential input channels . . . . .943
27.4.8Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) . . . . .943
27.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .949
27.4.10Constraints when writing the ADC control bits . . . . .950
27.4.11Channel selection (SQRx, JSQRx) . . . . .951
27.4.12Channel preselection register (ADC_PCSEL) . . . . .951
27.4.13Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .952
27.4.14Single conversion mode (CONT=0) . . . . .953
27.4.15Continuous conversion mode (CONT=1) . . . . .953
27.4.16Starting conversions (ADSTART, JADSTART) . . . . .954
27.4.17Timing . . . . .955
27.4.18Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .955
27.4.19Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .957
27.4.20Injected channel management . . . . .960
27.4.21Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .962
27.4.22Queue of context for injected conversions . . . . .963
27.4.23Programmable resolution (RES) - fast conversion mode . . . . .971
27.4.24End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .971
27.4.25End of conversion sequence (EOS, JEOS) . . . . .971
27.4.26Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .972
27.4.27Data management . . . . .973
27.4.28Managing conversions using the DFSDM . . . . .981
27.4.29Dynamic low-power features . . . . .981
27.4.30Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)986
27.4.31Oversampler989
27.4.32Dual ADC modes995
27.4.33Temperature sensor1009
27.4.34VBAT supply monitoring1010
27.4.35Monitoring the internal voltage reference1011
27.5ADC interrupts1013
27.6ADC registers (for each ADC)1014
27.6.1ADC interrupt and status register (ADC_ISR)1014
27.6.2ADC interrupt enable register (ADC_IER)1017
27.6.3ADC control register (ADC_CR)1019
27.6.4ADC configuration register (ADC_CFGR)1024
27.6.5ADC configuration register 2 (ADC_CFGR2)1029
27.6.6ADC sample time register 1 (ADC_SMPR1)1031
27.6.7ADC sample time register 2 (ADC_SMPR2)1032
27.6.8ADC channel preselection register (ADC_PCSEL)1033
27.6.9ADC watchdog threshold register 1 (ADC_LTR1)1033
27.6.10ADC watchdog threshold register 1 (ADC_HTR1)1034
27.6.11ADC regular sequence register 1 (ADC_SQR1)1035
27.6.12ADC regular sequence register 2 (ADC_SQR2)1036
27.6.13ADC regular sequence register 3 (ADC_SQR3)1037
27.6.14ADC regular sequence register 4 (ADC_SQR4)1038
27.6.15ADC regular Data Register (ADC_DR)1039
27.6.16ADC injected sequence register (ADC_JSQR)1040
27.6.17ADC injected channel y offset register (ADC_OF Ry)1042
27.6.18ADC injected channel y data register (ADC_JDRy)1043
27.6.19ADC analog watchdog 2 configuration register (ADC_AWD2CR)1043
27.6.20ADC analog watchdog 3 configuration register (ADC_AWD3CR)1044
27.6.21ADC watchdog lower threshold register 2 (ADC_LTR2)1044
27.6.22ADC watchdog higher threshold register 2 (ADC_HTR2)1045
27.6.23ADC watchdog lower threshold register 3 (ADC_LTR3)1045
27.6.24ADC watchdog higher threshold register 3 (ADC_HTR3)1046
27.6.25ADC differential mode selection register (ADC_DIFSEL)1046
27.6.26ADC calibration factors register (ADC_CALFACT)1047
27.6.27ADC calibration factor register 2 (ADC_CALFACT2)1047
27.7ADC common registers . . . . .1048
27.7.1ADC xcommon status register (ADCx_CSR) (x=1/2) . . . . .1048
27.7.2ADC x common control register (ADCx_CCR) (x=1/2) . . . . .1050
27.7.3ADC x common regular data register for dual mode
(ADCx_CDR) (x=1/2) . . . . .		1053
27.7.4ADC x common regular data register for 32-bit dual mode
(ADCx_CDR2) (x=1/2) . . . . .		1053
27.8ADC register map . . . . .1054
28Digital temperature sensor (DTS) . . . . .1058
28.1DTS introduction . . . . .1058
28.2DTS main features . . . . .1058
28.3DTS functional description . . . . .1059
28.3.1DTS block diagram . . . . .1059
28.3.2DTS internal signals . . . . .1059
28.3.3DTS block operation . . . . .1060
28.3.4Operating modes . . . . .1060
28.3.5Calibration . . . . .1060
28.3.6Prescaler . . . . .1060
28.3.7Temperature measurement principles . . . . .1061
28.3.8Sampling time . . . . .1062
28.3.9Trigger input . . . . .1062
28.3.10On-off control and ready flag . . . . .1063
28.3.11Temperature measurement sequence . . . . .1063
28.4DTS low-power modes . . . . .1064
28.5DTS interrupts . . . . .1065
28.5.1Temperature window comparator . . . . .1065
28.5.2Synchronous interrupt . . . . .1065
28.5.3Asynchronous wake-up . . . . .1065
28.6DTS registers . . . . .1066
28.6.1Temperature sensor configuration register 1 (DTS_CFGR1) . . . . .1066
28.6.2Temperature sensor T0 value register 1 (DTS_T0VALR1) . . . . .1067
28.6.3Temperature sensor ramp value register (DTS_RAMPVALR) . . . . .1068
28.6.4Temperature sensor interrupt threshold register 1 (DTS_ITR1) . . . . .1069
28.6.5Temperature sensor data register (DTS_DR) . . . . .1069
28.6.6Temperature sensor status register (DTS_SR) . . . . .1070
28.6.7Temperature sensor interrupt enable register (DTS_ITENR) . . . . .1071
28.6.8Temperature sensor clear interrupt flag register (DTS_ICIFR) . . . . .1072
28.6.9Temperature sensor option register (DTS_OR) . . . . .1073
28.6.10DTS register map . . . . .1074
29Digital-to-analog converter (DAC) . . . . .1076
29.1DAC introduction . . . . .1076
29.2DAC main features . . . . .1076
29.3DAC implementation . . . . .1077
29.4DAC functional description . . . . .1078
29.4.1DAC block diagram . . . . .1078
29.4.2DAC pins and internal signals . . . . .1079
29.4.3DAC channel enable . . . . .1081
29.4.4DAC data format . . . . .1081
29.4.5DAC conversion . . . . .1082
29.4.6DAC output voltage . . . . .1082
29.4.7DAC trigger selection . . . . .1083
29.4.8DMA requests . . . . .1083
29.4.9Noise generation . . . . .1084
29.4.10Triangle-wave generation . . . . .1085
29.4.11DAC channel modes . . . . .1086
29.4.12DAC channel buffer calibration . . . . .1089
29.4.13DAC channel conversion modes . . . . .1090
29.4.14Dual DAC channel conversion modes (if dual channels are available) . . . . .1091
29.5DAC in low-power modes . . . . .1095
29.6DAC interrupts . . . . .1095
29.7DAC registers . . . . .1096
29.7.1DAC control register (DAC_CR) . . . . .1096
29.7.2DAC software trigger register (DAC_SWTRGR) . . . . .1099
29.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .1100
29.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .1100
29.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .1101
29.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .1101
29.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .1102
29.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .1102
29.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .1103
29.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .1103
29.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .1103
29.7.12DAC channel1 data output register (DAC_DOR1) . . . . .1104
29.7.13DAC channel2 data output register (DAC_DOR2) . . . . .1104
29.7.14DAC status register (DAC_SR) . . . . .1105
29.7.15DAC calibration control register (DAC_CCR) . . . . .1106
29.7.16DAC mode control register (DAC_MCR) . . . . .1106
29.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .1108
29.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .1108
29.7.19DAC sample and hold time register (DAC_SHHR) . . . . .1108
29.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .1109
29.7.21DAC register map . . . . .1110
30Voltage reference buffer (VREFBUF) . . . . .1112
30.1VREFBUF introduction . . . . .1112
30.2VREFBUF functional description . . . . .1112
30.3VREFBUF registers . . . . .1113
30.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .1113
30.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .1114
30.3.3VREFBUF register map . . . . .1114
31Comparator (COMP) . . . . .1115
31.1Introduction . . . . .1115
31.2COMP main features . . . . .1115
31.3COMP functional description . . . . .1116
31.3.1COMP block diagram . . . . .1116
31.3.2COMP pins and internal signals . . . . .1117
31.3.3COMP reset and clocks . . . . .1118
31.3.4Comparator LOCK mechanism . . . . .1118
31.3.5Window comparator . . . . .1119
31.3.6Hysteresis . . . . .1119
31.3.7Comparator output blanking function . . . . .1119
31.3.8Comparator output on GPIOs . . . . .1120
31.3.9Comparator output redirection . . . . .1121
31.3.10COMP power and speed modes . . . . .1122
31.3.11Scaler function . . . . .1123
31.4COMP low-power modes . . . . .1123
31.5COMP interrupts . . . . .1124
31.5.1Interrupt through EXTI block . . . . .1124
31.5.2Interrupt through NVIC of the CPU . . . . .1124
31.6COMP registers . . . . .1125
31.6.1COMP status register (COMP_SR) . . . . .1125
31.6.2COMP interrupt clear flag register (COMP_ICFR) . . . . .1125
31.6.3COMP option register [alternate] (COMP_OR) . . . . .1126
31.6.4COMP configuration register 1 (COMP_CFGR1) . . . . .1127
31.6.5COMP configuration register 2 (COMP_CFGR2) . . . . .1129
31.6.6COMP register map . . . . .1132
32Operational amplifiers (OPAMP) . . . . .1133
32.1OPAMP introduction . . . . .1133
32.2OPAMP main features . . . . .1133
32.3OPAMP functional description . . . . .1133
32.3.1OPAMP reset and clocks . . . . .1133
32.3.2Initial configuration . . . . .1134
32.3.3Signal routing . . . . .1134
32.3.4OPAMP modes . . . . .1135
32.3.5Calibration . . . . .1142
32.4OPAMP low-power modes . . . . .1144
32.5OPAMP PGA gain . . . . .1144
32.6OPAMP registers . . . . .1144
32.6.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .1144
32.6.2OPAMP1 trimming register in normal mode (OPAMP1_OTR) . . . . .1146
32.6.3OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR) . . . . .1147
32.6.4OPAMP option register (OPAMP_OR) . . . . .1147
32.6.5OPAMP2 control/status register (OPAMP2_CSR) . . . . .1147
32.6.6OPAMP2 trimming register in normal mode (OPAMP2_OTR) . . . . .1149
32.6.7OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR) 1150
32.6.8OPAMP register map . . . . .1151
33Digital filter for sigma delta modulators (DFSDM) . . . . .1152
33.1Introduction . . . . .1152
33.2DFSDM main features . . . . .1153
33.3DFSDM implementation . . . . .1154
33.4DFSDM functional description . . . . .1155
33.4.1DFSDM block diagram . . . . .1155
33.4.2DFSDM pins and internal signals . . . . .1156
33.4.3DFSDM reset and clocks . . . . .1158
33.4.4Serial channel transceivers . . . . .1159
33.4.5Configuring the input serial interface . . . . .1169
33.4.6Parallel data inputs . . . . .1169
33.4.7Channel selection . . . . .1172
33.4.8Digital filter configuration . . . . .1172
33.4.9Integrator unit . . . . .1173
33.4.10Analog watchdog . . . . .1174
33.4.11Short-circuit detector . . . . .1176
33.4.12Extreme detector . . . . .1177
33.4.13Data unit block . . . . .1177
33.4.14Signed data format . . . . .1178
33.4.15Launching conversions . . . . .1179
33.4.16Continuous and fast continuous modes . . . . .1179
33.4.17Request precedence . . . . .1180
33.4.18Power optimization in run mode . . . . .1181
33.5DFSDM interrupts . . . . .1181
33.6DFSDM DMA transfer . . . . .1183
33.7DFSDM channel y registers (y=0..7) . . . . .1183
33.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . .1183
33.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . .1185
33.7.3DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . .		1186
33.7.4DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . .		1187
33.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .1187
33.7.6DFSDM channel y delay register (DFSDM_CHyDLYR) . . . . .1188
33.8DFSDM filter x module registers (x=0..7) . . . . .1189
33.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .1189
33.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .1192
33.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .1193
33.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .1195
33.8.5DFSDM filter x injected channel group selection register
(DFSDM_FLTxJCHGR) . . . . .		1196
33.8.6DFSDM filter x control register (DFSDM_FLTxFCR) . . . . .1196
33.8.7DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . .		1197
33.8.8DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . .		1198
33.8.9DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . .		1199
33.8.10DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . .		1199
33.8.11DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . .		1200
33.8.12DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . .		1201
33.8.13DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . .		1201
33.8.14DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . .		1202
33.8.15DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . .1202
33.8.16DFSDM register map . . . . .1203
34Digital camera interface (DCMI) . . . . .1218
34.1DCMI introduction . . . . .1218
34.2DCMI main features . . . . .1218
34.3DCMI functional description . . . . .1218
34.3.1DCMI block diagram . . . . .1219
34.3.2DCMI pins and internal signals . . . . .1219
34.3.3DCMI clocks . . . . .1220
34.3.4DCMI DMA interface . . . . .1220
34.3.5DCMI physical interface . . . . .1220
34.3.6DCMI synchronization . . . . .1222
34.3.7DCMI capture modes . . . . .1224
34.3.8DCMI crop feature . . . . .1225
34.3.9DCMI JPEG format . . . . .1226
34.3.10DCMI FIFO . . . . .1226
34.3.11DCMI data format description . . . . .1227
34.4DCMI interrupts . . . . .1229
34.5DCMI registers . . . . .1229
34.5.1DCMI control register (DCMI_CR) . . . . .1229
34.5.2DCMI status register (DCMI_SR) . . . . .1232
34.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .1232
34.5.4DCMI interrupt enable register (DCMI_IER) . . . . .1233
34.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .1234
34.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .1235
34.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .1236
34.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .1236
34.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .1237
34.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .1238
34.5.11DCMI data register (DCMI_DR) . . . . .1238
34.5.12DCMI register map . . . . .1239
35Parallel synchronous slave interface (PSSI) . . . . .1240
35.1PSSI introduction . . . . .1240
35.2PSSI main features . . . . .1240
35.3PSSI functional description . . . . .1240
35.3.1PSSI block diagram . . . . .1241
35.3.2PSSI pins and internal signals . . . . .1241
35.3.3PSSI clock . . . . .1242
35.3.4PSSI data management . . . . .1242
35.3.5PSSI optional control signals . . . . .1244
35.4PSSI interrupts . . . . .1247
35.5PSSI registers . . . . .1248
35.5.1PSSI control register (PSSI_CR) . . . . .1248
35.5.2PSSI status register (PSSI_SR) . . . . .1249
35.5.3PSSI raw interrupt status register (PSSI_RIS) . . . . .1250
35.5.4PSSI interrupt enable register (PSSI_IER) . . . . .1251
35.5.5PSSI masked interrupt status register (PSSI_MIS) . . . . .1251
35.5.6PSSI interrupt clear register (PSSI_ICR) . . . . .1252

35.5.7 PSSI data register (PSSI_DR) . . . . . 1252

35.5.8 PSSI register map . . . . . 1253

36 LCD-TFT display controller (LTDC) . . . . . 1254

36.1 Introduction . . . . . 1254

36.2 LTDC main features . . . . . 1254

36.3 LTDC functional description . . . . . 1255

36.3.1 LTDC block diagram . . . . . 1255

36.3.2 LTDC pins and internal signals . . . . . 1255

36.3.3 LTDC reset and clocks . . . . . 1256

36.4 LTDC programmable parameters . . . . . 1258

36.4.1 LTDC global configuration parameters . . . . . 1258

36.4.2 Layer programmable parameters . . . . . 1260

36.5 LTDC interrupts . . . . . 1264

36.6 LTDC programming procedure . . . . . 1265

36.7 LTDC registers . . . . . 1266

36.7.1 LTDC synchronization size configuration register (LTDC_SSCR) . . . . . 1266

36.7.2 LTDC back porch configuration register (LTDC_BPCR) . . . . . 1266

36.7.3 LTDC active width configuration register (LTDC_AWCR) . . . . . 1267

36.7.4 LTDC total width configuration register (LTDC_TWCR) . . . . . 1268

36.7.5 LTDC global control register (LTDC_GCR) . . . . . 1268

36.7.6 LTDC shadow reload configuration register (LTDC_SRCR) . . . . . 1270

36.7.7 LTDC background color configuration register (LTDC_BCCR) . . . . . 1270

36.7.8 LTDC interrupt enable register (LTDC_IER) . . . . . 1271

36.7.9 LTDC interrupt status register (LTDC_ISR) . . . . . 1272

36.7.10 LTDC interrupt clear register (LTDC_ICR) . . . . . 1272

36.7.11 LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . . 1273

36.7.12 LTDC current position status register (LTDC_CPSR) . . . . . 1273

36.7.13 LTDC current display status register (LTDC_CDSR) . . . . . 1274

36.7.14 LTDC layer x control register (LTDC_LxCR) . . . . . 1274

36.7.15 LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR) . . . . . 1275

36.7.16 LTDC layer x window vertical position configuration register (LTDC_LxWVPCR) . . . . . 1276

36.7.17 LTDC layer x color keying configuration register (LTDC_LxCKCR) . . . . . 1277

36.7.18LTDC layer x pixel format configuration register (LTDC_LxPFCR) . . . . .1277
36.7.19LTDC layer x constant alpha configuration register (LTDC_LxCACR) . . . . .1278
36.7.20LTDC layer x default color configuration register (LTDC_LxDCCR) . . . . .1278
36.7.21LTDC layer x blending factors configuration register (LTDC_LxBFCR) . . . . .1279
36.7.22LTDC layer x color frame buffer address register (LTDC_LxCFBAR) . . . . .1280
36.7.23LTDC layer x color frame buffer length register (LTDC_LxCFBLR) . . . . .1280
36.7.24LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR) . . . . .1281
36.7.25LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . .1281
36.7.26LTDC register map . . . . .1282
37JPEG codec (JPEG) . . . . .1285
37.1JPEG introduction . . . . .1285
37.2JPEG codec main features . . . . .1285
37.3JPEG codec block functional description . . . . .1286
37.3.1General description . . . . .1286
37.3.2JPEG internal signals . . . . .1286
37.3.3JPEG decoding procedure . . . . .1287
37.3.4JPEG encoding procedure . . . . .1288
37.4JPEG codec interrupts . . . . .1290
37.5JPEG codec registers . . . . .1291
37.5.1JPEG codec control register (JPEG_CONFR0) . . . . .1291
37.5.2JPEG codec configuration register 1 (JPEG_CONFR1) . . . . .1291
37.5.3JPEG codec configuration register 2 (JPEG_CONFR2) . . . . .1292
37.5.4JPEG codec configuration register 3 (JPEG_CONFR3) . . . . .1293
37.5.5JPEG codec configuration register x (JPEG_CONFRx) . . . . .1293
37.5.6JPEG control register (JPEG_CR) . . . . .1294
37.5.7JPEG status register (JPEG_SR) . . . . .1295
37.5.8JPEG clear flag register (JPEG_CFR) . . . . .1296
37.5.9JPEG data input register (JPEG_DIR) . . . . .1297
37.5.10JPEG data output register (JPEG_DOR) . . . . .1297
37.5.11JPEG quantization memory x (JPEG_QMEMx_y) . . . . .1298
37.5.12JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .1298
37.5.13JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . .1299
37.5.14JPEG Huffman base (JPEG_HUFFBASEx) . . . . .1299
37.5.15JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . .1300
37.5.16JPEG DHT memory (JPEG_DHTMEMx) . . . . .1301
37.5.17JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . .1301
37.5.18JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . .1302
37.5.19JPEG codec register map . . . . .1303
38True random number generator (RNG) . . . . .1305
38.1RNG introduction . . . . .1305
38.2RNG main features . . . . .1305
38.3RNG functional description . . . . .1306
38.3.1RNG block diagram . . . . .1306
38.3.2RNG internal signals . . . . .1306
38.3.3Random number generation . . . . .1306
38.3.4RNG initialization . . . . .1309
38.3.5RNG operation . . . . .1310
38.3.6RNG clocking . . . . .1312
38.3.7Error management . . . . .1312
38.3.8RNG low-power use . . . . .1313
38.4RNG interrupts . . . . .1313
38.5RNG processing time . . . . .1314
38.6RNG entropy source validation . . . . .1314
38.6.1Introduction . . . . .1314
38.6.2Validation conditions . . . . .1314
38.6.3Data collection . . . . .1315
38.7RNG registers . . . . .1315
38.7.1RNG control register (RNG_CR) . . . . .1315
38.7.2RNG status register (RNG_SR) . . . . .1317
38.7.3RNG data register (RNG_DR) . . . . .1318
38.7.4RNG health test control register (RNG_HTCR) . . . . .1319
38.7.5RNG register map . . . . .1319
39Cryptographic processor (CRYP) . . . . .1320
39.1Introduction . . . . .1320
39.2CRYP main features . . . . .1320
39.3CRYP implementation . . . . .1321
39.4CRYP functional description . . . . .1322
39.4.1CRYP block diagram . . . . .1322
39.4.2CRYP internal signals . . . . .1323
39.4.3CRYP DES/TDES cryptographic core . . . . .1323
39.4.4CRYP AES cryptographic core . . . . .1324
39.4.5CRYP procedure to perform a cipher operation . . . . .1330
39.4.6CRYP busy state . . . . .1332
39.4.7Preparing the CRYP AES key for decryption . . . . .1333
39.4.8CRYP stealing and data padding . . . . .1333
39.4.9CRYP suspend/resume operations . . . . .1334
39.4.10CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . .1335
39.4.11CRYP AES basic chaining modes (ECB, CBC) . . . . .1340
39.4.12CRYP AES counter mode (AES-CTR) . . . . .1345
39.4.13CRYP AES Galois/counter mode (GCM) . . . . .1349
39.4.14CRYP AES Galois message authentication code (GMAC) . . . . .1354
39.4.15CRYP AES Counter with CBC-MAC (CCM) . . . . .1355
39.4.16CRYP data registers and data swapping . . . . .1360
39.4.17CRYP key registers . . . . .1364
39.4.18CRYP initialization vector registers . . . . .1364
39.4.19CRYP DMA interface . . . . .1365
39.4.20CRYP error management . . . . .1367
39.5CRYP interrupts . . . . .1368
39.6CRYP processing time . . . . .1369
39.7CRYP registers . . . . .1370
39.7.1CRYP control register (CRYP_CR) . . . . .1370
39.7.2CRYP status register (CRYP_SR) . . . . .1372
39.7.3CRYP data input register (CRYP_DIN) . . . . .1373
39.7.4CRYP data output register (CRYP_DOUT) . . . . .1373
39.7.5CRYP DMA control register (CRYP_DMACR) . . . . .1374
39.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .1375
39.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .1375
39.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .1376
39.7.9CRYP key register 0L (CRYP_K0LR) . . . . .1377
39.7.10CRYP key register 0R (CRYP_K0RR) . . . . .1377
39.7.11CRYP key register 1L (CRYP_K1LR) . . . . .1378
39.7.12CRYP key register 1R (CRYP_K1RR)1378
39.7.13CRYP key register 2L (CRYP_K2LR)1379
39.7.14CRYP key register 2R (CRYP_K2RR)1379
39.7.15CRYP key register 3L (CRYP_K3LR)1380
39.7.16CRYP key register 3R (CRYP_K3RR)1380
39.7.17CRYP initialization vector register 0L (CRYP_IV0LR)1381
39.7.18CRYP initialization vector register 0R (CRYP_IV0RR)1381
39.7.19CRYP initialization vector register 1L (CRYP_IV1LR)1382
39.7.20CRYP initialization vector register 1R (CRYP_IV1RR)1382
39.7.21CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR)1382
39.7.22CRYP context swap GCM registers (CRYP_CSGCMxR)1383
39.7.23CRYP register map1383
40Hash processor (HASH)1386
40.1Introduction1386
40.2HASH main features1386
40.3HASH implementation1387
40.4HASH functional description1387
40.4.1HASH block diagram1387
40.4.2HASH internal signals1388
40.4.3About secure hash algorithms1388
40.4.4Message data feeding1388
40.4.5Message digest computing1390
40.4.6Message padding1391
40.4.7HMAC operation1393
40.4.8HASH suspend/resume operations1395
40.4.9HASH DMA interface1397
40.4.10HASH error management1397
40.4.11HASH processing time1397
40.5HASH interrupts1398
40.6HASH registers1399
40.6.1HASH control register (HASH_CR)1399
40.6.2HASH data input register (HASH_DIN)1401
40.6.3HASH start register (HASH_STR)1402
40.6.4HASH digest registers1403
40.6.5HASH interrupt enable register (HASH_IMR)1404
40.6.6HASH status register (HASH_SR) . . . . .1405
40.6.7HASH context swap registers . . . . .1405
40.6.8HASH register map . . . . .1406
41On-The-Fly decryption engine - AXI (OTFDEC) . . . . .1408
41.1Introduction . . . . .1408
41.2OTFDEC main features . . . . .1408
41.3OTFDEC functional description . . . . .1409
41.3.1OTFDEC block diagram . . . . .1409
41.3.2OTFDEC internal signals . . . . .1410
41.3.3OTFDEC on-the-fly decryption . . . . .1410
41.3.4AES in counter mode decryption . . . . .1411
41.3.5Flow control management . . . . .1413
41.3.6OTFDEC error management . . . . .1415
41.4OTFDEC interrupts . . . . .1415
41.5OTFDEC application information . . . . .1416
41.5.1OTFDEC initialization process . . . . .1416
41.5.2OTFDEC and power management . . . . .1417
41.5.3Encrypting for OTFDEC . . . . .1417
41.5.4OTFDEC Key CRC source code . . . . .1418
41.6OTFDEC registers . . . . .1419
41.6.1OTFDEC region x configuration register (OTFDEC_RxCFGR) . . . . .1419
41.6.2OTFDEC region x start address register
(OTFDEC2_RxSTARTADDR) . . . . .		1420
41.6.3OTFDEC region x end address register (OTFDEC_RxENDADDR) . . . . .1420
41.6.4OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . .1421
41.6.5OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . .1421
41.6.6OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . .1422
41.6.7OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . .1422
41.6.8OTFDEC region x key register 2 (OTFDEC_RxKEYR2) . . . . .1422
41.6.9OTFDEC region x key register 3 (OTFDEC_RxKEYR3) . . . . .1423
41.6.10OTFDEC interrupt status register (OTFDEC_ISR) . . . . .1423
41.6.11OTFDEC interrupt clear register (OTFDEC_ICR) . . . . .1424
41.6.12OTFDEC interrupt enable register (OTFDEC_IER) . . . . .1425
41.6.13OTFDEC register map . . . . .1426
42Advanced-control timers (TIM1/TIM8) . . . . .1430
42.1TIM1/TIM8 introduction . . . . .1430
42.2TIM1/TIM8 main features . . . . .1430
42.3TIM1/TIM8 functional description . . . . .1432
42.3.1Time-base unit . . . . .1432
42.3.2Counter modes . . . . .1434
42.3.3Repetition counter . . . . .1445
42.3.4External trigger input . . . . .1447
42.3.5Clock selection . . . . .1448
42.3.6Capture/compare channels . . . . .1452
42.3.7Input capture mode . . . . .1454
42.3.8PWM input mode . . . . .1455
42.3.9Forced output mode . . . . .1456
42.3.10Output compare mode . . . . .1457
42.3.11PWM mode . . . . .1458
42.3.12Asymmetric PWM mode . . . . .1461
42.3.13Combined PWM mode . . . . .1462
42.3.14Combined 3-phase PWM mode . . . . .1463
42.3.15Complementary outputs and dead-time insertion . . . . .1464
42.3.16Using the break function . . . . .1466
42.3.17Bidirectional break inputs . . . . .1472
42.3.18Clearing the OCxREF signal on an external event . . . . .1473
42.3.196-step PWM generation . . . . .1475
42.3.20One-pulse mode . . . . .1476
42.3.21Retriggerable one pulse mode . . . . .1477
42.3.22Encoder interface mode . . . . .1478
42.3.23UIF bit remapping . . . . .1480
42.3.24Timer input XOR function . . . . .1481
42.3.25Interfacing with Hall sensors . . . . .1481
42.3.26Timer synchronization . . . . .1484
42.3.27ADC synchronization . . . . .1488
42.3.28DMA burst mode . . . . .1488
42.3.29Debug mode . . . . .1489
42.4TIM1/TIM8 registers . . . . .1490
42.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1490
42.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .1491
42.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		1494
42.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . .		1496
42.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .1498
42.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .1500
42.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) . . . . .1501
42.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1502
42.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . . . .1505
42.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1506
42.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		1507
42.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1511
42.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1511
42.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .1511
42.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1512
42.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . .		1512
42.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . .		1513
42.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . .		1513
42.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . .		1514
42.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		1514
42.4.21TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . .		1518
42.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . .		1519
42.4.23TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . .		1520
42.4.24TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . .		1521
42.4.25TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . .		1522
42.4.26TIM1 alternate function option register 1 (TIM1_AF1) . . . . .1522
42.4.27TIM1 Alternate function register 2 (TIM1_AF2) . . . . .1524
42.4.28TIM8 Alternate function option register 1 (TIM8_AF1) . . . . .1525
42.4.29TIM8 Alternate function option register 2 (TIM8_AF2) . . . . .1527
42.4.30TIM1 timer input selection register (TIM1_TISEL) . . . . .1529
42.4.31TIM8 timer input selection register (TIM8_TISEL) . . . . .1529
42.4.32TIM1 register map . . . . .1531
42.4.33TIM8 register map . . . . .1533
43General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1536
43.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1536
43.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1536
43.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .1538
43.3.1Time-base unit . . . . .1538
43.3.2Counter modes . . . . .1540
43.3.3Clock selection . . . . .1550
43.3.4Capture/Compare channels . . . . .1554
43.3.5Input capture mode . . . . .1555
43.3.6PWM input mode . . . . .1556
43.3.7Forced output mode . . . . .1557
43.3.8Output compare mode . . . . .1558
43.3.9PWM mode . . . . .1559
43.3.10Asymmetric PWM mode . . . . .1562
43.3.11Combined PWM mode . . . . .1563
43.3.12Clearing the OCxREF signal on an external event . . . . .1564
43.3.13One-pulse mode . . . . .1566
43.3.14Retriggerable one pulse mode . . . . .1567
43.3.15Encoder interface mode . . . . .1568
43.3.16UIF bit remapping . . . . .1570
43.3.17Timer input XOR function . . . . .1570
43.3.18Timers and external trigger synchronization . . . . .1571
43.3.19Timer synchronization . . . . .1574
43.3.20DMA burst mode . . . . .1579
43.3.21Debug mode . . . . .1580
43.4TIM2/TIM3/TIM4/TIM5 registers . . . . .1581
43.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1581
43.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1582
43.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1584
43.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1587
43.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1588
43.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1589
43.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1591
43.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		1592
43.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1595
43.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . .		1596
43.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . .		1597
43.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .1598
43.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . .1599
43.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1599
43.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . .1600
43.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .1600
43.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .1600
43.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .1601
43.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .1601
43.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1602
43.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1603
43.4.22TIM2 alternate function option register 1 (TIM2_AF1) . . . . .1603
43.4.23TIM3 alternate function option register 1 (TIM3_AF1) . . . . .1603
43.4.24TIM4 alternate function option register 1 (TIM4_AF1) . . . . .1604
43.4.25TIM5 alternate function option register 1 (TIM5_AF1) . . . . .1604
43.4.26TIM2 timer input selection register (TIM2_TISEL) . . . . .1605
43.4.27TIM3 timer input selection register (TIM3_TISEL) . . . . .1606
43.4.28TIM4 timer input selection register (TIM4_TISEL) . . . . .1606
43.4.29TIM5 timer input selection register (TIM5_TISEL) . . . . .1607
43.4.30TIMx register map . . . . .1609
44General-purpose timers (TIM12/TIM13/TIM14) . . . . .1612
44.1TIM12/TIM13/TIM14 introduction . . . . .1612
44.2TIM12/TIM13/TIM14 main features . . . . .1612
44.2.1TIM12 main features . . . . .1612
44.2.2TIM13/TIM14 main features . . . . .1613
44.3TIM12/TIM13/TIM14 functional description . . . . .1615
44.3.1Time-base unit . . . . .1615
44.3.2Counter modes . . . . .1617
44.3.3Clock selection . . . . .1620
44.3.4Capture/compare channels . . . . .1622
44.3.5Input capture mode . . . . .1624
44.3.6PWM input mode (only for TIM12) . . . . .1625
44.3.7Forced output mode . . . . .1626
44.3.8Output compare mode . . . . .1627
44.3.9PWM mode . . . . .1628
44.3.10Combined PWM mode (TIM12 only) . . . . .1629
44.3.11One-pulse mode . . . . .1630
44.3.12Retriggerable one pulse mode (TIM12 only) . . . . .1632
44.3.13UIF bit remapping . . . . .1632
44.3.14Timer input XOR function . . . . .1633
44.3.15TIM12 external trigger synchronization . . . . .1633
44.3.16Slave mode – combined reset + trigger mode . . . . .1636
44.3.17Timer synchronization (TIM12) . . . . .1637
44.3.18Using timer output as trigger for other timers (TIM13/TIM14) . . . . .1637
44.3.19Debug mode . . . . .1637
44.4TIM12 registers . . . . .1637
44.4.1TIM12 control register 1 (TIM12_CR1) . . . . .1637
44.4.2TIM12 control register 2 (TIM12_CR2) . . . . .1638
44.4.3TIM12 slave mode control register (TIM12_SMCR) . . . . .1639
44.4.4TIM12 Interrupt enable register (TIM12_DIER) . . . . .1641
44.4.5TIM12 status register (TIM12_SR) . . . . .1641
44.4.6TIM12 event generation register (TIM12_EGR) . . . . .1642
44.4.7TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . .1643
44.4.8TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1644
44.4.9TIM12 capture/compare enable register (TIM12_CCER) . . . . .1647
44.4.10TIM12 counter (TIM12_CNT) . . . . .1648
44.4.11TIM12 prescaler (TIM12_PSC) . . . . .1649
44.4.12TIM12 auto-reload register (TIM12_ARR) . . . . .1649
44.4.13TIM12 capture/compare register 1 (TIM12_CCR1) . . . . .1649
44.4.14TIM12 capture/compare register 2 (TIM12_CCR2) . . . . .1650
44.4.15TIM12 timer input selection register (TIM12_TISEL) . . . . .1650
44.4.16TIM12 register map . . . . .1651
44.5TIM13/TIM14 registers . . . . .1653
44.5.1TIMx control register 1 (TIMx_CR1)(x = 13 to 14) . . . . .1653
44.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 13 to 14) . . . . .1654
44.5.3TIMx status register (TIMx_SR)(x = 13 to 14) . . . . .1654
44.5.4TIMx event generation register (TIMx_EGR)(x = 13 to 14) . . . . .1655
44.5.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 13 to 14) .....		1656
44.5.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13 to 14) .....		1657
44.5.7TIMx capture/compare enable register
(TIMx_CCER)(x = 13 to 14) .....		1659
44.5.8TIMx counter (TIMx_CNT)(x = 13 to 14) .....1660
44.5.9TIMx prescaler (TIMx_PSC)(x = 13 to 14) .....1661
44.5.10TIMx auto-reload register (TIMx_ARR)(x = 13 to 14) .....1661
44.5.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 13 to 14) .....1661
44.5.12TIM13 timer input selection register (TIM13_TISEL) .....1662
44.5.13TIM14 timer input selection register (TIM14_TISEL) .....1662
44.5.14TIM13/TIM14 register map .....1663
45General-purpose timers (TIM15/TIM16/TIM17) .....1665
45.1TIM15/TIM16/TIM17 introduction .....1665
45.2TIM15 main features .....1665
45.3TIM16/TIM17 main features .....1666
45.4TIM15/TIM16/TIM17 functional description .....1669
45.4.1Time-base unit .....1669
45.4.2Counter modes .....1671
45.4.3Repetition counter .....1675
45.4.4Clock selection .....1676
45.4.5Capture/compare channels .....1678
45.4.6Input capture mode .....1680
45.4.7PWM input mode (only for TIM15) .....1681
45.4.8Forced output mode .....1682
45.4.9Output compare mode .....1683
45.4.10PWM mode .....1684
45.4.11Combined PWM mode (TIM15 only) .....1685
45.4.12Complementary outputs and dead-time insertion .....1686
45.4.13Using the break function .....1688
45.4.14Bidirectional break inputs .....1693
45.4.156-step PWM generation .....1694
45.4.16One-pulse mode .....1696
45.4.17Retriggerable one pulse mode (TIM15 only) .....1697
45.4.18UIF bit remapping .....1698
45.4.19Timer input XOR function (TIM15 only) .....1699
45.4.20External trigger synchronization (TIM15 only) . . . . .1700
45.4.21Slave mode – combined reset + trigger mode . . . . .1702
45.4.22DMA burst mode . . . . .1702
45.4.23Timer synchronization (TIM15) . . . . .1704
45.4.24Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1704
45.4.25Debug mode . . . . .1704
45.5TIM15 registers . . . . .1705
45.5.1TIM15 control register 1 (TIM15_CR1) . . . . .1705
45.5.2TIM15 control register 2 (TIM15_CR2) . . . . .1706
45.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1708
45.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1709
45.5.5TIM15 status register (TIM15_SR) . . . . .1710
45.5.6TIM15 event generation register (TIM15_EGR) . . . . .1712
45.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1713
45.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1714
45.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1717
45.5.10TIM15 counter (TIM15_CNT) . . . . .1720
45.5.11TIM15 prescaler (TIM15_PSC) . . . . .1720
45.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .1720
45.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .1721
45.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1721
45.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1722
45.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1722
45.5.17TIM15 DMA control register (TIM15_DCR) . . . . .1725
45.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1725
45.5.19TIM15 alternate register 1 (TIM15_AF1) . . . . .1726
45.5.20TIM15 input selection register (TIM15_TISEL) . . . . .1727
45.5.21TIM15 register map . . . . .1728
45.6TIM16/TIM17 registers . . . . .1731
45.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1731
45.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1732
45.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1733
45.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1734
45.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1735
45.6.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1736
45.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1737
45.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1739
45.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1741
45.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1742
45.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .1742
45.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1743
45.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1743
45.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1744
45.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1747
45.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .1747
45.6.17TIM16 alternate function register 1 (TIM16_AF1) . . . . .1748
45.6.18TIM16 input selection register (TIM16_TISEL) . . . . .1749
45.6.19TIM17 alternate function register 1 (TIM17_AF1) . . . . .1750
45.6.20TIM17 input selection register (TIM17_TISEL) . . . . .1751
45.6.21TIM16/TIM17 register map . . . . .1752
46Basic timers (TIM6/TIM7) . . . . .1754
46.1TIM6/TIM7 introduction . . . . .1754
46.2TIM6/TIM7 main features . . . . .1754
46.3TIM6/TIM7 functional description . . . . .1755
46.3.1Time-base unit . . . . .1755
46.3.2Counting mode . . . . .1757
46.3.3UIF bit remapping . . . . .1760
46.3.4Clock source . . . . .1760
46.3.5Debug mode . . . . .1761
46.4TIM6/TIM7 registers . . . . .1761
46.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1761
46.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1763
46.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1763
46.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1764
46.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1764
46.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1764
46.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1765
46.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .1765
46.4.9TIMx register map . . . . .1766
47Low-power timer (LPTIM) . . . . .1767
47.1Introduction . . . . .1767
47.2LPTIM main features . . . . .1767
47.3LPTIM implementation . . . . .1768
47.4LPTIM functional description . . . . .1768
47.4.1LPTIM block diagram . . . . .1768
47.4.2LPTIM pins and internal signals . . . . .1769
47.4.3LPTIM input and trigger mapping . . . . .1770
47.4.4LPTIM reset and clocks . . . . .1772
47.4.5Glitch filter . . . . .1772
47.4.6Prescaler . . . . .1773
47.4.7Trigger multiplexer . . . . .1773
47.4.8Operating mode . . . . .1774
47.4.9Timeout function . . . . .1776
47.4.10Waveform generation . . . . .1776
47.4.11Register update . . . . .1777
47.4.12Counter mode . . . . .1778
47.4.13Timer enable . . . . .1778
47.4.14Timer counter reset . . . . .1779
47.4.15Encoder mode . . . . .1779
47.4.16Debug mode . . . . .1781
47.5LPTIM low-power modes . . . . .1781
47.6LPTIM interrupts . . . . .1782
47.7LPTIM registers . . . . .1782
47.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1783
47.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1784
47.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1784
47.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1785
47.7.5LPTIM control register (LPTIM_CR) . . . . .1788
47.7.6LPTIM compare register (LPTIM_CMP) . . . . .1790
47.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1790
47.7.8LPTIM counter register (LPTIM_CNT) . . . . .1791
47.7.9LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .1791
47.7.10LPTIM register map . . . . .1793
48System window watchdog (WWDG) . . . . .1794
48.1WWDG introduction . . . . .1794
48.2WWDG main features . . . . .1794
48.3WWDG functional description . . . . .1794
48.3.1WWDG block diagram . . . . .1795
48.3.2WWDG internal signals . . . . .1795
48.3.3Enabling the watchdog . . . . .1795
48.3.4Controlling the down-counter . . . . .1795
48.3.5How to program the watchdog timeout . . . . .1796
48.3.6Debug mode . . . . .1797
48.4WWDG interrupts . . . . .1797
48.5WWDG registers . . . . .1797
48.5.1WWDG control register (WWDG_CR) . . . . .1798
48.5.2WWDG configuration register (WWDG_CFR) . . . . .1798
48.5.3WWDG status register (WWDG_SR) . . . . .1799
48.5.4WWDG register map . . . . .1799
49Independent watchdog (IWDG) . . . . .1800
49.1Introduction . . . . .1800
49.2IWDG main features . . . . .1800
49.3IWDG functional description . . . . .1800
49.3.1IWDG block diagram . . . . .1800
49.3.2IWDG internal signals . . . . .1801
49.3.3Window option . . . . .1801
49.3.4Hardware watchdog . . . . .1802
49.3.5Low-power freeze . . . . .1802
49.3.6Register access protection . . . . .1802
49.3.7Debug mode . . . . .1803
49.4IWDG registers . . . . .1804
49.4.1IWDG key register (IWDG_KR) . . . . .1804
49.4.2IWDG prescaler register (IWDG_PR) . . . . .1805
49.4.3IWDG reload register (IWDG_RLR) . . . . .1806
49.4.4IWDG status register (IWDG_SR) . . . . .1807
49.4.5IWDG window register (IWDG_WINR) . . . . .1808
49.4.6IWDG register map . . . . .1809
50Real-time clock (RTC) . . . . .1810
50.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1843
50.6.16RTC alarm B register (RTC_ALRMBR) . . . . .1844
50.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1845
50.6.18RTC status register (RTC_SR) . . . . .1845
50.6.19RTC masked interrupt status register (RTC_MISR) . . . . .1846
50.6.20RTC status clear register (RTC_SCR) . . . . .1847
50.6.21RTC configuration register (RTC_CFGR) . . . . .1848
50.6.22RTC register map . . . . .1849
51Tamper and backup registers (TAMP) . . . . .1851
51.1Introduction . . . . .1851
51.2TAMP main features . . . . .1851
51.3TAMP functional description . . . . .1852
51.3.1TAMP block diagram . . . . .1852
51.3.2TAMP pins and internal signals . . . . .1853
51.3.3TAMP register write protection . . . . .1854
51.3.4Tamper detection . . . . .1854
51.4TAMP low-power modes . . . . .1858
51.5TAMP interrupts . . . . .1858
51.6TAMP registers . . . . .1859
51.6.1TAMP control register 1 (TAMP_CR1) . . . . .1859
51.6.2TAMP control register 2 (TAMP_CR2) . . . . .1860
51.6.3TAMP filter control register (TAMP_FLTCR) . . . . .1862
51.6.4TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .1863
51.6.5TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .1864
51.6.6TAMP active tamper output register (TAMP_ATOR) . . . . .1865
51.6.7TAMP interrupt enable register (TAMP_IER) . . . . .1865
51.6.8TAMP status register (TAMP_SR) . . . . .1867
51.6.9TAMP masked interrupt status register (TAMP_MISR) . . . . .1868
51.6.10TAMP status clear register (TAMP_SCR) . . . . .1869
51.6.11TAMP monotonic counter register (TAMP_COUNTR) . . . . .1870
51.6.12TAMP configuration register (TAMP_CFGR) . . . . .1870
51.6.13TAMP backup x register (TAMP_BKPxR) . . . . .1871
51.6.14TAMP register map . . . . .1872
52Inter-integrated circuit interface (I2C) . . . . .1874
52.9.9I2C PEC register (I2C_PECR) .....1936
52.9.10I2C receive data register (I2C_RXDR) .....1936
52.9.11I2C transmit data register (I2C_TXDR) .....1937
52.9.12I2C register map .....1938
53Universal synchronous/asynchronous receiver transmitter (USART/UART) .....1939
53.1USART introduction .....1939
53.2USART main features .....1940
53.3USART extended features .....1941
53.4USART implementation .....1941
53.5USART functional description .....1942
53.5.1USART block diagram .....1942
53.5.2USART signals .....1943
53.5.3USART character description .....1944
53.5.4USART FIFOs and thresholds .....1946
53.5.5USART transmitter .....1946
53.5.6USART receiver .....1950
53.5.7USART baud rate generation .....1957
53.5.8Tolerance of the USART receiver to clock deviation .....1958
53.5.9USART auto baud rate detection .....1960
53.5.10USART multiprocessor communication .....1962
53.5.11USART Modbus communication .....1964
53.5.12USART parity control .....1965
53.5.13USART LIN (local interconnection network) mode .....1966
53.5.14USART synchronous mode .....1968
53.5.15USART single-wire half-duplex communication .....1972
53.5.16USART receiver timeout .....1972
53.5.17USART smartcard mode .....1973
53.5.18USART IrDA SIR ENDEC block .....1977
53.5.19Continuous communication using USART and DMA .....1980
53.5.20RS232 hardware flow control and RS485 Driver Enable .....1982
53.5.21USART low-power management .....1985
53.6USART in low-power modes .....1988
53.7USART interrupts .....1989
53.8USART registers .....1990
54.6LPUART interrupts . . . . .2053
54.7LPUART registers . . . . .2054
54.7.1LPUART control register 1 (LPUART_CR1) . . . . .2054
54.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2057
54.7.3LPUART control register 2 (LPUART_CR2) . . . . .2060
54.7.4LPUART control register 3 (LPUART_CR3) . . . . .2062
54.7.5LPUART baud rate register (LPUART_BRR) . . . . .2065
54.7.6LPUART request register (LPUART_RQR) . . . . .2065
54.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .2066
54.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .2071
54.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .2074
54.7.10LPUART receive data register (LPUART_RDR) . . . . .2075
54.7.11LPUART transmit data register (LPUART_TDR) . . . . .2075
54.7.12LPUART prescaler register (LPUART_PRESC) . . . . .2076
54.7.13LPUART register map . . . . .2077
55Serial peripheral interface (SPI) . . . . .2079
55.1Introduction . . . . .2079
55.2SPI main features . . . . .2080
55.3SPI implementation . . . . .2080
55.4SPI functional description . . . . .2081
55.4.1SPI block diagram . . . . .2081
55.4.2SPI signals . . . . .2082
55.4.3SPI communication general aspects . . . . .2083
55.4.4Communications between one master and one slave . . . . .2083
55.4.5Standard multislave communication . . . . .2085
55.4.6Multimaster communication . . . . .2088
55.4.7Slave select pin (NSS) management . . . . .2088
55.4.8Communication formats . . . . .2092
55.4.9Configuration of SPI . . . . .2094
55.4.10Procedure for enabling SPI . . . . .2095
55.4.11SPI data transmission and reception procedures . . . . .2095
55.4.12Procedure for disabling the SPI . . . . .2100
55.4.13Data packing . . . . .2101
55.4.14Communication using DMA (direct memory addressing) . . . . .2102
55.5SPI specific modes and control . . . . .2104
55.11.12SPI receiver CRC register (SPI_RXCRC) . . . . .2152
55.11.13SPI underrun data register (SPI_UDRDR) . . . . .2153
55.11.14SPI/I2S configuration register (SPI_I2SCFGR) . . . . .2153
55.12SPI register map and reset values . . . . .2156
56Serial audio interface (SAI) . . . . .2158
56.1SAI introduction . . . . .2158
56.2SAI main features . . . . .2158
56.3SAI implementation . . . . .2159
56.4SAI functional description . . . . .2160
56.4.1SAI block diagram . . . . .2160
56.4.2SAI pins and internal signals . . . . .2161
56.4.3Main SAI modes . . . . .2162
56.4.4SAI synchronization mode . . . . .2163
56.4.5Audio data size . . . . .2164
56.4.6Frame synchronization . . . . .2164
56.4.7Slot configuration . . . . .2167
56.4.8SAI clock generator . . . . .2169
56.4.9Internal FIFOs . . . . .2172
56.4.10PDM interface . . . . .2174
56.4.11AC'97 link controller . . . . .2182
56.4.12SPDIF output . . . . .2184
56.4.13Specific features . . . . .2187
56.4.14Error flags . . . . .2191
56.4.15Disabling the SAI . . . . .2194
56.4.16SAI DMA interface . . . . .2194
56.5SAI interrupts . . . . .2195
56.6SAI registers . . . . .2197
56.6.1SAI global configuration register (SAI_GCR) . . . . .2197
56.6.2SAI configuration register 1 (SAI_ACR1) . . . . .2197
56.6.3SAI configuration register 2 (SAI_ACR2) . . . . .2200
56.6.4SAI frame configuration register (SAI_AFRCR) . . . . .2202
56.6.5SAI slot register (SAI_ASLOTR) . . . . .2203
56.6.6SAI interrupt mask register (SAI_AIM) . . . . .2204
56.6.7SAI status register (SAI_ASR) . . . . .2206
56.6.8SAI clear flag register (SAI_ACLRFR) . . . . .2208
56.6.9SAI data register (SAI_ADR) . . . . .2209
56.6.10SAI configuration register 1 (SAI_BCR1) . . . . .2209
56.6.11SAI configuration register 2 (SAI_BCR2) . . . . .2212
56.6.12SAI frame configuration register (SAI_BFRFCR) . . . . .2214
56.6.13SAI slot register (SAI_BSLOTR) . . . . .2215
56.6.14SAI interrupt mask register (SAI_BIM) . . . . .2216
56.6.15SAI status register (SAI_BSR) . . . . .2217
56.6.16SAI clear flag register (SAI_BCLRFR) . . . . .2219
56.6.17SAI data register (SAI_BDR) . . . . .2220
56.6.18SAI PDM control register (SAI_PDMCR) . . . . .2221
56.6.19SAI PDM delay register (SAI_PDMPLY) . . . . .2222
56.6.20SAI register map . . . . .2224
57SPDIF receiver interface (SPDIFRX) . . . . .2226
57.1SPDIFRX interface introduction . . . . .2226
57.2SPDIFRX main features . . . . .2226
57.3SPDIFRX functional description . . . . .2226
57.3.1SPDIFRX pins and internal signals . . . . .2227
57.3.2S/PDIF protocol (IEC-60958) . . . . .2228
57.3.3SPDIFRX decoder (SPDIFRX_DC) . . . . .2230
57.3.4SPDIFRX tolerance to clock deviation . . . . .2234
57.3.5SPDIFRX synchronization . . . . .2234
57.3.6SPDIFRX handling . . . . .2236
57.3.7Data reception management . . . . .2238
57.3.8Dedicated control flow . . . . .2240
57.3.9Reception errors . . . . .2241
57.3.10Clocking strategy . . . . .2243
57.3.11Symbol clock generation . . . . .2243
57.3.12DMA interface . . . . .2245
57.3.13Interrupt generation . . . . .2246
57.3.14Register protection . . . . .2247
57.4Programming procedures . . . . .2247
57.4.1Initialization phase . . . . .2248
57.4.2Handling of interrupts coming from SPDIFRX . . . . .2249
57.4.3Handling of interrupts coming from DMA . . . . .2249
57.5SPDIFRX interface registers . . . . .2250
57.5.1SPDIFRX control register (SPDIFRX_CR) . . . . .2250
57.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .2252
57.5.3SPDIFRX status register (SPDIFRX_SR) . . . . .2253
57.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .2255
57.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .2256
57.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .2256
57.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .2257
57.5.8SPDIFRX channel status register (SPDIFRX_CSR) . . . . .2258
57.5.9SPDIFRX debug information register (SPDIFRX_DIR) . . . . .2258
57.5.10SPDIFRX interface register map . . . . .2259
58Single wire protocol master interface (SWPMI) . . . . .2260
58.1Introduction . . . . .2260
58.2SWPMI main features . . . . .2261
58.3SWPMI functional description . . . . .2262
58.3.1SWPMI block diagram . . . . .2262
58.3.2SWPMI pins and internal signals . . . . .2262
58.3.3SWP initialization and activation . . . . .2263
58.3.4SWP bus states . . . . .2264
58.3.5SWPMI_IO (internal transceiver) bypass . . . . .2265
58.3.6SWPMI bit rate . . . . .2265
58.3.7SWPMI frame handling . . . . .2266
58.3.8Transmission procedure . . . . .2266
58.3.9Reception procedure . . . . .2271
58.3.10Error management . . . . .2275
58.3.11Loopback mode . . . . .2277
58.4SWPMI low-power modes . . . . .2277
58.5SWPMI interrupts . . . . .2278
58.6SWPMI registers . . . . .2279
58.6.1SWPMI configuration/control register (SWPMI_CR) . . . . .2279
58.6.2SWPMI Bitrate register (SWPMI_BRR) . . . . .2280
58.6.3SWPMI Interrupt and Status register (SWPMI_ISR) . . . . .2281
58.6.4SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . .2282
58.6.5SWPMI Interrupt Enable register (SWPMI_IER) . . . . .2283
58.6.6SWPMI Receive Frame Length register (SWPMI_RFL) . . . . .2285
58.6.7SWPMI Transmit data register (SWPMI_TDR) . . . . .2285
58.6.8SWPMI Receive data register (SWPMI_RDR) . . . . .2285
58.6.9SWPMI Option register (SWPMI_OR) . . . . .2286
58.6.10SWPMI register map and reset value table . . . . .2287
59Management data input/output (MDIOS) . . . . .2288
59.1MDIOS introduction . . . . .2288
59.2MDIOS main features . . . . .2288
59.3MDIOS functional description . . . . .2289
59.3.1MDIOS block diagram . . . . .2289
59.3.2MDIOS pins and internal signals . . . . .2289
59.3.3MDIOS protocol . . . . .2289
59.3.4MDIOS enabling and disabling . . . . .2290
59.3.5MDIOS data . . . . .2291
59.3.6MDIOS APB frequency . . . . .2292
59.3.7Write/read flags and interrupts . . . . .2292
59.3.8MDIOS error management . . . . .2293
59.3.9MDIOS in Stop mode . . . . .2294
59.3.10MDIOS interrupts . . . . .2294
59.4MDIOS registers . . . . .2294
59.4.1MDIOS configuration register (MDIOS_CR) . . . . .2294
59.4.2MDIOS write flag register (MDIOS_WRFR) . . . . .2295
59.4.3MDIOS clear write flag register (MDIOS_CWRFR) . . . . .2296
59.4.4MDIOS read flag register (MDIOS_RDFR) . . . . .2296
59.4.5MDIOS clear read flag register (MDIOS_CRDFR) . . . . .2297
59.4.6MDIOS status register (MDIOS_SR) . . . . .2297
59.4.7MDIOS clear flag register (MDIOS_CLRFR) . . . . .2298
59.4.8MDIOS input data register x (MDIOS_DINRx) . . . . .2298
59.4.9MDIOS output data register x (MDIOS_DOUTRx) . . . . .2299
59.4.10MDIOS register map . . . . .2299
60Secure digital input/output MultiMediaCard interface (SDMMC) . . .2301
60.1SDMMC main features . . . . .2301
60.2SDMMC implementation . . . . .2301
60.3SDMMC bus topology . . . . .2302
60.4SDMMC operation modes . . . . .2304
60.5SDMMC functional description . . . . .2305
60.5.1SDMMC block diagram . . . . .2305
60.5.2SDMMC pins and internal signals . . . . .2305
60.5.3General description . . . . .2306
60.5.4SDMMC adapter . . . . .2308
60.5.5SDMMC AHB slave interface . . . . .2330
60.5.6SDMMC AHB master interface . . . . .2331
60.5.7MDMA request generation . . . . .2332
60.5.8AHB and SDMMC_CK clock relation . . . . .2333
60.6Card functional description . . . . .2334
60.6.1SD I/O mode . . . . .2334
60.6.2CMD12 send timing . . . . .2342
60.6.3Sleep (CMD5) . . . . .2346
60.6.4Interrupt mode (Wait-IRQ) . . . . .2347
60.6.5Boot operation . . . . .2348
60.6.6Response R1b handling . . . . .2351
60.6.7Reset and card cycle power . . . . .2352
60.7Hardware flow control . . . . .2353
60.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .2353
60.9SDMMC interrupts . . . . .2357
60.10SDMMC registers . . . . .2358
60.10.1SDMMC power control register (SDMMC_POWER) . . . . .2358
60.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .2359
60.10.3SDMMC argument register (SDMMC_ARGR) . . . . .2361
60.10.4SDMMC command register (SDMMC_CMDR) . . . . .2361
60.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .2363
60.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .2364
60.10.7SDMMC data timer register (SDMMC_TIMER) . . . . .2364
60.10.8SDMMC data length register (SDMMC_DLENR) . . . . .2365
60.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .2366
60.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .2367
60.10.11SDMMC status register (SDMMC_STAR) . . . . .2368
60.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .2371
60.10.13SDMMC mask register (SDMMC_MASKR) . . . . .2373
60.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .2376
60.10.15SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .2376
60.10.16SDMMC IDMA buffer size register (SDMMC_IDMABYSIZER) . . . . .2377
60.10.17SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . .		2378

60.10.18 SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) ..... 2378

60.10.19 SDMMC data FIFO registers x (SDMMC_FIFORx) ..... 2378

60.10.20 SDMMC register map ..... 2379

61 Controller area network with flexible data rate (FDCAN) ..... 2382

61.1 FDCAN introduction ..... 2382

61.2 FDCAN main features ..... 2385

61.3 TTCAN implementation ..... 2385

61.4 FDCAN functional description ..... 2386

61.4.1 Operating modes ..... 2387

61.4.2 Error management ..... 2396

61.4.3 Message RAM ..... 2396

61.4.4 FIFO acknowledge handling ..... 2408

61.4.5 Bit timing ..... 2409

61.4.6 Clock calibration on CAN ..... 2410

61.4.7 Application ..... 2414

61.4.8 TTCAN operations (FDCAN1 only) ..... 2415

61.4.9 TTCAN configuration ..... 2416

61.4.10 Message scheduling ..... 2418

61.4.11 TTCAN gap control ..... 2425

61.4.12 Stop watch ..... 2426

61.4.13 Local time, cycle time, global time,
and external clock synchronization ..... 2426

61.4.14 TTCAN error level ..... 2429

61.4.15 TTCAN message handling ..... 2430

61.4.16 TTCAN interrupt and error handling ..... 2433

61.4.17 Level 0 ..... 2434

61.4.18 Synchronization to external time schedule ..... 2436

61.4.19 FDCAN Rx buffer and FIFO element ..... 2437

61.4.20 FDCAN Tx buffer element ..... 2439

61.4.21 FDCAN Tx event FIFO element ..... 2441

61.4.22 FDCAN standard message ID filter element ..... 2442

61.4.23 FDCAN extended message ID filter element ..... 2444

61.4.24 FDCAN trigger memory element ..... 2445

61.5 FDCAN registers ..... 2447

61.5.1 FDCAN core release register (FDCAN_CREL) ..... 2447

61.5.2FDCAN Endian register (FDCAN_ENDN) . . . . .2447
61.5.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .2447
61.5.4FDCAN test register (FDCAN_TEST) . . . . .2448
61.5.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .2449
61.5.6FDCAN CC control register (FDCAN_CCCR) . . . . .2450
61.5.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .2452
61.5.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .2453
61.5.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .2453
61.5.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .2454
61.5.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .2455
61.5.12FDCAN error counter register (FDCAN_ECR) . . . . .2455
61.5.13FDCAN protocol status register (FDCAN_PSR) . . . . .2456
61.5.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .2458
61.5.15FDCAN interrupt register (FDCAN_IR) . . . . .2458
61.5.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2461
61.5.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2463
61.5.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2464
61.5.19FDCAN global filter configuration register (FDCAN_GFC) . . . . .2465
61.5.20FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . . . .2466
61.5.21FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . . . .2467
61.5.22FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2467
61.5.23FDCAN high priority message status register (FDCAN_HPMS) . . . . .2468
61.5.24FDCAN new data 1 register (FDCAN_NDAT1) . . . . .2469
61.5.25FDCAN new data 2 register (FDCAN_NDAT2) . . . . .2469
61.5.26FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . .2470
61.5.27FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2470
61.5.28FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2471
61.5.29FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . .2472
61.5.30FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . .2472
61.5.31FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .2473
61.5.32FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .2474
61.5.33FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . .		2474
61.5.34FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .2475
61.5.35FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .2476
61.5.36FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . .		2477
61.5.37FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .2478
61.5.38FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .2478
61.5.39FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . .2479
61.5.40FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) .2479
61.5.41FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . .2480
61.5.42FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		2480
61.5.43FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		2481
61.5.44FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . .2481
61.5.45FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .2482
61.5.46FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . .2483
61.5.47FDCAN register map . . . . .2483
61.6TT CAN registers . . . . .2487
61.6.1FDCAN TT trigger memory configuration register
(FDCAN_TTTMC) . . . . .		2487
61.6.2FDCAN TT reference message configuration register
(FDCAN_TTRMC) . . . . .		2487
61.6.3FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . .2488
61.6.4FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . .2490
61.6.5FDCAN TUR configuration register (FDCAN_TURCF) . . . . .2491
61.6.6FDCAN TT operation control register (FDCAN_TTOCN) . . . . .2492
61.6.7FDCAN TT global time preset register (FDCAN_TTGTP) . . . . .2494
61.6.8FDCAN TT time mark register (FDCAN_TTTMK) . . . . .2494
61.6.9FDCAN TT interrupt register (FDCAN_TTIR) . . . . .2495
61.6.10FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . .2497
61.6.11FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . .2499
61.6.12FDCAN TT operation status register (FDCAN_TTOST) . . . . .2500
61.6.13FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . .2502
61.6.14FDCAN TT local and global time register (FDCAN_TTLGT) . . . . .2503
61.6.15FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . .2503
61.6.16FDCAN TT capture time register (FDCAN_TTCPT) . . . . .2504
61.6.17FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . .2504
61.6.18FDCAN TT trigger select register (FDCAN_TTTS) . . . . .2505
61.6.19FDCAN TT register map . . . . .2505
61.7CCU registers . . . . .2507
61.7.1Clock calibration unit core release register (FDCAN_CCU_CREL) . . .2507
61.7.2Calibration configuration register (FDCAN_CCU_CCFG) . . . . .2507
61.7.3Calibration status register (FDCAN_CCU_CSTAT) . . . . .2509
61.7.4Calibration watchdog register (FDCAN_CCU_CWD) . . . . .2509
61.7.5Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . .2510
61.7.6Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . . . . .2511
61.7.7CCU register map . . . . .2511
62USB on-the-go high-speed (OTG_HS) . . . . .2513
62.1Introduction . . . . .2513
62.2OTG_HS main features . . . . .2514
62.2.1General features . . . . .2514
62.2.2Host-mode features . . . . .2515
62.2.3Peripheral-mode features . . . . .2515
62.3OTG_HS implementation . . . . .2516
62.4OTG_HS functional description . . . . .2516
62.4.1OTG_HS block diagram . . . . .2516
62.4.2OTG_HS pin and internal signals . . . . .2517
62.4.3OTG_HS core . . . . .2517
62.4.4Embedded full-speed OTG PHY connected to OTG_HS . . . . .2518
62.4.5OTG detections . . . . .2518
62.4.6High-speed OTG PHY connected to OTG_HS . . . . .2518
62.5OTG_HS dual role device (DRD) . . . . .2519
62.5.1ID line detection . . . . .2519
62.5.2HNP dual role device . . . . .2519
62.5.3SRP dual role device . . . . .2520
62.6OTG_HS as a USB peripheral . . . . .2520
62.6.1SRP-capable peripheral . . . . .2521
62.6.2Peripheral states . . . . .2521
62.6.3Peripheral endpoints . . . . .2522
62.7OTG_HS as a USB host . . . . .2524
62.7.1SRP-capable host . . . . .2525
62.7.2USB host states . . . . .2525
62.7.3Host channels . . . . .2527
62.7.4Host scheduler . . . . .2528
62.8OTG_HS SOF trigger . . . . .2529
62.8.1Host SOFs . . . . .2529
62.8.2Peripheral SOFs . . . . .2529
62.9OTG_HS low-power modes . . . . .2530
62.10OTG_HS dynamic update of the OTG_HFIR register . . . . .2531
62.11OTG_HS data FIFOs . . . . .2531
62.11.1FIFO allocation for DMA address register storage . . . . .2532
62.11.2Peripheral FIFO architecture . . . . .2533
62.11.3Host FIFO architecture . . . . .2534
62.11.4FIFO RAM allocation . . . . .2535
62.12OTG_HS interrupts . . . . .2537
62.13OTG_HS control and status registers . . . . .2539
62.13.1CSR memory map . . . . .2539
62.14OTG_HS registers . . . . .2544
62.14.1OTG control and status register (OTG_GOTGCTL) . . . . .2544
62.14.2OTG interrupt register (OTG_GOTGINT) . . . . .2547
62.14.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .2548
62.14.4OTG USB configuration register (OTG_GUSBCFG) . . . . .2550
62.14.5OTG reset register (OTG_GRSTCTL) . . . . .2552
62.14.6OTG core interrupt register (OTG_GINTSTS) . . . . .2554
62.14.7OTG interrupt mask register (OTG_GINTMSK) . . . . .2559
62.14.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .2561
62.14.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .2562
62.14.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .2563
62.14.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .2564
62.14.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .2565
62.14.13OTG host nonperiodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		2566
62.14.14OTG nonperiodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		2567
62.14.15OTG general core configuration register (OTG_GCCFG) . . . . .2568
62.14.16OTG core ID register (OTG_CID) . . . . .2569
62.14.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .2570
62.14.18OTG interrupt register (OTG_GDFIFOFCFG) . . . . .2574
62.14.19OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		2574
62.14.20OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		2575
62.14.21Host-mode registers . . . . .2575
62.14.22OTG host configuration register (OTG_HCFG) . . . . .2576
62.14.23OTG host frame interval register (OTG_HFIR) . . . . .2577
62.14.24OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		2578
62.14.25OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		2579
62.14.26OTG host all channels interrupt register (OTG_HAINT) . . . . .2580
62.14.27OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		2580
62.14.28OTG host frame list base address register
(OTG_HFLBADDR) . . . . .		2581
62.14.29OTG host port control and status register (OTG_HPRT) . . . . .2581
62.14.30OTG host channel x characteristics register (OTG_HCCHARx) . . . . .2584
62.14.31OTG host channel x split control register (OTG_HCSPLTx) . . . . .2585
62.14.32OTG host channel x interrupt register (OTG_HCINTx) . . . . .2586
62.14.33OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .2587
62.14.34OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .2589
62.14.35OTG host channel x transfer size register (OTG_HCTSIZSGx) . . . . .2590
62.14.36OTG host channel x DMA address register in buffer DMA [alternate]
(OTG_HCDMAx) . . . . .		2592
62.14.37OTG host channel x DMA address register in scatter/gather DMA
[alternate] (OTG_HCDMASGx) . . . . .		2592
62.14.38OTG host channel-n DMA address buffer register
(OTG_HCDMABx) . . . . .		2593
62.14.39Device-mode registers . . . . .2594
62.14.40OTG device configuration register (OTG_DCFG) . . . . .2594
62.14.41OTG device control register (OTG_DCTL) . . . . .2596
62.14.42OTG device status register (OTG_DSTS) . . . . .2598
62.14.43OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		2599
62.14.44OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		2600
62.14.45OTG device all endpoints interrupt register (OTG_Daint) . . . . .2601
62.14.46OTG all endpoints interrupt mask register
(OTG_Daintmsk) . . . . .		2602
62.14.47OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		2603
62.14.48OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		2603
62.14.49OTG device threshold control register (OTG_DTHRCTL) . . . . .2604
62.14.50OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		2605
62.14.51OTG device each endpoint interrupt register (OTG_DEACHINT) . . . . .2605
62.14.52OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) .....		2606
62.14.53OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) .....		2606
62.14.54OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) .....		2607
62.14.55OTG device IN endpoint x control register (OTG_DIEPCTLx) .....2609
62.14.56OTG device IN endpoint x interrupt register (OTG_DIEPINTx) .....2611
62.14.57OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) .....		2613
62.14.58OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) .....		2613
62.14.59OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) .....		2614
62.14.60OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) .2614
62.14.61OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) .....		2615
62.14.62OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . .2617
62.14.63OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) .....		2619
62.14.64OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) .....		2620
62.14.65OTG device OUT endpoint x control register
(OTG_DOEPCTLx) .....		2620
62.14.66OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) .....		2623
62.14.67OTG power and clock gating control register (OTG_PCGCCTL) . . .2624
62.14.68OTG_HS register map .....2625
62.15OTG_HS programming model .....2637
62.15.1Core initialization .....2637
62.15.2Host initialization .....2638
62.15.3Device initialization .....2639
62.15.4DMA mode .....2639
62.15.5Host programming model .....2640
62.15.6Device programming model .....2672
62.15.7Worst case response time .....2693
62.15.8OTG programming model .....2695
63HDMI-CEC controller (CEC) .....2701
63.1HDMI-CEC introduction .....2701
63.2HDMI-CEC controller main features . . . . .2701
63.3HDMI-CEC functional description . . . . .2702
63.3.1HDMI-CEC pin and internal signals . . . . .2702
63.3.2HDMI-CEC block diagram . . . . .2703
63.3.3Message description . . . . .2703
63.3.4Bit timing . . . . .2704
63.4Arbitration . . . . .2704
63.4.1SFT option bit . . . . .2706
63.5Error handling . . . . .2706
63.5.1Bit error . . . . .2706
63.5.2Message error . . . . .2707
63.5.3Bit rising error (BRE) . . . . .2707
63.5.4Short bit period error (SBPE) . . . . .2707
63.5.5Long bit period error (LBPE) . . . . .2707
63.5.6Transmission error detection (TXERR) . . . . .2709
63.6HDMI-CEC interrupts . . . . .2710
63.7HDMI-CEC registers . . . . .2711
63.7.1CEC control register (CEC_CR) . . . . .2711
63.7.2CEC configuration register (CEC_CFGR) . . . . .2712
63.7.3CEC Tx data register (CEC_TXDR) . . . . .2714
63.7.4CEC Rx data register (CEC_RXDR) . . . . .2714
63.7.5CEC interrupt and status register (CEC_ISR) . . . . .2714
63.7.6CEC interrupt enable register (CEC_IER) . . . . .2716
63.7.7HDMI-CEC register map . . . . .2718
64Debug infrastructure . . . . .2719
64.1Introduction . . . . .2719
64.2Debug infrastructure features . . . . .2720
64.3Debug infrastructure functional description . . . . .2721
64.3.1Debug infrastructure block diagram . . . . .2721
64.3.2Debug infrastructure pins and internal signals . . . . .2721
64.3.3Debug infrastructure powering, clocking and reset . . . . .2723
64.4Debug access port functional description . . . . .2725
64.4.1Serial-wire and JTAG debug port (SWJ-DP) . . . . .2725
64.4.2Access ports . . . . .2739
64.5Trace and debug subsystem functional description . . . . .2744
64.5.1System ROM tables . . . . .2744
64.5.2Cross trigger interfaces (CTI) and matrix (CTM) . . . . .2753
64.5.3Trace funnel (CSTF) . . . . .2773
64.5.4Embedded trace FIFO (ETF) . . . . .2784
64.5.5Trace port interface unit (TPIU) . . . . .2807
64.5.6Serial-wire output (SWO) . . . . .2826
64.5.7Microcontroller debug unit (DBGMCU) . . . . .2839
64.6Cortex-M7 debug functional description . . . . .2845
64.6.1Cortex-M7 ROM tables . . . . .2846
64.6.2Cortex-M7 data watchpoint and trace unit (DWT) . . . . .2860
64.6.3Cortex-M7 instrumentation trace macrocell (ITM) . . . . .2874
64.6.4Cortex-M7 breakpoint unit (FPB) . . . . .2883
64.6.5Cortex-M7 embedded trace macrocell (ETM) . . . . .2890
64.6.6Cortex-M7 cross trigger interface (CTI) . . . . .2922
64.7References for debug infrastructure . . . . .2922
65Device electronic signature . . . . .2923
65.1Unique device ID register (96 bits) . . . . .2923
65.2Flash size . . . . .2924
65.3Package data register . . . . .2924
66Important security notice . . . . .2926
67Revision history . . . . .2927

List of tables

Table 1.Availability of security features . . . . .101
Table 2.Bus-master-to-bus-slave interconnect . . . . .102
Table 3.ASIB configuration . . . . .110
Table 4.AMIB configuration . . . . .110
Table 5.AXI interconnect register map and reset values . . . . .120
Table 6.Memory map and default device memory area attributes . . . . .132
Table 7.Register boundary addresses . . . . .134
Table 8.Boot modes . . . . .139
Table 9.RAMECC internal input/output signals . . . . .143
Table 10.ECC controller mapping . . . . .143
Table 11.RAMECC register map and reset values . . . . .148
Table 12.FLASH internal input/output signals . . . . .151
Table 13.Flash memory organization (STM32H7A3xl/7B3xl devices) . . . . .154
Table 14.Flash memory organization (STM32H7B0 devices) . . . . .155
Table 15.Flash memory organization (STM32H7A3xG devices) . . . . .155
Table 16.FLASH recommended number of wait states and programming delay . . . . .162
Table 17.Flash memory OTP organization . . . . .173
Table 18.Read-only public data organization . . . . .175
Table 19.FLASH AXI interface memory map and the swapping option . . . . .175
Table 20.Flash register map vs swapping option . . . . .178
Table 21.Option byte organization . . . . .183
Table 22.Flash interface register protection summary . . . . .189
Table 23.RDP value vs readout protection level . . . . .191
Table 24.Protection vs RDP Level . . . . .192
Table 25.RDP transition and its effects . . . . .194
Table 26.Effect of low-power modes on the embedded flash memory . . . . .198
Table 27.Flash interrupt request . . . . .205
Table 28.Register map and reset value table . . . . .248
Table 29.List of preferred terms . . . . .254
Table 30.RSS API addresses . . . . .258
Table 31.Summary of flash protected areas access rights . . . . .261
Table 32.PWR input/output signals connected to package pins or balls . . . . .263
Table 33.PWR internal input/output signals . . . . .264
Table 34.Supply configuration control . . . . .269
Table 35.Operating mode summary . . . . .291
Table 36.PDDS_SRD and RETDS_CD low-power mode control . . . . .294
Table 37.Low-power exit mode flags . . . . .295
Table 38.CSleep mode . . . . .305
Table 39.Autonomous mode . . . . .306
Table 40.Stop mode operation . . . . .308
Table 41.Memory shut-off block selection . . . . .308
Table 42.Stop mode . . . . .310
Table 43.Standby and Stop flags . . . . .311
Table 44.Standby mode . . . . .311
Table 45.Overview of low-power mode monitoring pins . . . . .312
Table 46.GPIO state according to CPU and domain state . . . . .312
Table 47.Power control register map and reset values . . . . .324
Table 48.BDMA2 and DMAMUX2 initialization sequence (DMAMUX2_INIT) . . . . .332
Table 49.LPUART1 Initial programming (LPUART1_INIT) . . . . .334
Table 50.LPUART1 start programming (LPUART1_Start) . . . . .334
Table 51.RCC input/output signals connected to package pins or balls . . . . .338
Table 52.RCC internal input/output signals . . . . .339
Table 53.Reset distribution summary . . . . .342
Table 54.Reset source identification (RCC_RSR). . . . .343
Table 55.Ratio between clock timer and pclk . . . . .362
Table 56.STOPWUCK and STOPKERWUCK description. . . . .363
Table 57.HSIKERON and CSIKERON behavior . . . . .364
Table 58.Kernel clock distribution overview. . . . .365
Table 59.System states overview . . . . .379
Table 60.Peripheral clock enabling for the CPU domain peripherals . . . . .382
Table 61.Peripheral clock enabling for SmartRun domain peripherals . . . . .384
Table 62.Interrupt sources and control . . . . .388
Table 63.RCC register map and reset values . . . . .477
Table 64.CRS features . . . . .484
Table 65.CRS internal input/output signals . . . . .485
Table 66.CRS interconnection. . . . .486
Table 67.Effect of low-power modes on CRS . . . . .489
Table 68.Interrupt control bits . . . . .489
Table 69.CRS register map and reset values . . . . .494
Table 70.HSEM internal input/output signals. . . . .497
Table 71.Authorized AHB bus master ID . . . . .502
Table 72.HSEM register map and reset values . . . . .508
Table 73.Port bit configuration table . . . . .511
Table 74.GPIO register map and reset values . . . . .527
Table 75.SYSCFG register map and reset values. . . . .541
Table 76.Peripherals interconnect matrix (CD domain) . . . . .543
Table 77.Peripherals interconnect matrix (SRD domain) . . . . .544
Table 78.Peripherals interconnect matrix details. . . . .544
Table 79.EXTI wakeup inputs . . . . .556
Table 80.EXTI pending requests clear inputs . . . . .559
Table 81.MDMA. . . . .561
Table 82.DMAMUX1, DMA1, DMA2 and BDMA1 connections . . . . .563
Table 83.DMAMUX2 and BDMA2 connections . . . . .568
Table 84.MDMA internal input/output signals . . . . .573
Table 85.MDMA interrupt requests . . . . .579
Table 86.MDMA register map and reset values . . . . .595
Table 87.DMA internal input/output signals. . . . .598
Table 88.Source and destination address . . . . .600
Table 89.Source and destination address registers in double-buffer mode (DBM = 1). . . . .606
Table 90.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .607
Table 91.Restriction on NDT versus PSIZE and MSIZE . . . . .607
Table 92.FIFO threshold configurations . . . . .610
Table 93.Possible DMA configurations . . . . .614
Table 94.DMA interrupt requests. . . . .616
Table 95.DMA register map and reset values . . . . .626
Table 96.BDMA1 and BDMA2 implementation . . . . .631
Table 97.BDMA internal input/output signals. . . . .634
Table 98.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .640
Table 99.BDMA interrupt requests . . . . .642
Table 100.BDMA register map and reset values . . . . .652
Table 101.DMAMUX1 and DMAMUX2 instantiation . . . . .656
Table 102.DMAMUX1: assignment of multiplexer inputs to resources . . . . .657
Table 103.DMAMUX1: assignment of trigger inputs to resources . . . . .658
Table 104.DMAMUX1: assignment of synchronization inputs to resources . . . . .658
Table 105.DMAMUX2: assignment of multiplexer inputs to resources . . . . .658
Table 106.DMAMUX2: assignment of trigger inputs to resources . . . . .660
Table 107.DMAMUX2: assignment of synchronization inputs to resources . . . . .660
Table 108.DMAMUX signals . . . . .662
Table 109.DMAMUX interrupts . . . . .666
Table 110.DMAMUX register map and reset values . . . . .675
Table 111.DMAMUX register map and reset values . . . . .677
Table 112.DMA2D internal input/output signals . . . . .681
Table 113.Supported color mode in input . . . . .682
Table 114.Data order in memory . . . . .683
Table 115.Alpha mode configuration . . . . .684
Table 116.Supported CLUT color mode . . . . .685
Table 117.CLUT data order in memory . . . . .685
Table 118.Supported color mode in output . . . . .686
Table 119.Data order in memory . . . . .686
Table 120.Standard data order in memory . . . . .687
Table 121.Output FIFO byte reordering steps . . . . .688
Table 122.MCU order in memory . . . . .693
Table 123.DMA2D interrupt requests . . . . .694
Table 124.DMA2D register map and reset values . . . . .711
Table 125.NVIC . . . . .714
Table 126.EXTI event input configurations and register control . . . . .724
Table 127.Configurable event input asynchronous edge detector reset . . . . .726
Table 128.EXTI Event input mapping . . . . .731
Table 129.Masking functionality . . . . .733
Table 130.Asynchronous interrupt/event controller register map and reset values . . . . .753
Table 131.GFXMMU interrupt requests . . . . .765
Table 132.GFXMMU register map and reset values . . . . .773
Table 133.CRC internal input/output signals . . . . .775
Table 134.CRC register map and reset values . . . . .780
Table 135.FMC pins . . . . .784
Table 136.FMC bank mapping options . . . . .787
Table 137.NOR/PSRAM bank selection . . . . .787
Table 138.NOR/PSRAM External memory address . . . . .787
Table 139.NAND memory mapping and timing registers . . . . .788
Table 140.NAND bank selection . . . . .788
Table 141.SDRAM bank selection . . . . .788
Table 142.SDRAM address mapping . . . . .789
Table 143.SDRAM address mapping with 8-bit data bus width . . . . .789
Table 144.SDRAM address mapping with 16-bit data bus width . . . . .790
Table 145.SDRAM address mapping with 32-bit data bus width . . . . .791
Table 146.Programmable NOR/PSRAM access parameters . . . . .793
Table 147.Non-multiplexed I/O NOR flash memory . . . . .793
Table 148.16-bit multiplexed I/O NOR flash memory . . . . .794
Table 149.Non-multiplexed I/Os PSRAM/SRAM . . . . .794
Table 150.16-Bit multiplexed I/O PSRAM . . . . .794
Table 151.NOR flash/PSRAM: Example of supported memories
and transactions . . . . .		795
Table 152.FMC_BCRx bitfields (mode 1) .....798
Table 153.FMC_BTRx bitfields (mode 1) .....799
Table 154.FMC_BCRx bitfields (mode A) .....801
Table 155.FMC_BTRx bitfields (mode A) .....802
Table 156.FMC_BWTRx bitfields (mode A) .....802
Table 157.FMC_BCRx bitfields (mode 2/B) .....804
Table 158.FMC_BTRx bitfields (mode 2/B) .....805
Table 159.FMC_BWTRx bitfields (mode 2/B) .....805
Table 160.FMC_BCRx bitfields (mode C) .....807
Table 161.FMC_BTRx bitfields (mode C) .....808
Table 162.FMC_BWTRx bitfields (mode C) .....808
Table 163.FMC_BCRx bitfields (mode D) .....810
Table 164.FMC_BTRx bitfields (mode D) .....810
Table 165.FMC_BWTRx bitfields (mode D) .....811
Table 166.FMC_BCRx bitfields (Muxed mode) .....813
Table 167.FMC_BTRx bitfields (Muxed mode) .....813
Table 168.FMC_BCRx bitfields (Synchronous multiplexed read mode) .....819
Table 169.FMC_BTRx bitfields (Synchronous multiplexed read mode) .....819
Table 170.FMC_BCRx bitfields (Synchronous multiplexed write mode) .....820
Table 171.FMC_BTRx bitfields (Synchronous multiplexed write mode) .....821
Table 172.Programmable NAND flash access parameters .....831
Table 173.8-bit NAND flash memory .....831
Table 174.16-bit NAND flash memory .....832
Table 175.Supported memories and transactions .....832
Table 176.ECC result relevant bits .....842
Table 177.SDRAM signals .....843
Table 178.FMC register map .....860
Table 179.OCTOSPI implementation .....864
Table 180.OCTOSPI input/output pins .....866
Table 181.OCTOSPI internal signals .....866
Table 182.Command/address phase description .....875
Table 183.OctaRAM command address bit assignment
(based on 64-Mbyte OctaRAM) .....		886
Table 184.Address alignment cases .....893
Table 185.OCTOSPI interrupt requests .....894
Table 186.OCTOSPI register map and reset values .....917
Table 187.OCTOSPIM implementation .....921
Table 188.OCTOSPIM input/output pins .....922
Table 189.OCTOSPIM register map and reset values .....927
Table 190.DLYB internal input/output signals .....929
Table 191.Delay block control .....929
Table 192.DLYB register map and reset values .....932
Table 193.ADC features .....935
Table 194.ADC input/output pins .....937
Table 195.ADC internal input/output signals .....937
Table 196.ADC interconnection .....938
Table 197.Configuring the trigger polarity for regular external triggers .....957
Table 198.Configuring the trigger polarity for injected external triggers .....957
Table 199.ADC1 and ADC2- External triggers for regular channels .....958
Table 200.ADC1 and ADC2 - External triggers for injected channels .....959
Table 201.TSAR timings depending on resolution .....971
Table 202.Offset computation versus data resolution .....974
Table 203.16-bit data formats . . . . .977
Table 204.Numerical examples for 16-bit format (bold indicates saturation). . . . .977
Table 205.Analog watchdog channel selection . . . . .986
Table 206.Analog watchdog 1,2,3 comparison . . . . .987
Table 207.Oversampler operating modes summary . . . . .994
Table 208.ADC interrupts per each ADC. . . . .1013
Table 209.DELAY bits versus ADC resolution. . . . .1052
Table 210.ADC global register map. . . . .1054
Table 211.ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC). . . . .1054
Table 212.ADC register map and reset values (master and slave ADC common registers) offset =0x300) . . . . .1057
Table 213.DTS internal input/output signals . . . . .1059
Table 214.Sampling time configuration . . . . .1062
Table 215.Trigger configuration . . . . .1063
Table 216.Temperature sensor behavior in low-power modes . . . . .1064
Table 217.Interrupt control bits . . . . .1066
Table 218.DTS register map and reset values . . . . .1074
Table 219.DAC features . . . . .1077
Table 220.DAC input/output pins. . . . .1079
Table 221.DAC internal input/output signals . . . . .1079
Table 222.DAC1 interconnection . . . . .1080
Table 223.DAC2 interconnection . . . . .1080
Table 224.Sample and refresh timings . . . . .1087
Table 225.Channel output modes summary . . . . .1088
Table 226.Effect of low-power modes on DAC1 . . . . .1095
Table 227.Effect of low-power modes on DAC2 . . . . .1095
Table 228.DAC interrupts . . . . .1095
Table 229.DAC register map and reset values . . . . .1110
Table 230.VREF buffer modes . . . . .1112
Table 231.VREFBUF register map and reset values. . . . .1114
Table 232.COMP input/output internal signals . . . . .1117
Table 233.COMP input/output pins . . . . .1118
Table 234.COMP interconnection . . . . .1118
Table 235.COMP1_OUT assignment to GPIOs . . . . .1120
Table 236.COMP2_OUT assignment to GPIOs . . . . .1121
Table 237.Comparator behavior in the low-power modes . . . . .1123
Table 238.Interrupt control bits . . . . .1124
Table 239.Interrupt control bits . . . . .1124
Table 240.COMP register map and reset values. . . . .1132
Table 241.Operational amplifier possible connections . . . . .1134
Table 242.Operating modes and calibration . . . . .1142
Table 243.Effect of low-power modes on the OPAMP . . . . .1144
Table 244.OPAMP register map and reset values . . . . .1151
Table 245.DFSDMx implementation . . . . .1154
Table 246.DFSDM1 external pins . . . . .1156
Table 247.DFSDM2 external pins . . . . .1156
Table 248.DFSDM1 internal signals . . . . .1156
Table 249.DFSDM2 internal signals . . . . .1157
Table 250.DFSDM triggers connection . . . . .1157
Table 251.DFSDM1 break connection. . . . .1157
Table 252.Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . .1173
Table 253. Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .1174
Table 254. DFSDM interrupt requests . . . . .1182
Table 255. DFSDM register map and reset values. . . . .1203
Table 256. DCMI input/output pins . . . . .1219
Table 257. DCMI internal input/output signals . . . . .1219
Table 258. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1221
Table 259. Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .1221
Table 260. Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .1221
Table 261. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .1222
Table 262. Data storage in monochrome progressive video format . . . . .1227
Table 263. Data storage in RGB progressive video format . . . . .1228
Table 264. Data storage in YCbCr progressive video format . . . . .1228
Table 265. Data storage in YCbCr progressive video format - Y extraction mode . . . . .1228
Table 266. DCMI interrupts. . . . .1229
Table 267. DCMI register map and reset values . . . . .1239
Table 268. PSSI input/output pins . . . . .1242
Table 269. PSSI internal input/output signals . . . . .1242
Table 270. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1243
Table 271. Positioning of captured data bytes in 32-bit words (16-bit width) . . . . .1244
Table 272. PSSI interrupt requests. . . . .1247
Table 273. PSSI register map and reset values . . . . .1253
Table 274. LTDC external pins . . . . .1255
Table 275. LTDC internal signals . . . . .1256
Table 276. Clock domain for each register . . . . .1256
Table 277. LTDC register access and update durations . . . . .1257
Table 278. Pixel data mapping versus color format . . . . .1261
Table 279. LTDC interrupt requests . . . . .1265
Table 280. LTDC register map and reset values . . . . .1282
Table 281. JPEG internal signals . . . . .1286
Table 282. JPEG codec interrupt requests . . . . .1290
Table 283. JPEG codec register map and reset values . . . . .1303
Table 284. RNG internal input/output signals . . . . .1306
Table 285. RNG interrupt requests. . . . .1313
Table 286. RNG configurations . . . . .1314
Table 287. Configuration selection . . . . .1315
Table 288. RNG register map and reset map. . . . .1319
Table 289. CRYP internal input/output signals . . . . .1323
Table 290. Counter mode initialization vector. . . . .1347
Table 291. GCM last block definition . . . . .1350
Table 292. GCM mode IV registers initialization. . . . .1350
Table 293. CCM mode IV registers initialization. . . . .1357
Table 294. DES/TDES data swapping example . . . . .1361
Table 295. AES data swapping example . . . . .1362
Table 296. Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .1364
Table 297. Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .1364
Table 298. Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . .1365
Table 299. Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . .1365
Table 300. Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .1365
Table 301. Cryptographic processor configuration for
peripheral-to-memory DMA transfers . . . . .1366
Table 302. CRYPT interrupt requests . . . . .1368
Table 303. Processing latency for ECB, CBC and CTR . . . . .1369
Table 304. Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .1369
Table 305. CRYPT register map and reset values . . . . .1383
Table 306. HASH internal input/output signals . . . . .1388
Table 307. Hash processor outputs . . . . .1391
Table 308. Processing time (in clock cycle) . . . . .1397
Table 309. HASH interrupt requests . . . . .1398
Table 310. HASH register map and reset values . . . . .1406
Table 311. OTFDEC internal input/output signals . . . . .1410
Table 312. OTFDEC interrupt requests . . . . .1415
Table 313. OTFDEC register map and reset values . . . . .1426
Table 314. Behavior of timer outputs versus BRK/BRK2 inputs . . . . .1471
Table 315. Break protection disarming conditions . . . . .1473
Table 316. Counting direction versus encoder signals . . . . .1479
Table 317. TIMx internal trigger connection . . . . .1496
Table 318. Output control bits for complementary OCx and OCxN channels with break feature . . . . .1510
Table 319. TIM1 register map and reset values . . . . .1531
Table 320. TIM8 register map and reset values . . . . .1533
Table 321. Counting direction versus encoder signals . . . . .1569
Table 322. TIMx internal trigger connection . . . . .1587
Table 323. Output control bit for standard OCx channels . . . . .1598
Table 324. TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1609
Table 325. TIMx internal trigger connection . . . . .1640
Table 326. Output control bit for standard OCx channels . . . . .1648
Table 327. TIM12 register map and reset values . . . . .1651
Table 328. Output control bit for standard OCx channels . . . . .1660
Table 329. TIM13/TIM14 register map and reset values . . . . .1663
Table 330. Break protection disarming conditions . . . . .1693
Table 331. TIMx Internal trigger connection . . . . .1709
Table 332. Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .1719
Table 333. TIM15 register map and reset values . . . . .1728
Table 334. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .1741
Table 335. TIM16/TIM17 register map and reset values . . . . .1752
Table 336. TIMx register map and reset values . . . . .1766
Table 337. STM32H7A3/7B3 and STM32H7B0 LPTIM features . . . . .1768
Table 338. LPTIM input/output pins . . . . .1769
Table 339. LPTIM internal signals . . . . .1769
Table 340. LPTIM1 external trigger connection . . . . .1770
Table 341. LPTIM2 external trigger connection . . . . .1770
Table 342. LPTIM3 external trigger connection . . . . .1771
Table 343. LPTIM1 input 1 connection . . . . .1771
Table 344. LPTIM1 input 2 connection . . . . .1771
Table 345. LPTIM2 input 1 connection . . . . .1771
Table 346. LPTIM2 input 2 connection . . . . .1771
Table 347. Prescaler division ratios . . . . .1773
Table 348. Encoder counting scenarios . . . . .1780
Table 349. Effect of low-power modes on the LPTIM . . . . .1781
Table 350. Interrupt events . . . . .1782
Table 351.LPTIM register map and reset values . . . . .1793
Table 352.WWDG internal input/output signals . . . . .1795
Table 353.WWDG register map and reset values . . . . .1799
Table 354.IWDG internal input/output signals . . . . .1801
Table 355.IWDG register map and reset values . . . . .1809
Table 356.RTC input/output pins . . . . .1812
Table 357.RTC internal input/output signals . . . . .1812
Table 358.RTC interconnection . . . . .1813
Table 359.RTC pin PC13 configuration . . . . .1813
Table 360.PI8 configuration . . . . .1815
Table 361.RTC_OUT mapping . . . . .1817
Table 362.Effect of low-power modes on RTC . . . . .1827
Table 363.RTC pins functionality over modes . . . . .1828
Table 364.Interrupt requests . . . . .1828
Table 365.RTC register map and reset values . . . . .1849
Table 366.TAMP input/output pins . . . . .1853
Table 367.TAMP internal input/output signals . . . . .1853
Table 368.TAMP interconnection . . . . .1853
Table 369.Minimum ATPER value . . . . .1856
Table 370.Effect of low-power modes on TAMP . . . . .1858
Table 371.TAMP pins functionality over modes . . . . .1858
Table 372.Interrupt requests . . . . .1858
Table 373.TAMP register map and reset values . . . . .1872
Table 374.I2C implementation . . . . .1875
Table 375.I2C input/output pins . . . . .1876
Table 376.I2C internal input/output signals . . . . .1877
Table 377.Comparison of analog and digital filters . . . . .1879
Table 378.I 2 C-bus and SMBus specification data setup and hold times . . . . .1881
Table 379.I2C configuration . . . . .1885
Table 380.I 2 C-bus and SMBus specification clock timings . . . . .1896
Table 381.Timing settings for f I2CCLK of 8 MHz . . . . .1906
Table 382.Timing settings for f I2CCLK of 16 MHz . . . . .1906
Table 383.Timing settings for f I2CCLK of 48 MHz . . . . .1907
Table 384.SMBus timeout specifications . . . . .1909
Table 385.SMBus with PEC configuration . . . . .1911
Table 386.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1912
Table 387.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1912
Table 388.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1912
Table 389.Effect of low-power modes to I2C . . . . .1922
Table 390.I2C interrupt requests . . . . .1922
Table 391.I2C register map and reset values . . . . .1938
Table 392.USART / LPUART features . . . . .1941
Table 393.USART/UART input/output pins . . . . .1944
Table 394.USART internal input/output signals . . . . .1944
Table 395.Noise detection from sampled data . . . . .1956
Table 396.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1959
Table 397.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1960
Table 398.USART frame formats . . . . .1965
Table 399.Effect of low-power modes on the USART . . . . .1988
Table 400.USART interrupt requests . . . . .1989
Table 401.USART register map and reset values . . . . .2023
Table 402.USART / LPUART features . . . . .2027
Table 403.LPUART input/output pins . . . . .2029
Table 404.LPUART internal input/output signals . . . . .2029
Table 405.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .2039
Table 406.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .2040
Table 407.Tolerance of the LPUART receiver . . . . .2041
Table 409.Effect of low-power modes on the LPUART . . . . .2052
Table 410.LPUART interrupt requests . . . . .2053
Table 411.LPUART register map and reset values . . . . .2077
Table 412.STM32H7A3/7B3/7B0xx SPI features . . . . .2080
Table 413.SPI wake-up and interrupt requests . . . . .2112
Table 414.Bitfields usable in PCM/I2S mode . . . . .2115
Table 415.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .2123
Table 416.Serial data line swapping . . . . .2123
Table 417.CLKGEN programming examples for usual I2S frequencies . . . . .2128
Table 418.I2S interrupt requests . . . . .2137
Table 419.SPI register map and reset values . . . . .2156
Table 420.STM32H7A3/7B3 and STM32H7B0 SAI features . . . . .2159
Table 421.SAI internal input/output signals . . . . .2161
Table 422.SAI input/output pins . . . . .2161
Table 423.External synchronization selection . . . . .2164
Table 424.MCLK_x activation conditions . . . . .2169
Table 425.Clock generator programming examples . . . . .2172
Table 426.SAI_A configuration for TDM mode . . . . .2179
Table 427.TDM frame configuration examples . . . . .2181
Table 428.SOPD pattern . . . . .2185
Table 429.Parity bit calculation . . . . .2185
Table 430.Audio sampling frequency versus symbol rates . . . . .2186
Table 431.SAI interrupt sources . . . . .2195
Table 432.SAI register map and reset values . . . . .2224
Table 433.SPDIFRX internal input/output signals . . . . .2227
Table 434.SPDIFRX pins . . . . .2227
Table 435.Transition sequence for preamble . . . . .2233
Table 436.Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . .2243
Table 437.Conditions of spdifrx_symb_ck generation . . . . .2244
Table 438.Bit field property versus SPDIFRX state . . . . .2247
Table 439.SPDIFRX interface register map and reset values . . . . .2259
Table 440.SWPMI input/output signals connected to package pins or balls . . . . .2262
Table 441.SWPMI internal input/output signals . . . . .2263
Table 442.Effect of low-power modes on SWPMI . . . . .2277
Table 443.Interrupt control bits . . . . .2278
Table 444.Buffer modes selection for transmission/reception . . . . .2280
Table 445.SWPMI register map and reset values . . . . .2287
Table 446.MDIOS input/output signals connected to package pins or balls . . . . .2289
Table 447.MDIOS internal input/output signals . . . . .2289
Table 448.Interrupt control bits . . . . .2294
Table 449.MDIOS register map and reset values . . . . .2299
Table 450.SDMMC features . . . . .2301
Table 451.SDMMC operation modes SD and SDIO . . . . .2304
Table 452.SDMMC operation modes e•MMC . . . . .2304
Table 453.SDMMC internal input/output signals . . . . .2305
Table 454.SDMMC pins . . . . .2306
Table 455.SDMMC Command and data phase selection . . . . .2307
Table 456.Command token format . . . . .2313
Table 457.Short response with CRC token format . . . . .2314
Table 458.Short response without CRC token format . . . . .2314
Table 459.Long response with CRC token format . . . . .2314
Table 460.Specific Commands overview . . . . .2315
Table 461.Command path status flags . . . . .2316
Table 462.Command path error handling . . . . .2316
Table 463.Data token format . . . . .2324
Table 464.Data path status flags and clear bits . . . . .2324
Table 465.Data path error handling . . . . .2326
Table 466.Data FIFO access . . . . .2327
Table 467.Transmit FIFO status flags . . . . .2328
Table 468.Receive FIFO status flags . . . . .2329
Table 469.SDMMC connections to MDMA . . . . .2333
Table 470.AHB and SDMMC_CK clock frequency relation . . . . .2333
Table 471.SDIO special operation control . . . . .2334
Table 472.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .2338
Table 473.CMD12 use cases . . . . .2343
Table 474.SDMMC interrupts . . . . .2357
Table 475.Response type and SDMMC_RESPxR registers . . . . .2364
Table 476.SDMMC register map . . . . .2379
Table 477.CAN subsystem I/O signals . . . . .2382
Table 478.CAN subsystem I/O pins . . . . .2383
Table 479.CAN triggers . . . . .2383
Table 480.Main features . . . . .2385
Table 481.DLC coding in FDCAN . . . . .2390
Table 482.Example of filter configuration for Rx buffers . . . . .2403
Table 483.Example of filter configuration for Debug messages . . . . .2404
Table 484.Possible configurations for frame transmission . . . . .2404
Table 485.Tx buffer/FIFO - Queue element size . . . . .2405
Table 486.First byte of level 1 reference message . . . . .2415
Table 487.First four bytes of level 2 reference message . . . . .2416
Table 488.First four bytes of level 0 reference message . . . . .2416
Table 489.TUR configuration example . . . . .2417
Table 490.System matrix, Node A . . . . .2422
Table 491.Trigger list, Node A . . . . .2423
Table 492.Number of data bytes transmitted with a reference message . . . . .2430
Table 493.Rx buffer and FIFO element . . . . .2437
Table 494.Rx buffer and FIFO element description . . . . .2437
Table 495.Tx buffer and FIFO element . . . . .2439
Table 496.Tx buffer element description . . . . .2439
Table 497.Tx Event FIFO element . . . . .2441
Table 498.Tx Event FIFO element description . . . . .2441
Table 499.Standard message ID filter element . . . . .2442
Table 500.Standard message ID filter element field description . . . . .2443
Table 501.Extended message ID filter element . . . . .2444
Table 502.Extended message ID filter element field description . . . . .2444
Table 503.Trigger memory element . . . . .2445
Table 504.Trigger memory element description . . . . .2445
Table 505.FDCAN register map and reset values . . . . .2483
Table 506.FDCAN TT register map and reset values . . . . .2505
Table 507.CCU register map and reset values . . . . .2511
Table 508.OTG_HS speeds supported . . . . .2514
Table 509.OTG_HS implementation . . . . .2516
Table 510.OTG_HS input/output pins . . . . .2517
Table 511.OTG_HS input/output signals . . . . .2517
Table 512.Compatibility of STM32 low power modes with the OTG . . . . .2530
Table 513.FIFO allocation for DMA address register storage
(OTG_DIEPDMAX/DOEPDMAX and OTG_HCDMAX) . . . . .		2532
Table 514.Core global control and status registers (CSRs). . . . .2539
Table 515.Host-mode control and status registers (CSRs) . . . . .2540
Table 516.Device-mode control and status registers . . . . .2542
Table 517.Data FIFO (DFIFO) access register map . . . . .2544
Table 518.Power and clock gating control and status registers . . . . .2544
Table 519.TRDT values . . . . .2552
Table 520.Minimum duration for soft disconnect . . . . .2597
Table 521.OTG_HS register map and reset values . . . . .2625
Table 522.HDMI pin . . . . .2702
Table 523.HDMI-CEC internal input/output signals . . . . .2702
Table 524.Error handling timing parameters . . . . .2708
Table 525.TXERR timing parameters . . . . .2709
Table 526.HDMI-CEC interrupts . . . . .2710
Table 527.HDMI-CEC register map and reset values . . . . .2718
Table 528.JTAG/Serial-wire debug port pins . . . . .2721
Table 529.Trace port pins . . . . .2722
Table 530.Serial-wire trace port pins . . . . .2722
Table 531.Trigger pins . . . . .2722
Table 532.Packet request . . . . .2726
Table 533.ACK response . . . . .2726
Table 534.Data transfer . . . . .2726
Table 535.JTAG-DP data registers . . . . .2729
Table 536.Debug port registers . . . . .2730
Table 537.MEM-AP registers . . . . .2740
Table 538.System ROM table 1 . . . . .2744
Table 539.System ROM table 2 . . . . .2745
Table 540.System ROM table 1 register map and reset values . . . . .2751
Table 541.System ROM table 2 register map and reset values . . . . .2752
Table 542.System CTI inputs . . . . .2754
Table 543.System CTI outputs . . . . .2755
Table 544.Cortex-M7 CTI inputs . . . . .2755
Table 545.Cortex-M7 CTI outputs . . . . .2755
Table 546.CTI register map and reset values . . . . .2771
Table 547.CSTF register map and reset values . . . . .2783
Table 548.ETF register map and reset values . . . . .2805
Table 549.TPIU register map and reset values . . . . .2823
Table 550.SWO register map and reset values . . . . .2836
Table 551.DBGMCU register map and reset values . . . . .2845
Table 552.Cortex-M7 CPU ROM table . . . . .2846
Table 553.Cortex-M7 PPB ROM table . . . . .2846
Table 554.Cortex-M7 CPU ROM table register map and reset values . . . . .2852
Table 555.Cortex-M7 PPB ROM table register map and reset values . . . . .2858
Table 556.Cortex-M7 DWT register map and reset values . . . . .2872
Table 557.Cortex-M7 ITM register map and reset values . . . . .2881
Table 558.Cortex-M7 FPB register map and reset values . . . . .2888
Table 559. Cortex-M7 ETM register map and reset values . . . . .2917
Table 560. Document revision history . . . . .2927

List of figures

Figure 1.System architecture for STM32H7A3/7B3/7B0xx devices . . . . .104
Figure 2.AXI interconnect . . . . .109
Figure 3.RAM ECC controller implementation schematic. . . . .142
Figure 4.Connection between RAM ECC controller and RAMECC monitoring unit . . . . .142
Figure 5.FLASH block diagram . . . . .150
Figure 6.Detailed FLASH architecture . . . . .152
Figure 7.Embedded flash memory organization . . . . .153
Figure 8.Embedded flash memory usage . . . . .157
Figure 9.FLASH protection mechanisms . . . . .159
Figure 10.FLASH read pipeline architecture . . . . .161
Figure 11.FLASH write pipeline architecture . . . . .165
Figure 12.Flash bank swapping sequence . . . . .177
Figure 13.RDP protection transition scheme . . . . .193
Figure 14.Example of protected region overlapping . . . . .195
Figure 15.Flash memory areas and services in Standard and Secure access modes . . . . .256
Figure 16.Bootloader state machine in Secure access mode . . . . .257
Figure 17.Core access to flash memory areas . . . . .261
Figure 18.Power control block diagram . . . . .263
Figure 19.Power supply overview . . . . .267
Figure 20.System supply configurations for packages with SMPS . . . . .268
Figure 21.System supply configurations for packages without SMPS . . . . .269
Figure 22.Device startup with \( V_{CORE} \) supplied from LDO voltage regulator . . . . .272
Figure 23.Device startup with \( V_{CORE} \) supplied from SMPS . . . . .273
Figure 24.Device startup with \( V_{CORE} \) supplied in Bypass mode from external regulator . . . . .274
Figure 25.Backup domain . . . . .279
Figure 26.USB supply configurations . . . . .280
Figure 27.Power-on reset/power-down reset waveform . . . . .281
Figure 28.BOR thresholds . . . . .282
Figure 29.PVD thresholds . . . . .283
Figure 30.AVD thresholds . . . . .284
Figure 31.VBAT thresholds . . . . .285
Figure 32.Temperature thresholds . . . . .286
Figure 33.\( V_{CORE} \) overvoltage protection . . . . .287
Figure 34.\( V_{CORE} \) voltage scaling versus system power modes . . . . .293
Figure 35.Power-control modes detailed state diagram . . . . .294
Figure 36.Dynamic voltage scaling in Run mode . . . . .296
Figure 37.Dynamic voltage scaling behavior with CPU domain and system in Stop mode . . . . .298
Figure 38.Dynamic voltage scaling system Standby mode . . . . .300
Figure 39.Dynamic voltage scaling behavior with CPU domain in DStop or DStop2 mode and SmartRun domain in Autonomous mode . . . . .302
Figure 40.EXTI, RCC and PWR interconnections . . . . .326
Figure 41.Timing diagram of SRD SRAM-to-LPUART1 transfer with BDMA2 and SRD domain in Autonomous mode . . . . .330
Figure 42.BDMA2 and DMAMUX2 interconnection . . . . .332
Figure 43.Timing diagram of LPUART1 transmission with SRD domain in Autonomous mode . . . . .335
Figure 44.RCC block diagram. . . . .338
Figure 45.System reset circuit . . . . .341
Figure 46.Boot sequences versus system states . . . . .346
Figure 47.Top-level clock tree. . . . .348
Figure 48.HSE/LSE clock source . . . . .349
Figure 49.HSE/LSE bypass . . . . .350
Figure 50.HSI calibration flow . . . . .353
Figure 51.CSI calibration flow . . . . .354
Figure 52.PLL block diagram . . . . .357
Figure 53.PLLs Initialization flowchart . . . . .360
Figure 54.Core and bus clock generation . . . . .362
Figure 55.Kernel clock distribution for SAIs, DFSDMs and SPDIFRX . . . . .368
Figure 56.Kernel clock distribution for SPIs and SPI/I2S . . . . .369
Figure 57.Kernel clock distribution for I2Cs . . . . .370
Figure 58.Kernel clock distribution for UARTs, USARTs and LPUART1 . . . . .371
Figure 59.Kernel clock distribution for LTDC . . . . .371
Figure 60.Kernel clock distribution for SDMMC, OCTOSPI and FMC . . . . .372
Figure 61.Kernel clock distribution for USB (2) . . . . .372
Figure 62.Kernel clock distribution for ADCs, SWPMI, RNG and FDCANs . . . . .373
Figure 63.Kernel clock distribution for LPTIMs and HDMI-CEC (2) . . . . .374
Figure 64.Peripheral allocation example. . . . .377
Figure 65.Kernel clock switching . . . . .380
Figure 66.Peripheral kernel clock enable logic details . . . . .382
Figure 67.Bus clock enable logic . . . . .387
Figure 68.CRS block diagram . . . . .485
Figure 69.CRS counter behavior . . . . .487
Figure 70.HSEM block diagram . . . . .497
Figure 71.Procedure state diagram . . . . .498
Figure 72.Interrupt state diagram . . . . .501
Figure 73.Basic structure of an I/O port bit . . . . .510
Figure 74.Basic structure of a 5-Volt tolerant I/O port bit . . . . .510
Figure 75.Input floating / pull up / pull down configurations . . . . .515
Figure 76.Output configuration . . . . .516
Figure 77.Alternate function configuration . . . . .517
Figure 78.High impedance-analog configuration . . . . .518
Figure 79.Analog inputs connected to ADC inputs . . . . .518
Figure 80.Timer break input lockup block diagram . . . . .530
Figure 81.I/O compensation cell block diagram . . . . .531
Figure 82.MDMA block diagram . . . . .573
Figure 83.DMA block diagram . . . . .598
Figure 84.Peripheral-to-memory mode . . . . .602
Figure 85.Memory-to-peripheral mode . . . . .603
Figure 86.Memory-to-memory mode . . . . .604
Figure 87.FIFO structure. . . . .609
Figure 88.BDMA block diagram . . . . .633
Figure 89.DMAMUX block diagram . . . . .661
Figure 90.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .664
Figure 91.Event generation of the DMA request line multiplexer channel . . . . .664
Figure 92.DMA2D block diagram . . . . .681
Figure 93.Intel 8080 16-bit mode (RGB565) . . . . .687
Figure 94.Intel 8080 18/24-bit mode (RGB888) . . . . .688
Figure 95.EXTI block diagram . . . . .723
Figure 96.Configurable event triggering logic CPU wakeup . . . . .725
Figure 97.Configurable event triggering logic Any wakeup . . . . .727
Figure 98.Direct event triggering logic CPU wakeup . . . . .728
Figure 99.Direct event triggering logic Any wakeup . . . . .729
Figure 100.SRD domain pending request clear logic . . . . .730
Figure 101.GFXMMU block diagram . . . . .757
Figure 102.Virtual buffer . . . . .758
Figure 103.Virtual buffer and physical buffer memory map . . . . .759
Figure 104.MMU block diagram . . . . .760
Figure 105.Block validation/comparator implementation . . . . .761
Figure 106.CRC calculation unit block diagram . . . . .775
Figure 107.FMC block diagram. . . . .783
Figure 108.FMC memory banks (default mapping) . . . . .786
Figure 109.Mode 1 read access waveforms . . . . .797
Figure 110.Mode 1 write access waveforms . . . . .798
Figure 111.Mode A read access waveforms . . . . .800
Figure 112.Mode A write access waveforms . . . . .801
Figure 113.Mode 2 and mode B read access waveforms . . . . .803
Figure 114.Mode 2 write access waveforms . . . . .803
Figure 115.Mode B write access waveforms . . . . .804
Figure 116.Mode C read access waveforms . . . . .806
Figure 117.Mode C write access waveforms . . . . .806
Figure 118.Mode D read access waveforms . . . . .809
Figure 119.Mode D write access waveforms . . . . .809
Figure 120.Muxed read access waveforms . . . . .812
Figure 121.Muxed write access waveforms . . . . .812
Figure 122.Asynchronous wait during a read access waveforms . . . . .815
Figure 123.Asynchronous wait during a write access waveforms . . . . .815
Figure 124.Wait configuration waveforms . . . . .818
Figure 125.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .818
Figure 126.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .820
Figure 127.NAND flash controller waveforms for common memory access . . . . .834
Figure 128.Access to non 'CE don't care' NAND-flash . . . . .835
Figure 129.Burst write SDRAM access waveforms . . . . .845
Figure 130.Burst read SDRAM access . . . . .846
Figure 131.Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . .847
Figure 132.Read access crossing row boundary . . . . .849
Figure 133.Write access crossing row boundary . . . . .849
Figure 134.Self-refresh mode . . . . .852
Figure 135.Power-down mode . . . . .853
Figure 136.OCTOSPI block diagram in octal configuration . . . . .865
Figure 137.OCTOSPI block diagram in quad configuration . . . . .865
Figure 138.OCTOSPI block diagram in dual-quad configuration . . . . .866
Figure 139.SDR read command in octal configuration . . . . .868
Figure 140.DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .871
Figure 141.SDR write command in octo-SPI mode example . . . . .873
Figure 142.DTR write in octal-SPI mode (Macronix mode) example . . . . .873
Figure 143.Example of HyperBus read operation . . . . .875
Figure 144.HyperBus write operation with initial latency . . . . .876
Figure 145.HyperBus read operation with additional latency . . . . .877
Figure 146.HyperBus write operation with additional latency . . . . .877
Figure 147.HyperBus write operation with no latency (register write) . . . . .878
Figure 148.HyperBus read operation page crossing with latency . . . . .878
Figure 149.D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .885
Figure 150. OctaRAM read operation with reverse data ordering D1/D0 . . . . .886
Figure 151. NCS when CKMODE = 0 (T = CLK period) . . . . .891
Figure 152. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .892
Figure 153. NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . .892
Figure 154. NCS when CKMODE = 1 with an abort (T = CLK period). . . . .892
Figure 155. OCTOSPIM block diagram . . . . .922
Figure 156. DLYB block diagram . . . . .928
Figure 157. ADC block diagram . . . . .936
Figure 158. ADC Clock scheme . . . . .939
Figure 159. ADC1 connectivity . . . . .940
Figure 160. ADC2 connectivity . . . . .941
Figure 161. ADC calibration . . . . .945
Figure 162. Updating the ADC offset calibration factor . . . . .945
Figure 163. Mixing single-ended and differential channels . . . . .946
Figure 164. Enabling / Disabling the ADC . . . . .950
Figure 165. Analog-to-digital conversion time . . . . .955
Figure 166. Stopping ongoing regular conversions . . . . .956
Figure 167. Stopping ongoing regular and injected conversions . . . . .956
Figure 168. Triggers are shared between ADC master and ADC slave . . . . .958
Figure 169. Injected conversion latency . . . . .961
Figure 170. Example of ADC_JSQR queue of context (sequence change) . . . . .964
Figure 171. Example of ADC_JSQR queue of context (trigger change) . . . . .965
Figure 172. Example of ADC_JSQR queue of context with overflow before conversion. . . . .965
Figure 173. Example of ADC_JSQR queue of context with overflow during conversion . . . . .966
Figure 174. Example of ADC_JSQR queue of context with empty queue (case JQM=0). . . . .966
Figure 175. Example of ADC_JSQR queue of context with empty queue (case JQM=1). . . . .967
Figure 176. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . .		967
Figure 177. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		968
Figure 178. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . .		968
Figure 179. Flushing ADC_JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .969
Figure 180. Flushing ADC_JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .969
Figure 181. Flushing ADC_JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .970
Figure 182. Single conversions of a sequence, software trigger . . . . .972
Figure 183. Continuous conversion of a sequence, software trigger. . . . .972
Figure 184. Single conversions of a sequence, hardware trigger . . . . .973
Figure 185. Continuous conversions of a sequence, hardware trigger . . . . .973
Figure 186. Right alignment (offset disabled, unsigned value) . . . . .975
Figure 187. Right alignment (offset enabled, signed value) . . . . .975
Figure 188. Left alignment (offset disabled, unsigned value) . . . . .976
Figure 189. Left alignment (offset enabled, signed value) . . . . .976
Figure 190. Example of overrun (OVRMOD = 0). . . . .979
Figure 191. Example of overrun (OVRMOD = 1). . . . .979
Figure 192. AUTDLY=1, regular conversion in continuous mode, software trigger . . . . .983
Figure 193. AUTDLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . .		983
Figure 194. AUTDLY=1, regular HW conversions interrupted by injected conversions.
(DISCEN=1, JDISCEN=1) . . . . .		984
Figure 195. AUTDLY=1, regular continuous conversions interrupted by injected conversions . . . . .985
Figure 196. AUTDLY=1 in auto- injected mode (JAUTO=1) . . . . .985
Figure 197. Analog watchdog guarded area . . . . .986
Figure 198. ADC y _AWD x _OUT signal generation (on all regular channels). . . . .988
Figure 199. ADC y _AWD x _OUT signal generation (AWD x flag not cleared by SW) . . . . .988
Figure 200. ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .989
Figure 201. ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .989
Figure 202. 16-bit result oversampling with 10-bits right shift and rounding . . . . .990
Figure 203. Triggered regular oversampling mode (TROVS bit = 1) . . . . .991
Figure 204. Regular oversampling modes (4x ratio) . . . . .992
Figure 205. Regular and injected oversampling modes used simultaneously . . . . .993
Figure 206. Triggered regular oversampling with injection . . . . .993
Figure 207. Oversampling in auto-injected mode . . . . .994
Figure 208. Dual ADC block diagram (1) . . . . .996
Figure 209. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .997
Figure 210. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .999
Figure 211. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .1000
Figure 212. Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . .1001
Figure 213. Interleaved conversion with injection . . . . .1001
Figure 214. Alternate trigger: injected group of each ADC . . . . .1002
Figure 215. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .1003
Figure 216. Alternate + regular simultaneous . . . . .1004
Figure 217. Case of trigger occurring during injected conversion . . . . .1004
Figure 218. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .1005
Figure 219. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		1005
Figure 220. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		1005
Figure 221. DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . .1006
Figure 222. DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . .1007
Figure 223. DMA requests in interleaved mode when DAMDF=0b10 . . . . .1007
Figure 224. Temperature sensor channel block diagram . . . . .1009
Figure 225. VBAT channel block diagram . . . . .1011
Figure 226. VREFINT channel block diagram . . . . .1011
Figure 227. Temperature sensor functional block diagram . . . . .1059
Figure 228. Method for low REF_CLK frequencies . . . . .1061
Figure 229. Method for high REF_CLK frequencies . . . . .1061
Figure 230. Temperature sensor sequence . . . . .1064
Figure 231. Dual-channel DAC block diagram . . . . .1078
Figure 232. Data registers in single DAC channel mode . . . . .1081
Figure 233. Data registers in dual DAC channel mode . . . . .1082
Figure 234. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .1082
Figure 235. DAC LFSR register calculation algorithm . . . . .1084
Figure 236. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .1084
Figure 237. DAC triangle wave generation . . . . .1085
Figure 238. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .1085
Figure 239. DAC sample and hold mode phase diagram . . . . .1088
Figure 240. Comparator block diagram . . . . .1116
Figure 241. Comparator hysteresis . . . . .1119
Figure 242. Comparator output blanking . . . . .1120
Figure 243. Output redirection . . . . .1122
Figure 244. Scaler block diagram . . . . .1123
Figure 245. Standalone mode: external gain setting mode . . . . .1136
Figure 246. Follower configuration. . . . .1137
Figure 247. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .1138
Figure 248. PGA mode, internal gain setting (x2/x4/x8/x16),
inverting input used for filtering. . . . .		1139
Figure 249. PGA mode, non-inverting gain setting (x2/x4/x8/x16)
or inverting gain setting (x-1/x-3/x-7/x-15) . . . . .		1140
Figure 250. Example configuration . . . . .1140
Figure 251. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain
setting (x-1/x-3/x-7/x-15) with filtering. . . . .		1141
Figure 252. Example configuration . . . . .1141
Figure 253. Single DFSDM block diagram. . . . .1155
Figure 254. Input channel pins redirection. . . . .1160
Figure 255. Channel transceiver timing diagrams . . . . .1163
Figure 256. Clock absence timing diagram for SPI . . . . .1164
Figure 257. Clock absence timing diagram for Manchester coding . . . . .1165
Figure 258. First conversion for Manchester coding (Manchester synchronization) . . . . .1167
Figure 259. DFSDM_CHyDATINR registers operation modes and assignment . . . . .1171
Figure 260. Example: Sinc3 filter response . . . . .1173
Figure 261. DCMI block diagram . . . . .1219
Figure 262. DCMI signal waveforms . . . . .1220
Figure 263. Timing diagram . . . . .1222
Figure 264. Frame capture waveforms in snapshot mode. . . . .1224
Figure 265. Frame capture waveforms in continuous grab mode . . . . .1225
Figure 266. Coordinates and size of the window after cropping . . . . .1225
Figure 267. Data capture waveforms. . . . .1226
Figure 268. Pixel raster scan order . . . . .1227
Figure 269. PSSI block diagram . . . . .1241
Figure 270. Top-level block diagram . . . . .1241
Figure 271. Data enable in receive mode waveform diagram (CKPOL=0) . . . . .1245
Figure 272. Data enable waveform diagram in transmit mode (CKPOL=1). . . . .1245
Figure 273. Ready in receive mode waveform diagram (CKPOL=0). . . . .1246
Figure 274. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . .1247
Figure 275. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . .1247
Figure 276. LTDC block diagram . . . . .1255
Figure 277. LTDC synchronous timings. . . . .1258
Figure 278. Layer window programmable parameters . . . . .1261
Figure 279. Blending two layers with background . . . . .1263
Figure 280. Interrupt events. . . . .1265
Figure 281. JPEG codec block diagram . . . . .1286
Figure 282. RNG block diagram . . . . .1306
Figure 283. NIST SP800-90B entropy source model. . . . .1307
Figure 284. RNG initialization overview. . . . .1310
Figure 285. CRYP block diagram . . . . .1322
Figure 286. AES-ECB mode overview. . . . .1325
Figure 287. AES-CBC mode overview. . . . .1326
Figure 288. AES-CTR mode overview. . . . .1327
Figure 289. AES-GCM mode overview . . . . .1328
Figure 290. AES-GMAC mode overview . . . . .1328
Figure 291. AES-CCM mode overview . . . . .1329
Figure 292. Example of suspend mode management. . . . .1334
Figure 293. DES/TDES-ECB mode encryption . . . . .1335
Figure 294. DES/TDES-ECB mode decryption . . . . .1336
Figure 295. DES/TDES-CBC mode encryption . . . . .1337
Figure 296. DES/TDES-CBC mode decryption . . . . .1338
Figure 297. AES-ECB mode encryption . . . . .1340
Figure 298. AES-ECB mode decryption . . . . .1341
Figure 299. AES-CBC mode encryption . . . . .1342
Figure 300. AES-CBC mode decryption . . . . .1343
Figure 301. Message construction for the Counter mode . . . . .1345
Figure 302. AES-CTR mode encryption . . . . .1346
Figure 303. AES-CTR mode decryption . . . . .1347
Figure 304. Message construction for the Galois/counter mode . . . . .1349
Figure 305. Message construction for the Galois Message Authentication Code mode . . . . .1354
Figure 306. Message construction for the Counter with CBC-MAC mode. . . . .1355
Figure 307. 64-bit block construction according to the data type (IN FIFO). . . . .1362
Figure 308. 128-bit block construction according to the data type. . . . .1363
Figure 309. HASH block diagram . . . . .1387
Figure 310. Message data swapping feature . . . . .1389
Figure 311. HASH suspend/resume mechanism. . . . .1395
Figure 312. OTFDEC block diagram . . . . .1409
Figure 313. Typical OTFDEC usage in the device. . . . .1410
Figure 314. AES CTR decryption flow . . . . .1412
Figure 315. OTFDEC flow control overview (dual burst read request) . . . . .1413
Figure 316. OTFDEC flow control overview (burst then single read request) . . . . .1414
Figure 317. Advanced-control timer block diagram . . . . .1431
Figure 318. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1433
Figure 319. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1433
Figure 320. Counter timing diagram, internal clock divided by 1 . . . . .1435
Figure 321. Counter timing diagram, internal clock divided by 2 . . . . .1435
Figure 322. Counter timing diagram, internal clock divided by 4 . . . . .1436
Figure 323. Counter timing diagram, internal clock divided by N . . . . .1436
Figure 324. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1437
Figure 325. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1437
Figure 326. Counter timing diagram, internal clock divided by 1 . . . . .1439
Figure 327. Counter timing diagram, internal clock divided by 2 . . . . .1439
Figure 328. Counter timing diagram, internal clock divided by 4 . . . . .1440
Figure 329. Counter timing diagram, internal clock divided by N . . . . .1440
Figure 330. Counter timing diagram, update event when repetition counter is not used. . . . .1441
Figure 331. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1442
Figure 332. Counter timing diagram, internal clock divided by 2 . . . . .1443
Figure 333. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1443
Figure 334. Counter timing diagram, internal clock divided by N . . . . .1444
Figure 335. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .1444
Figure 336. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1445
Figure 337. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1446
Figure 338. External trigger input block . . . . .1447
Figure 339. TIM1/TIM8 ETR input circuitry . . . . .1447
Figure 340. Control circuit in normal mode, internal clock divided by 1 . . . . .1448
Figure 341. TI2 external clock connection example. . . . .1449
Figure 342. Control circuit in external clock mode 1 . . . . .1450
Figure 343. External trigger input block . . . . .1450
Figure 344. Control circuit in external clock mode 2 . . . . .1451
Figure 345. Capture/compare channel (example: channel 1 input stage). . . . .1452
Figure 346. Capture/compare channel 1 main circuit . . . . .1452
Figure 347. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .1453
Figure 348. Output stage of capture/compare channel (channel 4). . . . .1453
Figure 349. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1454
Figure 350. PWM input mode timing . . . . .1456
Figure 351. Output compare mode, toggle on OC1 . . . . .1458
Figure 352. Edge-aligned PWM waveforms (ARR=8) . . . . .1459
Figure 353. Center-aligned PWM waveforms (ARR=8). . . . .1460
Figure 354. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1462
Figure 355. Combined PWM mode on channel 1 and 3 . . . . .1463
Figure 356. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1464
Figure 357. Complementary output with dead-time insertion . . . . .1465
Figure 358. Dead-time waveforms with delay greater than the negative pulse . . . . .1465
Figure 359. Dead-time waveforms with delay greater than the positive pulse. . . . .1466
Figure 360. Break and Break2 circuitry overview . . . . .1468
Figure 361. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .1470
Figure 362. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .1471
Figure 363. PWM output state following BRK assertion (OSSI=0) . . . . .1472
Figure 364. Output redirection (BRK2 request not represented) . . . . .1473
Figure 365. Clearing TIMx OCxREF . . . . .1474
Figure 366. 6-step generation, COM example (OSSR=1) . . . . .1475
Figure 367. Example of one pulse mode. . . . .1476
Figure 368. Retriggerable one pulse mode . . . . .1478
Figure 369. Example of counter operation in encoder interface mode. . . . .1479
Figure 370. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .1480
Figure 371. Measuring time interval between edges on 3 signals . . . . .1481
Figure 372. Example of Hall sensor interface . . . . .1483
Figure 373. Control circuit in reset mode . . . . .1484
Figure 374. Control circuit in Gated mode . . . . .1485
Figure 375. Control circuit in trigger mode . . . . .1486
Figure 376. Control circuit in external clock mode 2 + trigger mode . . . . .1487
Figure 377. General-purpose timer block diagram . . . . .1537
Figure 378. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1539
Figure 379. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1539
Figure 380. Counter timing diagram, internal clock divided by 1 . . . . .1540
Figure 381. Counter timing diagram, internal clock divided by 2 . . . . .1541
Figure 382. Counter timing diagram, internal clock divided by 4 . . . . .1541
Figure 383. Counter timing diagram, internal clock divided by N. . . . .1542
Figure 384. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1542
Figure 385. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1543
Figure 386. Counter timing diagram, internal clock divided by 1 . . . . .1544
Figure 387. Counter timing diagram, internal clock divided by 2 . . . . .1544
Figure 388. Counter timing diagram, internal clock divided by 4 . . . . .1545
Figure 389. Counter timing diagram, internal clock divided by N. . . . .1545
Figure 390. Counter timing diagram, Update event . . . . .1546
Figure 391. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1547
Figure 392. Counter timing diagram, internal clock divided by 2 . . . . .1548
Figure 393. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1548
Figure 394. Counter timing diagram, internal clock divided by N. . . . .1549
Figure 395. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .1549
Figure 396. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .1550
Figure 397. Control circuit in normal mode, internal clock divided by 1 . . . . .1551
Figure 398. TI2 external clock connection example. . . . .1551
Figure 399.Control circuit in external clock mode 1 . . . . .1552
Figure 400.External trigger input block . . . . .1553
Figure 401.Control circuit in external clock mode 2 . . . . .1554
Figure 402.Capture/Compare channel (example: channel 1 input stage) . . . . .1554
Figure 403.Capture/Compare channel 1 main circuit . . . . .1555
Figure 404.Output stage of Capture/Compare channel (channel 1) . . . . .1555
Figure 405.PWM input mode timing . . . . .1557
Figure 406.Output compare mode, toggle on OC1 . . . . .1559
Figure 407.Edge-aligned PWM waveforms (ARR=8) . . . . .1560
Figure 408.Center-aligned PWM waveforms (ARR=8) . . . . .1561
Figure 409.Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1562
Figure 410.Combined PWM mode on channels 1 and 3 . . . . .1564
Figure 411.Clearing TIMx_OCxREF . . . . .1565
Figure 412.Example of one-pulse mode . . . . .1566
Figure 413.Retriggerable one-pulse mode . . . . .1568
Figure 414.Example of counter operation in encoder interface mode . . . . .1569
Figure 415.Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1570
Figure 416.Control circuit in reset mode . . . . .1571
Figure 417.Control circuit in gated mode . . . . .1572
Figure 418.Control circuit in trigger mode . . . . .1573
Figure 419.Control circuit in external clock mode 2 + trigger mode . . . . .1574
Figure 420.Master/Slave timer example . . . . .1575
Figure 421.Master/slave connection example with 1 channel only timers . . . . .1575
Figure 422.Gating TIM2 with OC1REF of TIM3 . . . . .1576
Figure 423.Gating TIM2 with Enable of TIM3 . . . . .1577
Figure 424.Triggering TIM2 with update of TIM3 . . . . .1578
Figure 425.Triggering TIM2 with Enable of TIM3 . . . . .1578
Figure 426.Triggering TIM3 and TIM2 with TIM3_TI1 input . . . . .1579
Figure 427.General-purpose timer block diagram (TIM12) . . . . .1613
Figure 428.General-purpose timer block diagram (TIM13/TIM14) . . . . .1614
Figure 429.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1616
Figure 430.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1616
Figure 431.Counter timing diagram, internal clock divided by 1 . . . . .1617
Figure 432.Counter timing diagram, internal clock divided by 2 . . . . .1618
Figure 433.Counter timing diagram, internal clock divided by 4 . . . . .1618
Figure 434.Counter timing diagram, internal clock divided by N . . . . .1619
Figure 435.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .1619
Figure 436.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .1620
Figure 437.Control circuit in normal mode, internal clock divided by 1 . . . . .1621
Figure 438.TI2 external clock connection example . . . . .1621
Figure 439.Control circuit in external clock mode 1 . . . . .1622
Figure 440.Capture/compare channel (example: channel 1 input stage) . . . . .1623
Figure 441.Capture/compare channel 1 main circuit . . . . .1623
Figure 442.Output stage of capture/compare channel (channel 1) . . . . .1624
Figure 443.PWM input mode timing . . . . .1626
Figure 444.Output compare mode, toggle on OC1 . . . . .1628
Figure 445.Edge-aligned PWM waveforms (ARR=8) . . . . .1629
Figure 446.Combined PWM mode on channel 1 and 2 . . . . .1630
Figure 447.Example of one pulse mode . . . . .1631
Figure 448.Retriggerable one pulse mode . . . . .1632
Figure 449.Measuring time interval between edges on 2 signals . . . . .1633
Figure 450.Control circuit in reset mode . . . . .1634
Figure 451.Control circuit in gated mode . . . . .1635
Figure 452.Control circuit in trigger mode . . . . .1635
Figure 453.TIM15 block diagram . . . . .1667
Figure 454.TIM16/TIM17 block diagram . . . . .1668
Figure 455.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1670
Figure 456.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1670
Figure 457.Counter timing diagram, internal clock divided by 1 . . . . .1672
Figure 458.Counter timing diagram, internal clock divided by 2 . . . . .1672
Figure 459.Counter timing diagram, internal clock divided by 4 . . . . .1673
Figure 460.Counter timing diagram, internal clock divided by N . . . . .1673
Figure 461.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1674
Figure 462.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1674
Figure 463.Update rate examples depending on mode and TIMx_RCR register settings . . . . .1676
Figure 464.Control circuit in normal mode, internal clock divided by 1 . . . . .1677
Figure 465.TI2 external clock connection example. . . . .1677
Figure 466.Control circuit in external clock mode 1 . . . . .1678
Figure 467.Capture/compare channel (example: channel 1 input stage). . . . .1679
Figure 468.Capture/compare channel 1 main circuit . . . . .1679
Figure 469.Output stage of capture/compare channel (channel 1). . . . .1680
Figure 470.Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1680
Figure 471.PWM input mode timing . . . . .1682
Figure 472.Output compare mode, toggle on OC1 . . . . .1684
Figure 473.Edge-aligned PWM waveforms (ARR=8) . . . . .1685
Figure 474.Combined PWM mode on channel 1 and 2 . . . . .1686
Figure 475.Complementary output with dead-time insertion. . . . .1687
Figure 476.Dead-time waveforms with delay greater than the negative pulse. . . . .1687
Figure 477.Dead-time waveforms with delay greater than the positive pulse. . . . .1688
Figure 478.Break circuitry overview . . . . .1690
Figure 479.Output behavior in response to a break . . . . .1692
Figure 480.Output redirection . . . . .1694
Figure 481.6-step generation, COM example (OSSR=1) . . . . .1695
Figure 482.Example of one pulse mode . . . . .1696
Figure 483.Retriggerable one pulse mode . . . . .1698
Figure 484.Measuring time interval between edges on 2 signals . . . . .1699
Figure 485.Control circuit in reset mode . . . . .1700
Figure 486.Control circuit in gated mode . . . . .1701
Figure 487.Control circuit in trigger mode . . . . .1702
Figure 488.Basic timer block diagram. . . . .1754
Figure 489.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1756
Figure 490.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1756
Figure 491.Counter timing diagram, internal clock divided by 1 . . . . .1757
Figure 492.Counter timing diagram, internal clock divided by 2 . . . . .1758
Figure 493.Counter timing diagram, internal clock divided by 4 . . . . .1758
Figure 494.Counter timing diagram, internal clock divided by N . . . . .1759
Figure 495.Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1759
Figure 496.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1760
Figure 497. Control circuit in normal mode, internal clock divided by 1 . . . . .1761
Figure 498. Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . .1768
Figure 499. Low-power timer block diagram (LPTIM3) . . . . .1769
Figure 500. Glitch filter timing diagram . . . . .1773
Figure 501. LPTIM output waveform, single counting mode configuration . . . . .1774
Figure 502. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		1775
Figure 503. LPTIM output waveform, Continuous counting mode configuration . . . . .1775
Figure 504. Waveform generation . . . . .1777
Figure 505. Encoder mode counting sequence . . . . .1781
Figure 506. Watchdog block diagram . . . . .1795
Figure 507. Window watchdog timing diagram . . . . .1796
Figure 508. Independent watchdog block diagram . . . . .1801
Figure 509. RTC block diagram . . . . .1811
Figure 510. TAMP block diagram . . . . .1852
Figure 511. Block diagram . . . . .1876
Figure 512. I 2 C-bus protocol . . . . .1878
Figure 513. Setup and hold timings . . . . .1880
Figure 514. I2C initialization flow . . . . .1882
Figure 515. Data reception . . . . .1883
Figure 516. Data transmission . . . . .1884
Figure 517. Target initialization flow . . . . .1887
Figure 518. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .1889
Figure 519. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .1890
Figure 520. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .1891
Figure 521. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .1892
Figure 522. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .1893
Figure 523. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		1893
Figure 524. Controller clock generation . . . . .1895
Figure 525. Controller initialization flow . . . . .1897
Figure 526. 10-bit address read access with HEAD10R = 0 . . . . .1897
Figure 527. 10-bit address read access with HEAD10R = 1 . . . . .1898
Figure 528. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .1899
Figure 529. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .1900
Figure 530. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		1901
Figure 531. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .1903
Figure 532. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .1904
Figure 533. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		1905
Figure 534. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1909
Figure 535. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .1913
Figure 536. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .1913
Figure 537. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .1915
Figure 538. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .1916
Figure 539. Bus transfer diagrams for SMBus controller transmitter . . . . .1917
Figure 540. Bus transfer diagrams for SMBus controller receiver . . . . .1919
Figure 541. I2C interrupt mapping diagram . . . . .1923
Figure 542. USART block diagram . . . . .1942
Figure 543. Word length programming . . . . .1945
Figure 544. Configurable stop bits . . . . .1947
Figure 545.TC/TXE behavior when transmitting . . . . .1950
Figure 546.Start bit detection when oversampling by 16 or 8 . . . . .1951
Figure 547.usart_ker_ck clock divider block diagram . . . . .1954
Figure 548.Data sampling when oversampling by 16 . . . . .1955
Figure 549.Data sampling when oversampling by 8 . . . . .1956
Figure 550.Mute mode using Idle line detection . . . . .1963
Figure 551.Mute mode using address mark detection . . . . .1964
Figure 552.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .1967
Figure 553.Break detection in LIN mode vs. Framing error detection. . . . .1968
Figure 554.USART example of synchronous master transmission. . . . .1969
Figure 555.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1969
Figure 556.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1970
Figure 557.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1971
Figure 558.ISO 7816-3 asynchronous protocol . . . . .1973
Figure 559.Parity error detection using the 1.5 stop bits . . . . .1975
Figure 560.IrDA SIR ENDEC block diagram. . . . .1979
Figure 561.IrDA data modulation (3/16) - normal mode . . . . .1979
Figure 562.Transmission using DMA . . . . .1981
Figure 563.Reception using DMA . . . . .1982
Figure 564.Hardware flow control between 2 USARTs . . . . .1982
Figure 565.RS232 RTS flow control . . . . .1983
Figure 566.RS232 CTS flow control . . . . .1984
Figure 567.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1987
Figure 568.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1987
Figure 569.LPUART block diagram . . . . .2028
Figure 570.LPUART word length programming . . . . .2031
Figure 571.Configurable stop bits . . . . .2033
Figure 572.TC/TXE behavior when transmitting . . . . .2035
Figure 573.lpuart_ker_ck clock divider block diagram . . . . .2038
Figure 574.Mute mode using Idle line detection . . . . .2042
Figure 575.Mute mode using address mark detection . . . . .2043
Figure 576.Transmission using DMA . . . . .2045
Figure 577.Reception using DMA . . . . .2046
Figure 578.Hardware flow control between 2 LPUARTs . . . . .2047
Figure 579.RS232 RTS flow control . . . . .2047
Figure 580.RS232 CTS flow control . . . . .2048
Figure 581.Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		2051
Figure 582.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2051
Figure 583.SPI2S block diagram . . . . .2081
Figure 584.Full-duplex single master/ single slave application. . . . .2083
Figure 585.Half-duplex single master/ single slave application . . . . .2084
Figure 586.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		2085
Figure 587.Master and three independent slaves at star topology. . . . .2086
Figure 588.Master and three slaves at circular (daisy chain) topology. . . . .2087
Figure 589.Multimaster application . . . . .2088
Figure 590. Scheme of slave select control logic. . . . .2090
Figure 591. Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . .2090
Figure 592. NSS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0) . . . . .2091
Figure 593. Data clock timing diagram . . . . .2093
Figure 594. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . .2094
Figure 595. Packing data in FIFO for transmission and reception. . . . .2102
Figure 596. TI mode transfer . . . . .2104
Figure 597. Optional configurations of slave behavior at detection of underrun condition . . . . .2106
Figure 598. Low-power mode application example . . . . .2110
Figure 599. Waveform examples . . . . .2117
Figure 600. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .2118
Figure 601. I2S Philips standard waveforms . . . . .2118
Figure 602. Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . .2119
Figure 603. Master MSB justified 16 or 24-bit data length. . . . .2119
Figure 604. Slave MSB justified . . . . .2120
Figure 605. LSB justified 16 or 24-bit data length . . . . .2120
Figure 606. Master PCM when the frame length is equal the data length. . . . .2121
Figure 607. Master PCM standard waveforms (16 or 24-bit data length) . . . . .2121
Figure 608. Slave PCM waveforms . . . . .2122
Figure 609. Startup sequence, I2S Philips standard, master. . . . .2125
Figure 610. Startup sequence, I2S Philips standard, slave . . . . .2125
Figure 611. Stop sequence, I2S Philips standard, master. . . . .2126
Figure 612. I 2 S clock generator architecture . . . . .2127
Figure 613. Data Format . . . . .2129
Figure 614. Handling of underrun situation . . . . .2131
Figure 615. Handling of overrun situation . . . . .2132
Figure 616. Frame error detection, with FIXCH=0. . . . .2133
Figure 617. Frame error detection, with FIXCH=1. . . . .2133
Figure 618. SAI functional block diagram . . . . .2160
Figure 619. Audio frame . . . . .2164
Figure 620. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2166
Figure 621. FS role is start of frame (FSDEF = 0). . . . .2167
Figure 622. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2168
Figure 623. First bit offset . . . . .2168
Figure 624. Audio block clock generator overview . . . . .2170
Figure 625. PDM typical connection and timing. . . . .2174
Figure 626. Detailed PDM interface block diagram . . . . .2175
Figure 627. Start-up sequence . . . . .2176
Figure 628. SAI_ADR format in TDM mode, 32-bit slot width . . . . .2177
Figure 629. SAI_ADR format in TDM mode, 16-bit slot width . . . . .2178
Figure 630. SAI_ADR format in TDM mode, 8-bit slot width . . . . .2179
Figure 631. AC'97 audio frame . . . . .2182
Figure 632. Example of typical AC'97 configuration on devices featuring at least
two embedded SAIs (three external AC'97 decoders) . . . . .		2183
Figure 633. SPDIF format . . . . .2184
Figure 634. SAI_xDR register ordering . . . . .2185
Figure 635. Data companding hardware in an audio block in the SAI. . . . .2188
Figure 636. Tristate strategy on SD output line on an inactive slot . . . . .2190
Figure 637. Tristate on output data line in a protocol like I2S . . . . .2191
Figure 638. Overrun detection error. . . . .2192
Figure 639. FIFO underrun event . . . . .2192
Figure 640. SPDIFRX block diagram . . . . .2227
Figure 641. S/PDIF sub-frame format . . . . .2228
Figure 642. S/PDIF block format . . . . .2229
Figure 643. S/PDIF preambles . . . . .2229
Figure 644. Channel coding example . . . . .2230
Figure 645. SPDIFRX decoder . . . . .2231
Figure 646. Noise filtering and edge detection . . . . .2231
Figure 647. Thresholds . . . . .2233
Figure 648. Synchronization flowchart. . . . .2235
Figure 649. Synchronization process scheduling . . . . .2236
Figure 650. SPDIFRX states . . . . .2237
Figure 651. SPDIFRX_FMTx_DR register format . . . . .2239
Figure 652. Channel/user data format . . . . .2240
Figure 653. S/PDIF overrun error when RXSTEO = 0 . . . . .2242
Figure 654. S/PDIF overrun error when RXSTEO = 1 . . . . .2243
Figure 655. SPDIFRX interface interrupt mapping diagram . . . . .2246
Figure 656. S1 signal coding . . . . .2260
Figure 657. S2 signal coding . . . . .2260
Figure 658. SWPMI block diagram . . . . .2262
Figure 659. SWP bus states . . . . .2265
Figure 660. SWP frame structure . . . . .2266
Figure 661. SWPMI No software buffer mode transmission . . . . .2267
Figure 662. SWPMI No software buffer mode transmission, consecutive frames . . . . .2268
Figure 663. SWPMI Multi software buffer mode transmission . . . . .2270
Figure 664. SWPMI No software buffer mode reception . . . . .2272
Figure 665. SWPMI single software buffer mode reception. . . . .2273
Figure 666. SWPMI Multi software buffer mode reception . . . . .2275
Figure 667. SWPMI single buffer mode reception with CRC error. . . . .2276
Figure 668. MDIOS block diagram . . . . .2289
Figure 669. MDIO protocol write frame waveform . . . . .2290
Figure 670. MDIO protocol read frame waveform . . . . .2290
Figure 671. SDMMC “no response” and “no data” operations. . . . .2302
Figure 672. SDMMC (multiple) block read operation . . . . .2302
Figure 673. SDMMC (multiple) block write operation. . . . .2303
Figure 674. SDMMC (sequential) stream read operation . . . . .2303
Figure 675. SDMMC (sequential) stream write operation . . . . .2303
Figure 676. SDMMC block diagram. . . . .2305
Figure 677. SDMMC Command and data phase relation . . . . .2307
Figure 678. Control unit . . . . .2309
Figure 679. Command/response path . . . . .2310
Figure 680. Command path state machine (CPSM) . . . . .2311
Figure 681. Data path . . . . .2317
Figure 682. DDR mode data packet clocking . . . . .2318
Figure 683. DDR mode CRC status / boot acknowledgment clocking. . . . .2318
Figure 684. Data path state machine (DPSM) . . . . .2319
Figure 685. CLKMUX unit . . . . .2330
Figure 686. Asynchronous interrupt generation. . . . .2335
Figure 687. Synchronous interrupt period data read . . . . .2336
Figure 688. Synchronous interrupt period data write . . . . .2336
Figure 689. Asynchronous interrupt period data read . . . . .2337
Figure 690. Asynchronous interrupt period data write . . . . .2338
Figure 691. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . .2341
Figure 692. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104. . . . .2341
Figure 693. Read Wait with SDMMC_CK < 50 MHz . . . . .2342
Figure 694. Read Wait with SDMMC_CK > 50 MHz . . . . .2342
Figure 695. CMD12 stream timing . . . . .2345
Figure 696. CMD5 Sleep Awake procedure . . . . .2347
Figure 697. Normal boot mode operation . . . . .2349
Figure 698. Alternative boot mode operation . . . . .2350
Figure 699. Command response R1b busy signaling . . . . .2351
Figure 700. SDMMC state control . . . . .2352
Figure 701. Card cycle power / power up diagram . . . . .2353
Figure 702. CMD11 signal voltage switch sequence . . . . .2354
Figure 703. Voltage switch transceiver typical application . . . . .2356
Figure 704. CAN subsystem . . . . .2384
Figure 705. FDCAN block diagram . . . . .2386
Figure 706. Transceiver delay measurement . . . . .2391
Figure 707. Pin control in bus monitoring mode . . . . .2393
Figure 708. Pin control in loop back mode . . . . .2395
Figure 709. CAN error state diagram . . . . .2396
Figure 710. Message RAM configuration . . . . .2397
Figure 711. Standard message ID filter path . . . . .2400
Figure 712. Extended message ID filter path . . . . .2401
Figure 713. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . .2407
Figure 714. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . .2407
Figure 715. Bit timing . . . . .2409
Figure 716. Bypass operation . . . . .2411
Figure 717. FSM calibration . . . . .2412
Figure 718. Cycle time and global time synchronization . . . . .2427
Figure 719. TTCAN level 0 and level 2 drift compensation . . . . .2428
Figure 720. Level 0 schedule synchronization state machine . . . . .2435
Figure 721. Level 0 master to slave relation . . . . .2436
Figure 722. OTG_HS high-speed block diagram . . . . .2516
Figure 723. OTG_HS A-B device connection . . . . .2519
Figure 724. OTG_HS peripheral-only connection . . . . .2521
Figure 725. OTG_HS host-only connection . . . . .2525
Figure 726. SOF connectivity (SOF trigger output to TIM and ITRx connection). . . . .2529
Figure 727. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .2531
Figure 728. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .2533
Figure 729. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .2534
Figure 730. Interrupt hierarchy . . . . .2538
Figure 731. Transmit FIFO write task . . . . .2642
Figure 732. Receive FIFO read task . . . . .2643
Figure 733. Normal bulk/control OUT/SETUP . . . . .2644
Figure 734. Bulk/control IN transactions . . . . .2648
Figure 735. Normal interrupt OUT . . . . .2651
Figure 736. Normal interrupt IN . . . . .2656
Figure 737. Isochronous OUT transactions . . . . .2658
Figure 738. Isochronous IN transactions . . . . .2661
Figure 739. Normal bulk/control OUT/SETUP transactions - DMA . . . . .2663
Figure 740. Normal bulk/control IN transaction - DMA . . . . .2665
Figure 741. Normal interrupt OUT transactions - DMA mode . . . . .2666
Figure 742. Normal interrupt IN transactions - DMA mode . . . . .2667
Figure 743. Normal isochronous OUT transaction - DMA mode . . . . .2668
Figure 744. Normal isochronous IN transactions - DMA mode . . . . .2669
Figure 745. Receive FIFO packet read . . . . .2675
Figure 746. Processing a SETUP packet . . . . .2677
Figure 747. Bulk OUT transaction . . . . .2684
Figure 748. TRDT max timing case . . . . .2694
Figure 749. A-device SRP . . . . .2695
Figure 750. B-device SRP . . . . .2696
Figure 751. A-device HNP . . . . .2697
Figure 752. B-device HNP . . . . .2699
Figure 753. HDMI-CEC block diagram . . . . .2703
Figure 754. Message structure . . . . .2703
Figure 755. Blocks . . . . .2704
Figure 756. Bit timings . . . . .2704
Figure 757. Signal free time . . . . .2705
Figure 758. Arbitration phase . . . . .2705
Figure 759. SFT of three nominal bit periods . . . . .2705
Figure 760. Error bit timing . . . . .2706
Figure 761. Error handling . . . . .2708
Figure 762. TXERR detection . . . . .2709
Figure 763. Block diagram of debug infrastructure . . . . .2721
Figure 764. Power domains of debug infrastructure . . . . .2723
Figure 765. Clock domains of debug infrastructure . . . . .2724
Figure 766. SWD successful data transfer . . . . .2727
Figure 767. JTAG TAP state machine . . . . .2728
Figure 768. Debug and access port connections . . . . .2739
Figure 769. APB-D CoreSight component topology . . . . .2746
Figure 770. Embedded cross trigger . . . . .2754
Figure 771. Mapping of trigger inputs to outputs . . . . .2756
Figure 772. ETF state transition diagram . . . . .2786
Figure 773. Cortex-M7 CoreSight Topology . . . . .2847

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