31. Revision history

Table 157. Document revision history

Date	Revision	Changes
21-Nov-2018	1	Initial release
17-Apr-2019	2	Integration of STM32G030xx, affecting: – Section 1.4: Availability of peripherals – Figure 2: Memory map – Table 4: STM32G030xx and STM32G050xx memory boundary addresses (added) – Section 2.3: Embedded SRAM – Section 2.5: Boot configuration – Section 3.3: FLASH functional description – Section Table 8.: Flash memory organization for single-bank devices (title modified) – Section 4: Power control (PWR) (indication of bits not available on STM32G030xx) – Figure 8: Clock tree – Section 5: Reset and clock control (RCC) (indication of bits not available on STM32G030xx) – Section 7: System configuration controller (SYSCFG) (indication of bits not available on STM32G030xx) – Section 7.1.2: SYSCFG configuration register 2 (SYSCFG_CFGR2) (clamping diode enable bits added) – Section 9.1: Introduction – Table 33: DMA implementation – Table 38: DMAMUX instantiation – Section 11.3: Interrupt and exception vectors – Section 12: Extended interrupt and event controller (EXTI) (indication of bits not available on STM32G030xx) – Figure 115: General-purpose timer block diagram and Figure 138: External trigger input block – Section 20: Infrared interface (IRTIM) – Table 121: USART features – Table 155: DEV_ID and REV_ID field values – Table 29.10.4: DBG APB freeze register 2 (DBG_APB_FZ2) – Section 30.2: Package data register
27-May-2020	3	– Empty check section – Section 3.3.8: FLASH Main memory programming sequences – User and read protection option bytes section – Option byte loading section – Table 14: Access status versus protection level and execution modes – Section 3.7.1: FLASH access control register (FLASH_ACR) Section 3.7.8: FLASH option register (FLASH_OPTR) (BORR_LEV[1:0] swapped with BORF_LEV[1:0]) – Section 6.3: GPIO functional description : introductory information modified – Former USB PD / Dead battery section removed

Table 157. Document revision history (continued)

Date	Revision	Changes
27-May-2020	3 cont'd	– Section 30.1: Flash memory size data register : reset value corrected – Table 35: Programmable data width and endian behavior (when PINC = MINC = 1) : NDT in the first row corrected from 8 to 4 – Table 39: DMAMUX: assignment of multiplexer inputs to resources : TIM16/17_TRG_COM corrected to TIM16/17_COM – Section 14.2: ADC main features : V _TScorrected to V _SENSE – Section 14.3.1: ADC pins and internal signals : tables and their organization ( External triggers table brought to this section) – Table 58: Latency between trigger and start of conversion : latency values – Section : Calculating the actual V _REF+voltage using the internal reference voltage - corrected from V _DDAto V _REF+ – Section 15: Advanced-control timer (TIM1) : general update – Figure 141: Capture/Compare channel 1 main circuit and Figure 142: Output stage of Capture/Compare channel (channel 1) updated – Figure 159: Master/slave connection example with 1 channel only timers added – Table 74: Output control bit for standard OCx channels updated – Section 16.4.24: TIM3 timer input selection register (TIM3_TISEL) : removed TI4SEL[3:0] and TI3SEL[3:0] – Figure 175: General-purpose timer block diagram (TIM14) : updated – Figure 186: Capture/compare channel 1 main circuit and Figure 187: Output stage of capture/compare channel (channel 1) updated – Section 18.3.11: Using timer output as trigger for other timers (TIM14) added – Figure 205: Capture/compare channel 1 main circuit updated – Section 19.4.23: Using timer output as trigger for other timers (TIM16/TIM17) added – Former Section 28.3.4 Advanced watchdog interrupt feature moved to Section 22.4: WWDG interrupts – Section 25.4.3: I2C pins and internal signals added – Section 25.7.3: I2C own address 1 register (I2C_OAR1) and Section 25.7.8: I2C interrupt clear register (I2C_ICR) updated – Section 26.4: USART implementation updated - tables reorganized – Section 38: USB Type-C™ / USB Power Delivery interface (UCPD) : general update – Table 155: DEV_ID and REV_ID field values – Section 29.10.2: DBG configuration register (DBG_CR)

Table 157. Document revision history (continued)

Date	Revision	Changes
6-Oct-2020	4	Updated Section 3.4.2: FLASH option byte programming .
20-Nov-2020	5	Extension of the document scope to cover STM32G050xx and STM32G0B0 devices, with corresponding addition or update of: – Section 1.1: General information – Section 1.4: Availability of peripherals – Section 2.2: Memory organization – Section 3: Embedded Flash memory (FLASH) – Section 4: Power control (PWR) – Section 5: Reset and clock control (RCC) – Section 7: System configuration controller (SYSCFG) – Section 8: Interconnect matrix – Section 9: Direct memory access controller (DMA) – Section 10: DMA request multiplexer (DMAMUX) – Section 11: Nested vectored interrupt controller (NVIC) – Section 12: Extended interrupt and event controller (EXTI) – Section 14: Analog-to-digital converter (ADC) – Section 15: Advanced-control timer (TIM1) – Section 16: General-purpose timers (TIM3/TIM4) – Section 18: General-purpose timers (TIM14) – Section 19: General-purpose timers (TIM15/TIM16/TIM17) – Section 24: Tamper and backup registers (TAMP) – Section 25: Inter-integrated circuit (I2C) interface – Section 26: Universal synchronous receiver transmitter (USART) – Section 27: Serial peripheral interface / integrated interchip sound (SPI/I2S) – Section 28: Universal serial bus full-speed host/device interface (USB) – Section 29: Debug support (DBG) – Section 30: Device electronic signature