29. Debug support (DBG)

29.1 Overview

The STM32G0x0 devices are built around a Cortex ^® -M0+ core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core's internal state and the system's external state may be examined. Once examination is complete, the core and the system may be restored and program execution resumed.

The debug features are used by the debugger host when connecting to and debugging the STM32G0x0 MCUs.

One interface for debug is available:

• • Serial wire

Figure 327. Block diagram of STM32G0x0 MCU and Cortex ^® -M0+-level debug support

1. 1. The debug features embedded in the Cortex ^® -M0+ core are a subset of the Arm CoreSight Design Kit.

The Arm Cortex ^® -M0+ core provides integrated on-chip debug support. It is comprised of:

• • SW-DP: Serial wire
• • BPU: Break point unit
• • DWT: Data watchpoint trigger

It also includes debug features dedicated to the STM32G0x0:

• • Flexible debug pinout assignment
• • MCU debug box (support for low-power modes, control over peripheral clocks, etc.)

Note: For further information on debug functionality supported by the Arm Cortex ^® -M0+ core, refer to the Cortex ^® -M0+ Technical Reference Manual (see Section 29.2: Reference Arm documentation ).

29.2 Reference Arm documentation

• • Cortex ^® -M0+ Technical Reference Manual (TRM), available from http://infocenter.arm.com
• • Arm Debug Interface V5
• • Arm CoreSight Design Kit revision r1p1 Technical Reference Manual

29.3 Pinout and debug port pins

The STM32G0x0 MCUs are available in various packages with different numbers of available pins.

29.3.1 SWD port pins

Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os. These pins are available on all packages.

Table 148. SW debug port pins

29.3.2 SW-DP pin assignment

After reset (SYSRESETn or PORESETn), the pins used for the SW-DP are assigned as dedicated pins which are immediately usable by the debugger host.

However, the MCU offers the possibility to disable the SWD port and can then release the associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable SW-DP port pins, refer to Section 6.3.2: I/O pin alternate function multiplexer and mapping on page 175 .

29.3.3 Internal pull-up & pull-down on SWD pins

Once the SW I/O is released by the user software, the GPIO controller takes control of these pins. The reset states of the GPIO control registers put the I/Os in the equivalent states:

• • SWDIO: input pull-up
• • SWCLK: input pull-down

Having embedded pull-up and pull-down resistors removes the need to add external resistors.

29.4 ID codes and locking mechanism

There are several ID codes inside the MCU. ST strongly recommends the tool manufacturers (for example Keil, IAR, Raisonance) to lock their debugger using the MCU device ID located at address 0x40015800.

Only the DEV_ID[15:0] should be used for identification by the debugger/programmer tools (the revision ID must not be taken into account).

29.5 SWD port

29.5.1 SWD protocol introduction

This synchronous serial protocol uses two pins:

• • SWCLK: clock from host to target
• • SWDIO: bidirectional

The protocol allows two banks of registers (DPACC registers and APACC registers) to be read and written to.

Bits are transferred LSB-first on the wire.

For SWDIO bidirectional management, the line must be pulled-up on the board (100 k \( \Omega \) recommended by Arm).

Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted where the line is not driven by the host nor the target. By default, this turnaround time is one bit time, however this can be adjusted by configuring the SWCLK frequency.

29.5.2 SWD protocol sequence

Each sequence consist of three phases:

1. 1. Packet request (8 bits) transmitted by the host
2. 2. Acknowledge response (3 bits) transmitted by the target
3. 3. Data transfer phase (33 bits) transmitted by the host or the target

Refer to the Cortex ^® -M0+ TRM for a detailed description of DPACC and APACC registers.

The packet request is always followed by the turnaround time (default 1 bit) where neither the host nor target drive the line.

The ACK Response must be followed by a turnaround time only if it is a READ transaction or if a WAIT or FAULT acknowledge has been received.

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

29.5.3 SW-DP state machine (reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It follows the JEP-106 standard. This ID code is the default Arm one and is set to 0x0BB11477 (corresponding to Cortex ^® -M0+).

Note: Note that the SW-DP state machine is inactive until the target reads this ID code.

• • The SW-DP state machine is in RESET STATE either after power-on reset, or after the line is high for more than 50 cycles
• • The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles after RESET state.
• • After RESET state, it is mandatory to first enter into an IDLE state AND to perform a READ access of the DP-SW ID CODE register. Otherwise, the target issues a FAULT acknowledge response on another transactions.

Further details of the SW-DP state machine can be found in the Cortex®-M0+ TRM and the CoreSight Design Kit r1p0 TRM .

29.5.4 DP and AP read/write accesses

• • Read accesses to the DP are not posted: the target response can be immediate (if ACK=OK) or can be delayed (if ACK=WAIT).
• • Read accesses to the AP are posted. This means that the result of the access is returned on the next transfer. If the next access to be done is NOT an AP access, then the DP-RDBUFF register must be read to obtain the result.
  The READOK flag of the DP-CTRL/STAT register is updated on every AP read access or RDBUFF read request to know if the AP read access was successful.
• • The SW-DP implements a write buffer (for both DP or AP writes), that enables it to accept a write operation even when other transactions are still outstanding. If the write buffer is full, the target acknowledge response is “WAIT”. With the exception of IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write buffer is full.
• • Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK cycles are needed after a write transaction (after the parity bit) to make the write effective internally. These cycles should be applied while driving the line low (IDLE state)
  This is particularly important when writing the CTRL/STAT for a power-up request. If the next transaction (requiring a power-up) occurs immediately, it fails.

29.5.5 SW-DP registers

Access to these registers are initiated when APnDP=0

Table 152. SW-DP registers

Table 152. SW-DP registers (continued)

29.5.6 SW-AP registers

Access to these registers are initiated when APnDP=1

There are many AP Registers addressed as the combination of:

• • The shifted value A[3:2]
• • The current value of the DP SELECT register.

Table 153. 32-bit debug port registers addressed through the shifted value A[3:2]

29.6 Core debug

Core debug is accessed through the core debug registers. Debug access to these registers is by means of the debug access port. It consists of four registers:

These registers are not reset by a system reset. They are only reset by a power-on reset. Refer to the Cortex®-M0+ TRM for further details.

To Halt on reset, it is necessary to:

• • enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control Register
• • enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register

29.7 BPU (Break Point Unit)

The Cortex®-M0+ BPU implementation provides four breakpoint registers. The BPU is a subset of the Flash Patch and Breakpoint (FPB) block available in Armv7-M (Cortex-M3 & Cortex-M4).

29.7.1 BPU functionality

The processor breakpoints implement PC based breakpoint functionality.

Refer the Armv6-M Arm and the Arm CoreSight Components Technical Reference Manual for more information about the BPU CoreSight identification registers, and their addresses and access types.

29.8 DWT (Data Watchpoint)

The Cortex ^® -M0+ DWT implementation provides two watchpoint register sets.

29.8.1 DWT functionality

The processor watchpoints implement both data address and PC based watchpoint functionality, a PC sampling register, and support comparator address masking, as described in the Armv6-M Arm .

29.8.2 DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the Armv6-M optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a debugger to periodically sample the PC without halting the processor. This provides coarse grained profiling. See the Armv6-M Arm for more information.

The Cortex ^® -M0+ DWT_PCSR records both instructions that pass their condition codes and those that fail.

29.9 MCU debug component (DBG)

The MCU debug component helps the debugger provide support for:

• • Low-power modes
• • Clock control for timers, watchdog and I2C during a breakpoint

29.9.1 Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.

The MCU implements several low-power modes which can either deactivate the CPU clock or reduce the power of the CPU.

The core does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the debugger connection, during a debug, they must remain active. The MCU integrates special means to allow the user to debug software in low-power modes.

For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior:

• • In Sleep mode: FCLK and HCLK are still active. Consequently, this mode does not impose any restrictions on the standard debug features.
• • In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.

This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.

29.9.2 Debug support for timers, watchdog and I ² C

During a breakpoint, it is necessary to choose how the counter of timers and watchdog should behave:

• • They can continue to count inside a breakpoint. This is usually required when a PWM is controlling a motor, for example.
• • They can stop to count inside a breakpoint. This is required for watchdog purposes.

For the I ² C, the user can choose to block the SMBUS timeout during a breakpoint.

29.10 DBG registers

29.10.1 DBG device ID code register (DBG_IDCODE)

The STM32G0x0 products integrate a device ID code identifying the device and its die revision.

This code is accessible by the software debug port (two pins) or by the user software.

DBG_IDCODE

Address offset: 0x00

Only 32-bit access supported. Read-only

Bits 31:16 REV_ID[15:0] Revision identifier

This field indicates the revision of the device. Refer to Table 155 .

Bits 15:12 Reserved: read 0b0110.

Bits 11:0 DEV_ID[11:0] : Device identifier

This field indicates the device ID. Refer to Table 155 .

Table 155. DEV_ID and REV_ID field values

29.10.2 DBG configuration register (DBG_CR)

This register configures the low-power modes of the MCU under debug.

It is asynchronously reset by the POR (and not the system reset). It can be written by the debugger under system reset.

If the debugger host does not support this feature, it is still possible for the user software to write to this register.

Address offset: 0x04

POR Reset: 0x0000 0000 (not reset by system reset)

Only 32-bit access supported

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DBG_STANDBY : Debug Standby mode

Debug options in Standby mode.

0: Digital part powered. From software point of view, exiting Standby mode is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)

1: Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby mode has the same effect as starting from reset.

Bit 1 DBG_STOP : Debug Stop mode

Debug options in Stop mode.

0: All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator.

1: FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.

Upon Stop mode exit, the software must re-establish the desired clock configuration.

29.10.3 DBG APB freeze register 1 (DBG_APB_FZ1)

This register configures the clocking of timers, RTC, IWDG, WWDG, and I2C SMBUS peripherals of the MCU under debug:

The register is asynchronously reset by the POR (and not the system reset). It can be written by the debugger under system reset.

Address offset: 0x08

Power on reset (POR): 0x0000 0000 (not reset by system reset)

Only 32-bit access are supported.

1. Only significant on devices integrating I2C2, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 31 Reserved, must be kept at reset value.

Bit 30 Reserved, must be kept at reset value.

Bits 29:23 Reserved, must be kept at reset value.

Bit 22 DBG_I2C2_SMBUS_TIMEOUT : SMBUS timeout when core is halted

0: Same behavior as in normal mode

1: The SMBUS timeout is frozen

Bit 21 DBG_I2C1_SMBUS_TIMEOUT : SMBUS timeout when core is halted

0: Same behavior as in normal mode

1: The SMBUS timeout is frozen

Bits 20:13 Reserved, must be kept at reset value.

Bit 12 DBG_IWDG_STOP : Clocking of IWDG counter when the core is halted

This bit enables/disables the clock to the counter of IWDG when the core is halted:

0: Enable

1: Disable

Bit 11 DBG_WWDG_STOP : Clocking of WWDG counter when the core is halted

This bit enables/disables the clock to the counter of WWDG when the core is halted:

0: Enable

1: Disable

Bit 10 DBG_RTC_STOP : Clocking of RTC counter when the core is halted

This bit enables/disables the clock to the counter of RTC when the core is halted:

0: Enable

1: Disable

Bits 9:6 Reserved, must be kept at reset value.

Bit 5 DBG_TIM7_STOP : Clocking of TIM7 counter when the core is halted.

This bit enables/disables the clock to the counter of ITIM7 when the core is halted:

0: Enable

1: Disable

Bit 4 DBG_TIM6_STOP : Clocking of TIM6 counter when the core is halted

This bit enables/disables the clock to the counter of TIM6 when the core is halted:

0: Enable

1: Disable

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 DBG_TIM3_STOP : Clocking of TIM3 counter when the core is halted

This bit enables/disables the clock to the counter of TIM3 when the core is halted:

0: Enable

1: Disable

Bit 0 Reserved, must be kept at reset value.

29.10.4 DBG APB freeze register 2 (DBG_APB_FZ2)

This register configures the clocking of timer counters when the MCU is under debug.

It is asynchronously reset by the POR (and not the system reset). It can be written by the debugger under system reset.

Address offset: 0x0C

POR: 0x0000 0000 (not reset by system reset)

Only 32-bit access is supported.

1. Only significant on devices integrating TIM15, otherwise reserved. Refer to Section 1.4: Availability of peripherals

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 DBG_TIM17_STOP : Clocking of TIM17 counter when the core is halted
This bit enables/disables the clock to the counter of TIM17 when the core is halted:
0: Enable
1: Disable

Bit 17 DBG_TIM16_STOP : Clocking of TIM16 counter when the core is halted
This bit enables/disables the clock to the counter of TIM16 when the core is halted:
0: Enable
1: Disable

Bit 16 DBG_TIM15_STOP : Clocking of TIM15 counter when the core is halted
This bit enables/disables the clock to the counter of TIM15 when the core is halted:
0: Enable
1: Disable

Bit 15 DBG_TIM14_STOP : Clocking of TIM14 counter when the core is halted
This bit enables/disables the clock to the counter of TIM14 when the core is halted:
0: Enable
1: Disable

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 DBG_TIM1_STOP : Clocking of TIM1 counter when the core is halted
This bit enables/disables the clock to the counter of TIM1 when the core is halted:
0: Enable
1: Disable

Bits 10:0 Reserved, must be kept at reset value.

29.10.5 DBG register map

The following table summarizes the Debug registers.

Table 156. DBG register map and reset values

Table 156. DBG register map and reset values (continued)

1. 1. The reset value is product dependent. For more information, refer to Section 29.10.1: DBG device ID code register (DBG_IDCODE) .

Refer to Section 2.2 on page 44 for the register boundary addresses.