17. Basic timers (TIM6/TIM7)

17.1 TIM6/TIM7 introduction

The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used as generic timers for time base generation.

The timers are completely independent, and do not share any resources.

17.2 TIM6/TIM7 main features

Basic timer (TIM6/TIM7) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535
• Interrupt/DMA generation on the update event: counter overflow

Figure 165. Basic timer block diagram

The block diagram illustrates the internal architecture of a basic timer (TIM6/TIM7). The main components are:

Input: TIMxCLK from RCC enters the system.
Internal clock (CK_INT): Derived from TIMxCLK, it is fed into the Trigger controller.
Trigger controller: Receives CK_INT and Control signals. It generates the TRGO output and provides Reset, enable, and Count signals to the CNT counter.
Control: A block within the Trigger controller that receives external inputs and sends signals to the Trigger controller.
CK_PSC: Input to the PSC prescaler.
PSC prescaler: Divides the CK_PSC frequency to produce CK_CNT.
CK_CNT: Output of the PSC prescaler, fed into the CNT counter.
CNT counter: A 16-bit upcounter that receives CK_CNT, Reset, enable, and Count signals. It also receives input from the Auto-reload register (Stop, clear or up).
Auto-reload register: Receives external input U and sends Stop, clear or up signals to the CNT counter. It also generates the UI (Update Interrupt) output.
Outputs: TRGO (from Trigger controller), UI (from Auto-reload register).

Notes:

Reg (Preload registers transferred to active registers on U event according to control bit)
Event (indicated by a lightning bolt symbol)
Interrupt & DMA output (indicated by a jagged line symbol)

MSV50981V1

Figure 165. Basic timer block diagram

17.3 TIM6/TIM7 functional description

17.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 166 and Figure 167 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 166. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 166 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 2.

This timing diagram shows the relationship between several signals over time. The signals are:

CK_PSC : A periodic square wave clock signal.
CEN : Counter Enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01, 02, 03.
Update event (UEV) : A pulse generated when the counter overflows from FC to 00.
Prescaler control register : Shows a value of 0 initially, then changes to 1 after a write operation.
Write a new value in TIMx_PSC : An arrow indicating the write operation to the prescaler control register.
Prescaler buffer : Shows a value of 0 initially, then changes to 1 after the UEV.
Prescaler counter : Shows a sequence of values 0, 1, 0, 1, 0, 1, 0, 1, indicating a division of 2.

Vertical dashed lines indicate key timing points: the start of counting, the write operation, the first update event, and the second update event where the new prescaler value takes effect. The text 'MS31076V2' is in the bottom right corner.

Timing diagram for Figure 166 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 2.

Figure 167. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 167 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 4.

This timing diagram is similar to Figure 166 but shows a prescaler division change from 1 to 4. The signals and their behavior are:

CK_PSC and CEN are the same as in Figure 166.
Timerclock = CK_CNT has a longer period due to the higher prescaler division.
Counter register shows values F7, F8, F9, FA, FB, FC, 00, 01.
Update event (UEV) occurs at the overflow from FC to 00.
Prescaler control register changes from 0 to 3 (which corresponds to a division of 4).
Write a new value in TIMx_PSC indicates the write operation.
Prescaler buffer changes from 0 to 3 after the UEV.
Prescaler counter shows a sequence of values 0, 1, 2, 3, 0, 1, 2, 3, indicating a division of 4.

Vertical dashed lines mark the start of counting, the write operation, the first update event, and the second update event. The text 'MS31077V2' is in the bottom right corner.

Timing diagram for Figure 167 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 4.

17.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 168. Counter timing diagram, internal clock divided by 1

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (Timerclock = CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

The timing diagram illustrates the operation of a counter in counting mode. The top signal, CK_PSC, is a periodic square wave representing the prescaler clock. Below it, CNT_EN is a signal that goes high to enable the counter. The third signal, Timerclock = CK_CNT, is the clock for the counter, which is derived from CK_PSC. The fourth signal shows the Counter register values, which count from 31 to 36, then overflow to 00 and continue counting (01, 02, 03, 04, 05, 06, 07). The fifth signal, Counter overflow, is a pulse that goes high when the counter reaches the auto-reload value (36) and then goes low. The sixth signal, Update event (UEV), is a pulse that goes high when the counter overflows. The bottom signal, Update interrupt flag (UIF), is a pulse that goes high when the counter overflows and remains high until it is cleared.

Counter register	31	32	33	34	35	36	00	01	02	03	04	05	06	07

MS31078V2

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (Timerclock = CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 169. Counter timing diagram, internal clock divided by 2

This timing diagram illustrates the operation of a counter with an internal clock divided by 2. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a high-level enable signal. The Timerclock = CK_CNT signal is a square wave with a frequency half that of CK_PSC. The Counter register shows a sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, and 0003. Vertical dashed lines indicate the rising edges of the Timerclock. At the rising edge following 0036, the Counter overflow signal pulses high. Simultaneously, the Update event (UEV) and Update interrupt flag (UIF) signals also pulse high. The counter then continues with values 0001, 0002, and 0003. The identifier MS31079V2 is located in the bottom right corner.

Timing diagram for internal clock divided by 2. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0034, 0035, 0036, 0000, 0001, 0002, 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

Figure 170. Counter timing diagram, internal clock divided by 4

This timing diagram illustrates the operation of a counter with an internal clock divided by 4. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a high-level enable signal. The Timerclock = CK_CNT signal is a square wave with a frequency one-quarter that of CK_PSC. The Counter register shows a sequence of values: 0035, 0036, 0000, and 0001. Vertical dashed lines indicate the rising edges of the Timerclock. At the rising edge following 0036, the Counter overflow signal pulses high. Simultaneously, the Update event (UEV) and Update interrupt flag (UIF) signals also pulse high. The counter then continues with values 0001. The identifier MS31080V2 is located in the bottom right corner.

Timing diagram for internal clock divided by 4. It shows CK_PSC, CNT_EN, Timerclock = CK_CNT, Counter register values (0035, 0036, 0000, 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time.

Figure 171. Counter timing diagram, internal clock divided by N

Timing diagram showing the relationship between the prescaler clock (CK_PSC), the timer clock (Timerclock = CK_CNT), the counter register value, the counter overflow signal, the update event (UEV), and the update interrupt flag (UIF). The diagram illustrates the counter incrementing from 1F to 20, overflowing, and then resetting to 00. The overflow, UEV, and UIF signals are shown as pulses that occur when the counter reaches 00. The CK_PSC signal is a square wave, and the Timerclock signal is a square wave with a frequency divided by N from the CK_PSC signal. The counter register value is shown as a sequence of hexadecimal values: 1F, 20, 00. The overflow signal is a pulse that occurs when the counter reaches 00. The update event (UEV) is a pulse that occurs when the counter reaches 00. The update interrupt flag (UIF) is a pulse that occurs when the counter reaches 00. The diagram is labeled MS31081V2.

Timing diagram for internal clock divided by N

Figure 172. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

Timing diagram showing the relationship between the prescaler clock (CK_PSC), the counter enable (CEN), the timer clock (Timerclock = CK_CNT), the counter register value, the counter overflow signal, the update event (UEV), the update interrupt flag (UIF), and the auto-reload preload register. The diagram illustrates the counter incrementing from 31 to 36, overflowing, and then resetting to 00. The overflow, UEV, and UIF signals are shown as pulses that occur when the counter reaches 00. The CK_PSC signal is a square wave, and the Timerclock signal is a square wave with a frequency divided by N from the CK_PSC signal. The counter register value is shown as a sequence of hexadecimal values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The overflow signal is a pulse that occurs when the counter reaches 00. The update event (UEV) is a pulse that occurs when the counter reaches 00. The update interrupt flag (UIF) is a pulse that occurs when the counter reaches 00. The auto-reload preload register value is shown as FF, then 36. A note indicates that a new value should be written in TIMx_ARR. The diagram is labeled MS31082V2.

Timing diagram for update event when ARPE = 0

Figure 173. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Figure 173: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the timing of an update event when ARPE=1 and the auto-reload register is preloaded.

The timing diagram shows the following signals and their states over time:

CK_PSC : A periodic clock signal.
CEN : Counter Enable signal, which is initially low and then goes high to enable the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC.
Counter register : Shows the counter values F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments by 1 at each rising edge of the timer clock.
Counter overflow : A signal that goes high when the counter reaches its maximum value (F5) and rolls over to 00.
Update event (UEV) : A signal that goes high when the counter overflows.
Update interrupt flag (UIF) : A signal that goes high when the counter overflows.
Auto-reload preload register : Shows the value F5 being written to the register, and then the value 36 being loaded into the counter when it overflows.
Auto-reload shadow register : Shows the value F5 being written to the register, and then the value 36 being loaded into the counter when it overflows.

An annotation "Write a new value in TIMx_ARR" points to the value F5 in the Auto-reload preload register. The diagram is labeled MS31083V2.

Figure 173: Counter timing diagram showing the relationship between CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The diagram illustrates the timing of an update event when ARPE=1 and the auto-reload register is preloaded.

17.3.3 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into the timer counter register's bit 31 (TIMxCNT[31]). This allows to atomically read both the counter value and a potential roll-over condition signaled by the UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions caused for instance by a processing shared between a background task (counter reading) and an interrupt (Update Interrupt).

There is no latency between the assertions of the UIF and UIFCPY flags.

17.3.4 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 174 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 174. Control circuit in normal mode, internal clock divided by 1

MS31085V2

Timing diagram showing the control circuit in normal mode. It displays the Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and Counter register (bits 31 to 07). The diagram shows the relationship between these signals and the counter register values over time. The internal clock is a high-frequency square wave. CEN=CNT_EN is a high-level signal. UG is a pulse that triggers the counter. CNT_INIT is a pulse that initializes the counter. The counter clock is a square wave derived from the internal clock. The counter register shows values from 31 to 07, indicating a countdown sequence.

17.3.5 Debug mode

When the microcontroller enters the debug mode (Cortex®-M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 29.9.2: Debug support for timers, watchdog and I ²C .

17.4 TIM6/TIM7 registers

Refer to Section 1.2 on page 39 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

17.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	UIFREMAP	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
				rw				rw				rw	rw	rw	rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 UIFREMAP : UIF status bit remapping

0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.

1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software.

However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

17.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]				Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS[2:0] : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bits 3:0 Reserved, must be kept at reset value.

17.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

17.4.4 TIMx status register (TIMx_SR)(x = 6 to 7)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

17.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

17.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7)

Address offset: 0x24

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIF CPY	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
r

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 UIFCPY : UIF Copy

This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.

Bits 30:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0] : Counter value

17.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency $CK\_CNT$ is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

17.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Prescaler value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 17.3.1: Time-base unit on page 509 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

17.4.9 TIMx register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 76. TIMx register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIFREMA	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value																					0				0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS [2:0]			Res.	Res.	Res.	Res.
0x04	Reset value																										0	0	0
0x08	Reserved
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value																								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																																0
0x18-0x20	Reserved
0x24	TIMx_CNT	UIFCOPY or Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CNT[15:0]
0x24	Reset value	0																															0
0x28	TIMx_PSC	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PSC[15:0]
0x28	Reset value																																0
0x2C	TIMx_ARR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARR[15:0]
0x2C	Reset value																																1

Refer to Section 2.2 on page 44 for the register boundary addresses.