14. Analog-to-digital converter (ADC)

14.1 Introduction

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external and 3 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined higher or lower thresholds.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

A built-in hardware oversampler allows analog performances to be improved while off-loading the related computational burden from the CPU.

14.2 ADC main features

• High performance
- – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
- – ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion times can be obtained by lowering resolution.
- – Self-calibration
- – Programmable sampling time
- – Data alignment with built-in data coherency
- – DMA support
• Low-power
- – The application can reduce PCLK frequency for low-power operation while still keeping optimum ADC performance. For example, 0.4 µs conversion time is kept, whatever the PCLK frequency)
- – Wait mode: prevents ADC overrun in applications with low PCLK frequency
- – Auto off mode: ADC is automatically powered off except during the active conversion phase. This dramatically reduces the power consumption of the ADC.
• Analog input channels
- – 16 external analog inputs
- – 1 channel for internal temperature sensor ( $V_{\text{SENSE}}$ )
- – 1 channel for internal reference voltage ( $V_{\text{REFINT}}$ )
- – 1 channel for monitoring external $V_{\text{BAT}}$ power supply pin
• Start-of-conversion can be initiated:
- – By software
- – By hardware triggers with configurable polarity (timer events or GPIO input events)
• Conversion modes
- – Can convert a single channel or can scan a sequence of channels.
- – Single mode converts selected inputs once per trigger
- – Continuous mode converts selected inputs continuously
- – Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence conversion, and in case of analog watchdog or overrun events
• Analog watchdog
• Oversampler
- – 16-bit data register
- – Oversampling ratio adjustable from 2 to 256x
- – Programmable data shift up to 8-bits
• ADC supply requirements: 1.62 to 3.6 V
• ADC input range: $V_{\text{SSA}} \leq V_{\text{IN}} \leq V_{\text{REF+}}$

14.3 ADC functional description

Figure 27 shows the ADC block diagram and Table 55 gives the ADC pin description.

Figure 27. ADC block diagram

The block diagram illustrates the internal architecture of the ADC. At the core is the SAR ADC, which receives analog input from 16 external channels (ADC_IN [18:15, 11:0]) through an input selection and scan control block. This block also manages channel selection (CH_SEL[18:0]), conversion mode (CONT single/cont.), and sampling time (SMP[2:0]). The ADC is triggered by various sources including software (ADSTART), hardware (HW), and timers (TIM1_TRGO2, TIM1_CC4, TIM3_TRGO, TIM15_TRGO, TIM6_TRGO). The SAR ADC produces converted data (DATA[15:0]) which is then processed by an oversampler. The oversampler has various configuration registers (OVRMODE, ALIGN, RES[1:0], JOFFSETx[11:0], JOFFSETx_CH[11:0]) and output signals (TOVS, OVSS[3:0], OVSR[3:0], OVSE). The ADC also features an analog watchdog (AWD) with a comparator that outputs to an external watchdog (ADC_AWDx_OUT). The ADC is connected to a CPU via an AHB to APB bridge, generating interrupts (AREADY, EOSMP, EOSEQ, EOC, OVR, AWD) and DMA requests. Power supply and reference pins (VDD/VDDA, VREF+) are also shown.

ADC block diagram showing internal components like SAR ADC, oversampler, and interfaces to CPU and DMA.

14.3.1 ADC pins and internal signals

Table 55. ADC input/output pins

Name	Signal type	Remarks
VDDA	Input, analog power supply	Analog power supply and positive reference voltage for the ADC, $V_{DDA} \geq V_{DD}$
VSSA	Input, analog supply ground	Ground for analog power supply. Must be at $V_{SS}$ potential
VREF+	Input, analog reference positive	The higher/positive reference voltage for the ADC.
ADC_INx	Analog input signals	16 external analog input channels

Table 56. ADC internal input/output signals

Internal signal name	Signal type	Description
V _IN[x]	Analog Input channels	Connected either to internal channels or to ADC_IN i external channels
TRGx	Input	ADC conversion triggers
V _SENSE	Input	Internal temperature sensor output voltage
V _REFINT	Input	Internal voltage reference output voltage
V _BAT/3	Input	VBAT pin input voltage divided by 3
ADC_AWDx_OUT	Output	Internal analog watchdog output signal connected to on-chip timers (x = Analog watchdog number = 1,2,3)

Table 57. External triggers

Name	Source	EXTSEL[2:0]
TRG0	TIM1_TRGO2	000
TRG1	TIM1_CC4	001
TRG2	Reserved	010
TRG3	TIM3_TRGO	011
TRG4	TIM15_TRGO	100
TRG5	TIM6_TRGO	101
TRG6	TIM4_TRGO	110
TRG7	EXTI11	111

14.3.2 ADC voltage regulator (ADVREGEN)

The ADC has a specific internal voltage regulator which must be enabled and stable before using the ADC.

The ADC internal voltage regulator can be enabled by setting ADVREGEN bit to 1 in the ADC_CR register. The software must wait for the ADC voltage regulator startup time ( $t_{ADCVREG\_SETUP}$ ) before launching a calibration or enabling the ADC. This delay must be managed by software (for details on $t_{ADCVREG\_SETUP}$ , refer to the device datasheet).

After ADC operations are complete, the ADC is disabled (ADEN = 0). It is then possible to save additional power by disabling the ADC voltage regulator (refer to Section : ADC voltage regulator disable sequence ).

Note: When the internal voltage regulator is disabled, the internal analog calibration is kept.

Analog reference from the power control unit

The internal ADC voltage regulator internally uses an analog reference delivered by the power control unit through a buffer. This buffer is always enabled when the main voltage regulator of the power control unit operates in normal Run mode (refer to Reset and clock control and power control sections).

If the main voltage regulator enters low-power mode (such as Low-power run mode), this buffer is disabled and the ADC cannot be used.

ADC Voltage regulator enable sequence

To enable the ADC voltage regulator, set ADVREGEN bit to 1 in ADC_CR register.

ADC voltage regulator disable sequence

To disable the ADC voltage regulator, follow the sequence below:

1. Make sure that the ADC is disabled (ADEN = 0).
2. Clear ADVREGEN bit in ADC_CR register.

14.3.3 Calibration (ADCAL)

The ADC has a calibration feature. During the procedure, the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power-off. The application must not use the ADC during calibration and must wait until it is complete.

Calibration should be performed before starting A/D conversion. It removes the offset error which may vary from chip to chip due to process variation.

The calibration is initiated by software by setting bit ADCAL = 1. Calibration can only be initiated when the ADC voltage regulator is enabled (ADVREGEN = 1 and t _{ADCVREG_SETUP}has elapsed) and the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. After this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).

The internal analog calibration is kept if the ADC is disabled (ADEN = 0). When the ADC operating conditions change (V _DDAchanges are the main contributor to ADC offset variations and temperature change to a lesser extend), it is recommended to re-run a calibration cycle.

The calibration factor is lost in the following cases:

• The power supply is removed from the ADC (for example when the product enters STANDBY or VBAT mode)
• The ADC peripheral is reset.

The calibration factor is lost each time power is removed from the ADC (for example when the product enters Standby or V _BATmode). Still, it is possible to save and restore the calibration factor by software to save time when re-starting the ADC (as long as temperature and voltage are stable during the ADC power-down).

The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion.

Software calibration procedure

1. Ensure that ADEN = 0, ADVREGEN = 1 and DMAEN = 0.
2. Set ADCAL = 1.
3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the interrupt is enabled by setting the EOCALIE bit in the ADC_IER register
4. The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT registers.

Figure 28. ADC calibration

Timing diagram for ADC calibration showing ADCAL, ADC State, ADC_DR[6:0], and ADC_CALFACT[6:0] signals over time. The sequence starts with ADC State at OFF. ADCAL is set by S/W, triggering a Startup phase, then a CALIBRATE phase of duration tCAB. During CALIBRATE, ADC_DR[6:0] is 0x00. After tCAB, ADCAL is reset by H/W, ADC State returns to OFF, and ADC_CALFACT[6:0] is updated with the CALIBRATION FACTOR.

Calibration factor forcing Software Procedure

1. Ensure that ADEN = 1 and ADSTART = 0 (ADC started with no conversion ongoing)
2. Write ADC_CALFACT with the saved calibration factor
3. The calibration factor is used as soon as a new conversion is launched.

Figure 29. Calibration factor forcing

Timing diagram for calibration factor forcing. It shows ADC state transitions: Ready (not converting) -> Converting channel (Single ended) -> Ready -> Converting channel (Single ended). A WRITE ADC_CALFACT by S/W occurs during the first Ready state, setting CALFACT[6:0] to F2. When a conversion starts (hardware or software), there is a brief 'Updating calibration' period where the internal calibration factor changes from F1 to F2 before the conversion proceeds.

14.3.4 ADC on-off control (ADEN, ADDIS, ADRDY)

At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).

As shown in Figure 30, the ADC needs a stabilization time of $t_{STAB}$ before it starts converting accurately.

Two control bits are used to enable or disable the ADC:

• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation.
• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled.

Conversion can then start either by setting ADSTART to 1 (refer to Section 14.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) on page 289 ) or when an external trigger event occurs if triggers are enabled.

Follow this procedure to enable the ADC:

1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2. Set ADEN = 1 in the ADC_CR register.
3. Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup time). This can be handled by interrupt if the interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register.

Follow this procedure to disable the ADC:

1. Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the ADC_CR register and waiting until this bit is read at 0.
2. Set ADDIS = 1 in the ADC_CR register.
3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).

Figure 30. Enabling/disabling the ADC

The diagram illustrates the timing for enabling and disabling the ADC. The top signal, ADEN, is set high by software (upward arrow) to enable the ADC. A stabilization time $t_{STAB}$ is indicated between the rising edge of ADEN and the rising edge of ADRDY. The ADRDY signal goes high (by hardware, downward arrow) after the startup phase. The ADDIS signal is set high by software (upward arrow) to disable the ADC. The ADC stat signal shows a sequence of states: OFF, Startup, RDY, CONVERTING CH, RDY, REQ-OFF, and OFF. The transition from REQ-OFF to OFF is triggered by hardware (downward arrow). A legend at the bottom left indicates that upward arrows represent software (S/W) actions and downward arrows represent hardware (H/W) actions. The identifier MS30264V/2 is in the bottom right corner.

Timing diagram showing the sequence of signals (ADEN, ADRDY, ADDIS, ADC stat) for enabling and disabling the ADC. It includes phases like OFF, Startup, RDY, CONVERTING CH, and REQ-OFF. A legend indicates 'by S/W' (software) and 'by H/W' (hardware) transitions.

Note: In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by hardware and the ADRDY flag is not set.

14.3.5 ADC clock (CKMODE, PRESC[3:0])

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 31. ADC clock scheme

The diagram illustrates the ADC clock scheme. On the left, the RCC (Reset & Clock Controller) provides two clock signals: PCLK and an ADC asynchronous clock. These signals enter the ADITF block. Inside the ADITF, the PCLK signal is connected to an APB interface and a prescaler block labeled "/1 or /2 or /4". This prescaler is controlled by bits CKMODE[1:0] of the ADC_CFGR2 register. The ADC asynchronous clock is connected to a divider block labeled "/1,2,4,6,8,10,12,16,32,64,128,256", which is controlled by bits PRESC[3:0] of the ADC_CCR register. Both the prescaler and the divider output to a multiplexer. The multiplexer is controlled by bits CKMODE[1:0] of the ADC_CFGR2 register. The output of the multiplexer is labeled "Analog ADC_CK" and is connected to the "Analog ADC" block. The diagram is labeled with the reference MSV31926V2.

Figure 31. ADC clock scheme diagram showing the RCC (Reset & Clock Controller) providing PCLK and an ADC asynchronous clock to the ADITF. The ADITF contains an APB interface, a prescaler (/1 or /2 or /4) controlled by CKMODE[1:0] of ADC_CFGR2, and a divider (/1,2,4,6,8,10,12,16,32,64,128,256) controlled by PRESC[3:0] of ADC_CCR. A multiplexer selects between these sources based on CKMODE[1:0] of ADC_CFGR2 to provide the Analog ADC_CK to the Analog ADC.

1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are enabled.

The input clock of the analog ADC can be selected between two different clock sources (see Figure 31: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock are enabled):

a) The ADC clock can be a specific clock source, named “ADC asynchronous clock” which is independent and asynchronous with the APB clock.

Refer to RCC Section for more information on generating this clock source.

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be reset.

b) The ADC clock can be derived from the APB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be different from “00”.

In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR register).

Option a) has the advantage of reaching the maximum ADC clock frequency whatever the APB clock scheme selected.

Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains).

Table 58. Latency between trigger and start of conversion ⁽¹⁾⁽²⁾

ADC clock source	CKMODE[1:0]	Latency between the trigger event and the start of conversion
HSI16, SYSCLK, or PLLPCLK ⁽³⁾	00	Latency is not deterministic (jitter)
PCLK divided by 2	01	Latency is deterministic (no jitter) and equal to 3.25 ADC clock cycles
PCLK divided by 4	10	Latency is deterministic (no jitter) and equal to 3.125 ADC clock cycles
PCLK divided by 1	11	Latency is deterministic (no jitter) and equal to 3.5 ADC clock cycles

1. Refer to the device datasheet for the maximum ADC_CLK frequency.
2. If the trigger is generated by TIM1 or TIM15 clocked at twice the CPU clock frequency, then the latency is not deterministic and can be increased by one TIM1 or TIM15 clock cycle.
3. Selected with ADCSEL bitfield of the RCC_CCIPR register.

Caution: When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and clock controller section). If an internal source clock is selected, the AHB and APB prescalers do not divide the clock.

14.3.6 ADC connectivity

ADC inputs are connected to the external channels as well as internal sources as described in Figure 32.

Figure 32. ADC connectivity

The diagram illustrates the internal architecture of the ADC1 SAR block within an STM32G0xx microcontroller. On the left, a vertical bus labeled "STM32G0xx" provides connections for various ADC input channels. These include external channels (ADC_IN0 to ADC_IN18) and internal sources (V _SENSE, V _REFINT, and V _BAT/3). Each channel is connected to a switch that can route the signal to a common vertical bus labeled "Channel selection". The "Channel selection" bus is connected to the V _INinput of a SAR ADC1 block. The SAR ADC1 block also receives V _REF+and V _REF-inputs. The diagram is labeled with "MSV45361V3" in the bottom right corner.

Figure 32. ADC connectivity diagram showing the internal connections of the ADC1 SAR block in an STM32G0xx microcontroller.

14.3.7 Configuring the ADC

Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is disabled (ADEN must be 0).

Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).

For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_CHSELR and ADC_CCR registers, refer to the description of the corresponding control bit in Section 14.12: ADC registers .

ADC_AWDTRx registers can be modified when conversion is ongoing.

Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled (and possibly converting) and there is no pending request to disable the ADC (ADSTART = 1 and ADDIS = 0).

Note: There is no hardware protection preventing software from making write operations forbidden by the above rules. If such a forbidden write access occurs, the ADC may enter an undefined state. To recover correct operation in this case, the ADC must be disabled (clear ADEN = 0 and all the bits in the ADC_CR register).

14.3.8 Channel selection (CHSEL, SCANDIR, CHSELROMOD)

There are up to 19 multiplexed channels:

• 16 analog inputs from GPIO pins (ADC_INx)
• 3 internal analog inputs (Temperature Sensor, Internal Reference Voltage, V _BATchannel)

It is possible to convert a single channel or a sequence of channels.

The sequence of the channels to be converted can be programmed in the ADC_CHSELR channel selection register: each analog input channel has a dedicated selection bit (CHSELx).

The ADC scan sequencer can be used in two different modes:

• Sequencer not fully configurable:
The order in which the channels are scanned is defined by the channel number (CHSELROMOD bit must be cleared in ADC_CFGR1 register):
- – Sequence length configured through CHSELx bits in ADC_CHSELR register
- – Sequence direction: the channels are scanned in a forward direction (from the lowest to the highest channel number) or backward direction (from the highest to the lowest channel number) depending on the value of SCANDIR bit (SCANDIR = 0: forward scan, SCANDIR = 1: backward scan)

– Any channel can belong to in these sequences
• Sequencer fully configurable
The CHSELRMOD bit is set in ADC_CFGR1 register.
- – Sequencer length is up to 8 channels
- – The order in which the channels are scanned is independent from the channel number. Any order can be configured through SQ1[3:0] to SQ8[3:0] bits in ADC_CHSELR register.
- – Only channel 0 to channel 14 can be selected in this sequence
- – If the sequencer detects SQx[3:0] = 0b1111, the following SQx[3:0] registers are ignored.
- – If no 0b1111 is programmed in SQx[3:0], the sequencer scans full eight channels.

After programming ADC CHSELR, SCANDIR and CHSELRMOD bits, it is mandatory to wait for CCRDY flag before starting conversions. It indicates that the new channel setting has been applied. If a new configuration is required, the CCRDY flag must be cleared prior to starting the conversion.

The software is allowed to program the CHSEL, SCANDIR, CHSELRMOD bits only when ADSTART bit is cleared to 0 (which ensures that no conversion is ongoing).

Temperature sensor, $V_{REFINT}$ and $V_{BAT}$ internal channels

The temperature sensor is connected to channel ADC $V_{IN}[12]$ .

The internal voltage reference $V_{REFINT}$ is connected to channel ADC $V_{IN}[13]$ .

The $V_{BAT}$ channel is connected to ADC $V_{IN}[14]$ channel.

14.3.9 Programmable sampling time (SMPx[2:0])

Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level.

Having a programmable sampling time allows the conversion speed to be trimmed according to the input resistance of the input voltage source.

The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the SMP1[2:0] and SMP2[2:0] bits in the ADC_SMPR register.

Each channel can choose one out of two sampling times configured in SMP1[2:0] and SMP2[2:0] bitfields, through SMPSELx bits in ADC_SMPR register.

The total conversion time is calculated as follows:

t_{CONV} = \text{Sampling time} + 12.5 \times \text{ADC clock cycles}

Example:

With $ADC\_CLK = 16 \text{ MHz}$ and a sampling time of 1.5 ADC clock cycles:

t_{CONV} = 1.5 + 12.5 = 14 \text{ ADC clock cycles} = 0.875 \mu\text{s}

The ADC indicates the end of the sampling phase by setting the EOSMP flag.

14.3.10 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again.

Note: To convert a single channel, program a sequence with a length of 1.

14.3.11 Continuous conversion mode (CONT = 1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

Note: To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

14.3.12 Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART = 1.

When ADSTART is set, the conversion:

• Starts immediately if EXTEN = 00 (software trigger)
• At the next active edge of the selected hardware trigger if EXTEN ≠ 00

The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.

The ADSTART bit is cleared by hardware:

• In single mode with software trigger (CONT = 0, EXTEN = 00)
- – At any end of conversion sequence (EOS = 1)
• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
- – At end of conversion (EOC = 1)
• In all cases (CONT = x, EXTEN = XX)
- – After execution of the ADSTP procedure invoked by software (see Section 14.3.14: Stopping an ongoing conversion (ADSTP) on page 289 )

Note: In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the EOS flag is set because the sequence is automatically relaunched.

When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART is not cleared by hardware when the EOS flag is set. This avoids the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed.

After changing channel selection configuration (by programming ADC_CHSELR register or changing CHSELRMOD or SCANDIR), it is mandatory to wait until CCRDY flag is asserted before asserting ADSTART, otherwise the value written to ADSTART is ignored.

14.3.13 Timings

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution:

t_{CONV} = t_{SMPL} + t_{SAR} = [1.5_{|min} + 12.5_{|12bit}] \times t_{ADC\_CLK}

t_{CONV} = t_{SMPL} + t_{SAR} = 42.9 \text{ ns}_{|min} + 357.1 \text{ ns}_{|12bit} = 0.400 \text{ } \mu\text{s}_{|min} \text{ (for } f_{ADC\_CLK} = 35 \text{ MHz)}

Figure 33. Analog to digital conversion time

The diagram shows the timing of an ADC conversion. The ADC state transitions from RDY to SAMPLING CH(N), then to CONVERTING CH(N), and finally to SAMPLING CH(N+1). The analog channel switches from CH(N) to CH(N+1) during the sampling phase. The internal S/H signal shows 'Sample AIN(N+1)' during the sampling phase and 'Hold AIN(N)' during the converting phase. The ADSTART signal is set by software (SW) to start the conversion. The EOSMP signal is set by hardware (HW) at the end of sampling and cleared by SW. The EOC signal is set by HW at the end of conversion and cleared by SW. The ADC_DR register contains DATA N-1 during the conversion of CH(N) and DATA N during the conversion of CH(N+1).
(1) $t_{SMPL}$ depends on SMP[2:0]
(2) $t_{SAR}$ depends on RES[2:0]
MS30336V1

Timing diagram for Figure 33 showing ADC state, Analog channel, Internal S/H, ADSTART, EOSMP, EOC, and ADC_DR signals over time. It illustrates the sampling and converting phases for channels N and N+1.

Figure 34. ADC conversion timings

The diagram illustrates the timing from the start of a conversion sequence to the availability of data. The ADSTART signal is shown with a latency $t_{LATENCY}$ before the ADC state changes from Ready to S0. The ADC state sequence is Ready, S0, Conversion 0, S1, Conversion 1, S2, Conversion 2, S3, Conversion 3. The ADC_DR register shows a write latency $W_{LATENCY}$ from the start of each conversion (S0, S1, S2) to the data (Data 0, Data 1, Data 2) becoming available.
1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)
MSV33174V1

Timing diagram for Figure 34 showing ADSTART, ADC state, and ADC_DR signals. It details the latency from ADSTART to the start of conversion and the write latency for the ADC_DR register.

14.3.14 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register.

This resets the ADC operation and the ADC is idle, ready for a new operation.

When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).

The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).

Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 35. Stopping an ongoing conversion

The diagram illustrates the timing for stopping an ongoing conversion. The ADC state transitions from RDY to SAMPLING CH(N) to CONVERTING CH(N) and back to RDY. The ADSTART bit is set by software at the beginning and cleared by hardware when the ADC returns to the RDY state. The ADSTOP bit is set by software while the ADC is in the CONVERTING CH(N) state and is cleared by hardware when the ADC returns to the RDY state. The ADC_DR register contains DATA N-1 during the conversion.

Timing diagram showing the sequence of events to stop an ongoing conversion. The diagram shows four horizontal timelines: ADC state, ADSTART, ADSTOP, and ADC_DR. The ADC state transitions from RDY to SAMPLING CH(N) to CONVERTING CH(N) and back to RDY. ADSTART is set by software at the start and cleared by hardware when the ADC returns to RDY. ADSTOP is set by software while the ADC is in the CONVERTING CH(N) state and is cleared by hardware when the ADC returns to RDY. The ADC_DR register contains DATA N-1 during the conversion.

14.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)

A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to "0b00", then external events are able to trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit ADSTART = 1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

If bit ADSTART = 0, any hardware triggers which occur are ignored.

Table 59 provides the correspondence between the EXTEN[1:0] values and the trigger polarity.

Table 59. Configuring the trigger polarity

Source	EXTEN[1:0]
Trigger detection disabled	00
Detection on rising edge	01
Detection on falling edge	10
Detection on both rising and falling edges	11

Note: The polarity of the external trigger can be changed only when the ADC is not converting (ADSTART = 0).

The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger conversions.

Refer to Table 57: External triggers in Section 14.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion.

The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.

Note: The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

14.4.1 Discontinuous mode (DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.

In this mode (DISCEN = 1), a hardware or software trigger event is required to start each conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or software trigger event successively starts all the conversions defined in the sequence.

Example:

• DISCEN = 1, channels to be converted = 0, 3, 7, 10
- – 1st trigger: channel 0 is converted and an EOC event is generated
- – 2nd trigger: channel 3 is converted and an EOC event is generated
- – 3rd trigger: channel 7 is converted and an EOC event is generated
- – 4th trigger: channel 10 is converted and both EOC and EOS events are generated.
- – 5th trigger: channel 0 is converted an EOC event is generated
- – 6th trigger: channel 3 is converted and an EOC event is generated
- – ...
• DISCEN = 0, channels to be converted = 0, 3, 7, 10
- – 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each conversion generates an EOC event and the last one also generates an EOS event.
- – Any subsequent trigger events restarts the complete sequence.

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

14.4.2 Programmable resolution (RES) - Fast conversion mode

It is possible to obtain faster conversion times ( $t_{SAR}$ ) by reducing the ADC resolution.

The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times for applications where high data precision is not required.

Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.

The result of the conversion is always 12 bits wide and any unused LSB bits are read as zeros.

Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table 60 .

Table 60.

t_{SAR}

timings depending on resolution

RES[1:0] bits	$t_{SAR}$ (ADC clock cycles)	$t_{SAR}$ (ns) at $f_{ADC} = 35$ MHz	$t_{SMPL}$ (min) (ADC clock cycles)	$t_{CONV}$ (ADC clock cycles) (with min. $t_{SMPL}$ )	$t_{CONV}$ (ns) at $f_{ADC} = 35$ MHz
12	12.5	357	1.5	14	400
10	10.5	300	1.5	12	343
8	8.5	243	1.5	10	286
6	6.5	186	1.5	8	229

14.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

The ADC indicates each end of conversion (EOC) event.

The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.

The ADC also indicates the end of sampling phase by setting the EOSMP flag in the ADC_ISR register. The EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if the EOSMPIE bit is set in the ADC_IER register.

The aim of this interrupt is to allow the processing to be synchronized with the conversions. Typically, an analog multiplexer can be accessed in hidden time during the conversion phase, so that the multiplexer is positioned when the next sampling starts.

Note: As there is only a very short time left between the end of the sampling and the end of the conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt and a WFI instruction.

14.4.4 End of conversion sequence (EOS flag)

The ADC notifies the application of each end of sequence (EOS) event.

The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a conversion sequence is available in the ADC_DR register. An interrupt can be generated if the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing 1 to it.

14.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)

Figure 36. Single conversions of a sequence, software trigger

MSv30338V3

Timing diagram for Figure 36 showing single conversions of a sequence with a software trigger. Signals include ADSTART(1), EOC, EOS, SCANDIR, ADC state(2), and ADC_DR. The sequence shows conversions for CH0, CH9, CH10, and CH17, with corresponding data D0, D9, D10, and D17. A second sequence shows the reverse order: CH17, CH10, CH9, CH0 with data D17, D10, D9, D0. Legend indicates rising arrows are 'by S/W' and falling arrows are 'by H/W'.

1. EXTEN = 00, CONT = 0
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

Figure 37. Continuous conversion of a sequence, software trigger

MSv30339V2

Timing diagram for Figure 37 showing continuous conversion of a sequence with a software trigger. Signals include ADSTART(1), EOC, EOS, ADSTP, SCANDIR, ADC state(2), and ADC_DR. The sequence continuously converts CH0, CH9, CH10, and CH17 until an ADSTP signal occurs. After a direction change (SCANDIR), it converts CH17 and CH10. Legend indicates rising arrows are 'by S/W' and falling arrows are 'by H/W'.

1. EXTEN = 00, CONT = 1,
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

Figure 38. Single conversions of a sequence, hardware trigger

Timing diagram for single conversions of a sequence with hardware trigger. It shows the relationship between ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR signals over time. The diagram illustrates that the ADC starts on a rising edge of TRGx, converts four channels (CH0-CH3), and returns to the READY state. The process repeats for a second sequence. A legend indicates that solid lines represent software (S/W) or hardware (H/W) triggers, while dashed lines represent ignored signals.

Timing diagram for single conversions of a sequence, hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR signals over time. The legend indicates that solid lines represent software (S/W) or hardware (H/W) triggers, while dashed lines represent ignored signals.

Legend:

by S/W (solid line with rising edge)
by H/W (solid line with falling edge)
triggered (solid line with rising edge)
ignored (dashed line with falling edge)

MSv30340V2

Timing diagram for single conversions of a sequence with hardware trigger. It shows the relationship between ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR signals over time. The diagram illustrates that the ADC starts on a rising edge of TRGx, converts four channels (CH0-CH3), and returns to the READY state. The process repeats for a second sequence. A legend indicates that solid lines represent software (S/W) or hardware (H/W) triggers, while dashed lines represent ignored signals.

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

Figure 39. Continuous conversions of a sequence, hardware trigger

Timing diagram for continuous conversions of a sequence with hardware trigger. It shows the relationship between ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR signals over time. The diagram illustrates that the ADC starts on a falling edge of TRGx, enters a continuous conversion loop of four channels (CH0-CH3), and stops when ADSTP is asserted. A legend indicates that solid lines represent software (S/W) or hardware (H/W) triggers, while dashed lines represent ignored signals.

Timing diagram for continuous conversions of a sequence, hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR signals over time. The legend indicates that solid lines represent software (S/W) or hardware (H/W) triggers, while dashed lines represent ignored signals.

Legend:

by S/W (solid line with rising edge)
by H/W (solid line with falling edge)
triggered (solid line with rising edge)
ignored (dashed line with falling edge)

MSv30341V2

Timing diagram for continuous conversions of a sequence with hardware trigger. It shows the relationship between ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR signals over time. The diagram illustrates that the ADC starts on a falling edge of TRGx, enters a continuous conversion loop of four channels (CH0-CH3), and stops when ADSTP is asserted. A legend indicates that solid lines represent software (S/W) or hardware (H/W) triggers, while dashed lines represent ignored signals.

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

14.4.6 Low frequency trigger mode

Once the ADC is enabled or the last ADC conversion is complete, the ADC is ready to start a new conversion. The ADC needs to be started at a predefined time ( $t_{idle}$ ) otherwise ADC converted data might be corrupted due to the transistor leakage (refer to the device datasheet for the maximum value of $t_{idle}$ ).

If the application has to support a time longer than the maximum $t_{idle}$ value (between one trigger to another for single conversion mode or between the ADC enable and the first ADC conversion), then the ADC internal state needs to be rearmed. This mechanism can be enabled by setting LFTRIG bit to 1 in ADC_CFGR2 register. By setting this bit, any trigger (software or hardware) sends a rearm command to ADC. The conversion is started after a two ADC clock cycle delay compared to LFTRIG set to 0.

It is not necessary to use this mode when AUTOFF bit is set to 1. For Wait mode, only the first trigger generates an internal rearm command.

14.5 Data management

14.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide.

The format of the ADC_DR depends on the configured data alignment and resolution.

The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in Figure 40.

Figure 40. Data alignment and resolution (oversampling disabled: OVSE = 0)

ALIGN	RES	15	5	1	0
0	0x0	0x0	DR[11:0]
	0x1	0x00	DR[9:0]
	0x2	0x00	DR[7:0]
	0x3	0x00	DR[5:0]
1	0x0	DR[11:0]		0x0
	0x1	DR[9:0]		0x00
	0x2	DR[7:0]		0x00
	0x3	0x00	DR[5:0]		0x0

MS30342V1

14.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the CPU or the DMA, before the data from a new conversion is available.

The OVR flag is set in the ADC_ISR register if the EOC flag is still at '1' at the time when a new conversion completes. An interrupt can be generated if the OVRIE bit is set in the ADC_IER register.

When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register.

The OVR flag is cleared by software by writing 1 to it.

It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register:

• OVRMOD = 0
- – An overrun event preserves the data register from being overwritten: the old data is maintained and the new conversion is discarded. If OVR remains at 1, further conversions can be performed but the resulting data is discarded.
• OVRMOD = 1
- – The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, further conversions can be performed and the ADC_DR register always contains the data from the latest conversion.

Figure 41. Example of overrun (OVR)

Timing diagram illustrating an overrun condition in an ADC. The diagram shows the relationship between ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR data for two modes: OVRMOD=0 and OVRMOD=1. An overrun occurs when a new conversion starts before the previous one is read.

The diagram illustrates the timing of an ADC overrun condition. The signals shown are:

ADSTART ⁽¹⁾: Software trigger signal, active high.
EOC : End of Conversion signal, toggles for each conversion.
EOS : End of Sequence signal, toggles at the end of a sequence.
OVR : Overrun flag, set when a new conversion starts before the previous one is read.
ADSTP : Stop conversion signal, active high.
TRGx ⁽¹⁾: Hardware trigger signal, active high.
ADC state ⁽²⁾: States of the ADC: RDY, CH0, CH1, CH2, CH0, CH1, CH2, CH0, STOP, RDY.
ADC_DR read access : Software read access to the data register. An 'OVERRUN' is indicated when a read is attempted while the OVR flag is set.
ADC_DR (OVRMOD=0) : Data register contents when OVRMOD=0. The data is preserved during an overrun: D0, D1, D2, D0.
ADC_DR (OVRMOD=1) : Data register contents when OVRMOD=1. The data is overwritten during an overrun: D0, D1, D2, D0, D1, D2.

Legend for signal transitions:

by S/W (Software): rising edge
by H/W (Hardware): rising edge
triggered: falling edge

MSV30343V3

Timing diagram illustrating an overrun condition in an ADC. The diagram shows the relationship between ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR data for two modes: OVRMOD=0 and OVRMOD=1. An overrun occurs when a new conversion starts before the previous one is read.

14.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register should be configured to 0 to manage overrun events as an error.

14.5.4 Managing converted data without using the DMA without overrun

It may be useful to let the ADC convert one or more channels without reading the data after each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent the ADC from continuing to convert and the ADC_DR register always contains the latest conversion data.

14.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use DMA when converting more than one channel. This avoids losing the conversion data results stored in the ADC_DR register.

When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA request is generated after the conversion of each channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.

Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section 14.5.2: ADC overrun (OVR, OVRMOD) on page 294 ).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG in the ADC_CFGR1 register:

• DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed number of data words.
• DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode or double buffer mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when a DMA_EOT interrupt occurs, see Section 9: Direct memory access controller (DMA) on page 213 ) even if a conversion has been started again.

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted and its partial result discarded
• No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available in the data register, even if the DMA has reached the last DMA transfer. This allows the DMA to be configured in circular mode to handle a continuous analog input data stream.

14.6 Low-power features

14.6.1 Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the performance of applications clocked at low frequency where there might be a risk of ADC overrun occurring.

When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared.

This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.

Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the read access are ignored.

Figure 42. Wait mode conversion (continuous mode, software trigger)

The timing diagram illustrates the sequence of events for a software-triggered continuous conversion in wait mode.
1. ADSTART : A rising edge (by S/W) initiates the conversion sequence.
2. ADC state : The state transitions from RDY to CH1 , then DLY , CH2 , DLY , CH3 , DLY , CH1 , DLY , STOP , and finally RDY .
3. ADC_DR : Data values D1 , D2 , D3 , and D1 are produced during the conversion phases.
4. ADC_DR Read access : Pulses occur when the data register is read, coinciding with the EOC signals.
5. EOC : End-of-conversion signals toggle between high and low for each conversion.
6. EOS : End-of-sequence signal goes high after the third conversion (CH3) and returns low when the sequence stops.
7. ADSTP : A falling edge (by H/W) stops the conversion sequence.
Legend: by S/W (rising edge), by H/W (falling edge).

Timing diagram for Figure 42 showing ADC signals over time. The diagram includes ADSTART (software trigger), EOC (end of conversion), EOS (end of sequence), ADSTP (stop), ADC_DR Read access, ADC state (RDY, CH1, DLY, CH2, DLY, CH3, DLY, CH1, DLY, STOP, RDY), and ADC_DR (data registers D1, D2, D3, D1). A legend indicates 'by S/W' for rising edges and 'by H/W' for falling edges.

MSV30344V2

1. EXTEN = 00, CONT = 1
2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0

14.6.2 Auto-off mode (AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.

When AUTOFF = 1, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger). A startup-time is automatically inserted between the trigger event which starts the conversion and the sampling time of the ADC. The ADC is then automatically disabled once the sequence of conversions is complete.

Auto-off mode can cause a dramatic reduction in the power consumption of applications which need relatively few conversions or when conversion requests are timed far enough apart (for example with a low frequency hardware trigger) to justify the extra power and extra time used for switching the ADC on and off.

Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications clocked at low frequency. This combination can provide significant power savings if the ADC is automatically powered-off during the wait phase and restarted as soon as the ADC_DR register is read by the application (see Figure 44: Behavior with WAIT = 1, AUTOFF = 1 ).

Note: Please refer to the Section Reset and clock control (RCC) for the description of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch ON/OFF the 14 MHz internal oscillator to save power.

Figure 43. Behavior with WAIT = 0, AUTOFF = 1

Timing diagram for Figure 43 showing ADC behavior with WAIT = 0 and AUTOFF = 1. The diagram illustrates the relationship between the trigger signal (TRGx), End of Conversion (EOC), End of Sequence (EOS), ADC data register (ADC_DR) read access, and the ADC state across four channels (CH1, CH2, CH3, CH4).

The timing diagram for Figure 43 shows the following signals and states over time:

TRGx: A trigger signal that is initially low and has two rising edges. The first rising edge starts the conversion sequence.
EOC: End of Conversion signal. It pulses high when each channel's conversion is complete (CH1, CH2, CH3, CH4) and returns low.
EOS: End of Sequence signal. It goes high after the last channel (CH4) conversion is complete and returns low when the sequence restarts.
ADC_DR Read access: A signal indicating when the ADC data register is being read. It is shown as a series of pulses corresponding to the completion of each channel's conversion.
ADC state: Shows the state of the ADC: RDY (Ready) → Startup → CH1 → CH2 → CH3 → CH4 → OFF → Startup. The OFF state occurs after the sequence completes and before the next startup.
ADC_DR: The data register, which contains the digital values D1, D2, D3, and D4 corresponding to the conversions of CH1, CH2, CH3, and CH4 respectively.

Legend for trigger edges:

by S/W (Software): rising edge
by H/W (Hardware): falling edge
triggered: rising edge

MSv30345V2

Timing diagram for Figure 43 showing ADC behavior with WAIT = 0 and AUTOFF = 1. The diagram illustrates the relationship between the trigger signal (TRGx), End of Conversion (EOC), End of Sequence (EOS), ADC data register (ADC_DR) read access, and the ADC state across four channels (CH1, CH2, CH3, CH4).

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1

Figure 44. Behavior with WAIT = 1, AUTOFF = 1

Timing diagram for Figure 44 showing ADC behavior with WAIT = 1 and AUTOFF = 1. This diagram is similar to Figure 43 but includes a 'DLY' (delay) period between the completion of one channel's conversion and the start of the next. The ADC state includes 'OFF' periods between sequences.

The timing diagram for Figure 44 shows the following signals and states over time:

TRGx: Similar to Figure 43, with two rising edges triggering the sequence.
EOC: Pulses high for each channel conversion (CH1, CH2, CH3, CH4).
EOS: Goes high after CH4 and returns low at the start of the next sequence.
ADC_DR Read access: Pulses when data is read from the register.
ADC state: RDY → Startup → CH1 → OFF → Startup → CH2 → OFF → Startup → CH3 → OFF → Startup → CH1 → CH2. The 'OFF' state is entered after each channel's conversion when WAIT=1.
DLY: A delay period indicated between the EOC pulse of one channel and the start of the next.
ADC_DR: Contains digital values D1, D2, D3, and D4.

Legend for trigger edges:

by S/W (Software): rising edge
by H/W (Hardware): falling edge
triggered: rising edge

MSv30346V2

Timing diagram for Figure 44 showing ADC behavior with WAIT = 1 and AUTOFF = 1. This diagram is similar to Figure 43 but includes a 'DLY' (delay) period between the completion of one channel's conversion and the start of the next. The ADC state includes 'OFF' periods between sequences.

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1

14.7 Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR)

The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window).

14.7.1 Description of analog watchdog 1

AWD1 analog watchdog is enabled by setting the AWD1EN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 62: Analog watchdog 1 channel selection ) remain within a configured voltage range (window) as shown in Figure 45 .

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in HT1[11:0] and LT1[11:0] bits of ADC_AWD1TR register. An interrupt can be enabled by setting the AWD1IE bit in the ADC_IER register.

The AWD1 flag is cleared by software by programming it to 1.

When converting data with a resolution of less than 12-bit (according to bits DRES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

Table 61 describes how the comparison is performed for all the possible resolutions.

Table 61. Analog watchdog comparison

Resolution bits RES[1:0]	Analog Watchdog comparison between:		Comments
Resolution bits RES[1:0]	Raw converted data, left aligned ⁽¹⁾	Thresholds	Comments
00: 12-bit	DATA[11:0]	LTx[11:0] and HTx[11:0]	-
01: 10-bit	DATA[11:2],00	LTx[11:0] and HTx[11:0]	The user must configure LTx[1:0] and HTx[1:0] to “00”
10: 8-bit	DATA[11:4],0000	LTx[11:0] and HTx[11:0]	The user must configure LTx[3:0] and HTx[3:0] to “0000”
11: 6-bit	DATA[11:6],000000	LTx[11:0] and HTx[11:0]	The user must configure LTx[5:0] and HTx[5:0] to “000000”

1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 62 shows how to configure the AWD1SGL and AWD1EN bits in the ADC_CFGR1 register to enable the analog watchdog on one or more channels.

Figure 45. Analog watchdog guarded area

The diagram illustrates the 'Guarded area' for an analog watchdog. A vertical axis on the left is labeled 'Analog voltage' with an upward-pointing arrow. Two horizontal lines extend from this axis to the right, labeled 'Higher threshold' (HTx) and 'Lower threshold' (LTx). The rectangular region between these two lines is shaded gray and labeled 'Guarded area'. In the bottom right corner of the diagram, there is a small text label 'MS45396V1'.

Diagram showing the analog watchdog guarded area. A vertical axis represents 'Analog voltage'. Two horizontal lines represent the 'Higher threshold' (HTx) and 'Lower threshold' (LTx). The region between these two thresholds is shaded and labeled 'Guarded area'.

Table 62. Analog watchdog 1 channel selection

Channels guarded by the analog watchdog	AWD1SGL bit	AWD1EN bit
None	x	0
All channels	0	1
Single ⁽¹⁾channel	1	1

1. Selected by the AWD1CH[4:0] bits

14.7.2 Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected channels by programming the AWDxCHy in ADC_AWDxCR (x = 2, 3).

The corresponding watchdog is enabled when any AWDxCHy bit (x = 2,3) is set in ADC_AWDxCR register.

When converting data with a resolution of less than 12 bits (configured through DRES[1:0] bits), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

Table 61 describes how the comparison is performed for all the possible resolutions.

The AWD2/3 analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in HTx[11:0] and LTx[11:0] of ADC_AWDxTR registers (x = 2 or 3). An interrupt can be enabled by setting the AWDxIE bit in the ADC_IER register.

The AWD2 and ADW3 flags are cleared by software by programming them to 1.

14.7.3 ADC_AWDx_OUT output signal generation

Each analog watchdog is associated to an internal hardware signal, ADC_AWDx_OUT (x being the watchdog number) that is directly connected to the ETR input (external trigger) of some on-chip timers (refer to the timers section for details on how to select the ADC_AWDx_OUT signal as ETR).

ADC_AWDx_OUT is activated when the associated analog watchdog is enabled:

• ADC_AWDx_OUT is set when a guarded conversion is outside the programmed thresholds.
• ADC_AWDx_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds. It remains at 1 if the next guarded conversions are still outside the programmed thresholds.
• ADC_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS to 1). Note that stopping conversions (ADSTP set to 1), might clear the ADC_AWDx_OUT state.
• ADC_AWDx_OUT state does not change when the ADC converts the none-guarded channel (see Figure 48 )

AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the generation of ADC_AWDx_OUT (as an example, ADC_AWDx_OUT can toggle while AWDx flag remains at 1 if the software has not cleared the flag).

The ADC_AWDx_OUT signal is generated by the ADC_CLK domain. This signal can be generated even the APB clock is stopped.

The AWD comparison is performed at the end of each ADC conversion. The ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison.

As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized.

Figure 46. ADC_AWDx_OUT signal generation

Timing diagram for Figure 46 showing ADC STATE, EOC FLAG, AWDx FLAG, and ADC_AWDx_OUT signals across seven conversions. The AWDx FLAG is cleared by software for conversions 3, 4, 5, and 6.

The diagram shows four signal lines over time, divided into segments for each conversion. The ADC STATE line shows a sequence of RDY, Conversion1 (inside), Conversion2 (outside), Conversion3 (inside), Conversion4 (outside), Conversion5 (outside), Conversion6 (outside), and Conversion7 (inside). The EOC FLAG pulses high at the end of each conversion. The AWDx FLAG goes high after Conversion2 and is cleared by software (SW) after Conversions 3, 4, 5, and 6. The ADC_AWDx_OUT signal changes state based on the AWDx FLAG, with edges occurring two clock cycles after the comparison points.

Legend:

- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

MSv45362V1

Timing diagram for Figure 46 showing ADC STATE, EOC FLAG, AWDx FLAG, and ADC_AWDx_OUT signals across seven conversions. The AWDx FLAG is cleared by software for conversions 3, 4, 5, and 6.

Figure 47. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software)

Timing diagram for Figure 47 similar to Figure 46, but the AWDx FLAG is not cleared by software after Conversion3, remaining high until the end of the sequence.

This diagram is similar to Figure 46 but with a key difference in the AWDx FLAG signal. After the first pulse following Conversion2, the AWDx FLAG is not cleared by software after Conversion3 and remains high through the end of the sequence shown. The ADC_AWDx_OUT signal follows this persistent high state of the AWDx FLAG.

Legend:

- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

MSv45363V1

Timing diagram for Figure 47 similar to Figure 46, but the AWDx FLAG is not cleared by software after Conversion3, remaining high until the end of the sequence.

Figure 48. ADC_AWDx_OUT signal generation (on a single channel)

Timing diagram for ADC_AWDx_OUT signal generation. The diagram shows four signals over time: ADC STATE, EOC FLAG, EOS FLAG, and ADCy_AWDx_OUT. The ADC STATE is divided into segments for Conversion1 and Conversion2, with labels 'outside', 'inside', 'outside', and 'outside'. The EOC FLAG pulses at the end of each conversion. The EOS FLAG is cleared by software (SW) after the first conversion. The ADCy_AWDx_OUT signal is high when Conversion1 is 'inside' the threshold and low otherwise. A legend indicates: - Converted channels: 1 and 2; - Only channel 1 is guarded. The diagram is labeled MSv45364V1.

14.7.4 Analog Watchdog threshold control

LTx[11:0] and HTx[11:0] can be changed during an analog-to-digital conversion (that is between the start of the conversion and the end of conversion of the ADC internal state). If HTx and LTx bits are programmed during the ADC guarded channel conversion, the watchdog function is masked for this conversion. This mask is cleared when starting a new conversion, and the resulting new AWD threshold is applied starting the next ADC conversion result. AWD comparison is performed at each end of conversion. If the current ADC data are out of the new threshold interval, this does not generate any interrupt or an ADC_AWDx_OUT signal. The Interrupt and the ADC_AWDx_OUT generation only occurs at the end of the ADC conversion that started after the threshold update. If ADC_AWDx_OUT is already asserted, programming the new threshold does not deactivate the ADC_AWDx_OUT signal.

Figure 49. Analog watchdog threshold update

Timing diagram for analog watchdog threshold update. The diagram shows three signals over time: ADC state, LTx, HTx, and Comparison. The ADC state shows four conversion segments. The LTx, HTx signal shows threshold values XXXX, XXXY, and XXXZ, with an arrow indicating a threshold update between the second and third conversions. The Comparison signal shows 'Active' periods corresponding to the first and fourth conversions, and a 'Masked' period during the third conversion which starts after the threshold update. The diagram is labeled MSv45365V1.

14.8 Oversampler

The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit.

It provides a result with the following form, where N and M can be adjusted:

\text{Result} = \frac{1}{M} \times \sum_{n=0}^{n=N-1} \text{Conversion}(t_n)

It allows the following functions to be performed by hardware: averaging, data rate reduction, SNR improvement, basic filtering.

The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits. It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.

The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register.

Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated.

Figure 50. 20-bit to 16-bit result truncation

Diagram illustrating the 20-bit to 16-bit result truncation process. It shows three horizontal bars representing bit sequences. The top bar, 'Raw 20-bit data', has bits 19, 15, 11, 7, 3, and 0 marked. The middle bar, 'Shifting', shows a rightward arrow indicating a shift. The bottom bar, 'Truncation and rounding', shows the resulting 16-bit sequence with bits 15 and 0 marked. A dashed vertical line separates the 20-bit raw data from the 16-bit truncated result. The text 'MS31928V2' is in the bottom right corner.

The Figure 51 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.

Figure 51. Numerical example with 5-bits shift and rounding

Figure 51: Numerical example with 5-bits shift and rounding. The diagram shows two rows of data. The first row, 'Raw 20-bit data:', has five fields with bit positions 19, 15, 11, 7, and 3 above them. The values are 3, B, 7, D, and 7. The second row, 'Final result after 5-bits shift and rounding to nearest', has four fields with bit positions 15 and 0 above them. The values are 1, D, B, and F. A small text 'MS31929V1' is in the bottom right corner.

The Table 63 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.

Table 63. Maximum output results vs N and M. Grayed values indicates truncation

Oversampling ratio	Max Raw data	No-shift OVSS = 0000	1-bit shift OVSS = 0001	2-bit shift OVSS = 0010	3-bit shift OVSS = 0011	4-bit shift OVSS = 0100	5-bit shift OVSS = 0101	6-bit shift OVSS = 0110	7-bit shift OVSS = 0111	8-bit shift OVSS = 1000
2x	0x1FFE	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040	0x0020
4x	0x3FFC	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040
8x	0x7FF8	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080
16x	0xFFF0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100
32x	0x1FFE0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200
64x	0x3FFC0	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400
128x	0x7FF80	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800
256x	0xFFF00	0xFF00	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF

The conversion timings in oversampled mode do not change compared to standard conversion mode: the sample time is maintained equal during the whole oversampling sequence. New data are provided every N conversion, with an equivalent delay equal to $N \times t_{\text{CONV}} = N \times (t_{\text{SMP}} + t_{\text{SAR}})$ . The flags features are raised as following:

• the end of the sampling phase (EOSMP) is set after each sampling phase
• the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available
• the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total)

14.8.1 ADC operating modes supported when oversampling

In oversampling mode, most of the ADC operating modes are available:

• Single or continuous mode conversions, forward or backward scanned sequences and up to 8 channels programmed sequence
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (WAIT, AUTOFF)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are

Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in ADC_CFGR1 is ignored and the data are always provided right-aligned.

14.8.2 Analog watchdog

The analog watchdog functionality is available (AWDxSGL, AW1DEN and AWDxCH bits), with the following differences:

• the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits values HTx[11:0] and LTx[11:0]
• the comparison is performed on the most significant 12 bits of the 16 bits oversampled results ADC_DR[15:4]

Note: Care must be taken when using high shifting values. This reduces the comparison range. For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data right-aligned, the affective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HTx[7:0] / LTx[7:0], and HTx[11:8] / LTx[11:8] must be kept reset.

14.8.3 Triggered mode

The averager can also be used for basic filtering purposes. Although not a very efficient filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself.

Figure 52 below shows how conversions are started in response to triggers in discontinuous mode.

If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

Figure 52. Triggered oversampling mode (TOVS bit = 1)

CONT = 0
(DISCEN = 1)*
TOVS = 0

Trigger

Ch(N) 0 | Ch(N) 1 | Ch(N) 2 | Ch(N) 3

EOC flag set

CONT = 0
(DISCEN = 1)*
TOVS = 1

Trigger Trigger Trigger Trigger Trigger Trigger Trigger

Ch(N) 0 | Ch(N) 1 | Ch(N) 2 | Ch(N) 3 | Ch(N) 0 | Ch(N) 1 | Ch(N) 2

EOC flag set

(DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set

MS33700V1

Figure 52: Triggered oversampling mode (TOVS bit = 1). The diagram illustrates two ADC conversion scenarios. The top scenario shows a single trigger initiating a sequence of four conversions (Ch(N) 0, 1, 2, 3) with settings CONT = 0, (DISCEN = 1)*, and TOVS = 0. The bottom scenario shows seven triggers initiating a sequence of seven conversions (Ch(N) 0, 1, 2, 3, 0, 1, 2) with settings CONT = 0, (DISCEN = 1)*, and TOVS = 1. Both sequences end with an 'EOC flag set'.

14.9 Temperature sensor and internal reference voltage

The temperature sensor can be used to measure the junction temperature ( $$ T_J $$ ) of the device. The temperature sensor is internally connected to the ADC $V_{IN}[12]$ input channel which is used to convert the sensor's output voltage to a digital value. The sampling time for the temperature sensor analog pin must be greater than the minimum $T_{S\_temp}$ value specified in the datasheet. When not in use, the sensor can be put in power down mode.

The internal voltage reference ( $V_{REFINT}$ ) provides a stable (bandgap) voltage output for the ADC. $V_{REFINT}$ is internally connected to the ADC $V_{IN}[13]$ input channel. The precise voltage of $V_{REFINT}$ is individually measured for each part by ST during production test and stored in the system memory area.

Figure 53 shows the block diagram of connections between the temperature sensor, the internal voltage reference and the ADC.

The TSEN bit must be set to enable the conversion of ADC $V_{IN}[12]$ (temperature sensor) and the VREFEN bit must be set to enable the conversion of ADC $V_{IN}[13]$ ( $V_{REFINT}$ ).

The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another).

The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production.

During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference. Refer to the datasheet for additional information.

Main features

• Supported temperature range: –40 to 125 °C
• Linearity: $\pm 2$ °C max., precision depending on calibration

Figure 53. Temperature sensor and V _REFINTchannel block diagram

Figure 53. Temperature sensor and VREFINT channel block diagram. The diagram shows two input sources connected to an ADC. The first source is a 'Temperature sensor' connected to an operational amplifier (op-amp) configured as a buffer. The op-amp's non-inverting input (+) is connected to the temperature sensor, and its output is labeled VSENSE. The op-amp is controlled by a 'TSEN control bit'. The VSENSE output is connected to the 'ADC VIN[12]' input. The second source is an 'Internal power block' connected to another op-amp configured as a buffer. This op-amp's non-inverting input (+) is connected to the internal power block, and its output is labeled VREFINT. This op-amp is controlled by a 'VREFEN control bit'. The VREFINT output is connected to the 'ADC VIN[13]' input. Both ADC inputs (VIN[12] and VIN[13]) are part of a larger 'ADC' block. The ADC outputs 'converted data' to an 'Address/data bus'. The diagram is labeled MSv62466V1 in the bottom right corner.

Reading the temperature

1. Select the ADC V _IN[12] input channel
2. Select an appropriate sampling time specified in the device datasheet (T _{S_temp}).
3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from power down mode and wait for its stabilization time (t _START).
4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by external trigger)
5. Read the resulting V _SENSEdata in the ADC_DR register
6. Calculate the temperature using the following formula

\text{Temperature (in } ^\circ\text{C)} = \frac{\text{TS\_CAL2\_TEMP} - \text{TS\_CAL1\_TEMP}}{\text{TS\_CAL2} - \text{TS\_CAL1}} \times (\text{TS\_DATA} - \text{TS\_CAL1}) + \text{TS\_CAL1\_TEMP}

Where:

• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP (refer to the datasheet for TS_CAL2 value)
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP (refer to the datasheet for TS_CAL1 value)
• TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points.

Note: The sensor has a startup time after waking from power down mode before it can output V _SENSEat the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and TSEN bits should be set at the same time.

Calculating the actual $V_{REF+}$ voltage using the internal reference voltage

$V_{REF+}$ voltage may be subject to variation or not precisely known. The embedded internal reference voltage ( $V_{REFINT}$ ) and its calibration data acquired by the ADC during the manufacturing process at $V_{REF+\_Charac}$ can be used to evaluate the actual $V_{REF+}$ voltage level.

The following formula gives the actual $V_{REF+}$ voltage supplying the device:

V_{REF+} = V_{REF+\_Charac} \times VREFINT\_CAL / VREFINT\_DATA

Where:

• $V_{REF+\_Charac}$ is the value of $V_{REF+}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.
• $VREFINT\_CAL$ is the $$ VREFINT $$ calibration value
• $VREFINT\_DATA$ is the actual $$ VREFINT $$ output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of $V_{REF+}$ . For applications where $V_{REF+}$ is known and ADC converted values are right-aligned you can use the following formula to get this absolute value:

V_{CHANNELx} = \frac{V_{REF+}}{FULL\_SCALE} \times ADC\_DATA_x

For applications where $V_{REF+}$ value is not known, you must use the internal voltage reference and $V_{REF+}$ can be replaced by the expression provided in Section : Calculating the actual $V_{REF+}$ voltage using the internal reference voltage , resulting in the following formula:

V_{CHANNELx} = \frac{V_{REF+\_Charac} \times VREFINT\_CAL \times ADC\_DATA_x}{VREFINT\_DATA \times FULL\_SCALE}

Where:

• $V_{REF+\_Charac}$ is the value of $V_{REF+}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.
• $VREFINT\_CAL$ is the $$ VREFINT $$ calibration value
• $ADC\_DATA_x$ is the value measured by the ADC on channelx (right-aligned)
• $VREFINT\_DATA$ is the actual $$ VREFINT $$ output value converted by the ADC
• $full\_SCALE$ is the maximum digital value of the ADC output. For example with 12-bit resolution, it is $2^{12} - 1 = 4095$ or with 8-bit resolution, $$ 2^8 - 1 = 255 $$ .

Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

14.10 Battery voltage monitoring

The $$ VBATEN $$ bit in the $ADC\_CCR$ register allows the application to measure the backup battery voltage on the $$ VBAT $$ pin. As the $V_{BAT}$ voltage could be higher than $V_{REF+}$ , to ensure

the correct operation of the ADC, the $V_{BAT}$ pin is internally connected to a bridge divider. This bridge is automatically enabled when $V_{BATEN}$ is set, to connect $V_{BAT}$ to the ADC $V_{IN}[14]$ input channel. As a consequence, the converted digital value is half the $V_{BAT}$ voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed for ADC conversion.

Figure 54. $V_{BAT}$ channel block diagram

Block diagram of the VBAT channel showing a bridge divider connected to the ADC VIN[14] input, controlled by the VBATEN control bit. The diagram shows VBAT connected to a switch controlled by VBATEN, which then connects to a bridge divider. The output of the divider, VBAT/3, is connected to the non-inverting input of an operational amplifier. The op-amp's output is connected to the ADC VIN[14] input. The ADC is connected to an Address/data bus. The diagram is labeled MSV45367V2.

14.11 ADC interrupts

An interrupt can be generated by any of the following events:

• End Of Calibration (EOCAL flag)
• ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
• End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD1, AWD2, AWD3 flags)
• When the Channel configuration is ready (CCRDY flag)
• When the end of sampling phase occurs (EOSMP flag)
• when a data overrun occurs (OVR flag)

Separate interrupt enable bits are available for flexibility.

Table 64. ADC interrupts

Interrupt event	Event flag	Enable control bit
End Of Calibration	EOCAL	EOCALIE
ADC ready	ADRDY	ADRDYIE
End of conversion	EOC	EOCIE
End of sequence of conversions	EOS	EOSIE
Analog watchdog 1 status bit is set	AWD1	AWD1IE

Table 64. ADC interrupts (continued)

Interrupt event	Event flag	Enable control bit
Analog watchdog 2 status bit is set	AWD2	AWD2IE
Analog watchdog 3 status bit is set	AWD3	AWD3IE
Channel Configuration Ready	CCRDY	CCRDYIE
End of sampling phase	EOSMP	EOSMPIE
Overrun	OVR	OVRIE

14.12 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

14.12.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	CCRDY	Res.	EOCAL	Res.	AWD3	AWD2	AWD1	Res.	Res.	OVR	EOS	EOC	EOSMP	ADRDY
		rc_w1		rc_w1		rc_w1	rc_w1	rc_w1			rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 CCRDY : Channel Configuration Ready flag

This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to 0.

0: Channel configuration update not applied.

1: Channel configuration update is applied.

Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCAL : End Of Calibration flag

This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.

0: Calibration is not complete

1: Calibration is complete

Bit 10 Reserved, must be kept at reset value.

Bit 9 AWD3 : Analog watchdog 3 flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1.

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog event occurred

Bit 8 AWD2 : Analog watchdog 2 flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it to 1.

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog event occurred

Bit 7 AWD1: Analog watchdog 1 flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1.

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog event occurred

Bits 6:5 Reserved, must be kept at reset value. Bit 4 OVR: ADC overrun

This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS: End of sequence flag

This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.

0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Conversion sequence complete

Bit 2 EOC: End of conversion flag

This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Channel conversion complete

Bit 1 EOSMP: End of sampling flag

This bit is set by hardware during the conversion, at the end of the sampling phase. It is cleared by software by programming it to '1'.

0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)

1: End of sampling phase reached

Bit 0 ADRDY: ADC ready

This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)

1: ADC is ready to start conversion

14.12.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	CCRD YIE	Res.	EOCAL IE	Res.	AWD3I E	AWD2I E	AWD1I E	Res.	Res.	OVR IE	EOS IE	EOC IE	EOSMP IE	ADRDY IE
		rw		rw		rw	rw	rw			rw	rw	rw	rw	rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 CCRDYIE : Channel Configuration Ready Interrupt enable

This bit is set and cleared by software to enable/disable the channel configuration ready interrupt.

0: Channel configuration ready interrupt disabled

1: Channel configuration ready interrupt enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCALIE : End of calibration interrupt enable

This bit is set and cleared by software to enable/disable the end of calibration interrupt.

0: End of calibration interrupt disabled

1: End of calibration interrupt enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 10 Reserved, must be kept at reset value.

Bit 9 AWD3IE : Analog watchdog 3 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 8 AWD2IE : Analog watchdog 2 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 7 AWD1IE : Analog watchdog 1 interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the overrun interrupt.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 3 EOSIE: End of conversion sequence interrupt enable

This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 2 EOCIE: End of conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of conversion interrupt.

0: EOC interrupt disabled

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 1 EOSMPIE: End of sampling flag interrupt enable

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 0 ADRDYIE: ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled.

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

14.12.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL	Res.	Res.	ADVR EGEN	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rs			rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ADSTP	Res.	ADSTA RT	ADDIS	ADEN
											rs		rs	rs	rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC.

It is cleared by hardware after calibration is complete.

0: Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.

Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).

Bits 30:29 Reserved, must be kept at reset value.

Bit 28 ADVREGEN: ADC Voltage Regulator Enable

This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after $t_{ADCVREG\_SETUP}$ .

It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is set to 0.

0: ADC voltage regulator disabled

1: ADC voltage regulator enabled

Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 27:5 Reserved, must be kept at reset value.

Bit 4 ADSTP: ADC stop conversion command

This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command.

0: No ADC stop conversion command ongoing

1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.

Note: Setting ADSTP to '1' is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)

Bit 3 Reserved, must be kept at reset value.

Bit 2 ADSTART: ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode (CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware.

0: No ADC conversion is ongoing.

1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.

Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC).

After writing to ADC_CHSELR register or changing CHSELROMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: No ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: Setting ADDIS to '1' is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)

Bit 0 ADEN: ADC enable command

This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

14.12.4 ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	AWD1CH[4:0]					Res.	Res.	AWD1EN	AWD1SGL	CHSEL RMOD	Res.	Res.	Res.	Res.	DISCEN
	rw	rw	rw	rw	rw			rw	rw	rw					rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AUTOFF	WAIT	CONT	OVRMOD	EXTEN[1:0]		Res.	EXTSEL[2:0]			ALIGN	RES[1:0]		SCAND IR	DMAC FG	DMAEN
rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWD1CH[4:0] : Analog watchdog channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input Channel 0 monitored by AWD

00001: ADC analog input Channel 1 monitored by AWD

.....

10001: ADC analog input Channel 17 monitored by AWD

10010: ADC analog input Channel 18 monitored by AWD

Others: Reserved

Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register.

The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bits 25:24 Reserved, must be kept at reset value.

Bit 23 AWD1EN : Analog watchdog enable

This bit is set and cleared by software.

0: Analog watchdog 1 disabled

1: Analog watchdog 1 enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 22 AWD1SGL : Enable the watchdog on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels

0: Analog watchdog 1 enabled on all channels

1: Analog watchdog 1 enabled on a single channel

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 21 CHSELROMOD : Mode selection of the ADC_CHSELR register

This bit is set and cleared by software to control the ADC_CHSELR feature:

0: Each bit of the ADC_CHSELR register enables an input

1: ADC_CHSELR register is able to sequence up to 8 channels

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELROMOD or SCANDIR), the value written to this bit is ignored.

Bits 20:17 Reserved, must be kept at reset value.

Bit 16 DISCEN : Discontinuous mode

This bit is set and cleared by software to enable/disable discontinuous mode.

0: Discontinuous mode disabled

1: Discontinuous mode enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 15 AUTOFF : Auto-off mode

This bit is set and cleared by software to enable/disable auto-off mode.

0: Auto-off mode disabled

1: Auto-off mode enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 14 WAIT : Wait conversion mode

This bit is set and cleared by software to enable/disable wait conversion mode.

0: Wait conversion mode off

1: Wait conversion mode on

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 13 CONT : Single / continuous conversion mode

This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 12 OVRMOD : Overrun management mode

This bit is set and cleared by software and configure the way data overruns are managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bits 11:10 EXTEN[1:0] : External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable the trigger.

00: Hardware trigger detection disabled (conversions can be started by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 9 Reserved, must be kept at reset value.

Bits 8:6 EXTSEL[2:0] : External trigger selection

These bits select the external event used to trigger the start of conversion (refer to Table 57: External triggers for details):

000: TRG0

001: TRG1

010: TRG2

011: TRG3

100: TRG4

101: TRG5

110: TRG6

111: TRG7

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 5 ALIGN : Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to Figure 40: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 294

0: Right alignment

1: Left alignment

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bits 4:3 RES[1:0] : Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12 bits

01: 10 bits

10: 8 bits

11: 6 bits

Note: The software is allowed to write these bits only when ADEN = 0.

Bit 2 SCANDIR: Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0.

0: Upward scan (from CHSEL0 to CHSEL18)

1: Backward scan (from CHSEL18 to CHSEL0)

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1.

0: DMA one shot mode selected

1: DMA circular mode selected

For more details, refer to Section 14.5.5: Managing converted data using the DMA on page 296

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bit 0 DMAEN: Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section 14.5.5: Managing converted data using the DMA on page 296 .

0: DMA disabled

1: DMA enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

14.12.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKMODE[1:0]	LFTRIG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	TOVS	OVSS[3:0]			OVSR[2:0]			Res.	OVSE
						rw	rw	rw	rw	rw	rw	rw	rw		rw

Bits 31:30 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:

00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)

01: PCLK/2 (Synchronous clock mode)

10: PCLK/4 (Synchronous clock mode)

11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must be 50% duty cycle)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bit 29 LFTRIG: Low frequency trigger mode enable

This bit is set and cleared by software.

0: Low Frequency Trigger Mode disabled

1: Low Frequency Trigger Mode enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).

Bits 28:10 Reserved, must be kept at reset value.

Bit 9 TOVS: Triggered Oversampling

This bit is set and cleared by software.

0: All oversampled conversions for a channel are done consecutively after a trigger

1: Each oversampled conversion for a channel needs a trigger

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 8:5 OVSS[3:0] : Oversampling shift

This bit is set and cleared by software.

0000: No shift

0001: Shift 1-bit

0010: Shift 2-bits

0011: Shift 3-bits

0100: Shift 4-bits

0101: Shift 5-bits

0110: Shift 6-bits

0111: Shift 7-bits

1000: Shift 8-bits

Others: Reserved

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 4:2 OVSR[2:0] : Oversampling ratio

This bit field defines the number of oversampling ratio.

000: 2x

001: 4x

010: 8x

011: 16x

100: 32x

101: 64x

110: 128x

111: 256x

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 1 Reserved, must be kept at reset value.

Bit 0 OVSE : Oversampler Enable

This bit is set and cleared by software.

0: Oversampler disabled

1: Oversampler enabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

14.12.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	SMPSE L18	SMPSE L17	SMPSE L16	SMPSE L15	SMPSE L14	SMPSE L13	SMPSE L12	SMPSE L11	SMPSE L10	SMPSE L9	SMPSE L8
					rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMPSE L7	SMPSE L6	SMPSE L5	SMPSE L4	SMPSE L3	SMPSE L2	SMPSE L1	SMPSE L0	Res.	SMP2[2:0]			Res.	SMP1[2:0]
rw	rw	rw	rw	rw	rw	rw	rw		rw	rw	rw		rw	rw	rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:8 SMPSEL[18:0] Channel-x sampling time selection

These bits are written by software to define which sampling time is used.
0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 SMP2[2:0] : Sampling time selection 2

These bits are written by software to select the sampling time that applies to all channels.

000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 SMP1[2:0] : Sampling time selection 1

These bits are written by software to select the sampling time that applies to all channels.

000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

14.12.7 ADC watchdog threshold register (ADC_AWD1TR)

Address offset: 0x20

Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT1[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	LT1[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0] : Analog watchdog 1 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 300 .

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT1[11:0] : Analog watchdog 1 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 300 .

14.12.8 ADC watchdog threshold register (ADC_AWD2TR)

Address offset: 0x24

Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT2[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	LT2[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT2[11:0] : Analog watchdog 2 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 300 .

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT2[11:0] : Analog watchdog 2 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 300 .

14.12.9 ADC channel selection register [alternate] (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

The same register can be used in two different modes:

– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in ADC_CFGR1). Refer to next section.

CHSELRMOD = 0 in ADC_CFGR1:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CHSEL 18	CHSEL 17	CHSEL 16
													rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CHSEL 15	CHSEL 14	CHSEL 13	CHSEL 12	CHSEL 11	CHSEL 10	CHSEL 9	CHSEL 8	CHSEL 7	CHSEL 6	CHSEL 5	CHSEL 4	CHSEL 3	CHSEL 2	CHSEL 1	CHSEL 0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 CHSEL[18:0] : Channel-x selection

These bits are written by software and define which channels are part of the sequence of channels to be converted.

0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.

14.12.10 ADC channel selection register [alternate] (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

The same register can be used in two different modes:

– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to the current previous section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in ADC_CFGR1). Refer to this section.

CHSELRMOD = 1 in ADC_CFGR1:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SQ8[3:0]				SQ7[3:0]				SQ6[3:0]				SQ5[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ4[3:0]				SQ3[3:0]				SQ2[3:0]				SQ1[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 SQ8[3:0]: 8th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

0000: CH0

0001: CH1

...

1100: CH12

1101: CH13

1110: CH14

1111: No channel selected (End of sequence)

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 27:24 SQ7[3:0]: 7th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 23:20 SQ6[3:0]: 6th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 19:16 SQ5[3:0] : 5th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 15:12 SQ4[3:0] : 4th conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 11:8 SQ3[3:0] : 3rd conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 7:4 SQ2[3:0] : 2nd conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 3:0 SQ1[3:0] : 1st conversion of the sequence

These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence.

When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored.

Refer to SQ8[3:0] for a definition of channel selection.

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

14.12.11 ADC watchdog threshold register (ADC_AWD3TR)

Address offset: 0x2C

Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT3[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	LT3[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT3[11:0] : Analog watchdog 3 higher threshold

These bits are written by software to define the higher threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 300 .

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT3[11:0] : Analog watchdog 3 lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 14.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR) on page 300 .

14.12.12 ADC data register (ADC_DR)

Address offset: 0x40

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0] : Converted data

These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 40: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 294 .

Just after a calibration is complete, DATA[6:0] contains the calibration factor.

14.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)

Address offset: 0xA0

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD2CH18	AWD2CH17	AWD2CH16
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH15	AWD2CH14	AWD2CH13	AWD2CH12	AWD2CH11	AWD2CH10	AWD2CH9	AWD2CH8	AWD2CH7	AWD2CH6	AWD2CH5	AWD2CH4	AWD2CH3	AWD2CH2	AWD2CH1	AWD2CH0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0] : Analog watchdog channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2).

0: ADC analog channel-x is not monitored by AWD2

1: ADC analog channel-x is monitored by AWD2

Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

14.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)

Address offset: 0xA4

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD3CH18	AWD3CH17	AWD3CH16
													rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH15	AWD3CH14	AWD3CH13	AWD3CH12	AWD3CH11	AWD3CH10	AWD3CH9	AWD3CH8	AWD3CH7	AWD3CH6	AWD3CH5	AWD3CH4	AWD3CH3	AWD3CH2	AWD3CH1	AWD3CH0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0] : Analog watchdog channel selection

These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3).

0: ADC analog channel-x is not monitored by AWD3

1: ADC analog channel-x is monitored by AWD3

Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

14.12.15 ADC Calibration factor (ADC_CALFACT)

Address offset: 0xB4

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CALFACT[6:0]
									rw	rw	rw	rw	rw	rw	rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT[6:0] : Calibration factor

These bits are written by hardware or by software.

– Once a calibration is complete, they are updated by hardware with the calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.

Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection.

14.12.16 ADC common configuration register (ADC_CCR)

Address offset: 0x308

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	VBAT EN	TSEN	VREF EN	PRESC[3:0]				Res.	Res.
							rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 VBATEN : V _BATenable

This bit is set and cleared by software to enable/disable the V _BATchannel.

0: V _BATchannel disabled

1: V _BATchannel enabled

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)

Bit 23 TSEN : Temperature sensor enable

This bit is set and cleared by software to enable/disable the temperature sensor.

0: Temperature sensor disabled

1: Temperature sensor enabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 22 VREFEN : V _REFINTenable

This bit is set and cleared by software to enable/disable the V _REFINT.

0: V _REFINTdisabled

1: V _REFINTenabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 21:18 PRESC[3:0] : ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADC.

0000: input ADC clock not divided

0001: input ADC clock divided by 2

0010: input ADC clock divided by 4

0011: input ADC clock divided by 6

0100: input ADC clock divided by 8

0101: input ADC clock divided by 10

0110: input ADC clock divided by 12

0111: input ADC clock divided by 16

1000: input ADC clock divided by 32

1001: input ADC clock divided by 64

1010: input ADC clock divided by 128

1011: input ADC clock divided by 256

Other: Reserved

Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 17:0 Reserved, must be kept at reset value.

14.13 ADC register map

The following table summarizes the ADC registers.

Table 65. ADC register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Offset	Register	0x00	ADC_ISR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CCRDY	Res.	EOCAL	Res.	AWD3	AWD2	AWD1	Res.	Res.	OVR	EOS	EOC	EOSMP	ADRDY
Reset value		0x00																		0		0		0	0	0			0	0	0	0	0
0x04	ADC_IER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CCRDYIE	Res.	EOCALIE	Res.	AWD3IE	AWD2IE	AWD1IE	Res.	Res.	OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x04	Reset value																			0		0		0	0	0			0	0	0	0	0
0x08	ADC_CR	ADCAL	Res.	Res.	ADVREGEN	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ADSTP	Res.	ADSTART	ADDIS	ADEN
0x08	Reset value	0			0																								0		0	0	0
0x0C	ADC_CFGR1	Res.	AWDCH[4:0]					Res.	Res.	AWD1EN	AWD1SGL	CHSELRMOD	Res.	Res.	Res.	Res.	DISCEN	AUTOFF	WAIT	CONT	OVRMOD	EXTEN[1:0]		Res.	EXTSEL [2:0]			ALIGN	RES [1:0]		SCANDIR	DMACFG	DMAEN
0x0C	Reset value		0	0	0	0	0			0	0	0					0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0
0x10	ADC_CFGR2	CKMODE[1:0]		LFTRIG		Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TOVS	OVSS[3:0]				OVSR[2:0]				Res.	OVSE
0x10	Reset value	0	0	0																				0	0	0	0	0	0	0	0		0
0x14	ADC_SMPR	Res.	Res.	Res.	Res.	Res.	SMPSEL18	SMPSEL17	SMPSEL16	SMPSEL15	SMPSEL14	SMPSEL13	SMPSEL12	SMPSEL11	SMPSEL10	SMPSEL9	SMPSEL8	SMPSEL7	SMPSEL6	SMPSEL5	SMPSEL4	SMPSEL3	SMPSEL2	SMPSEL1	SMPSEL0	Res.	SMP2 [2:0]			Res.	SMP1 [2:0]
0x14	Reset value						0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0		0	0	0
0x18	Reserved
0x1C	Reserved
0x20	ADC_AWD1TR	Res.	Res.	Res.	Res.	HT1[11:0]												Res.	Res.	Res.	Res.	LT1[11:0]
0x20	Reset value					1	1	1	1	1	1	1	1	1	1	1	1					0	0	0	0	0	0	0	0	0	0	0	0
0x24	ADC_AWD2TR	Res.	Res.	Res.	Res.	HT2[11:0]												Res.	Res.	Res.	Res.	LT2[11:0]
0x24	Reset value					1	1	1	1	1	1	1	1	1	1	1	1					0	0	0	0	0	0	0	0	0	0	0	0
0x28	ADC_CHSELR (CHSELRMOD=0)	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CHSEL18	CHSEL17	CHSEL16	CHSEL15	CHSEL14	CHSEL13	CHSEL12	CHSEL11	CHSEL10	CHSEL9	CHSEL8	CHSEL7	CHSEL6	CHSEL5	CHSEL4	CHSEL3	CHSEL2	CHSEL1	CHSEL0
0x28	Reset value														0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	ADC_CHSELR (CHSELRMOD=1)	SQ8[3:0]				SQ7[3:0]				SQ6[3:0]				SQ5[3:0]				SQ4[3:0]				SQ3[3:0]				SQ2[3:0]				SQ1[3:0]
0x28	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	ADC_AWD3TR	Res.	Res.	Res.	Res.	HT3[11:0]												Res.	Res.	Res.	Res.	LT3[11:0]
0x2C	Reset value					1	1	1	1	1	1	1	1	1	1	1	1					0	0	0	0	0	0	0	0	0	0	0	0

Table 65. ADC register map and reset values (continued)

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Offset	Register	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
0x30 0x34 0x38 0x3C	Reserved	Reserved
0x40	ADC_DR	DATA[15:0]
0x40	Reset value	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
...	Reserved	Reserved
0xA0	ADC_AWD2CR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD2CH18	AWD2CH17	AWD2CH16	AWD2CH15	AWD2CH14	AWD2CH13	AWD2CH12	AWD2CH11	AWD2CH10	AWD2CH9	AWD2CH8	AWD2CH7	AWD2CH6	AWD2CH5	AWD2CH4	AWD2CH3	AWD2CH2	AWD2CH1	AWD2CH0
0xA0	Reset value	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xA4	ADC_AWD3CR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD3CH18	AWD3CH17	AWD3CH16	AWD3CH15	AWD3CH14	AWD3CH13	AWD3CH12	AWD3CH11	AWD3CH10	AWD3CH9	AWD3CH8	AWD3CH7	AWD3CH6	AWD3CH5	AWD3CH4	AWD3CH3	AWD3CH2	AWD3CH1	AWD3CH0
0xA4	Reset value	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
...	Reserved	Reserved
0xB4	ADC_CALFACT	CALFACT[6:0]
0xB4	Reset value	0 0 0 0 0 0 0
...	Reserved	Reserved
0x308	ADC_CCR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
0x308	Reset value	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 44 for the register boundary addresses.

14. Analog-to-digital converter (ADC)

14.1 Introduction

14.2 ADC main features

14.3 ADC functional description

14.3.1 ADC pins and internal signals

14.3.2 ADC voltage regulator (ADVREGEN)

Analog reference from the power control unit

ADC Voltage regulator enable sequence

ADC voltage regulator disable sequence

14.3.3 Calibration (ADCAL)

Software calibration procedure

14.3.5 ADC clock (CKMODE, PRESC[3:0])

14.3.6 ADC connectivity

14.3.7 Configuring the ADC

14.3.8 Channel selection (CHSEL, SCANDIR, CHSELROMOD)

Temperature sensor, \( V_{REFINT} \) and \( V_{BAT} \) internal channels

14.3.9 Programmable sampling time (SMPx[2:0])

14.3.10 Single conversion mode (CONT = 0)

14.3.11 Continuous conversion mode (CONT = 1)

14.3.12 Starting conversions (ADSTART)

14.3.13 Timings

14.3.14 Stopping an ongoing conversion (ADSTP)

14.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)

14.4.1 Discontinuous mode (DISCEN)

14.4.2 Programmable resolution (RES) - Fast conversion mode

14.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

14.4.4 End of conversion sequence (EOS flag)

14.4.6 Low frequency trigger mode

14.5 Data management

14.5.1 Data register and data alignment (ADC_DR, ALIGN)

14.5.2 ADC overrun (OVR, OVRMOD)

14.5.3 Managing a sequence of data converted without using the DMA

14.5.4 Managing converted data without using the DMA without overrun

14.5.5 Managing converted data using the DMA

DMA one shot mode (DMACFG = 0)

DMA circular mode (DMACFG = 1)

14.6 Low-power features

14.6.1 Wait mode conversion

14.6.2 Auto-off mode (AUTOFF)

14.7 Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR)

14.7.1 Description of analog watchdog 1

14.7.2 Description of analog watchdog 2 and 3

14.7.3 ADC_AWDx_OUT output signal generation

14.7.4 Analog Watchdog threshold control

14.8 Oversampler

14.8.1 ADC operating modes supported when oversampling

14.8.2 Analog watchdog

14.8.3 Triggered mode

14.9 Temperature sensor and internal reference voltage

Main features

Reading the temperature

Calculating the actual \( V_{REF+} \) voltage using the internal reference voltage

Converting a supply-relative ADC measurement to an absolute voltage value

14.10 Battery voltage monitoring

14.11 ADC interrupts

14.12 ADC registers

14.12.1 ADC interrupt and status register (ADC_ISR)

14.12.2 ADC interrupt enable register (ADC_IER)

14.12.3 ADC control register (ADC_CR)

14.12.4 ADC configuration register 1 (ADC_CFGR1)

14.12.5 ADC configuration register 2 (ADC_CFGR2)

Bits 31:30 CKMODE[1:0]: ADC clock mode

Bit 29 LFTRIG: Low frequency trigger mode enable

Bits 28:10 Reserved, must be kept at reset value.

Bit 9 TOVS: Triggered Oversampling

14.12.6 ADC sampling time register (ADC_SMPR)

14.12.7 ADC watchdog threshold register (ADC_AWD1TR)

14.12.8 ADC watchdog threshold register (ADC_AWD2TR)

14.12.9 ADC channel selection register [alternate] (ADC_CHSELR)

CHSELRMOD = 0 in ADC_CFGR1:

14.12.10 ADC channel selection register [alternate] (ADC_CHSELR)

CHSELRMOD = 1 in ADC_CFGR1:

Bits 31:28 SQ8[3:0]: 8th conversion of the sequence

Bits 27:24 SQ7[3:0]: 7th conversion of the sequence

Bits 23:20 SQ6[3:0]: 6th conversion of the sequence

14.12.11 ADC watchdog threshold register (ADC_AWD3TR)

14.12.12 ADC data register (ADC_DR)

14.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)

14.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)

14.12.15 ADC Calibration factor (ADC_CALFACT)

Temperature sensor, $V_{REFINT}$ and $V_{BAT}$ internal channels

Calculating the actual $V_{REF+}$ voltage using the internal reference voltage