12. Extended interrupt and event controller (EXTI)

The Extended interrupt and event controller (EXTI) manages the CPU and system wakeup through configurable and direct event inputs (lines). It provides wakeup requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wakeup requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can also be used in Run modes.

The EXTI also includes the EXTI I/O port mux.

12.1 EXTI main features

The EXTI main features are the following:

• System wakeup upon event on any input
• Wakeup flag and CPU interrupt generation for events not having a wakeup flag in their source peripheral
• Configurable events (from I/Os, peripherals not having an associated interrupt pending status bit, or peripherals generating a pulse)
- – Selectable active trigger edge
- – Independent rising and falling edge interrupt pending status bits
- – Individual interrupt and event generation mask, used for conditioning the CPU wakeup, interrupt and event generation
- – SW trigger possibility
• Direct events (from peripherals having an associated flag and interrupt pending status bit)
- – Fixed rising edge active trigger
- – No interrupt pending status bit in the EXTI
- – Individual interrupt and event generation mask for conditioning the CPU wakeup and event generation
- – No SW trigger possibility
• I/O port selector

12.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger block, the masking block, and EXTI mux as shown in Figure 22 .

The register block contains all the EXTI registers.

The event input trigger block provides an event input edge trigger logic.

The masking block provides the event input distribution to the different wakeup, interrupt and event outputs, and the masking of these.

The EXTI mux provides the I/O port selection on to the EXTI event signal.

Figure 22. EXTI block diagram

The diagram illustrates the internal architecture of the EXTI block. On the left, external components include GPIO (connected via IOPort), Peripherals (connected via Wakeup, Direct event(x), and Interrupt signals), and an AHB interface (connected to Registers). The central part of the block contains Registers, an EXTI mux, an Event Trigger, and a Masking unit. The EXTI mux receives inputs from GPIO IOPort and Configurable event(15:0), and its output goes to the Event Trigger. Peripherals provide Direct event(x) and Interrupt signals to the Event Trigger. The Event Trigger's output goes to the Masking unit. The Masking unit has several output signals: exti[15:0] (To interconnect), sys_wakeup, c_wakeup, it_exti_per(y)*, c_evt_exti, and c_evt_rst. The c_evt_exti signal goes to a Pulse block, which also receives c_evt_rst. The Pulse block's output, c_event, goes to the CPU via the rxev signal. The CPU also receives c_fclk from an EVG block. The EVG block receives c_fclk from the CPU and provides c_event and c_evt_rst to the CPU. The PWR block receives sys_wakeup and c_wakeup signals. A note at the bottom left states: "* it_exti_per(y) are only available for configurable events (y)". The code MS44733V2 is at the bottom right.

EXTI block diagram showing connections to GPIO, Peripherals, Registers, Event Trigger, Masking, PWR, and CPU. It includes signals like AHB interface, hclk, IOPort, Configurable event(15:0), Direct event(x), Interrupt, exti[15:0], sys_wakeup, c_wakeup, it_exti_per(y)*, c_evt_exti, c_evt_rst, Pulse, EVG, c_event, c_fclk, and rxev.

Table 46. EXTI signal overview

Signal name	I/O	Description
AHB interface	I/O	EXTI register bus interface. When one event is configured to allow security, the AHB interface support secure accesses
hclk	I	AHB bus clock and EXTI system clock
Configurable event(y)	I	Asynchronous wakeup events from peripherals that do not have an associated interrupt and flag in the peripheral
Direct event(x)	I	Synchronous and asynchronous wakeup events from peripherals having an associated interrupt and flag in the peripheral
IOPort(n)	I	GPIO ports[15:0]
exti[15:0]	O	EXTI output port to trigger other IPs
it_exti_per (y)	O	Interrupts to the CPU associated with configurable event (y)
c_evt_exti	O	High-level sensitive event output for CPU synchronous to hclk
c_evt_rst	I	Asynchronous reset input to clear c_evt_exti
sys_wakeup	O	Asynchronous system wakeup request to PWR for ck_sys and hclk
c_wakeup	O	Wakeup request to PWR for CPU, synchronous to hclk

Table 47. EVG pin overview

Pin name	I/O	Description
c_fclk	I	CPU free-running clock
c_evt_in	I	High-level sensitive event input from EXTI, asynchronous to CPU clock
c_event	O	Event pulse, synchronous to CPU clock
c_evt_rst	O	Event reset signal, synchronous to CPU clock

12.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wakeup or interrupt events when the system is in Stop mode are connected to the EXTI.

• Peripheral wakeup signals that generate a pulse or that do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable line. For these events the EXTI provides a status pending bit which requires to be cleared. It is the EXTI interrupt associated with the status bit that interrupts the CPU.
• Peripheral interrupt and wakeup signals that have a status bit in the peripheral which requires to be cleared in the peripheral, are connected to an EXTI direct line. There is no status pending bit within the EXTI. The interrupt or wakeup is cleared by the CPU in the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
• All GPIO ports input to the EXTI multiplexer, allowing to select a port to wake up the system via a configurable event.

The EXTI configurable event interrupts are connected to the NVIC(a) of the CPU.

The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.

The EXTI CPU wakeup signals are connected to the PWR block, and are used to wake up the system and CPU sub-system bus clocks.

12.3 EXTI functional description

Depending on the EXTI line type and wakeup target(s), different logic implementations are used. The applicable features and control or status registers are:

• rising and falling edge event enable through
- – EXTI rising trigger selection register (EXTI_RTSR1)
- – EXTI falling trigger selection register 1 (EXTI_FTSR1)
• software trigger through EXTI software interrupt event register 1 (EXTI_SWIER1)
• pending interrupt flagging through
- – EXTI rising edge pending register 1 (EXTI_RPR1)
- – EXTI falling edge pending register 1 (EXTI_FPR1)
- – EXTI external interrupt selection register (EXTI_EXTICRx)
• CPU wakeup and interrupt enable through
- – EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)
• CPU wakeup and event enable through
- – EXTI CPU wakeup with event mask register (EXTI_EMR1)

Table 48. EXTI event input configurations and register control

Event input type	Logic implementation	EXTI_RTSR1	EXTI_FTSR1	EXTI_SWIER1	EXTI_R/FPR1	EXTI_IMR1	EXTI_EMR1
Configurable	Configurable event input wakeup logic	x	x	x	x	x	x
Direct	Direct event input wakeup logic	-	-	-	-	x	x

12.3.1 EXTI configurable event input wakeup

Figure 23 is a detailed representation of the logic associated with configurable event inputs which wake up the CPU sub-system bus clocks and generated an EXTI pending flag and interrupt to the CPU and or a CPU wakeup event.

Figure 23. Configurable event trigger logic CPU wakeup

Figure 23: Configurable event trigger logic CPU wakeup. This block diagram illustrates the internal logic of the EXTI for configurable events. On the left, an 'AHB interface' and 'hclk' clock are connected to a 'Peripheral interface' block. This block contains several registers: 'Falling trigger selection register', 'Rising trigger selection register', 'Software interrupt event register', 'CPU Event mask register', 'CPU Interrupt mask register', and 'Pending request register'. A 'Configurable Event input(y)' enters from the left and is processed by an 'Asynchronous Edge detection circuit' which is reset by 'rst'. The output of this circuit goes through a 'Delay' block and a 'Rising Edge detect Pulse generator' (also reset by 'rst'). These signals are then processed by a series of AND and OR gates. The 'Software interrupt event register' and 'CPU Event mask register' are used to filter these signals. The output of the logic is 'CPU Event(y)', which is OR-ed with 'Other CPU Events(x,y)' to produce 'it_exti_per(y)'. This signal is also processed by an 'EVG' (Event Generator) block containing a 'CPU Rising Edge detect Pulse generator' (reset by 'c_evt_rst') to produce 'c_event'. Another path from the logic goes through a 'Sync' block to produce 'c_wakeup', which is OR-ed with 'Other Wakeups' to produce 'sys_wakeup'. The 'EVG' block also receives 'ck_fclk_c' and 'c_evt_exti' as inputs. The diagram is labeled 'EXTI' at the bottom left and 'MS46537V1' at the bottom right.

The software interrupt event register allows triggering configurable events by software, writing the corresponding register bit, irrespective of the edge selection setting.

The rising edge and falling edge selection registers allow to enable and select the configurable event active trigger edge or both edges.

The CPU has its dedicated interrupt mask register and a dedicated event mask registers. The enabled event allows generating an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The event pending registers (EXTI_RPR1 and EXTI_FPR1) is not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers, shared by the CPU. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to the CPU. The configurable event interrupts need to be acknowledged by software in the EXTI_RPR1 and/or EXTI_FPR1 registers.

When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees the wakeup of the EXTI hclk clock before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request can be cleared by the CPU. The system cannot enter low-power modes as long as an interrupt pending request is active.

12.3.2 EXTI direct event input wakeup

Figure 24 is a detailed representation of the logic associated with direct event inputs waking up the system.

The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the system and CPU sub-system clocks and may generate a CPU wakeup event. The peripheral synchronous interrupt, associated with the direct wakeup event wakes up the CPU.

The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU. The CPU event may occur before the interrupt flag of the associated peripheral is set.

Figure 24. Direct event trigger logic CPU wakeup

The diagram illustrates the internal logic of the EXTI direct event trigger. It starts with 'Direct Event input(x)' entering a 'Delay' block and an 'Asynchronous Rising Edge detect circuit'. The 'Delay' block output goes to an AND gate, which also receives inputs from 'CPU Interrupt mask register' and 'CPU Event mask register' via a 'Peripheral interface'. The output of this AND gate is 'CPU Event(x)'. The 'Asynchronous Rising Edge detect circuit' output goes to an OR gate, which also receives 'Other CPU Events(x,y)'. The output of this OR gate is 'CPU Wakeup(x)'. Both 'CPU Event(x)' and 'CPU Wakeup(x)' enter a 'Same circuit for Configurable and Direct events' block. 'CPU Event(x)' goes through a 'Rising Edge detect' block to produce 'c_evt_rst'. 'CPU Wakeup(x)' goes through a 'Synch' block to produce 'c_wakeup'. 'Other CPU Events(x,y)' and 'Other CPU Wakeups' are combined in an OR gate to produce 'sys_wakeup'. 'c_evt_rst' and 'c_evt_exti' (from an EVG block) enter a 'CPU Rising Edge detect Pulse generator' to produce the final 'c_event' output. Clock signals 'hclk' and 'ck_fclk_c' are shown throughout the diagram.

Figure 24: Direct event trigger logic CPU wakeup block diagram. The diagram shows the logic for generating CPU events and wakeups from EXTI direct events. Inputs include AHB interface (hclk), Direct Event input(x), and hclk. The logic consists of a Delay block, an Asynchronous Rising Edge detect circuit, a Falling Edge detect Pulse generator, and a 'Same circuit for Configurable and Direct events' block containing a Rising Edge detect. Outputs include CPU Event(x), Other CPU Events(x,y), CPU Wakeup(x), Other CPU Wakeups, c_evt_rst, c_evt_exti, c_wakeup, sys_wakeup, and c_event. The EVG (CPU Rising Edge detect Pulse generator) is also shown.

12.3.3 EXTI mux

The EXTI mux allows selecting GPIOs as interrupts and wakeup. The GPIOs are connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The selection of GPIO port as EXTI mux output is controlled through the EXTI external interrupt selection register (EXTI_EXTICRx) register.

Figure 25. EXTI GPIO mux

The diagram shows three separate multiplexers for EXTI0, EXTI1, and EXTI15. Each multiplexer has multiple input lines representing different GPIO pins. For EXTI0, the inputs are PA0, PB0, PC0, and Px0. For EXTI1, the inputs are PA1, PB1, PC1, and Px1. For EXTI15, the inputs are PA15, PB15, PC15, and Px15. Each multiplexer is controlled by a configuration register: EXTI_EXTICR1.EXTI0 for EXTI0, EXTI_EXTICR1.EXTI1 for EXTI1, and EXTI_EXTICR4.EXTI15 for EXTI15. The output of each multiplexer is labeled EXTI0, EXTI1, and EXTI15 respectively. A dashed line connects the output of the EXTI1 multiplexer to the input of the EXTI15 multiplexer.

Figure 25: EXTI GPIO mux block diagram. It shows three multiplexers for EXTI0, EXTI1, and EXTI15. Each multiplexer selects between multiple GPIO pins (e.g., PA0, PB0, PC0, Px0 for EXTI0) based on configuration registers (EXTI_EXTICR1.EXTI0, EXTI_EXTICR1.EXTI1, EXTI_EXTICR4.EXTI15). The outputs are labeled EXTI0, EXTI1, and EXTI15.

The EXTIs mux outputs are available as output signals from the EXTI, to trigger other functional blocks. The EXTI mux outputs are available independently of mask setting through the EXTI_IMR and EXTI_EMR registers.

The EXTI lines (event inputs) are connected as shown in the following table.

Table 49. EXTI line connections

EXTI line	Line source	Line type
0-15	GPIO	Configurable
16	Reserved	-
17	Reserved	-
18	Reserved	-
19	RTC	Direct
20	Reserved	-
21	TAMP	Direct
22	I2C2 wakeup	Direct
23	I2C1 wakeup	Direct
24	USART3 wakeup	Direct
25	USART1 wakeup	Direct
26	USART2 wakeup	Direct
27	Reserved	-
28	Reserved	-
29	Reserved	-
30	Reserved	-
31	LSE_CSS	Direct
32	Reserved	-
33	Reserved	-

12.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wakeup event. The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the generation of a CPU wakeup is conditioned by the CPU interrupt mask and CPU event mask.

Table 50. Masking functionality

CPU interrupt enable EXTI_IMR.IMn	CPU event enable EXTI_EMR.EMn	Configurable event inputs EXTI_RPR.RPIFn EXTI_FPR.FPIFn	exti(n) interrupt ⁽¹⁾	CPU event	CPU wakeup
0	0	No	Masked	Masked	Masked
0	1	No	Masked	Yes	Yes
1	0	Status latched	Yes	Masked	Yes ⁽²⁾
1	1	Status latched	Yes	Yes	Yes

1. The single exti(n) interrupt goes to the CPU. If no interrupt is required for CPU, the exti(n) interrupt must be masked in the CPU NVIC.

2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.

For configurable event inputs, upon an edge on the event input, an event request is generated if that edge (rising or/and falling) is enabled. When the associated CPU interrupt is unmasked, the corresponding RPIFn and/or FPIFn bit is/are set in the EXTI_RPR or/and EXTI_FPR register, waking up the CPU subsystem and activating CPU interrupt signal. The RPIFn and/or FPIFn pending bit is cleared by writing 1 to it, which clears the CPU interrupt request.

For direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI. When the associated CPU interrupt is unmasked, the corresponding CPU subsystem is woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.

The CPU event must be unmasked to generate an event. Upon an enabled edge occurring on an event input, a CPU event pulse is generated. There is no event pending bit.

For the configurable event inputs, the software can generate an event request by setting the corresponding bit of the software interrupt/event register EXTI_SWIER1, which has the effect of a rising edge on the event input. The pending rising edge event flag is set in the EXTI_RPR1 register, irrespective of the EXTI_RTSR1 register setting.

12.5 EXTI registers

The EXTI register map is divided in the following sections:

Table 51. EXTI register map sections

Address	Description
0x000 - 0x01C	General configurable event [31:0] configuration
0x060 - 0x06C	EXTI I/O port multiplexer
0x080 - 0x0BC	CPU input event configuration

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

12.5.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RTx : Rising trigger event configuration bit of configurable line x (x = 15 to 0) ⁽¹⁾

Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.
0: Disable
1: Enable

1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger.

12.5.2 EXTI falling trigger selection register 1 (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 FTx : Falling trigger event configuration bit of configurable line x (x = 15 to 0) ⁽¹⁾.

Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0: Disable
1: Enable

1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger.

12.5.3 EXTI software interrupt event register 1 (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SWI x : Software rising edge event trigger on line x ( x = 15 to 0)

Setting of any bit by software triggers a rising edge event on the corresponding line x , resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0.

0: No effect

1: Rising edge event generated on the corresponding line, followed by an interrupt

12.5.4 EXTI rising edge pending register 1 (EXTI_RPR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RPIF x : Rising edge event pending for configurable line x ( x = 15 to 0)

Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

12.5.5 EXTI falling edge pending register 1 (EXTI_FPR1)

Address offset: 0x010

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 FPFx : Falling edge event pending for configurable line x (x = 15 to 0)

Each bit is set upon a falling edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

12.5.6 EXTI external interrupt selection register (EXTI_EXTICRx)

Address offset: $$ 0x060 + 0x4 * (x - 1) $$ , (x = 1 to 4)

Reset value: 0x0000 0000

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTIm+3[7:0]								EXTIm+2[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTIm+1[7:0]								EXTIm[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 EXTIm+3[7:0] : EXTIm+3 GPIO port selection ( $$ m = 4 * (x - 1) $$ )

These bits are written by software to select the source input for EXTIm+3 external interrupt.

0x00: PA[m+3] pin

0x01: PB[m+3] pin

0x02: PC[m+3] pin

0x03: PD[m+3] pin

0x04: reserved

0x05: PF[m+3] pin

Others reserved

Bits 23:16 EXTIm+2[7:0] : EXTIm+2 GPIO port selection ( $$ m = 4 * (x - 1) $$ )

These bits are written by software to select the source input for EXTIm+2 external interrupt.

0x00: PA[m+2] pin

0x01: PB[m+2] pin

0x02: PC[m+2] pin

0x03: PD[m+2] pin

0x04: reserved

0x05: PF[m+2] pin

Others reserved

Bits 15:8 EXTIm+1[7:0] : EXTIm+1 GPIO port selection ( $$ m = 4 * (x - 1) $$ )

These bits are written by software to select the source input for EXTIm+1 external interrupt.

0x00: PA[m+1] pin

0x01: PB[m+1] pin

0x02: PC[m+1] pin

0x03: PD[m+1] pin

0x04: reserved

0x05: PF[m+1] pin

Others reserved

Bits 7:0 EXTIm[7:0] : EXTIm GPIO port selection ( $$ m = 4 * (x - 1) $$ )

These bits are written by software to select the source input for EXTIm external interrupt.

0x00: PA[m] pin

0x01: PB[m] pin

0x02: PC[m] pin

0x03: PD[m] pin

0x04: reserved

0x05: PF[m] pin

Others reserved

12.5.7 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)

Address offset: 0x080 (EXTI_IMR1)

Reset value: 0xFFF8 0000

Contains register bits for configurable events and direct events.

The reset value is set such as to, by default, enable interrupt from direct lines, and disable interrupt from configurable lines.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM31	Res.	Res.	Res.	Res.	IM26	IM25	IM24	IM23	IM22	IM21	Res.	IM19	Res.	Res.	Res.
rw					rw	rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 IM31 : CPU wakeup with interrupt mask on line 31

Setting/clearing this bit unmask/mask the CPU wakeup with interrupt, by an event on the corresponding line.

0: wakeup with interrupt masked

1: wakeup with interrupt unmasked

Bits 30:27 Reserved, must be kept at reset value.

Bits 26:21 IMx : CPU wakeup with interrupt mask on line x ( $$ x = 26 $$ to 21)

Setting/clearing each bit unmask/mask the CPU wakeup with interrupt, by an event on the corresponding line.

0: wakeup with interrupt masked

1: wakeup with interrupt unmasked

The IM24 and IM22 bits are only available in STM32G0B0xx. They are reserved in STM32G030xx as well as STM32G050xx as well as STM32G070xx.

Bit 20 Reserved, must be kept at reset value.

Bit 19 IM19 : CPU wakeup with interrupt mask on line 19

Setting/clearing this bit unmask/masks the CPU wakeup with interrupt, by an event on the corresponding line.

0: wakeup with interrupt masked

1: wakeup with interrupt unmasked

Bits 18:16 Reserved, must be kept at reset value.

Bits 15:0 IMx : CPU wakeup with interrupt mask on line x (x = 15 to 0)

Setting/clearing each bit unmask/masks the CPU wakeup with interrupt, by an event on the corresponding line.

0: wakeup with interrupt masked

1: wakeup with interrupt unmasked

12.5.8 EXTI CPU wakeup with event mask register (EXTI_EMR1)

Address offset: 0x084 (EXTI_EMR1)

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EM31	Res.	Res.	Res.	Res.	EM26	EM25	EM24	EM23	EM22	EM21	Res.	EM19	Res.	Res.	Res.
rw					rw	rw	rw	rw	rw	rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 EM31 CPU wakeup with event generation mask on line 31

Setting/clearing this bit unmask/masks the CPU wakeup with event generation on the corresponding line.

0: wakeup with event generation masked

1: wakeup with event generation unmasked

Bit 30:27 Reserved, must be kept at reset value.

Bits 26:21 EMx : CPU wakeup with event generation mask on line x (x = 26 to 21)

Setting/clearing each bit unmask/masks the CPU wakeup with event generation on the corresponding line.

0: wakeup with event generation masked

1: wakeup with event generation unmasked

The EM24 and EM22 bits are only available in STM32G0B0xx. They are reserved in STM32G030xx as well as STM32G050xx as well as STM32G070xx.

Bit 20 Reserved, must be kept at reset value.

Bit 19 EM19 CPU wakeup with event generation mask on line 19

Setting/clearing this bit unmasks/masks the CPU wakeup with event generation on the corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked

Bits 18:16 Reserved, must be kept at reset value.

Bits 15:0 EMx : CPU wakeup with event generation mask on line x ( x = 15 to 0)

Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked

12.5.9 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 52. EXTI controller register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	EXTI_RTSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RT[15:0]
0x000	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x004	EXTI_FTSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FT[15:0]
0x004	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x008	EXTI_SWIER1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWI[15:0]
0x008	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x00C	EXTI_RPR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RPIF[15:0]
0x00C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x010	EXTI_FPR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FPIF[16:0]
0x010	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x014-0x05C	Reserved	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
0x060	EXTI_EXTICR1	EXTI3[7:0]								EXTI2[7:0]								EXTI1[7:0]								EXTI0[7:0]
0x060	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x064	EXTI_EXTICR2	EXTI7[7:0]								EXTI6[7:0]								EXTI5[7:0]								EXTI4[7:0]
0x064	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x068	EXTI_EXTICR3	EXTI11[7:0]								EXTI10[7:0]								EXTI9[7:0]								EXTI8[7:0]
0x068	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x06C	EXTI_EXTICR4	EXTI15[7:0]								EXTI14[7:0]								EXTI13[7:0]								EXTI12[7:0]
0x06C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x070-0x07C	Reserved	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Table 52. EXTI controller register map and reset values (continued)

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x080	EXTI_IMR1	IM31	Res.	Res.	Res.	Res.	IM26	IM25	IM24	IM23	IM22	IM21	Res.	IM19	Res.	Res.	Res.	IM[15:0]
0x080	Reset value	1					1	1	1	1	1	1		1				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x084	EXTI_EMR1	EM31	Res.	Res.	Res.	Res.	EM26	EM25	EM24	EM23	EM22	EM21	Res.	EM19	Res.	Res.	Res.	EM[15:0]
0x084	Reset value	0					0	0	0	0	0	0		0				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x088-0x08C	Reserved	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Refer to Section 2.2 on page 44 for the register boundary addresses.