4. Power control (PWR)

4.1 Power supplies

The STM32G0x0 devices require a 2.0 V to 3.6 V operating supply voltage ( \( V_{DD} \) ). Several different power supplies are provided to specific peripherals:

• • \( V_{DD} = 2.0 \text{ V to } 3.6 \text{ V} \)
  \( V_{DD} \) is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin.
• • \( V_{DDA} = 2.0 \text{ V to } 3.6 \text{ V} \)
  \( V_{DDA} \) is the analog power supply for the A/D converter. \( V_{DDA} \) voltage level is identical to \( V_{DD} \) voltage as it is provided externally through VDD/VDDA pin.
• • \( V_{DDIO1} = V_{DD} \)
  \( V_{DDIO1} \) is the power supply for the I/Os. \( V_{DDIO1} \) voltage level is identical to \( V_{DD} \) voltage as it is provided externally through VDD/VDDA pin.
• • \( V_{BAT} = 1.55 \text{ V to } 3.6 \text{ V} \)
  \( V_{BAT} \) is the power supply (through a power switch) for RTC, TAMP, low-speed external 32.768 kHz oscillator and backup registers when \( V_{DD} \) is not present. \( V_{BAT} \) is provided externally through VBAT pin. When this pin is not available on the package, it is internally bonded to VDD/VDDA.
• • \( V_{REF+} \) is the input reference voltage for the ADC. It must be between 2 V and \( V_{DDA} \) . It can be grounded when the ADC is not active.
  \( V_{REF+} \) is delivered through VREF+ pin. On packages without VREF+ pin, \( V_{REF+} \) is internally connected with \( V_{DD} \) .
• • \( V_{CORE} \)
  An embedded linear voltage regulator is used to supply the \( V_{CORE} \) internal digital power. \( V_{CORE} \) is the power supply for digital peripherals, SRAM and Flash memory. The Flash memory is also supplied by \( V_{DD} \) .

Figure 4. Power supply overview

4.1.1 ADC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to V _REF+ a separate reference voltage lower than V _DDA . V _REF+ is the highest voltage, represented by the full scale value, for an analog input (ADC) signal.

4.1.2 Battery backup of RTC domain

To retain the content of the backup registers and supply the RTC and TAMP functions when V _DD is turned off, the V _BAT pin can be connected to an optional backup voltage supplied by a battery or by another source.

The V _BAT pin powers the RTC and TAMP units, the LSE oscillator and the PC13 to PC15 I/Os, allowing the RTC and TAMP to operate even when the main power supply is turned off. The switch to the V _BAT supply is controlled by the power-down reset embedded in the Reset block.

Warning: During \( t_{RSTTEMPO} \) (temporization at V _DD startup) or after a PDR has been detected, the power switch between V _BAT and V _DD remains connected to V _BAT . During the startup phase, if V _DD is established in less than \( t_{RSTTEMPO} \) (refer to the datasheet for the value of \( t_{RSTTEMPO} \) ) and \( V_{DD} > V_{BAT} + 0.6 \) V, a current may be injected into V _BAT through an internal diode connected between V _DD and the power switch (V _BAT ). If the power supply/battery connected to the V _BAT pin cannot

support this current injection, it is recommended to connect an external low-drop diode between this power supply and the VBAT pin.

If no external battery is used in the user application, it is recommended to connect VBAT pin externally to VDD/VDDA pin with a 100 nF external ceramic decoupling capacitor.

When the RTC domain is supplied by \( V_{DD} \) (power switch connected to \( V_{DD} \) ), all the related pin functions are available:

When the RTC domain is supplied by \( V_{BAT} \) (power switch connected to \( V_{BAT} \) because \( V_{DD} \) is not present), only the following functions are available:

• • PC13, PC14 and PC15 can be controlled only by RTC, TAMP or LSE (refer to Section 23.3: RTC functional description )
• • RTC_OUT1 function on PC13
• • RTC_TS function on PC13 or PA4
• • TAMP_IN1 function on PC13 or PA4 and TAMP_IN2 function on PA0

Note: Due to the fact that the power switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive a LED).

RTC domain access

After a system reset, the RTC domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the RTC domain, proceed as follows:

1. 1. Enable the power interface clock by setting the PWREN bits of the APB peripheral clock enable register 1 (RCC_APBENR1) .
2. 2. Set the DBP bit of the Power control register 1 (PWR_CR1) to enable access to the RTC domain.
3. 3. Select the RTC clock source in the RTC domain control register (RCC_BDCR) .
4. 4. Enable the RTC clock by setting the RTCEN bit in the RTC domain control register (RCC_BDCR) .

VBAT battery charging

When \( V_{DD} \) is present, it is possible to charge the external battery on VBAT through an internal resistance.

The VBAT charging is done either through a 5 k \( \Omega \) resistor or through a 1.55 k \( \Omega \) resistor depending on the VBRS bit value in the PWR_CR4 register.

The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is automatically disabled in VBAT mode.

4.1.3 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the RTC domain. The main regulator output voltage ( \( V_{CORE} \) ) can be programmed by software to two different power ranges (Range 1 and Range 2) in order to optimize the consumption depending on the system maximum operating frequency (refer to Section 5.2.7: Clock source frequency versus voltage scaling and to Section 3.3.4: FLASH read access latency ).

The voltage regulators are always enabled after a reset. Depending on the user application modes, the \( V_{CORE} \) supply is provided either by the main regulator (MR) or by the low-power regulator (LPR).

• • In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator (MR) supplies full power to the \( V_{CORE} \) domain (core, memories and digital peripherals).
• • In Low-power run and Low-power sleep modes, the main regulator is off and the low-power regulator (LPR) supplies low-power to the \( V_{CORE} \) domain, preserving the contents of the registers and SRAM.
• • In Stop 1 mode, the main regulator is off and the low-power regulator (LPR) supplies low-power to the \( V_{CORE} \) domain, preserving the contents of the registers and SRAM.
• • In Standby mode, both regulators are powered off. The contents of the registers and SRAM is lost except for the Standby circuitry and the RTC domain.

4.1.4 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals ( \( V_{CORE} \) ), according to the application performance and power consumption needs.

Dynamic voltage scaling to increase \( V_{CORE} \) is known as overvolting. It allows to improve the device performance.

Dynamic voltage scaling to decrease \( V_{CORE} \) is known as undervolting. It is performed to save power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited.

Two voltage ranges are available:

• • Range 1: High-performance range
  The main regulator provides a typical output voltage at 1.2 V. The system clock frequency can be up to 64 MHz. The Flash access time for read access is minimum, write and erase operations are possible.
• • Range 2: Low-power range
  The main regulator provides a typical output voltage at 1.0 V. The system clock frequency can be up to 16 MHz. The Flash memory access time for a read access is increased as compared to Range 1; write and erase operations are not possible.

The voltage scaling is selected through the VOS bit in the PWR_CR1 register.

The sequence to go from Range 1 to Range 2 is:

1. 1. Reduce the system frequency to a value lower than 16 MHz
2. 2. Adjust number of wait states according new frequency target in Range 2 (LATENCY bits in the FLASH_ACR).
3. 3. Program the VOS[1:0] bits to 10 in the Power control register 1 (PWR_CR1) .

The sequence to go from Range 2 to Range 1 is:

1. 1. Program the VOS[1:0] bits to 01 in the Power control register 1 (PWR_CR1) .
2. 2. Wait until the VOSF flag is cleared in the Power status register 2 (PWR_SR2) .
3. 3. Adjust number of wait states according new frequency target in Range 1 (LATENCY bits in the FLASH access control register (FLASH_ACR) ).
4. 4. Increase the system frequency.

4.2 Power supply supervisor

4.2.1 Power-on reset (POR) / power-down reset (PDR)

The device features an integrated power-on reset (POR) / power-down reset (PDR). The POR/PDR is active in all power modes.

During power-on, the POR keeps the device under reset until the \( V_{DD} \) supply voltage reaches the specified POR threshold ( \( V_{POR} \) ). At this point, the device reset is released and the system can start. During power-down, when \( V_{DD} \) drops below the PDR threshold ( \( V_{PDR} \) ), the device is put under reset again.

Figure 5. POR, PDR thresholds

MSV47933V1

4.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The device features seven low-power modes:

• • Sleep mode: CPU clock off, all peripherals including Cortex ^® -M0+ core peripherals such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event occurs. Refer to Section 4.3.4: Sleep mode .
• • Low-power run mode: This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 4.3.2: Low-power run mode (LP run) .
• • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex ^® -M0+ is off. Refer to Section 4.3.5: Low-power sleep mode (LP sleep) .
• • Stop 0 and Stop 1 modes: SRAM and all registers content are retained. All clocks in the V _CORE domain are stopped, the PLL, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC and TAMP can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop mode to detect their wakeup condition.

In Stop 0 mode, the main regulator remains ON, which allows the fastest wakeup time but with higher consumption. The active peripherals and wakeup sources are the same as in Stop 1 mode.

The system clock, when exiting Stop 0 or Stop 1 mode, is the HSISYS clock. If the device is configured to wake up in Low-power run mode, the HSIDIV bits in RCC_CR register must be configured prior to entering Stop mode to provide a frequency not greater than 2 MHz.

Refer to Section 4.3.6: Stop 0 mode for details on Stop 0 mode.

• • Standby mode: V _CORE domain, the main regulator and the low-power regulator are powered off.

All clocks in the V _CORE domain are stopped and the PLL, the HSI16, and the HSE oscillators are disabled. The LSI and the LSE oscillators can be kept running.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The system clock, when exiting Standby modes, is the HSI16 oscillator clock.

Refer to Section 4.3.8: Standby mode .

In addition, the power consumption in Run mode can be reduced by one of the following means:

• • Slowing down the system clocks
• • Gating the clocks to the APB and AHB peripherals when they are unused.

Figure 6. Low-power modes state diagram

stateDiagram-v2
    [*] --> Run mode
    Run mode --> Low-power run mode
    Run mode --> Stop 0 mode
    Run mode --> Stop 1 mode
    Run mode --> Sleep mode
    Run mode --> Standby mode
    Low-power run mode --> Low-power sleep mode
    Low-power run mode --> Run mode
    Low-power run mode --> Standby mode
    Low-power sleep mode --> Low-power run mode
    Stop 0 mode --> Run mode
    Stop 0 mode --> Low-power run mode
    Stop 1 mode --> Run mode
    Stop 1 mode --> Low-power run mode
    Sleep mode --> Run mode
    Standby mode --> Run mode
    Standby mode --> Low-power run mode

Table 18. Low-power mode summary

1. Refer to Table 19: Functionalities depending on the working mode .

Table 19. Functionalities depending on the working mode ⁽¹⁾ (continued)

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash memory can be configured in power-down mode. By default, it is not in power-down mode.

1. 3. The SRAM clock can be gated ON or OFF.
2. 4. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put OFF when the peripheral does not need it anymore.
3. 5. If CSS is used on HSE clock in Low power run or Low power sleep modes, configure HSIDIV such as not to drive SYSCLK clock above the maximum frequency for either mode, in case of external clock failure detection.
4. 6. USART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
5. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
6. 8. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
7. 9. I/Os with wakeup from Standby mode capability (WKUPPx).

Debug mode

By default, the debug connection is lost if the user application puts the MCU in Stop 0, Stop1, or Standby mode while the debug features are used. This is due to the fact that the Cortex ^® -M0+ core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 29.9.1: Debug support for low-power modes .

4.3.1 Run mode

Slowing down system clocks

In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering Sleep mode.

For more details, refer to Section 5.4.3: Clock configuration register (RCC_CFGR) .

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption.

To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

The peripheral clock gating is controlled by the RCC_AHBENR and RCC_APBENRx registers.

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBSMENR and RCC_APBSMENRx registers.

4.3.2 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed 2 MHz.

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering Low-power run mode

To enter Low-power run mode, proceed as follows:

1. 1. Optional: Jump into the SRAM and power-down the Flash memory by setting the FPD_LPRUN bit in the Power control register 1 (PWR_CR1) .
2. 2. Decrease the system clock frequency below 2 MHz.
3. 3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.

Refer to Table 20: Low-power run on how to enter Low-power run mode.

Exiting Low-power run mode

To exit Low-power run mode, proceed as follows:

1. 1. Force the regulator in main mode by clearing the LPR bit in the Power control register 1 (PWR_CR1) .
2. 2. Wait until REGLPF bit is cleared in the Power status register 2 (PWR_SR2) .
3. 3. Increase the system clock frequency.

Refer to Table 20: Low-power run on how to exit Low-power run mode.

Table 20. Low-power run

4.3.3 Low-power modes

Entering low-power modes

The MCU enters low-power modes by executing the WFI (wait for interrupt), or WFE (wait for event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M0+ system control register is set on return from ISR.

Entering low-power mode through WFI or WFE is executed only if no interrupt is pending or no event is pending.

Exiting low-power modes

The MCU exits Sleep and Stop low-power modes in a way depending on how the low-power

mode was entered:

• • If the WFI instruction or Return from ISR was used to enter low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
• • If the WFE instruction is used to enter low-power mode, the MCU exits low-power mode as soon as an event occurs. The wakeup event can be generated either by:
  • – NVIC IRQ interrupt.

When SEVONPEND = 0 in the Cortex ^® -M0+ system control register: by enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

When SEVONPEND = 1 in the Cortex ^® -M0+ system control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

All NVIC interrupts wake the MCU up, even the disabled ones.

• – Event

Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set.

It may be necessary to clear the interrupt flag in the peripheral.

The MCU exits Standby low-power mode upon an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of enabled WKUPx pins, or upon an RTC event. See Figure 228: RTC block diagram .

After waking up from Standby mode, program execution restarts in the same way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

4.3.4 Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The MCU enters Sleep mode according to section Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is clear.

Refer to Table 21: Sleep mode summary for details on how to enter Sleep mode.

Exiting Sleep mode

The MCU exits Sleep mode according to Exiting low-power modes .

Refer to Table 21: Sleep mode summary for more details on how to exit Sleep mode.

4.3.5 Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

The MCU enters Low-power sleep mode from Low-power run mode according to Entering low-power modes , when the SLEEPDEEP bit in the Cortex®-M0+ System Control register is clear.

Refer to Table 22: Low-power sleep mode summary for details on how to enter Low-power sleep mode.

Exiting Low-power sleep mode

The MCU exits Low-power sleep mode according to Exiting low-power modes . When exiting Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run mode.

Refer to Table 22: Low-power sleep mode summary for details on how to exit Low-power sleep mode.

Table 22. Low-power sleep mode summary

4.3.6 Stop 0 mode

The Stop 0 mode is based on the Cortex®-M0+ deepsleep mode combined with the peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all clocks in the V _CORE domain are stopped; the PLL, the HSI16 and the HSE oscillators are disabled. Some peripherals with the wakeup capability (I2C1, USART1, USART2) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.

SRAM and register contents are preserved.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop 0 mode

The MCU enters Stop 0 mode according to section Entering low-power modes , when the SLEEPDEEP bit in the Cortex®-M0+ System Control register is set.

Refer to Table 23: Stop 0 mode summary for details on how to enter Stop 0 mode.

If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB access is finished.

In Stop 0 mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except upon a reset. See Section 21.3: IWDG functional description .
• • real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control register (RCC_BDCR) .
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC domain control register (RCC_BDCR) .

Several peripherals can be used in Stop 0 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: USART1, USART2, and I2C1.

The ADC and the temperature sensor can consume power during the Stop 0 mode, unless they are disabled before entering this mode.

Exiting Stop 0 mode

The MCU exits Stop 0 mode according to section Entering low-power modes .

Refer to Table 23: Stop 0 mode summary for details on how to exit Stop 0 mode.

When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSISYS oscillator is selected as system clock. If the device is configured to wake up in Low-power run mode, the HSIDIV bits in RCC_CR register must be configured prior to entering Stop 0 mode to provide a frequency not greater than 2 MHz.

When exiting Stop 0 mode, the MCU is either in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the Power control register 1 (PWR_CR1) .

Table 23. Stop 0 mode summary

Table 23. Stop 0 mode summary (continued)

4.3.7 Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the main regulator is off, and only the low-power regulator is on. Stop 1 mode can be entered from Run mode and from Low-power run mode.

Refer to Table 24: Stop 1 mode summary for details on how to enter and exit Stop 1 mode.

Table 24. Stop 1 mode summary

Table 24. Stop 1 mode summary

4.3.8 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex ^® -M0+ deepsleep mode, with the voltage regulators disabled (except when the SRAM content is preserved). The PLL, the HSI16 and the HSE oscillators are also switched off.

The content of the registers is lost except for the registers in the RTC domain and Standby circuitry (see Figure 4 ). The SRAM content is lost.

I/O states in Standby mode

In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A, B, C, D, F), or with a pull-down (refer to PWR_PDCRx registers (x=A, B, C, D, F)), or can be kept in analog mode.

The RTC outputs on PC13 and PA4 are functional in Standby mode. PC14 and PC15 used for LSE are also functional. Five wakeup pins (WKUPx, x=1,2,4,5,6) and the two tampers are available.

Entering Standby mode

The MCU enters Standby mode according to Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is set.

Refer to Table 25: Standby mode summary for details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 21.3: IWDG functional description .
• • Real-time clock (RTC) and tamper (TAMP): this is configured by the RTCEN bit in the RTC domain control register (RCC_BDCR)
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR).
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC domain control register (RCC_BDCR)

Exiting Standby mode

The MCU exits Standby mode according to section Entering low-power modes . The SBF status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in Standby mode. All registers are reset after wakeup from Standby except for Power control register 3 (PWR_CR3) .

Refer to Table 25: Standby mode summary for more details on how to exit Standby mode.

Table 25. Standby mode summary

4.3.9 Auto-wakeup from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop (0, 1) or Standby modes at regular intervals. For this purpose, two of

the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR) :

• • Low-power 32.768 kHz external crystal oscillator (LSE OSC)
  This clock source provides a precise time base with very low-power consumption.
• • Low-power internal RC Oscillator (LSI)
  This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.

To wake up from Stop mode with an RTC alarm or an RTC wakeup event, it is necessary to:

• • Configure the EXTI Line 19 to be sensitive to rising edge.
• • Configure the RTC to generate the wakeup event.

To wake up from Standby mode, there is no need to configure the EXTI line 19.

4.4 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

4.4.1 Power control register 1 (PWR_CR1)

Address offset: 0x00

Reset value: 0x0000 0208. This register is reset after wakeup from Standby mode.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR : Low-power run

When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).

Bits 13:11 Reserved, must be kept at reset value.

Bits 10:9 VOS : Voltage scaling range selection

• 00: Cannot be written (forbidden by hardware)
• 01: Range 1
• 10: Range 2
• 11: Cannot be written (forbidden by hardware)

Bit 8 DBP : Disable RTC domain write protection

In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers.

• 0: Access to RTC and backup registers disabled
• 1: Access to RTC and backup registers enabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 FPD_LPSLP : Flash memory powered down during Low-power sleep mode

This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode.

0: Flash memory idle

1: Flash memory powered down

Bit 4 FPD_LPRUN : Flash memory powered down during Low-power run mode

This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Low-power run mode. The Flash memory can be put in power-down mode only when the user code is executed from SRAM.

0: Flash memory idle

1: Flash memory powered down

Bit 3 FPD_STOP : Flash memory powered down during Stop mode

This bit determines whether the Flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode.

0: Flash memory idle

1: Flash memory powered down

Bits 2:0 LPMS[2:0] : Low-power mode selection

These bits select the low-power mode entered when CPU enters deepsleep mode.

000: Stop 0 mode

001: Stop 1 mode

010: Reserved

011: Standby mode

Note: 1xx: Reserved

4.4.2 Power control register 2 (PWR_CR2)

This register is available on STM32G0B0xx only. It is reserved otherwise.

Address offset: 0x04

Reset value: 0x0000 0000. This register is reset when exiting Standby mode.

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 USV : USB supply enable

0: Disable

1: Enable

The bit must be set for the USB peripheral to operate.

Bits 9:0 Reserved, must be kept at reset value.

4.4.3 Power control register 3 (PWR_CR3)

Address offset: 0x08

Reset value: 0x0000 8000. This register is not reset when exiting Standby modes and with the PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wakeup line

0: Disable

1: Enable

Bits 14:11 Reserved, must be kept at reset value.

Bit 10 APC : Apply pull-up and pull-down configuration

This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied.

0: Not applied

1: Applied

Bit 9 Reserved, must be kept at reset value.

Bit 8 Reserved, must be kept at reset value.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 EWUP6 : Enable WKUP6 wakeup pin

When this bit is set, the WKUP6 external wakeup pin is enabled and triggers a wakeup from Standby mode when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register.

Bit 4 EWUP5 : Enable WKUP5 wakeup pin

When this bit is set, the WKUP5 external wakeup pin is enabled and triggers a wakeup from Standby mode when a rising or a falling edge occurs. The active edge is configured via the WP5 bit in the PWR_CR4 register.

Bit 3 EWUP4 : Enable WKUP4 wakeup pin

When this bit is set, the WKUP4 external wakeup pin is enabled and triggers a wakeup from Standby mode when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.

Bit 2 EWUP3 : Enable WKUP3 wakeup pin

When this bit is set, the WKUP3 external wakeup pin is enabled and triggers a wakeup from Standby mode when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register.

Bit 1 EWUP2 : Enable WKUP2 wakeup pin

When this bit is set, the WKUP2 external wakeup pin is enabled and triggers a wakeup from Standby mode when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register.

Bit 0 EWUP1 : Enable WKUP1 wakeup pin

When this bit is set, the WKUP1 external wakeup pin is enabled and triggers a wakeup from Standby mode when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register.

4.4.4 Power control register 4 (PWR_CR4)

Address offset: 0x0C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with the PWRRST bit in the APB peripheral reset register 1 (RCC_APBHRSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 VBR : V _BAT battery charging resistor selection

0: 5 kΩ
1: 1.5 kΩ

Bit 8 VBE : V _BAT battery charging enable

0: Disable
1: Enable

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 WP6 : WKUP6 wakeup pin polarity

WKUP6 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge

Bit 4 WP5 : WKUP5 wakeup pin polarity

WKUP5 external wakeup signal polarity (level or edge) triggering wakeup event:
0: High level or rising edge
1: Low level or falling edge

• Bit 3 WP4 : WKUP4 wakeup pin polarity
  WKUP4 external wakeup signal polarity (level or edge) triggering wakeup event:
  0: High level or rising edge
  1: Low level or falling edge
• Bit 1 WP3 : WKUP3 wakeup pin polarity
  WKUP3 external wakeup signal polarity (level or edge) triggering wakeup event:
  0: High level or rising edge
  1: Low level or falling edge
• Bit 1 WP2 : WKUP2 wakeup pin polarity
  WKUP2 external wakeup signal polarity (level or edge) triggering wakeup event:
  0: High level or rising edge
  1: Low level or falling edge
• Bit 0 WP1 : WKUP1 wakeup pin polarity
  WKUP1 external wakeup signal polarity (level or edge) triggering wakeup event:
  0: High level or rising edge
  1: Low level or falling edge

4.4.5 Power status register 1 (PWR_SR1)

Address offset: 0x10

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with the PWRRST bit in the APB peripheral reset register 1 (RCC_APBHRSTR1) .

Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI : Wakeup flag internal
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared.

Bits 14:9 Reserved, must be kept at reset value.

Bit 8 SBF : Standby flag
This bit is set by hardware when the device enters Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.
0: The device did not enter Standby mode
1: The device entered Standby mode

Bits 7:6 Reserved, must be kept at reset value.

This bit is set when a wakeup event is detected on WKUP6 wakeup pin. It is cleared by writing 1 in the CWUF6 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP5 wakeup pin. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP4 wakeup pin. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP3 wakeup pin. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP2 wakeup pin. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP1 wakeup pin. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register.

4.4.6 Power status register 2 (PWR_SR2)

Address offset: 0x14

Reset value: 0x0000 0000. This register is partially reset when exiting Standby mode.

Bits 31:11 Reserved, must be kept at reset value.

A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.

0: The regulator is ready in the selected voltage range

1: The regulator output voltage is changing to the required voltage level

This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency.

This bit is cleared by hardware when the regulator is ready.

0: The regulator is ready in main mode (MR)

1: The regulator is in low-power mode (LPR)

Bit 8 REGLPS : Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on reset or Standby. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased.

0: The low-power regulator is not ready
1: The low-power regulator is ready

Bit 7 FLASH_RDY : Flash ready flag

This bit is set by hardware to indicate when the Flash memory is ready to be accessed after wakeup from power-down. To place the Flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits.

0: Flash memory in power-down
1: Flash memory ready to be accessed

Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to Flash memory.

Bits 6:0 Reserved, must be kept at reset value.

4.4.7 Power status clear register (PWR_SCR)

Address offset: 0x18

Reset value: 0x0000 0000.

Access: three additional APB cycles are needed to write this register, compared to a standard APB write.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSBF : Clear standby flag

Setting this bit clears the SBF flag in the PWR_SR1 register.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 CWUF6 : Clear wakeup flag 6

Setting this bit clears the WUF6 flag in the PWR_SR1 register.

Bit 4 CWUF5 : Clear wakeup flag 5

Setting this bit clears the WUF5 flag in the PWR_SR1 register.

Bit 3 CWUF4 : Clear wakeup flag 4

Setting this bit clears the WUF4 flag in the PWR_SR1 register.

Bit 2 CWUF3 : Clear wakeup flag 3

Setting this bit clears the WUF3 flag in the PWR_SR1 register.

Bit 1 CWUF2 : Clear wakeup flag 2

Setting this bit clears the WUF2 flag in the PWR_SR1 register.

Bit 0 CWUF1 : Clear wakeup flag 1

Setting this bit clears the WUF1 flag in the PWR_SR1 register.

4.4.8 Power Port A pull-up control register (PWR_PUCRA)

Address offset: 0x20

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port A pull-up bit y (y = 0 to 15)

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[y] I/O.

4.4.9 Power Port A pull-down control register (PWR_PDCRA)

Address offset: 0x24

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port A pull-down bit y (y = 0 to 15)

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[y] I/O.

4.4.10 Power Port B pull-up control register (PWR_PUCRB)

Address offset: 0x28

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port B pull-up bit y (y = 0 to 15)

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[y] I/O.

4.4.11 Power Port B pull-down control register (PWR_PDCRB)

Address offset: 0x2C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port B pull-down bit y (y = 0 to 15)

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[y] I/O.

4.4.12 Power Port C pull-up control register (PWR_PUCRC)

Address offset: 0x30

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port C pull-up bit y (y = 0 to 15) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[y] I/O.

1. 1. In STM32G030xx as well as STM32G050xx devices, the bits PD0 to PD5 and PD8 to PD12 are reserved.

4.4.13 Power Port C pull-down control register (PWR_PDCRC)

Address offset: 0x34

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port C pull-down bit y (y = 0 to 15) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[y] I/O.

1. 1. In STM32G030xx as well as STM32G050xx devices, the bits PD0 to PD5 and PD8 to PD12 are reserved.

4.4.14 Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port D pull-up bit y (y = 0 to 15) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[y] I/O.

1. 1. In STM32G070xx devices, the bits PU15 to PU10 and PU7 are reserved. In STM32G030xx as well as in STM32G050xx devices, PU15 to PU4 are reserved.

4.4.15 Power Port D pull-down control register (PWR_PDCRD)

Address offset: 0x3C

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port D pull-down bit y (y = 0 to 15) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[y] I/O.

1. 1. In STM32G070xx devices, the bits PD15 to PD10 and PD7 are reserved. In STM32G030xx as well as in STM32G050xx devices, PD15 to PD4 are reserved.

4.4.16 Power Port E pull-up control register (PWR_PUCRE)

Address offset: 0x40

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBHRSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port E pull-up bit y (y = 0 to 15) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PE[y] I/O.

1. 1. Only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.17 Power Port E pull-down control register (PWR_PDCRE)

Address offset: 0x44

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBHRSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port E pull-down bit y (y = 0 to 15) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PE[y] I/O.

1. 1. Only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.18 Power Port F pull-up control register (PWR_PUCRF)

Address offset: 0x48

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 PUy : Port F pull-up bit y (y = 0 to 13) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[y] I/O.

1. 1. Bits PU13 to PU3 only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.19 Power Port F pull-down control register (PWR_PDCRF)

Address offset: 0x4C.

Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 PDy : Port F pull-down bit y (y = 0 to 13) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[y] I/O.

1. 1. Bits PU13 to PU3 only applies to STM32G0B0xx devices. Reserved for the other devices.

4.4.20 PWR register map

Table 26. PWR register map and reset values

Table 26. PWR register map and reset values (continued)

Refer to Section 2.2 on page 44 for the register boundary addresses.