RM0454-STM32G0x0

This reference manual complements the datasheets of the STM32G0x0 microcontrollers, providing information required for application and in particular for software development. It pertains to the superset of feature sets available on STM32G0x0 microcontrollers.

For feature set, ordering information, and mechanical and electrical characteristics of a particular STM32G0x0 device, refer to its corresponding datasheet.

For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ technical reference manual.

a. Available on STMicroelectronics website www.st.com

Contents

3.5.2FLASH write protection (WRP) .....72
3.6FLASH interrupts .....73
3.7FLASH registers .....74
3.7.1FLASH access control register (FLASH_ACR) .....74
3.7.2FLASH key register (FLASH_KEYR) .....75
3.7.3FLASH option key register (FLASH_OPTKEYR) .....75
3.7.4FLASH status register (FLASH_SR) .....75
3.7.5FLASH control register (FLASH_CR) .....77
3.7.6FLASH ECC register (FLASH_ECCR) .....79
3.7.7FLASH ECC register 2 (FLASH_ECCR2) .....80
3.7.8FLASH option register (FLASH_OPTR) .....80
3.7.9FLASH WRP area A address register (FLASH_WRP1AR) .....82
3.7.10FLASH WRP area B address register (FLASH_WRP1BR) .....82
3.7.11FLASH WRP2 area A address register (FLASH_WRP2AR) .....83
3.7.12FLASH WRP2 area B address register (FLASH_WRP2BR) .....84
3.7.13FLASH register map .....85
4Power control (PWR) .....86
4.1Power supplies .....86
4.1.1ADC reference voltage .....87
4.1.2Battery backup of RTC domain .....87
4.1.3Voltage regulator .....89
4.1.4Dynamic voltage scaling management .....89
4.2Power supply supervisor .....90
4.2.1Power-on reset (POR) / power-down reset (PDR) .....90
4.3Low-power modes .....91
4.3.1Run mode .....95
4.3.2Low-power run mode (LP run) .....95
4.3.3Low-power modes .....96
4.3.4Sleep mode .....97
4.3.5Low-power sleep mode (LP sleep) .....98
4.3.6Stop 0 mode .....99
4.3.7Stop 1 mode .....101
4.3.8Standby mode .....102
4.3.9Auto-wakeup from low-power mode .....103
4.4PWR registers .....104
4.4.1Power control register 1 (PWR_CR1) . . . . .104
4.4.2Power control register 2 (PWR_CR2) . . . . .105
4.4.3Power control register 3 (PWR_CR3) . . . . .106
4.4.4Power control register 4 (PWR_CR4) . . . . .107
4.4.5Power status register 1 (PWR_SR1) . . . . .108
4.4.6Power status register 2 (PWR_SR2) . . . . .109
4.4.7Power status clear register (PWR_SCR) . . . . .110
4.4.8Power Port A pull-up control register (PWR_PUCRA) . . . . .111
4.4.9Power Port A pull-down control register (PWR_PDCRA) . . . . .111
4.4.10Power Port B pull-up control register (PWR_PUCRB) . . . . .112
4.4.11Power Port B pull-down control register (PWR_PDCRB) . . . . .112
4.4.12Power Port C pull-up control register (PWR_PUCRC) . . . . .113
4.4.13Power Port C pull-down control register (PWR_PDCRC) . . . . .113
4.4.14Power Port D pull-up control register (PWR_PUCRD) . . . . .114
4.4.15Power Port D pull-down control register (PWR_PDCRD) . . . . .114
4.4.16Power Port E pull-up control register (PWR_PUCRE) . . . . .115
4.4.17Power Port E pull-down control register (PWR_PDCRE) . . . . .115
4.4.18Power Port F pull-up control register (PWR_PUCRF) . . . . .115
4.4.19Power Port F pull-down control register (PWR_PDCRF) . . . . .116
4.4.20PWR register map . . . . .117
5Reset and clock control (RCC) . . . . .119
5.1Reset . . . . .119
5.1.1Power reset . . . . .119
5.1.2System reset . . . . .119
5.1.3RTC domain reset . . . . .121
5.2Clocks . . . . .121
5.2.1HSE clock . . . . .125
5.2.2HSI16 clock . . . . .126
5.2.3PLL . . . . .127
5.2.4LSE clock . . . . .127
5.2.5LSI clock . . . . .128
5.2.6System clock (SYSCLK) selection . . . . .128
5.2.7Clock source frequency versus voltage scaling . . . . .128
5.2.8Clock security system (CSS) . . . . .129
5.2.9Clock security system for LSE clock (LSECSS) . . . . .129
5.2.10ADC clock . . . . .130
5.2.11RTC clock . . . . .130
5.2.12Timer clock . . . . .130
5.2.13Watchdog clock . . . . .130
5.2.14Clock-out capability . . . . .131
5.2.15Internal/external clock measurement with TIM14/TIM16/TIM17 . . . . .131
5.2.16Peripheral clock enable registers . . . . .134
5.3Low-power modes . . . . .134
5.4RCC registers . . . . .135
5.4.1Clock control register (RCC_CR) . . . . .135
5.4.2Internal clock source calibration register (RCC_ICSCR) . . . . .136
5.4.3Clock configuration register (RCC_CFGR) . . . . .137
5.4.4PLL configuration register (RCC_PLLCFGR) . . . . .140
5.4.5Clock interrupt enable register (RCC_CIER) . . . . .143
5.4.6Clock interrupt flag register (RCC_CIFR) . . . . .143
5.4.7Clock interrupt clear register (RCC_CICR) . . . . .145
5.4.8I/O port reset register (RCC_IOPRSTR) . . . . .146
5.4.9AHB peripheral reset register (RCC_AHBRSTR) . . . . .147
5.4.10APB peripheral reset register 1 (RCC_APBSTR1) . . . . .148
5.4.11APB peripheral reset register 2 (RCC_APBSTR2) . . . . .150
5.4.12I/O port clock enable register (RCC_IOPENR) . . . . .151
5.4.13AHB peripheral clock enable register (RCC_AHBENR) . . . . .152
5.4.14APB peripheral clock enable register 1 (RCC_APBENR1) . . . . .153
5.4.15APB peripheral clock enable register 2(RCC_APBENR2) . . . . .155
5.4.16I/O port in Sleep mode clock enable register (RCC_IOPSMENR) . . . . .157
5.4.17AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR) . . . . .		158
5.4.18APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1) . . . . .		159
5.4.19APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2) . . . . .		161
5.4.20Peripherals independent clock configuration register (RCC_CCIPR) . . . . .163
5.4.21Peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . .		164
5.4.22RTC domain control register (RCC_BDCR) . . . . .165
5.4.23Control/status register (RCC_CSR) . . . . .167
5.4.24RCC register map . . . . .169
6General-purpose I/Os (GPIO) . . . . .173
6.1Introduction .....173
6.2GPIO main features .....173
6.3GPIO functional description .....173
6.3.1General-purpose I/O (GPIO) .....175
6.3.2I/O pin alternate function multiplexer and mapping .....175
6.3.3I/O port control registers .....176
6.3.4I/O port data registers .....176
6.3.5I/O data bitwise handling .....177
6.3.6GPIO locking mechanism .....177
6.3.7I/O alternate function input/output .....177
6.3.8External interrupt/wakeup lines .....178
6.3.9Input configuration .....178
6.3.10Output configuration .....179
6.3.11Alternate function configuration .....179
6.3.12Analog configuration .....180
6.3.13Using the HSE or LSE oscillator pins as GPIOs .....181
6.3.14Using the GPIO pins in the RTC domain .....181
6.4GPIO registers .....182
6.4.1GPIO port mode register (GPIOx_MODER)
(x =A to F) .....		182
6.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to F) .....		182
6.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to F) .....		183
6.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to F) .....		183
6.4.5GPIO port input data register (GPIOx_IDR)
(x = A to F) .....		184
6.4.6GPIO port output data register (GPIOx_ODR)
(x = A to F) .....		184
6.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to F) .....		184
6.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to F) .....		185
6.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to F) .....		186
6.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to F) .....		187
6.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to F) .....187
6.4.12GPIO register map .....188
7System configuration controller (SYSCFG) . . . . .189
7.1SYSCFG registers . . . . .189
7.1.1SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .189
7.1.2SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .192
7.1.3SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . .194
7.1.4SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . .194
7.1.5SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . .195
7.1.6SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . .195
7.1.7SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . .196
7.1.8SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . .196
7.1.9SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . .196
7.1.10SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . .197
7.1.11SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . .197
7.1.12SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . .198
7.1.13SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . .198
7.1.14SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . .199
7.1.15SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . .199
7.1.16SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . .199
7.1.17SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . .200
7.1.18SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . .200
7.1.19SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . .200
7.1.20SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . .201
7.1.21SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . .201
7.1.22SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . .201
7.1.23SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . .202
7.1.24SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . .202
7.1.25SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . .202
7.1.26SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . .203
7.1.27SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . .203
7.1.28SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . .204
7.1.29SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . .204
7.1.30SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . .204
7.1.31SYSCFG register map . . . . .205
8Interconnect matrix . . . . .208
8.1Introduction . . . . .208
8.2Connection summary . . . . .208
8.3Interconnection details . . . . .209
8.3.1From TIM1, TIM3, TIM4, TIM15, TIM16, and TIM17,
to TIM1, TIM3, TIM4, and TIM15 . . . . .		209
8.3.2From TIM1, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC . . . . .210
8.3.3From ADC to TIM1 . . . . .210
8.3.4From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM14,
TIM16, and TIM17 . . . . .		211
8.3.5From internal analog sources to ADC211
8.3.6From system errors to TIM1, TIM3, TIM4, TIM15, TIM16,
and TIM17 . . . . .		211
8.3.7From TIM16, TIM17, USART1, and USART4, to IRTIM . . . . .212
8.3.8From TIM14 to DMAMUX . . . . .212
9Direct memory access controller (DMA) . . . . .213
9.1Introduction . . . . .213
9.2DMA main features . . . . .213
9.3DMA implementation . . . . .214
9.3.1DMA . . . . .214
9.3.2DMA request mapping . . . . .214
9.4DMA functional description . . . . .214
9.4.1DMA block diagram . . . . .214
9.4.2DMA pins and internal signals . . . . .215
9.4.3DMA transfers . . . . .215
9.4.4DMA arbitration . . . . .216
9.4.5DMA channels . . . . .217
9.4.6DMA data width, alignment and endianness . . . . .220
9.4.7DMA error management . . . . .222
9.5DMA interrupts . . . . .222
9.6DMA registers . . . . .222
9.6.1DMA interrupt status register (DMA_ISR) . . . . .223
9.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .225
9.6.3DMA channel x configuration register (DMA_CCRx) . . . . .226
9.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .229
9.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .230
9.6.6DMA channel x memory address register (DMA_CMARx) . . . . .230
9.6.7DMA register map .....231
10DMA request multiplexer (DMAMUX) .....234
10.1Introduction .....234
10.2DMAMUX main features .....235
10.3DMAMUX implementation .....235
10.3.1DMAMUX instantiation .....235
10.3.2DMAMUX mapping .....235
10.4DMAMUX functional description .....238
10.4.1DMAMUX block diagram .....238
10.4.2DMAMUX signals .....239
10.4.3DMAMUX channels .....239
10.4.4DMAMUX request line multiplexer .....239
10.4.5DMAMUX request generator .....242
10.5DMAMUX interrupts .....243
10.6DMAMUX registers .....244
10.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) .....		244
10.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) .....		245
10.6.3DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) .....		245
10.6.4DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) .....		246
10.6.5DMAMUX request generator interrupt status register
(DMAMUX_RGS) .....		247
10.6.6DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) .....		247
10.6.7DMAMUX register map .....248
11Nested vectored interrupt controller (NVIC) .....250
11.1Main features .....250
11.2SysTick calibration value register .....250
11.3Interrupt and exception vectors .....250
12Extended interrupt and event controller (EXTI) .....253
12.1EXTI main features .....253
12.2EXTI block diagram .....253
12.2.1EXTI connections between peripherals and CPU . . . . .255
12.3EXTI functional description . . . . .255
12.3.1EXTI configurable event input wakeup . . . . .256
12.3.2EXTI direct event input wakeup . . . . .256
12.3.3EXTI mux . . . . .257
12.4EXTI functional behavior . . . . .258
12.5EXTI registers . . . . .259
12.5.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .259
12.5.2EXTI falling trigger selection register 1 (EXTI_FTSR1) . . . . .260
12.5.3EXTI software interrupt event register 1 (EXTI_SWIER1) . . . . .260
12.5.4EXTI rising edge pending register 1 (EXTI_RPR1) . . . . .261
12.5.5EXTI falling edge pending register 1 (EXTI_FPR1) . . . . .261
12.5.6EXTI external interrupt selection register (EXTI_EXTICRx) . . . . .262
12.5.7EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . .263
12.5.8EXTI CPU wakeup with event mask register (EXTI_EMR1) . . . . .264
12.5.9EXTI register map . . . . .265
13Cyclic redundancy check calculation unit (CRC) . . . . .267
13.1Introduction . . . . .267
13.2CRC main features . . . . .267
13.3CRC functional description . . . . .268
13.3.1CRC block diagram . . . . .268
13.3.2CRC internal signals . . . . .268
13.3.3CRC operation . . . . .268
13.4CRC registers . . . . .270
13.4.1CRC data register (CRC_DR) . . . . .270
13.4.2CRC independent data register (CRC_IDR) . . . . .270
13.4.3CRC control register (CRC_CR) . . . . .271
13.4.4CRC initial value (CRC_INIT) . . . . .272
13.4.5CRC polynomial (CRC_POL) . . . . .272
13.4.6CRC register map . . . . .273
14Analog-to-digital converter (ADC) . . . . .274
14.1Introduction . . . . .274
14.2ADC main features . . . . .275
14.3ADC functional description . . . . .276
14.3.1ADC pins and internal signals . . . . .276
14.3.2ADC voltage regulator (ADVREGEN) . . . . .277
14.3.3Calibration (ADCAL) . . . . .278
14.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .279
14.3.5ADC clock (CKMODE, PRESC[3:0]) . . . . .281
14.3.6ADC connectivity . . . . .283
14.3.7Configuring the ADC . . . . .284
14.3.8Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .284
14.3.9Programmable sampling time (SMPx[2:0]) . . . . .285
14.3.10Single conversion mode (CONT = 0) . . . . .286
14.3.11Continuous conversion mode (CONT = 1) . . . . .286
14.3.12Starting conversions (ADSTART) . . . . .287
14.3.13Timings . . . . .288
14.3.14Stopping an ongoing conversion (ADSTP) . . . . .289
14.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .289
14.4.1Discontinuous mode (DISCEN) . . . . .290
14.4.2Programmable resolution (RES) - Fast conversion mode . . . . .290
14.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .291
14.4.4End of conversion sequence (EOS flag) . . . . .291
14.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		292
14.4.6Low frequency trigger mode . . . . .294
14.5Data management . . . . .294
14.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .294
14.5.2ADC overrun (OVR, OVRMOD) . . . . .294
14.5.3Managing a sequence of data converted without using the DMA . . . . .296
14.5.4Managing converted data without using the DMA without overrun . . . . .296
14.5.5Managing converted data using the DMA . . . . .296
14.6Low-power features . . . . .297
14.6.1Wait mode conversion . . . . .297
14.6.2Auto-off mode (AUTOFF) . . . . .298
14.7Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH,
ADC_AWDxCR, ADC_AWDxTR) . . . . .		300
14.7.1Description of analog watchdog 1 . . . . .300
14.7.2Description of analog watchdog 2 and 3 . . . . .301
14.7.3ADC_AWDx_OUT output signal generation . . . . .301
14.7.4Analog Watchdog threshold control . . . . .303
14.8Oversampler . . . . .304
14.8.1ADC operating modes supported when oversampling . . . . .306
14.8.2Analog watchdog . . . . .306
14.8.3Triggered mode . . . . .306
14.9Temperature sensor and internal reference voltage . . . . .307
14.10Battery voltage monitoring . . . . .309
14.11ADC interrupts . . . . .310
14.12ADC registers . . . . .312
14.12.1ADC interrupt and status register (ADC_ISR) . . . . .312
14.12.2ADC interrupt enable register (ADC_IER) . . . . .314
14.12.3ADC control register (ADC_CR) . . . . .316
14.12.4ADC configuration register 1 (ADC_CFGR1) . . . . .318
14.12.5ADC configuration register 2 (ADC_CFGR2) . . . . .322
14.12.6ADC sampling time register (ADC_SMPR) . . . . .323
14.12.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .324
14.12.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .325
14.12.9ADC channel selection register [alternate] (ADC_CHSELR) . . . . .326
14.12.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .327
14.12.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .329
14.12.12ADC data register (ADC_DR) . . . . .329
14.12.13ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) . . . . .330
14.12.14ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .330
14.12.15ADC Calibration factor (ADC_CALFACT) . . . . .331
14.12.16ADC common configuration register (ADC_CCR) . . . . .331
14.13ADC register map . . . . .333
15Advanced-control timer (TIM1) . . . . .335
15.1TIM1 introduction . . . . .335
15.2TIM1 main features . . . . .336
15.3TIM1 functional description . . . . .338
15.3.1Time-base unit . . . . .338
15.3.2Counter modes . . . . .340
15.3.3Repetition counter . . . . .351
15.3.4External trigger input . . . . .353
15.3.5Clock selection . . . . .354
15.3.6Capture/compare channels . . . . .358
15.3.7Input capture mode . . . . .360
15.3.8PWM input mode . . . . .361
15.3.9Forced output mode . . . . .362
15.3.10Output compare mode . . . . .363
15.3.11PWM mode . . . . .364
15.3.12Asymmetric PWM mode . . . . .367
15.3.13Combined PWM mode . . . . .368
15.3.14Combined 3-phase PWM mode . . . . .369
15.3.15Complementary outputs and dead-time insertion . . . . .370
15.3.16Using the break function . . . . .372
15.3.17Bidirectional break inputs . . . . .378
15.3.18Clearing the OCxREF signal on an external event . . . . .380
15.3.196-step PWM generation . . . . .381
15.3.20One-pulse mode . . . . .382
15.3.21Retriggerable one pulse mode . . . . .383
15.3.22Encoder interface mode . . . . .384
15.3.23UIF bit remapping . . . . .386
15.3.24Timer input XOR function . . . . .387
15.3.25Interfacing with Hall sensors . . . . .387
15.3.26Timer synchronization . . . . .390
15.3.27ADC synchronization . . . . .394
15.3.28DMA burst mode . . . . .394
15.3.29Debug mode . . . . .395
15.4TIM1 registers . . . . .396
15.4.1TIM1 control register 1 (TIM1_CR1) . . . . .396
15.4.2TIM1 control register 2 (TIM1_CR2) . . . . .397
15.4.3TIM1 slave mode control register (TIM1_SMCR) . . . . .400
15.4.4TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . .402
15.4.5TIM1 status register (TIM1_SR) . . . . .404
15.4.6TIM1 event generation register (TIM1_EGR) . . . . .406
15.4.7TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		407
15.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		408
15.4.9TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		411
15.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		412
15.4.11TIM1 capture/compare enable register (TIM1_CCER) . . . . .414
15.4.12TIM1 counter (TIM1_CNT) . . . . .417
15.4.13TIM1 prescaler (TIM1_PSC) . . . . .417
15.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .417
15.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .418
15.4.16TIM1 capture/compare register 1 (TIM1_CCR1) . . . . .418
15.4.17TIM1 capture/compare register 2 (TIM1_CCR2) . . . . .419
15.4.18TIM1 capture/compare register 3 (TIM1_CCR3) . . . . .419
15.4.19TIM1 capture/compare register 4 (TIM1_CCR4) . . . . .420
15.4.20TIM1 break and dead-time register (TIM1_BDTR) . . . . .420
15.4.21TIM1 DMA control register (TIM1_DCR) . . . . .424
15.4.22TIM1 DMA address for full transfer (TIM1_DMAR) . . . . .425
15.4.23TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . .426
15.4.24TIM1 capture/compare register 5 (TIM1_CCR5) . . . . .427
15.4.25TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .428
15.4.26TIM1 alternate function option register 1 (TIM1_AF1) . . . . .428
15.4.27TIM1 Alternate function register 2 (TIM1_AF2) . . . . .429
15.4.28TIM1 timer input selection register (TIM1_TISEL) . . . . .430
15.4.29TIM1 register map . . . . .431
16General-purpose timers (TIM3/TIM4) . . . . .434
16.1TIM3/TIM4 introduction . . . . .434
16.2TIM3/TIM4 main features . . . . .434
16.3TIM3/TIM4 functional description . . . . .436
16.3.1Time-base unit . . . . .436
16.3.2Counter modes . . . . .438
16.3.3Clock selection . . . . .448
16.3.4Capture/Compare channels . . . . .452
16.3.5Input capture mode . . . . .454
16.3.6PWM input mode . . . . .455
16.3.7Forced output mode . . . . .456
16.3.8Output compare mode . . . . .456
16.3.9PWM mode . . . . .457
16.3.10Asymmetric PWM mode . . . . .461
16.3.11Combined PWM mode . . . . .461
16.3.12Clearing the OCxREF signal on an external event . . . . .462
16.3.13One-pulse mode . . . . .464
16.3.14Retriggerable one pulse mode . . . . .465
16.3.15Encoder interface mode . . . . .466
16.3.16UIF bit remapping . . . . .468
16.3.17Timer input XOR function . . . . .468
16.3.18Timers and external trigger synchronization . . . . .469
16.3.19Timer synchronization . . . . .472
16.3.20DMA burst mode . . . . .477
16.3.21Debug mode . . . . .478
16.4TIM3/TIM4 registers . . . . .479
16.4.1TIMx control register 1 (TIMx_CR1)(x = 3 to 4) . . . . .479
16.4.2TIMx control register 2 (TIMx_CR2)(x = 3 to 4) . . . . .480
16.4.3TIMx slave mode control register (TIMx_SMCR)(x = 3 to 4) . . . . .482
16.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 3 to 4) . . . . .485
16.4.5TIMx status register (TIMx_SR)(x = 3 to 4) . . . . .486
16.4.6TIMx event generation register (TIMx_EGR)(x = 3 to 4) . . . . .488
16.4.7TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 3 to 4) . . . . .		489
16.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 3 to 4) . . . . .		491
16.4.9TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 3 to 4) . . . . .		493
16.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 3 to 4) . . . . .		494
16.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 3 to 4) . . . . .		495
16.4.12TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4) . . . . .496
16.4.13TIMx counter [alternate] (TIMx_CNT)(x = 3 to 4) . . . . .497
16.4.14TIMx prescaler (TIMx_PSC)(x = 3 to 4) . . . . .497
16.4.15TIMx auto-reload register (TIMx_ARR)(x = 3 to 4) . . . . .498
16.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 3 to 4) . . . . .498
16.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 3 to 4) . . . . .499
16.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 3 to 4) . . . . .499
16.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 3 to 4) . . . . .500
16.4.20TIMx DMA control register (TIMx_DCR)(x = 3 to 4) . . . . .501
16.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 3 to 4) . . . . .501
16.4.22TIM3 alternate function option register 1 (TIM3_AF1) . . . . .502
16.4.23TIM4 alternate function option register 1 (TIM4_AF1) . . . . .502
16.4.24TIM3 timer input selection register (TIM3_TISEL) . . . . .502
16.4.25TIM4 timer input selection register (TIM4_TISEL) . . . . .503
16.4.26TIMx register map . . . . .505
17Basic timers (TIM6/TIM7) . . . . .508
17.1TIM6/TIM7 introduction . . . . .508
17.2TIM6/TIM7 main features . . . . .508
17.3TIM6/TIM7 functional description . . . . .509
17.3.1Time-base unit . . . . .509
17.3.2Counting mode . . . . .511
17.3.3UIF bit remapping . . . . .514
17.3.4Clock source . . . . .514
17.3.5Debug mode . . . . .515
17.4TIM6/TIM7 registers . . . . .515
17.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .515
17.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .517
17.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .517
17.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .518
17.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .518
17.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .518
17.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .519
17.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .519
17.4.9TIMx register map . . . . .520
18General-purpose timers (TIM14) . . . . .521
18.1TIM14 introduction . . . . .521
18.2TIM14 main features . . . . .521
18.2.1TIM14 main features . . . . .521
18.3TIM14 functional description . . . . .523
18.3.1Time-base unit . . . . .523
18.3.2Counter modes . . . . .525
18.3.3Clock selection . . . . .528
18.3.4Capture/compare channels . . . . .529
18.3.5Input capture mode . . . . .530
18.3.6Forced output mode . . . . .531
18.3.7Output compare mode . . . . .532
18.3.8PWM mode . . . . .533
18.3.9One-pulse mode . . . . .534
18.3.10UIF bit remapping . . . . .534
18.3.11Using timer output as trigger for other timers (TIM14) . . . . .535
18.3.12Debug mode . . . . .535
18.4TIM14 registers . . . . .536
18.4.1TIM14 control register 1 (TIM14_CR1) . . . . .536
18.4.2TIM14 Interrupt enable register (TIM14_DIER) . . . . .537
18.4.3TIM14 status register (TIM14_SR) . . . . .537
18.4.4TIM14 event generation register (TIM14_EGR) . . . . .538
18.4.5TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) . . . . .539
18.4.6TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) . . . . .540
18.4.7TIM14 capture/compare enable register (TIM14_CCER) . . . . .542
18.4.8TIM14 counter (TIM14_CNT) . . . . .543
18.4.9TIM14 prescaler (TIM14_PSC) . . . . .544
18.4.10TIM14 auto-reload register (TIM14_ARR) . . . . .544
18.4.11TIM14 capture/compare register 1 (TIM14_CCR1) . . . . .544
18.4.12TIM14 timer input selection register (TIM14_TISEL) . . . . .545
18.4.13TIM14 register map . . . . .545
19General-purpose timers (TIM15/TIM16/TIM17) . . . . .547
19.1TIM15/TIM16/TIM17 introduction . . . . .547
19.2TIM15 main features . . . . .547
19.3TIM16/TIM17 main features . . . . .548
19.4TIM15/TIM16/TIM17 functional description . . . . .551
19.4.1Time-base unit . . . . .551
19.4.2Counter modes . . . . .553
19.4.3Repetition counter . . . . .557
19.4.4Clock selection . . . . .558
19.4.5Capture/compare channels . . . . .560
19.4.6Input capture mode . . . . .562
19.4.7PWM input mode (only for TIM15) . . . . .563
19.4.8Forced output mode . . . . .564
19.4.9Output compare mode . . . . .565
19.4.10PWM mode . . . . .566
19.4.11Combined PWM mode (TIM15 only) . . . . .567
19.4.12Complementary outputs and dead-time insertion . . . . .568
19.4.13Using the break function . . . . .570
19.4.14Bidirectional break inputs . . . . .575
19.4.15One-pulse mode . . . . .577
19.4.16Retriggerable one pulse mode (TIM15 only) . . . . .579
19.4.17UIF bit remapping . . . . .579
19.4.18Timer input XOR function (TIM15 only) . . . . .581
19.4.19External trigger synchronization (TIM15 only) . . . . .582
19.4.20Slave mode – combined reset + trigger mode . . . . .584
19.4.21DMA burst mode . . . . .584
19.4.22Timer synchronization (TIM15) . . . . .586
19.4.23Using timer output as trigger for other timers (TIM16/TIM17) . . . . .586
19.4.24Debug mode . . . . .586
19.5TIM15 registers . . . . .587
19.5.1TIM15 control register 1 (TIM15_CR1) . . . . .587
19.5.2TIM15 control register 2 (TIM15_CR2) . . . . .588
19.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .590
19.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .591
19.5.5TIM15 status register (TIM15_SR) . . . . .592
19.5.6TIM15 event generation register (TIM15_EGR) . . . . .594
19.5.7TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		595
19.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		596
19.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .599
19.5.10TIM15 counter (TIM15_CNT) . . . . .602
19.5.11TIM15 prescaler (TIM15_PSC) . . . . .602
19.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .602
19.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .603
19.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .603
19.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .604
19.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .604
19.5.17TIM15 DMA control register (TIM15_DCR) . . . . .607
19.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .607
19.5.19TIM15 alternate register 1 (TIM15_AF1) . . . . .608
19.5.20TIM15 input selection register (TIM15_TISEL) . . . . .608
19.5.21TIM15 register map .....609
19.6TIM16/TIM17 registers .....612
19.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....612
19.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .....613
19.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .....614
19.6.4TIMx status register (TIMx_SR)(x = 16 to 17) .....615
19.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) .....616
19.6.6TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) .....		617
19.6.7TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) .....		618
19.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) ..620
19.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) .....622
19.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) .....623
19.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) .....623
19.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) .....624
19.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) .....624
19.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .....625
19.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) .....628
19.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) .....628
19.6.17TIM16 alternate function register 1 (TIM16_AF1) .....629
19.6.18TIM16 input selection register (TIM16_TISEL) .....629
19.6.19TIM17 alternate function register 1 (TIM17_AF1) .....630
19.6.20TIM17 input selection register (TIM17_TISEL) .....630
19.6.21TIM16/TIM17 register map .....632
20Infrared interface (IRTIM) .....634
21Independent watchdog (IWDG) .....635
21.1Introduction .....635
21.2IWDG main features .....635
21.3IWDG functional description .....635
21.3.1IWDG block diagram .....635
21.3.2Window option .....636
21.3.3Hardware watchdog .....637
21.3.4Register access protection .....637
21.3.5Debug mode .....637
23.3.9Reading the calendar . . . . .660
23.3.10Resetting the RTC . . . . .661
23.3.11RTC synchronization . . . . .661
23.3.12RTC reference clock detection . . . . .662
23.3.13RTC smooth digital calibration . . . . .662
23.3.14Timestamp function . . . . .664
23.3.15Calibration clock output . . . . .665
23.3.16Tamper and alarm output . . . . .665
23.4RTC low-power modes . . . . .666
23.5RTC interrupts . . . . .666
23.6RTC registers . . . . .667
23.6.1RTC time register (RTC_TR) . . . . .667
23.6.2RTC date register (RTC_DR) . . . . .668
23.6.3RTC sub second register (RTC_SSR) . . . . .669
23.6.4RTC initialization control and status register (RTC_ICSR) . . . . .669
23.6.5RTC prescaler register (RTC_PRER) . . . . .671
23.6.6RTC wakeup timer register (RTC_WUTR) . . . . .672
23.6.7RTC control register (RTC_CR) . . . . .672
23.6.8RTC write protection register (RTC_WPR) . . . . .675
23.6.9RTC calibration register (RTC_CALR) . . . . .676
23.6.10RTC shift control register (RTC_SHIFTR) . . . . .677
23.6.11RTC timestamp time register (RTC_TSTR) . . . . .678
23.6.12RTC timestamp date register (RTC_TSDR) . . . . .678
23.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .679
23.6.14RTC alarm A register (RTC_ALRMAR) . . . . .680
23.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .681
23.6.16RTC alarm B register (RTC_ALRMBR) . . . . .682
23.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .683
23.6.18RTC status register (RTC_SR) . . . . .683
23.6.19RTC masked interrupt status register (RTC_MISR) . . . . .684
23.6.20RTC status clear register (RTC_SCR) . . . . .685
23.6.21RTC register map . . . . .687
24Tamper and backup registers (TAMP) . . . . .689
24.1Introduction . . . . .689
24.2TAMP main features . . . . .689
25.4.14SMBus: I2C_TIMEOUTR register configuration examples . . . . .744
25.4.15SMBus slave mode . . . . .745
25.4.16Wakeup from Stop mode on address match . . . . .753
25.4.17Error conditions . . . . .753
25.4.18DMA requests . . . . .755
25.4.19Debug mode . . . . .756
25.5I2C low-power modes . . . . .756
25.6I2C interrupts . . . . .757
25.7I2C registers . . . . .758
25.7.1I2C control register 1 (I2C_CR1) . . . . .758
25.7.2I2C control register 2 (I2C_CR2) . . . . .761
25.7.3I2C own address 1 register (I2C_OAR1) . . . . .764
25.7.4I2C own address 2 register (I2C_OAR2) . . . . .765
25.7.5I2C timing register (I2C_TIMINGR) . . . . .766
25.7.6I2C timeout register (I2C_TIMEOUTR) . . . . .767
25.7.7I2C interrupt and status register (I2C_ISR) . . . . .768
25.7.8I2C interrupt clear register (I2C_ICR) . . . . .770
25.7.9I2C PEC register (I2C_PECR) . . . . .771
25.7.10I2C receive data register (I2C_RXDR) . . . . .772
25.7.11I2C transmit data register (I2C_TXDR) . . . . .772
25.7.12I2C register map . . . . .773
26Universal synchronous receiver transmitter (USART) . . . . .775
26.1USART introduction . . . . .775
26.2USART main features . . . . .776
26.3USART extended features . . . . .777
26.4USART implementation . . . . .777
26.5USART functional description . . . . .779
26.5.1USART block diagram . . . . .779
26.5.2USART signals . . . . .780
26.5.3USART character description . . . . .781
26.5.4USART FIFOs and thresholds . . . . .783
26.5.5USART transmitter . . . . .783
26.5.6USART receiver . . . . .787
26.5.7USART baud rate generation . . . . .794
26.5.8Tolerance of the USART receiver to clock deviation . . . . .795
26.5.9USART Auto baud rate detection . . . . .797
26.5.10USART multiprocessor communication . . . . .799
26.5.11USART Modbus communication . . . . .801
26.5.12USART parity control . . . . .802
26.5.13USART LIN (local interconnection network) mode . . . . .803
26.5.14USART synchronous mode . . . . .805
26.5.15USART single-wire Half-duplex communication . . . . .809
26.5.16USART receiver timeout . . . . .809
26.5.17USART Smartcard mode . . . . .810
26.5.18USART IrDA SIR ENDEC block . . . . .814
26.5.19Continuous communication using USART and DMA . . . . .817
26.5.20RS232 Hardware flow control and RS485 Driver Enable . . . . .819
26.5.21USART low-power management . . . . .822
26.6USART in low-power modes . . . . .825
26.7USART interrupts . . . . .826
26.8USART registers . . . . .827
26.8.1USART control register 1 [alternate] (USART_CR1) . . . . .827
26.8.2USART control register 1 [alternate] (USART_CR1) . . . . .831
26.8.3USART control register 2 (USART_CR2) . . . . .834
26.8.4USART control register 3 (USART_CR3) . . . . .838
26.8.5USART baud rate register (USART_BRR) . . . . .843
26.8.6USART guard time and prescaler register (USART_GTPR) . . . . .843
26.8.7USART receiver timeout register (USART_RTOR) . . . . .844
26.8.8USART request register (USART_RQR) . . . . .845
26.8.9USART interrupt and status register [alternate] (USART_ISR) . . . . .846
26.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .852
26.8.11USART interrupt flag clear register (USART_ICR) . . . . .857
26.8.12USART receive data register (USART_RDR) . . . . .859
26.8.13USART transmit data register (USART_TDR) . . . . .859
26.8.14USART prescaler register (USART_PRESC) . . . . .860
26.8.15USART register map . . . . .861
27Serial peripheral interface / integrated interchip sound (SPI/I2S) . . .863
27.1Introduction . . . . .863
27.2SPI main features . . . . .863
27.3I2S main features . . . . .864
27.4SPI/I2S implementation . . . . .864
27.5SPI functional description . . . . .865
27.5.1General description . . . . .865
27.5.2Communications between one master and one slave . . . . .866
27.5.3Standard multi-slave communication . . . . .868
27.5.4Multi-master communication . . . . .869
27.5.5Slave select (NSS) pin management . . . . .870
27.5.6Communication formats . . . . .871
27.5.7Configuration of SPI . . . . .873
27.5.8Procedure for enabling SPI . . . . .874
27.5.9Data transmission and reception procedures . . . . .874
27.5.10SPI status flags . . . . .884
27.5.11SPI error flags . . . . .885
27.5.12NSS pulse mode . . . . .886
27.5.13TI mode . . . . .886
27.5.14CRC calculation . . . . .887
27.6SPI interrupts . . . . .889
27.7I2S functional description . . . . .890
27.7.1I2S general description . . . . .890
27.7.2Supported audio protocols . . . . .891
27.7.3Start-up description . . . . .898
27.7.4Clock generator . . . . .900
27.7.5I 2 S master mode . . . . .903
27.7.6I 2 S slave mode . . . . .904
27.7.7I2S status flags . . . . .906
27.7.8I2S error flags . . . . .907
27.7.9DMA features . . . . .908
27.8I2S interrupts . . . . .908
27.9SPI and I2S registers . . . . .909
27.9.1SPI control register 1 (SPIx_CR1) . . . . .909
27.9.2SPI control register 2 (SPIx_CR2) . . . . .911
27.9.3SPI status register (SPIx_SR) . . . . .913
27.9.4SPI data register (SPIx_DR) . . . . .914
27.9.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .915
27.9.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .915
27.9.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .915
27.9.8SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . .916
27.9.9SPIx_I2S prescaler register (SPIx_I2SPR) . . . . .918
27.9.10SPI/I2S register map . . . . .919
28Universal serial bus full-speed host/device interface (USB) . . . . .920
28.1Introduction . . . . .920
28.2USB main features . . . . .920
28.3USB implementation . . . . .920
28.4USB functional description . . . . .921
28.4.1Description of USB blocks used in both Device and Host modes . . . . .923
28.4.2Description of host frame scheduler (HFS) specific to Host mode . . . . .924
28.5Programming considerations for Device and Host modes . . . . .925
28.5.1Generic USB Device programming . . . . .925
28.5.2System and power-on reset . . . . .925
28.5.3Double-buffered endpoints and usage in Device mode . . . . .932
28.5.4Double buffered channels: usage in Host mode . . . . .934
28.5.5Isochronous transfers in Device mode . . . . .935
28.5.6Isochronous transfers in Host mode . . . . .937
28.5.7Suspend/resume events . . . . .937
28.6USB and USB SRAM registers . . . . .941
28.6.1Common registers . . . . .941
28.6.2Buffer descriptor table . . . . .960
28.6.3USB register map . . . . .964
29Debug support (DBG) . . . . .966
29.1Overview . . . . .966
29.2Reference Arm documentation . . . . .967
29.3Pinout and debug port pins . . . . .967
29.3.1SWD port pins . . . . .967
29.3.2SW-DP pin assignment . . . . .967
29.3.3Internal pull-up & pull-down on SWD pins . . . . .968
29.4ID codes and locking mechanism . . . . .968
29.5SWD port . . . . .968
29.5.1SWD protocol introduction . . . . .968
29.5.2SWD protocol sequence . . . . .968
29.5.3SW-DP state machine (reset, idle states, ID code) . . . . .969
29.5.4DP and AP read/write accesses . . . . .970
29.5.5SW-DP registers . . . . .970
29.5.6SW-AP registers . . . . .971
29.6Core debug . . . . .972
29.7BPU (Break Point Unit) . . . . .972
29.7.1BPU functionality . . . . .973
29.8DWT (Data Watchpoint) . . . . .973
29.8.1DWT functionality . . . . .973
29.8.2DWT Program Counter Sample Register . . . . .973
29.9MCU debug component (DBG) . . . . .973
29.9.1Debug support for low-power modes . . . . .973
29.9.2Debug support for timers, watchdog and I 2 C . . . . .974
29.10DBG registers . . . . .974
29.10.1DBG device ID code register (DBG_IDCODE) . . . . .974
29.10.2DBG configuration register (DBG_CR) . . . . .975
29.10.3DBG APB freeze register 1 (DBG_APB_FZ1) . . . . .975
29.10.4DBG APB freeze register 2 (DBG_APB_FZ2) . . . . .977
29.10.5DBG register map . . . . .978
30Device electronic signature . . . . .980
30.1Flash memory size data register . . . . .980
30.2Package data register . . . . .980
31Revision history . . . . .982

List of tables

Table 1. Peripherals versus products . . . . . 40

Table 2. STM32G0B0xx memory boundary addresses . . . . . 46

Table 3. STM32G070xx memory boundary addresses . . . . . 46

Table 4. STM32G030xx and STM32G050xx memory boundary addresses . . . . . 47

Table 5. STM32G0x0 peripheral register boundary addresses . . . . . 47

Table 6. SRAM size . . . . . 49

Table 7. Boot modes . . . . . 51

Table 8. Flash memory organization for single-bank devices . . . . . 54

Table 9. Flash memory organization for 512 Kbytes dual-bank devices . . . . . 55

Table 10. Number of wait states according to Flash memory clock (HCLK) frequency . . . . . 56

Table 11. Option byte format . . . . . 64

Table 12. Organization of option bytes . . . . . 64

Table 13. Flash memory read protection status . . . . . 70

Table 14. Access status versus protection level and execution modes . . . . . 71

Table 16. FLASH interrupt requests . . . . . 73

Table 17. FLASH register map and reset values . . . . . 85

Table 18. Low-power mode summary . . . . . 93

Table 19. Functionalities depending on the working mode . . . . . 93

Table 20. Low-power run . . . . . 96

Table 21. Sleep mode summary . . . . . 98

Table 22. Low-power sleep mode summary . . . . . 99

Table 23. Stop 0 mode summary . . . . . 100

Table 24. Stop 1 mode summary . . . . . 101

Table 25. Standby mode summary . . . . . 103

Table 26. PWR register map and reset values . . . . . 117

Table 27. Clock source frequency . . . . . 128

Table 28. RCC register map and reset values . . . . . 169

Table 29. Port bit configuration table . . . . . 174

Table 30. GPIO register map and reset values . . . . . 188

Table 31. SYSCFG register map and reset values . . . . . 205

Table 32. Interconnect matrix . . . . . 208

Table 33. DMA implementation . . . . . 214

Table 34. DMA internal input/output signals . . . . . 215

Table 35. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . 221

Table 36. DMA interrupt requests . . . . . 222

Table 37. DMA register map and reset values . . . . . 231

Table 38. DMAMUX instantiation . . . . . 235

Table 39. DMAMUX: assignment of multiplexer inputs to resources . . . . . 236

Table 40. DMAMUX: assignment of trigger inputs to resources . . . . . 236

Table 41. DMAMUX: assignment of synchronization inputs to resources . . . . . 237

Table 42. DMAMUX signals . . . . . 239

Table 43. DMAMUX interrupts . . . . . 243

Table 44. DMAMUX register map and reset values . . . . . 248

Table 45. Vector table . . . . . 250

Table 46. EXTI signal overview . . . . . 254

Table 47. EVG pin overview . . . . . 254

Table 48. EXTI event input configurations and register control . . . . . 255

Table 49.EXTI line connections . . . . .258
Table 50.Masking functionality . . . . .258
Table 51.EXTI register map sections. . . . .259
Table 52.EXTI controller register map and reset values . . . . .265
Table 53.CRC internal input/output signals . . . . .268
Table 54.CRC register map and reset values . . . . .273
Table 55.ADC input/output pins . . . . .276
Table 56.ADC internal input/output signals . . . . .277
Table 57.External triggers . . . . .277
Table 58.Latency between trigger and start of conversion . . . . .282
Table 59.Configuring the trigger polarity . . . . .289
Table 60.tSAR timings depending on resolution . . . . .291
Table 61.Analog watchdog comparison. . . . .300
Table 62.Analog watchdog 1 channel selection . . . . .301
Table 63.Maximum output results vs N and M. Grayed values indicates truncation . . . . .305
Table 64.ADC interrupts . . . . .310
Table 65.ADC register map and reset values . . . . .333
Table 66.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .377
Table 67.Break protection disarming conditions . . . . .379
Table 68.Counting direction versus encoder signals. . . . .385
Table 69.TIM1 internal trigger connection . . . . .402
Table 70.Output control bits for complementary OCx and OCxN channels with break feature. . . . .416
Table 71.TIM1 register map and reset values . . . . .431
Table 72.Counting direction versus encoder signals. . . . .467
Table 73.TIM3 internal trigger connection . . . . .485
Table 74.Output control bit for standard OCx channels. . . . .496
Table 75.TIM3/TIM4 register map and reset values . . . . .505
Table 76.TIMx register map and reset values . . . . .520
Table 77.Output control bit for standard OCx channels. . . . .543
Table 78.TIM14 register map and reset values . . . . .545
Table 79.Break protection disarming conditions . . . . .575
Table 80.TIMx Internal trigger connection . . . . .591
Table 81.Output control bits for complementary OCx and OCxN channels with break feature (TIM15). . . . .601
Table 82.TIM15 register map and reset values . . . . .609
Table 83.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .622
Table 84.TIM16/TIM17 register map and reset values . . . . .632
Table 85.IWDG register map and reset values . . . . .643
Table 86.WWDG register map and reset values . . . . .649
Table 87.RTC input/output pins . . . . .652
Table 88.RTC internal input/output signals . . . . .652
Table 89.RTC interconnection. . . . .653
Table 90.PC13 configuration . . . . .653
Table 91.RTC_OUT mapping . . . . .655
Table 92.Effect of low-power modes on RTC . . . . .666
Table 93.RTC pins functionality over modes. . . . .666
Table 94.Interrupt requests . . . . .667
Table 95.RTC register map and reset values . . . . .687
Table 96.TAMP input/output pins . . . . .691
Table 97.TAMP internal input/output signals. . . . .691
Table 98.TAMP interconnection . . . . .691
Table 99.Effect of low-power modes on TAMP . . . . .694
Table 100.Interrupt requests . . . . .694
Table 101.TAMP register map and reset values . . . . .703
Table 102.STM32G0x0 I2C implementation . . . . .705
Table 103.I2C input/output pins . . . . .708
Table 104.I2C internal input/output signals . . . . .708
Table 105.Comparison of analog vs. digital filters . . . . .710
Table 106.I2C-SMBus specification data setup and hold times . . . . .713
Table 107.I2C configuration . . . . .717
Table 108.I2C-SMBus specification clock timings . . . . .728
Table 109.Examples of timing settings for f I2CCLK = 8 MHz . . . . .738
Table 110.Examples of timings settings for f I2CCLK = 16 MHz . . . . .738
Table 111.Examples of timings settings for f I2CCLK = 48 MHz . . . . .739
Table 112.SMBus timeout specifications . . . . .741
Table 113.SMBus with PEC configuration . . . . .743
Table 114.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t TIMEOUT = 25 ms) . . . . .		744
Table 115.Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .744
Table 116.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t IDLE = 50 µs) . . . . .		745
Table 117.Effect of low-power modes on the I2C . . . . .756
Table 118.I2C Interrupt requests . . . . .757
Table 119.I2C register map and reset values . . . . .773
Table 120.STM32G0x0 features . . . . .777
Table 121.USART features . . . . .778
Table 122.Noise detection from sampled data . . . . .793
Table 123.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .796
Table 124.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .797
Table 125.USART frame formats . . . . .802
Table 126.Effect of low-power modes on the USART . . . . .825
Table 127.USART interrupt requests . . . . .826
Table 128.USART register map and reset values . . . . .861
Table 129.STM32G0x0 SPI and SPI/I2S implementation . . . . .864
Table 130.SPI interrupt requests . . . . .889
Table 131.Audio-frequency precision using standard 8 MHz HSE . . . . .902
Table 132.I2S interrupt requests . . . . .908
Table 133.SPI/I2S register map and reset values . . . . .919
Table 134.STM32G0x0 USB implementation . . . . .920
Table 135.Double-buffering buffer flag definition . . . . .933
Table 136.Bulk double-buffering memory buffers usage (Device mode) . . . . .933
Table 137.Bulk double-buffering memory buffers usage (Host mode) . . . . .935
Table 138.Isochronous memory buffers usage . . . . .936
Table 139.Isochronous memory buffers usage . . . . .937
Table 140.Resume event detection . . . . .939
Table 141.Resume event detection for host . . . . .940
Table 142.Reception status encoding . . . . .958
Table 143.Endpoint/channel type encoding . . . . .958
Table 144.Endpoint/channel kind meaning . . . . .958
Table 145.Transmission status encoding . . . . .958
Table 146.Definition of allocated buffer memory . . . . .961
Table 147.USB register map and reset values . . . . .964
Table 148.SW debug port pins . . . . .967
Table 149.Packet request (8-bits) . . . . .969
Table 150.ACK response (3 bits). . . . .969
Table 151.DATA transfer (33 bits). . . . .969
Table 152.SW-DP registers. . . . .970
Table 153.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .971
Table 154.Core debug registers . . . . .972
Table 155.DEV_ID and REV_ID field values. . . . .974
Table 156.DBG register map and reset values . . . . .978
Table 157.Document revision history . . . . .982

List of figures

Figure 1.System architecture . . . . .42
Figure 2.Memory map . . . . .45
Figure 3.Changing read protection (RDP) level . . . . .71
Figure 4.Power supply overview . . . . .87
Figure 5.POR, PDR thresholds . . . . .90
Figure 6.Low-power modes state diagram . . . . .92
Figure 7.Simplified diagram of the reset circuit . . . . .120
Figure 8.Clock tree . . . . .124
Figure 9.HSE/ LSE clock sources . . . . .125
Figure 10.Frequency measurement with TIM14 in capture mode . . . . .132
Figure 11.Frequency measurement with TIM16 in capture mode . . . . .132
Figure 12.Frequency measurement with TIM17 in capture mode . . . . .133
Figure 13.Basic structure of an I/O port bit . . . . .174
Figure 14.Input floating/pull up/pull down configurations . . . . .178
Figure 15.Output configuration . . . . .179
Figure 16.Alternate function configuration- . . . . .180
Figure 17.High impedance-analog configuration . . . . .180
Figure 18.DMA block diagram . . . . .215
Figure 19.DMAMUX block diagram . . . . .238
Figure 20.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .241
Figure 21.Event generation of the DMA request line multiplexer channel . . . . .241
Figure 22.EXTI block diagram . . . . .254
Figure 23.Configurable event trigger logic CPU wakeup . . . . .256
Figure 24.Direct event trigger logic CPU wakeup . . . . .257
Figure 25.EXTI GPIO mux . . . . .257
Figure 26.CRC calculation unit block diagram . . . . .268
Figure 27.ADC block diagram . . . . .276
Figure 28.ADC calibration . . . . .279
Figure 29.Calibration factor forcing . . . . .279
Figure 30.Enabling/disabling the ADC . . . . .280
Figure 31.ADC clock scheme . . . . .281
Figure 32.ADC connectivity . . . . .283
Figure 33.Analog to digital conversion time . . . . .288
Figure 34.ADC conversion timings . . . . .288
Figure 35.Stopping an ongoing conversion . . . . .289
Figure 36.Single conversions of a sequence, software trigger . . . . .292
Figure 37.Continuous conversion of a sequence, software trigger . . . . .292
Figure 38.Single conversions of a sequence, hardware trigger . . . . .293
Figure 39.Continuous conversions of a sequence, hardware trigger . . . . .293
Figure 40.Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .294
Figure 41.Example of overrun (OVR) . . . . .295
Figure 42.Wait mode conversion (continuous mode, software trigger) . . . . .298
Figure 43.Behavior with WAIT = 0, AUTOFF = 1 . . . . .299
Figure 44.Behavior with WAIT = 1, AUTOFF = 1 . . . . .299
Figure 45.Analog watchdog guarded area . . . . .300
Figure 46.ADC_AWDx_OUT signal generation . . . . .302
Figure 47.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .302
Figure 48.ADC_AWDx_OUT signal generation (on a single channel) . . . . .303
Figure 49.Analog watchdog threshold update . . . . .303
Figure 50.20-bit to 16-bit result truncation . . . . .304
Figure 51.Numerical example with 5-bits shift and rounding . . . . .305
Figure 52.Triggered oversampling mode (TOVS bit = 1) . . . . .307
Figure 53.Temperature sensor and VREFINT channel block diagram . . . . .308
Figure 54.VBAT channel block diagram . . . . .310
Figure 55.Advanced-control timer block diagram . . . . .337
Figure 56.Counter timing diagram with prescaler division change from 1 to 2 . . . . .339
Figure 57.Counter timing diagram with prescaler division change from 1 to 4 . . . . .339
Figure 58.Counter timing diagram, internal clock divided by 1 . . . . .341
Figure 59.Counter timing diagram, internal clock divided by 2 . . . . .341
Figure 60.Counter timing diagram, internal clock divided by 4 . . . . .342
Figure 61.Counter timing diagram, internal clock divided by N . . . . .342
Figure 62.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .343
Figure 63.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .343
Figure 64.Counter timing diagram, internal clock divided by 1 . . . . .345
Figure 65.Counter timing diagram, internal clock divided by 2 . . . . .345
Figure 66.Counter timing diagram, internal clock divided by 4 . . . . .346
Figure 67.Counter timing diagram, internal clock divided by N . . . . .346
Figure 68.Counter timing diagram, update event when repetition counter is not used . . . . .347
Figure 69.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .348
Figure 70.Counter timing diagram, internal clock divided by 2 . . . . .349
Figure 71.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .349
Figure 72.Counter timing diagram, internal clock divided by N . . . . .350
Figure 73.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .350
Figure 74.Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .351
Figure 75.Update rate examples depending on mode and TIMx_RCR register settings . . . . .352
Figure 76.External trigger input block . . . . .353
Figure 77.TIM1 ETR input circuitry . . . . .353
Figure 78.Control circuit in normal mode, internal clock divided by 1 . . . . .354
Figure 79.TI2 external clock connection example . . . . .355
Figure 80.Control circuit in external clock mode 1 . . . . .356
Figure 81.External trigger input block . . . . .356
Figure 82.Control circuit in external clock mode 2 . . . . .357
Figure 83.Capture/compare channel (example: channel 1 input stage) . . . . .358
Figure 84.Capture/compare channel 1 main circuit . . . . .358
Figure 85.Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .359
Figure 86.Output stage of capture/compare channel (channel 4) . . . . .359
Figure 87.Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .360
Figure 88.PWM input mode timing . . . . .362
Figure 89.Output compare mode, toggle on OC1 . . . . .364
Figure 90.Edge-aligned PWM waveforms (ARR=8) . . . . .365
Figure 91.Center-aligned PWM waveforms (ARR=8) . . . . .366
Figure 92.Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .368
Figure 93.Combined PWM mode on channel 1 and 3 . . . . .369
Figure 94.3-phase combined PWM signals with multiple trigger pulses per period . . . . .370
Figure 95.Complementary output with dead-time insertion . . . . .371
Figure 96.Dead-time waveforms with delay greater than the negative pulse . . . . .371
Figure 97.Dead-time waveforms with delay greater than the positive pulse . . . . .372
Figure 98.Break and Break2 circuitry overview . . . . .374
Figure 99.Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .376
Figure 100.PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .377
Figure 101. PWM output state following BRK assertion (OSSI=0) . . . . .378
Figure 102. Output redirection (BRK2 request not represented) . . . . .379
Figure 103. Clearing TIMx OCxREF . . . . .380
Figure 104. 6-step generation, COM example (OSSR=1) . . . . .381
Figure 105. Example of one pulse mode. . . . .382
Figure 106. Retriggerable one pulse mode . . . . .384
Figure 107. Example of counter operation in encoder interface mode. . . . .385
Figure 108. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .386
Figure 109. Measuring time interval between edges on 3 signals . . . . .387
Figure 110. Example of Hall sensor interface . . . . .389
Figure 111. Control circuit in reset mode . . . . .390
Figure 112. Control circuit in Gated mode . . . . .391
Figure 113. Control circuit in trigger mode . . . . .392
Figure 114. Control circuit in external clock mode 2 + trigger mode . . . . .393
Figure 115. General-purpose timer block diagram . . . . .435
Figure 116. Counter timing diagram with prescaler division change from 1 to 2 . . . . .437
Figure 117. Counter timing diagram with prescaler division change from 1 to 4 . . . . .437
Figure 118. Counter timing diagram, internal clock divided by 1 . . . . .438
Figure 119. Counter timing diagram, internal clock divided by 2 . . . . .439
Figure 120. Counter timing diagram, internal clock divided by 4 . . . . .439
Figure 121. Counter timing diagram, internal clock divided by N . . . . .440
Figure 122. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .440
Figure 123. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .441
Figure 124. Counter timing diagram, internal clock divided by 1 . . . . .442
Figure 125. Counter timing diagram, internal clock divided by 2 . . . . .442
Figure 126. Counter timing diagram, internal clock divided by 4 . . . . .443
Figure 127. Counter timing diagram, internal clock divided by N . . . . .443
Figure 128. Counter timing diagram, Update event when repetition counter
is not used . . . . .		444
Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .445
Figure 130. Counter timing diagram, internal clock divided by 2 . . . . .446
Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .446
Figure 132. Counter timing diagram, internal clock divided by N . . . . .447
Figure 133. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .447
Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .448
Figure 135. Control circuit in normal mode, internal clock divided by 1 . . . . .449
Figure 136. TI2 external clock connection example. . . . .449
Figure 137. Control circuit in external clock mode 1 . . . . .450
Figure 138. External trigger input block . . . . .451
Figure 139. Control circuit in external clock mode 2 . . . . .452
Figure 140. Capture/Compare channel (example: channel 1 input stage) . . . . .452
Figure 141. Capture/Compare channel 1 main circuit . . . . .453
Figure 142. Output stage of Capture/Compare channel (channel 1). . . . .453
Figure 143. PWM input mode timing . . . . .455
Figure 144. Output compare mode, toggle on OC1 . . . . .457
Figure 145. Edge-aligned PWM waveforms (ARR=8) . . . . .458
Figure 146. Center-aligned PWM waveforms (ARR=8). . . . .460
Figure 147. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .461
Figure 148. Combined PWM mode on channels 1 and 3 . . . . .462
Figure 149. Clearing TIMx OCxREF . . . . .463
Figure 150. Example of one-pulse mode. . . . .464
Figure 151. Retriggerable one-pulse mode. . . . .466
Figure 152. Example of counter operation in encoder interface mode . . . . .467
Figure 153. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .468
Figure 154. Control circuit in reset mode . . . . .469
Figure 155. Control circuit in gated mode . . . . .470
Figure 156. Control circuit in trigger mode . . . . .471
Figure 157. Control circuit in external clock mode 2 + trigger mode . . . . .472
Figure 158. Master/Slave timer example . . . . .472
Figure 159. Master/slave connection example with 1 channel only timers . . . . .473
Figure 160. Gating TIMz with OC1REF of TIMy . . . . .474
Figure 161. Gating TIMz with Enable of TIMy . . . . .475
Figure 162. Triggering TIMz with update of TIMy . . . . .475
Figure 163. Triggering TIMz with Enable of TIMy . . . . .476
Figure 164. Triggering TIMy and TIMz with TIMy TI1 input . . . . .477
Figure 165. Basic timer block diagram . . . . .508
Figure 166. Counter timing diagram with prescaler division change from 1 to 2 . . . . .510
Figure 167. Counter timing diagram with prescaler division change from 1 to 4 . . . . .510
Figure 168. Counter timing diagram, internal clock divided by 1 . . . . .511
Figure 169. Counter timing diagram, internal clock divided by 2 . . . . .512
Figure 170. Counter timing diagram, internal clock divided by 4 . . . . .512
Figure 171. Counter timing diagram, internal clock divided by N . . . . .513
Figure 172. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .513
Figure 173. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .514
Figure 174. Control circuit in normal mode, internal clock divided by 1 . . . . .515
Figure 175. General-purpose timer block diagram (TIM14). . . . .522
Figure 176. Counter timing diagram with prescaler division change from 1 to 2 . . . . .524
Figure 177. Counter timing diagram with prescaler division change from 1 to 4 . . . . .524
Figure 178. Counter timing diagram, internal clock divided by 1 . . . . .525
Figure 179. Counter timing diagram, internal clock divided by 2 . . . . .526
Figure 180. Counter timing diagram, internal clock divided by 4 . . . . .526
Figure 181. Counter timing diagram, internal clock divided by N . . . . .527
Figure 182. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .527
Figure 183. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .528
Figure 184. Control circuit in normal mode, internal clock divided by 1 . . . . .529
Figure 185. Capture/compare channel (example: channel 1 input stage). . . . .529
Figure 186. Capture/compare channel 1 main circuit . . . . .530
Figure 187. Output stage of capture/compare channel (channel 1). . . . .530
Figure 188. Output compare mode, toggle on OC1. . . . .533
Figure 189. Edge-aligned PWM waveforms (ARR=8). . . . .534
Figure 190. TIM15 block diagram . . . . .549
Figure 191. TIM16/TIM17 block diagram . . . . .550
Figure 192. Counter timing diagram with prescaler division change from 1 to 2 . . . . .552
Figure 193. Counter timing diagram with prescaler division change from 1 to 4 . . . . .552
Figure 194. Counter timing diagram, internal clock divided by 1 . . . . .554
Figure 195. Counter timing diagram, internal clock divided by 2 . . . . .554
Figure 196. Counter timing diagram, internal clock divided by 4 . . . . .555
Figure 197. Counter timing diagram, internal clock divided by N . . . . .555
Figure 198. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .556
Figure 199. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .556
Figure 200. Update rate examples depending on mode and TIMx_RCR register settings . . . . .558
Figure 201. Control circuit in normal mode, internal clock divided by 1 . . . . .559
Figure 202. TI2 external clock connection example. . . . .559
Figure 203. Control circuit in external clock mode 1 . . . . .560
Figure 204. Capture/compare channel (example: channel 1 input stage) . . . . .561
Figure 205. Capture/compare channel 1 main circuit . . . . .561
Figure 206. Output stage of capture/compare channel (channel 1). . . . .562
Figure 207. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .562
Figure 208. PWM input mode timing . . . . .564
Figure 209. Output compare mode, toggle on OC1 . . . . .566
Figure 210. Edge-aligned PWM waveforms (ARR=8) . . . . .567
Figure 211. Combined PWM mode on channel 1 and 2 . . . . .568
Figure 212. Complementary output with dead-time insertion. . . . .569
Figure 213. Dead-time waveforms with delay greater than the negative pulse. . . . .569
Figure 214. Dead-time waveforms with delay greater than the positive pulse. . . . .570
Figure 215. Break circuitry overview . . . . .572
Figure 216. Output behavior in response to a break . . . . .574
Figure 217. Output redirection . . . . .576
Figure 218. Example of one pulse mode . . . . .578
Figure 219. Retriggerable one pulse mode . . . . .579
Figure 220. Measuring time interval between edges on 2 signals . . . . .581
Figure 221. Control circuit in reset mode . . . . .582
Figure 222. Control circuit in gated mode . . . . .583
Figure 223. Control circuit in trigger mode . . . . .584
Figure 224. IRTIM internal hardware connections . . . . .634
Figure 225. Independent watchdog block diagram . . . . .635
Figure 226. Watchdog block diagram . . . . .645
Figure 227. Window watchdog timing diagram . . . . .646
Figure 228. RTC block diagram . . . . .651
Figure 229. TAMP block diagram . . . . .690
Figure 230. I2C1 block diagram . . . . .706
Figure 231. I2C2 block diagram . . . . .707
Figure 232. I2C bus protocol . . . . .709
Figure 233. Setup and hold timings . . . . .711
Figure 234. I2C initialization flowchart . . . . .714
Figure 235. Data reception . . . . .715
Figure 236. Data transmission . . . . .716
Figure 237. Slave initialization flowchart . . . . .719
Figure 238. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 0 . . . . .		721
Figure 239. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 1 . . . . .		722
Figure 240. Transfer bus diagrams for I2C slave transmitter. . . . .723
Figure 241. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . .724
Figure 242. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . .725
Figure 243. Transfer bus diagrams for I2C slave receiver . . . . .725
Figure 244. Master clock generation . . . . .727
Figure 245. Master initialization flowchart . . . . .729
Figure 246. 10-bit address read access with HEAD10R=0 . . . . .729
Figure 247. 10-bit address read access with HEAD10R=1 . . . . .730
Figure 248. Transfer sequence flowchart for I2C master transmitter for \( N \leq 255 \) bytes . . . . .731
Figure 249. Transfer sequence flowchart for I2C master transmitter for \( N > 255 \) bytes . . . . .732
Figure 250. Transfer bus diagrams for I2C master transmitter . . . . .733
Figure 251. Transfer sequence flowchart for I2C master receiver for \( N \leq 255 \) bytes . . . . .735
Figure 252. Transfer sequence flowchart for I2C master receiver for \( N > 255 \) bytes . . . . .736
Figure 253. Transfer bus diagrams for I2C master receiver . . . . .737
Figure 254. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .742
Figure 255. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . .746
Figure 256. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .746
Figure 257. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . .748
Figure 258. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . .749
Figure 259. Bus transfer diagrams for SMBus master transmitter . . . . .750
Figure 260. Bus transfer diagrams for SMBus master receiver . . . . .752
Figure 261. USART block diagram . . . . .779
Figure 262. Word length programming . . . . .782
Figure 263. Configurable stop bits . . . . .784
Figure 264. TC/TXE behavior when transmitting . . . . .787
Figure 265. Start bit detection when oversampling by 16 or 8. . . . .788
Figure 266. usart_ker_ck clock divider block diagram . . . . .791
Figure 267. Data sampling when oversampling by 16 . . . . .792
Figure 268. Data sampling when oversampling by 8 . . . . .793
Figure 269. Mute mode using Idle line detection . . . . .800
Figure 270. Mute mode using address mark detection . . . . .801
Figure 271. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .804
Figure 272. Break detection in LIN mode vs. Framing error detection. . . . .805
Figure 273. USART example of synchronous master transmission. . . . .806
Figure 274. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		806
Figure 275. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		807
Figure 276. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		808
Figure 277. ISO 7816-3 asynchronous protocol . . . . .810
Figure 278. Parity error detection using the 1.5 stop bits . . . . .812
Figure 279. IrDA SIR ENDEC block diagram. . . . .816
Figure 280. IrDA data modulation (3/16) - Normal mode. . . . .816
Figure 281. Transmission using DMA . . . . .818
Figure 282. Reception using DMA . . . . .819
Figure 283. Hardware flow control between 2 USARTs . . . . .819
Figure 284. RS232 RTS flow control . . . . .820
Figure 285. RS232 CTS flow control . . . . .821
Figure 286. Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . .824
Figure 287. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . .		824
Figure 288. SPI block diagram. . . . .865
Figure 289. Full-duplex single master/ single slave application. . . . .866
Figure 290. Half-duplex single master/ single slave application . . . . .867
Figure 291. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		868
Figure 292. Master and three independent slaves. . . . .869
Figure 293. Multi-master application . . . . .870
Figure 294. Hardware/software slave select management . . . . .871
Figure 295. Data clock timing diagram . . . . .872
Figure 296. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .873
Figure 297. Packing data in FIFO for transmission and reception . . . . .877
Figure 298. Master full-duplex communication . . . . .880
Figure 299. Slave full-duplex communication . . . . .881
Figure 300. Master full-duplex communication with CRC . . . . .882
Figure 301. Master full-duplex communication in packed mode . . . . .883
Figure 302. NSSP pulse generation in Motorola SPI master mode . . . . .886
Figure 303. TI mode transfer . . . . .887
Figure 304. I2S block diagram . . . . .890
Figure 305. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .892
Figure 306. I 2 S Philips standard waveforms (24-bit frame) . . . . .892
Figure 307. Transmitting 0x8EAA33 . . . . .893
Figure 308. Receiving 0x8EAA33 . . . . .893
Figure 309. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .893
Figure 310. Example of 16-bit data frame extended to 32-bit channel frame . . . . .893
Figure 311. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .894
Figure 312. MSB justified 24-bit frame length . . . . .894
Figure 313. MSB justified 16-bit extended to 32-bit packet frame . . . . .895
Figure 314. LSB justified 16-bit or 32-bit full-accuracy . . . . .895
Figure 315. LSB justified 24-bit frame length . . . . .895
Figure 316. Operations required to transmit 0x3478AE. . . . .896
Figure 317. Operations required to receive 0x3478AE . . . . .896
Figure 318. LSB justified 16-bit extended to 32-bit packet frame . . . . .896
Figure 319. Example of 16-bit data frame extended to 32-bit channel frame . . . . .897
Figure 320. PCM standard waveforms (16-bit) . . . . .897
Figure 321. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .898
Figure 322. Start sequence in master mode . . . . .899
Figure 323. Audio sampling frequency definition . . . . .900
Figure 324. I 2 S clock generator architecture . . . . .900
Figure 325. USB peripheral block diagram . . . . .921
Figure 326. Packet buffer areas with examples of buffer description table locations . . . . .927
Figure 327. Block diagram of STM32G0x0 MCU and Cortex ® -M0+-level debug support . . . . .966

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