41. Revision history

Table 293. Document revision history

Date	Revision	Changes
5-Nov-2020	1	Initial version
24-Jun-2021	2	Updated: – Patented technology and errata sheet in the Introduction – Section 4.3.2: Empty check – OPTVAL in Section 4.4.2: Option bytes programming – OPTNV description in Section 4.10.5: FLASH status register (FLASH_SR) – Section 5.1: Sub-GHz radio introduction – Section 5.2: Sub-GHz radio main features – Section 5.5.5: Generic framing – New functionality in Section 5.6: Sub-GHz radio data buffer – Section 5.7.2: Sleep mode – Note removed in Set_RfFrequency() command – Section 5.9: Sub-GHz radio application configuration – Danger note removed in Section 5.10: Sub-GHz radio registers – Section 5.10.22: Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR) – Figure 20: Brownout reset waveform – PVD naming in Section 6.6.2: PWR control register 2 (PWR_CR2) and Section 6.6.6: Power status register 2 (PWR_SR2) – First sentence in Section 7.1.2: System reset – External source (HSE32 TXCO) – First sentence of Section 8.4: HSEM registers – Caution in Section 14.4.6: DMAMUX request line multiplexer – Note in Section 14.4.7: DMAMUX request generator – New note in Polynomial programmability – Figure 58: ADC block diagram – Formula in Figure 22.5: RNG processing time – Table 127: Interrupt control bits – Table 134: CTR mode initialization vector definition – Table 137: Initialization of AES_IVRx registers in CCM mode – Section 24.3.4: PKA public key acceleration – Table 149: Montgomery multiplication – Section 24.5: Example of configurations and processing times – Table 174: PKA interrupt requests – AFIO renamed in Section 26: General-purpose timer (TIM2) – New note in Section 28.4.7: Trigger multiplexer – Some bit descriptions in Section 28.7.2: LPTIM interrupt clear register (LPTIM_ICR) – Table 248: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz

Table 293. Document revision history (continued)

Date	Revision	Changes
19-Apr-2022	3	Updated: – Section 4.3.1: Flash memory organization – Section 5.1: Sub-GHz radio introduction – Section 5.2: Sub-GHz radio main features – Section 5.5.3: FSK modem – Figure 13: Generic packet frames format – Section 5.5.7: BPSK framing – Table 36: Recommended CAD configuration settings – LoRa Set_LoRaSymbTimeout() command – Get_RxBufferStatus() command – New registers in Section 5.10: Sub-GHz radio registers – SMPSEN desc in Section 6.6.8: PWR control register 5 (PWR_CR5) – Section 18.3.3: Calibration (ADCAL) – Section 18.3.7: Configuring the ADC – Notes in Section 18.12.4: ADC configuration register 1 (ADC_CFGR1) and Section 18.12.5: ADC configuration register 2 (ADC_CFGR2) – Health checks – Section 22.3.4: RNG initialization – Section 22.5: RNG processing time – Section 22.6.2: Validation conditions – RNDATA desc in Section 22.7.3: RNG data register (RNG_DR) – Section 23.4.16: AES DMA interface – Note in Section 25.3.16: Using the break function – Section 25.4.4: TIM1 DMA/interrupt enable register (TIM1_DIER) – Note in Section 27.3.12: Bidirectional break inputs – Section 27.3.13: 6-step PWM generation – Note on Section 32.6.1: RTC time register (RTC_TR) – New Section 40: Important security notice
16-Nov-2022	4	Updated: – Table 31: Sub-GHz radio transmit high output power – Table 35: LoRa bandwidth setting – Table 39: PA optimal setting and operating modes – Register names from Section 5.13.69 to Section 5.13.76: Sub-GHz radio generic synchronization word control register 7 (SUBGHZ_GSYNCR7) – Address offset of Section 5.13.167: Sub-GHz radio AGC RSSI control register (SUBGHZ_AGCRSSICTL0R) – New Section 5.13.238: Sub-GHz radio regulator drive control register (SUBGHZ_REGDRVCR) – RFEOLF description in Section 6.6.6: Power status register 2 (PWR_SR2) – SVCall description in Table 91: CPU1 vector table – HSEM description in Table 92: CPU2 vector table – DAC_DHR8RD, DAC_DHR12RD, and DAC_DHR12LD registers removed in Section 19: Digital-to-analog converter (DAC)
12-Jan-2023	5	Updated Section 7.2: Clocks , Section 7.2.12: SPI2S2 clock , Section 38.10.2: ITM trace enable register (ITM_TER) , and Section 38.10.3: ITM trace privilege register (ITM_TPR) . Minor text edits across the whole document.

Table 293. Document revision history (continued)

Date

Revision

Changes

22-Oct-2024

6

Updated Table 11: Flash memory - Single bank organization and Table 131: RNG configurations .

Updated Get_RssiInst() command , Section 18.3.5: ADC clock (CKMODE, PRESC[3:0]) , Section 18.12.5: ADC configuration register 2 (ADC_CFGR2) , Section 19.4.12: DAC channel buffer calibration , Section 32.3.4: Clock and prescalers , Section 32.6.18: RTC status register (RTC_SR) , Section 32.6.19: RTC masked interrupt status register (RTC_MISR) , Section 34.4: I2C functional description and its subsections.

Updated Figure 13: Generic packet frames format , Figure 59: ADC calibration , Figure 60: Calibration factor forcing , Figure 61: Enabling/disabling the ADC , Figure 62: ADC clock scheme , Figure 64: Analog-to-digital conversion time , Figure 66: Stopping an ongoing conversion , Figure 79: ADC_AWDx_OUT signal generation (on a single channel) , Figure 262: Low-power timer block diagram , Figure 271: Independent watchdog block diagram , Figure 282: Slave initialization flow , and Figure 333: LPUART block diagram .

Added Table 132: Configuration selection , Table 241: USART/UART input/output pins , Table 242: USART internal input/output signals , Table 251: LPUART input/output pins , and Table 252: LPUART internal input/output signals .

Minor text edits across the whole document.