15. Nested vectored interrupt controller (NVIC)

15.1 NVIC main features

CPU1 NVIC features:

• 62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt lines)
• 16 programmable priority levels (four bits of interrupt priority used)
• Low-latency exception interrupt handling
• Power management control
• Implementation of system control registers

CPU2 NVIC features:

• 32 maskable interrupt channels (not including the sixteen Cortex ^®-M0+ interrupt lines)
• Four programmable priority levels (two bits of interrupt priority used)
• Low-latency exception interrupt handling
• Power management control

The NVICs and the processor cores interfaces are closely coupled, resulting in low-latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC.

For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for Cortex ^®-M4 (PM0214), and programming manual for Cortex ^®-M0+ (PM0223).

15.2 Interrupt block diagram

The different peripheral interrupts are connected in different ways, depending on the sharing between the two CPUs.

To prevent a peripheral or EXTI interrupt to trigger both CPUs, they can be masked either in the NVIC, or, for the NVIC vector sharing multiple peripheral interrupts, by a pre-mask in the SYSCFG registers (see Section 11: System configuration controller (SYSCFG) ).

The interrupt block diagram is shown in the figure below.

Figure 53. Interrupt block diagram

Interrupt block diagram showing connections between Peripherals, AIEC, SYSCFG (C1IMRn, C2IMRn), and CPUs (CPU1, CPU2) via NVIC blocks. The diagram shows various interrupt sources connected to the NVIC for two CPUs. Peripherals and AIEC are connected directly to the NVIC. Some peripherals are also connected to the SYSCFG block, which contains C1IMRn and C2IMRn registers that then connect to the NVIC for CPU1 and CPU2 respectively.

15.3 Interrupt and exception vectors

The CPU1 and CPU2 vector tables are given respectively in Table 89 and Table 90 (shaded cells indicate the processor exceptions).

Table 89. CPU1 vector table

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
-	-	-	-	Reserved	0x0000 0000
-	-3	Fixed	Reset	Reset	0x0000 0004
-	-2	Fixed	NMI	Non maskable interrupt HSE32 CSS, flash ECC and SRAM2 parity	0x0000 0008
-	-1	Fixed	HardFault	All classes of fault	0x0000 000C
-	0	Settable	MemManager	Memory manager	0x0000 0010
-	1	Settable	BusFault	Prefetch fault, memory access fault	0x0000 0014
-	2	Settable	UsageFault	Undefined instruction or illegal state	0x0000 0018
-	-	-	-	Reserved	0x0000 001C 0x0000 0028
-	3	Settable	SVCall	System service call via SWI instruction	0x0000 002C
-	4	Settable	Debug	Debug monitor	0x0000 0030
-	-	-	-	Reserved	0x0000 0034

Table 89. CPU1 vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
-	5	Settable	PendSV	Pendable request for system service	0x0000 0038
-	6	Settable	SysTick	SysTick timer	0x0000 003C
0	7	Settable	WWDG	Window watchdog early wake-up	0x0000 0040
1	8	Settable	PVD, PWM[3]	PVD through EXTI[16] (IMR2[20]) PWM[3] through EXTI[34] (IMR2[18])	0x0000 0044
2	9	Settable	TAMP, RTC_STAMP, LSE_CSS, RTC_SSRU	TAMP tamper RTC timestamp LSE CSS interrupt (IMR1[0]) RTC SSR underflow interrupt (IMR1[2])	0x0000 0048
3	10	Settable	RTC_WKUP	RTC wake-up interrupt	0x0000 004C
4	11	Settable	FLASH	Flash memory global interrupt and flash memory ECC single error interrupt	0x0000 0050
5	12	Settable	RCC	RCC global interrupt	0x0000 0054
6	13	Settable	EXTI0	EXTI line 0 interrupt through EXTI[0]	0x0000 0058
7	14	Settable	EXTI1	EXTI line 1 interrupt through EXTI[1]	0x0000 005C
8	15	Settable	EXTI2	EXTI line 2 interrupt through EXTI[2]	0x0000 0060
9	16	Settable	EXTI3	EXTI line 3 interrupt through EXTI[3]	0x0000 0064
10	17	Settable	EXTI4	EXTI line 4 interrupt through EXTI[4]	0x0000 0068
11	18	Settable	DMA1_CH1	DMA1 channel 1 non-secure interrupt	0x0000 006C
12	19	Settable	DMA1_CH2	DMA1 channel 2 non-secure interrupt	0x0000 0070
13	20	Settable	DMA1_CH3	DMA1 channel 3 non-secure interrupt	0x0000 0074
14	21	Settable	DMA1_CH4	DMA1 channel 4 non-secure interrupt	0x0000 0078
15	22	Settable	DMA1_CH5	DMA1 channel 5 non-secure interrupt	0x0000 007C
16	23	Settable	DMA1_CH6	DMA1 channel 6 non-secure interrupt	0x0000 0080
17	24	Settable	DMA1_CH7	DMA1 channel 7 non-secure interrupt	0x0000 0084
18	25	Settable	ADC	ADC global interrupt	0x0000 0088
19	26	Settable	DAC	DAC global interrupt	0x0000 008C
20	27	Settable	C2SEV, PWR_C2H	CPU2 SEV through EXTI[40] PWR CPU2 HOLD wake-up interrupt	0x0000 0090
21	28	Settable	COMP	COMP2 and COMP1 interrupt through EXTI[22:21]	0x0000 0094
22	29	Settable	EXTI[9:5]	EXTI line [9:5] interrupt through EXTI[9:5] (IMR1[25:21])	0x0000 0098
23	30	Settable	TIM1_BRK	Timer 1 break interrupt	0x0000 009C
24	31	Settable	TIM1_UP	Timer 1 Update	0x0000 00A0
25	32	Settable	TIM1_TRG_COM	Timer 1 trigger and communication	0x0000 00A4
26	33	Settable	TIM1_CC	Timer 1 capture compare interrupt	0x0000 00A8

Table 89. CPU1 vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
27	34	Settable	TIM2	Timer 2 global interrupt	0x0000 00AC
28	35	Settable	TIM16	Timer 16 global interrupt	0x0000 00B0
29	36	Settable	TIM17	Timer 17 global interrupt	0x0000 00B4
30	37	Settable	I2C1_EV	I2C1 event interrupt	0x0000 00B8
31	38	Settable	I2C1_ER	I2C1 error interrupt	0x0000 00BC
32	39	Settable	I2C2_EV	I2C2 event interrupt	0x0000 00C0
33	40	Settable	I2C2_ER	I2C2 error interrupt	0x0000 00C4
34	41	Settable	SPI1	SPI1 global interrupt	0x0000 00C8
35	42	Settable	SPI2S2	SPI2S2 global interrupt	0x0000 00CC
36	43	Settable	USART1	USART1 global interrupt	0x0000 00D0
37	44	Settable	USART2	USART2 global interrupt	0x0000 00D4
38	45	Settable	LPUART1	LPUART1 global interrupt	0x0000 00D8
39	46	Settable	LPTIM1	LP timer 1 global interrupt	0x0000 00DC
40	47	Settable	LPTIM2	LP timer 2 global interrupt	0x0000 00E0
41	48	Settable	EXTI[15:10]	EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26])	0x0000 00E4
42	49	Settable	RTC_ALARM	RTC alarms A and B interrupt	0x0000 00E8
43	50	Settable	LPTIM3	LP timer 3 global interrupt	0x0000 00EC
44	51	Settable	Reserved	Reserved	0x0000 00F0
45	52	Settable	IPCC_C1_RX_IT	IPCC CPU1 RX occupied interrupt	0x0000 00F4
46	53	Settable	IPCC_C1_TX_IT	IPCC CPU1 TX free interrupt	0x0000 00F8
47	54	Settable	HSEM	Semaphore interrupt 0 to CPU1	0x0000 00FC
48	55	Settable	I2C3_EV	I2C3 event interrupt	0x0000 0100
49	56	Settable	I2C3_ER	I2C3 error interrupt	0x0000 0104
50	57	Settable	Radio IRQ, Busy	Radio IRQs RFBUSY interrupt through EXTI[45]	0x0000 0108
51	58	Settable	AES	AES global interrupt	0x0000 010C
52	59	Settable	True RNG	True random number generator interrupt	0x0000 0110
53	60	Settable	PKA	Private key accelerator interrupt	0x0000 0114
54	61	Settable	DMA2_CH1	DMA2 channel 1 non-secure interrupt	0x0000 0118
55	62	Settable	DMA2_CH2	DMA2 channel 2 non-secure interrupt	0x0000 011C
56	63	Settable	DMA2_CH3	DMA2 channel 3 non-secure interrupt	0x0000 0120
57	64	Settable	DMA2_CH4	DMA2 channel 4 non-secure interrupt	0x0000 0124
58	65	Settable	DMA2_CH5	DMA2 channel 5 non-secure interrupt	0x0000 0128

Table 89. CPU1 vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
59	66	Settable	DMA2_CH6	DMA2 channel 6 non-secure interrupt	0x0000 012C
60	67	Settable	DMA2_CH7	DMA2 channel 7 non-secure interrupt	0x0000 0130
61	68	Settable	DMAMUX1_OVR	DMAMUX1 overrun interrupt	0x0000 0134

1. IMRx[n] refer to the pre-mask bit[n] in SYSCFG_IMRx register.

2. EXTI[n] refer to the input event number [n] of the EXTI.

Table 90. CPU2 vector table

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
-	-	-	-	Reserved	0x0000 0000
-	-3	Fixed	Reset	Reset	0x0000 0004
-14	-2	Fixed	NMI	Non maskable interrupt HSE CSS, flash ECC and SRAM2 parity	0x0000 0008
-13	-1	Fixed	HardFault	All classes of fault	0x0000 000C
-	-	-	-	Reserved	0x0000 0010 0x0000 0028
-5	0	Settable	SVCall	System service call via SWI instruction	0x0000 002C
-	-	-	-	Reserved	0x0000 0030 0x0000 0034
-2	1	Settable	PendSV	Pendable request for system service	0x0000 0038
-1	2	Settable	SysTick	System tick timer	0x0000 003C
0	3	Settable	TZIC_ILA	Security Interrupt controller illegal access interrupt	0x0000 0040
1	4	Settable	PVD, PVM[3]	PVD through EXTI[16] (C2IMR2[20]) PVM[3] through EXTI[34] (C2IMR2[18])	0x0000 0044
2	5	Settable	TAMP, RTC_STAMP, LSE_CSS, RTC_ALARM, RTC_SSRU, RTC_WKUP	TAMP tamper RTC timestamp LSE CSS interrupt (C2IMR1[0]) RTC alarms A and B interrupt (C2IMR1[1]) RTC SSR underflow interrupt (C2IMR1[2]) RTC wake-up interrupt (C2IMR1[3])	0x0000 0048
3	6	Settable	RCC, FLASH, C1SEV	RCC global interrupt (C2IMR1[5]) Flash memory global interrupt and flash memory ECC single error interrupt (C2IMR1[6]) CPU1 SEV through EXTI[41]	0x0000 004C
4	7	Settable	EXTI[1:0]	EXTI line 1:0 interrupt through EXTI[1:0] (C2IMR1[17:16])	0x0000 0050
5	8	Settable	EXTI[3:2]	EXTI line 3:2 interrupt through EXTI[3:2] (C2IMR1[19:18])	0x0000 0054

Table 90. CPU2 vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
6	9	Settable	EXTI[15:4]	EXTI line 15:4 interrupt through EXTI[15:4] (C2IMR1[31:20])	0x0000 0058
7	10	Settable	COMP, ADC, DAC	COMP1 and COMP2 interrupt through EXTI[22:21] (C2IMR1[11]) ADC global interrupt (C2IMR1[12]) DAC global interrupt (C2IMR1[13])	0x0000 005C
8	11	Settable	DMA1_CH[3:1]	DMA1 channel 3:1 secure and non-secure interrupt (C2IMR2[2:0])	0x0000 0060
9	12	Settable	DMA1_CH[7:4]	DMA1 channel 7:4 secure and non-secure interrupt (C2IMR2[6:3])	0x0000 0064
10	13	Settable	DMA2_CH[7:1], DMAMUX1_OVR	DMA2 channel 7:1 secure and non-secure interrupt (C2IMR2[14:8]) DMAMUX1 overrun interrupt (C2IMR2[15])	0x0000 0068
11	14	Settable	LPTIM1	LPTimer 1 global interrupt	0x0000 006C
12	15	Settable	LPTIM2	LPTimer 2 global interrupt	0x0000 0070
13	16	Settable	LPTIM3	LPTimer 3 global interrupt	0x0000 0074
14	17	Settable	TIM1_BRK, TIM1_UP, TIM1_TRG_COM, TIM1_CC	Timer 1 break Timer 1 update Timer 1 trigger and communication Timer 1 capture compare interrupt	0x0000 0078
15	18	Settable	TIM2	Timer 2 global interrupt	0x0000 007C
16	19	Settable	TIM16	Timer 16 global interrupt	0x0000 0080
17	20	Settable	TIM17	Timer 17 global interrupt	0x0000 0084
18	21	Settable	IPCC_C2_RX_IT IPCC_C2_TX_IT	IPCC CPU2 RX occupied interrupt IPCC CPU2 TX free interrupt	0x0000 0088
19	22	Settable	HSEM	Semaphore interrupt to CPU2	0x0000 008C
20	23	Settable	True RNG	True random number generator interrupt	0x0000 0090
21	24	Settable	AES PKA	AES global interrupt (C2IMR1[10]) Private key accelerator interrupt (C2IMR1[8])	0x0000 0094
22	25	Settable	I2C1_EV I2C1_ER	I2C1 event interrupt I2C1 error interrupt	0x0000 0098
23	26	Settable	I2C2_EV I2C2_ER	I2C2 event interrupt I2C2 error interrupt	0x0000 009C
24	27	Settable	I2C3_EV I2C3_ER	I2C3 event interrupt I2C3 error interrupt	0x0000 00A0
25	28	Settable	SPI1	SPI1 global interrupt	0x0000 00A4
26	29	Settable	SPI2S2	SPI2S2 global interrupt	0x0000 00A8
27	30	Settable	USART1	USART1 global interrupt	0x0000 00AC

Table 90. CPU2 vector table (continued)

Position	Priority	Type of priority	Acronym	Description ⁽¹⁾⁽²⁾	Address
28	31	Settable	USART2	USART2 global interrupt	0x0000 00B0
29	32	Settable	LPUART1	LPUART1 global interrupt	0x0000 00B4
30	33	Settable	SUBGHZSPI	Sub-GHz radio SPI global interrupt	0x0000 00B8
31	34	Settable	Radio IRQ Busy	Radio IRQs RFBUSY interrupt through EXTI[45]	0x0000 00BC

1. C2IMRx[n] refer to the pre-mask bit[n] in SYSCFG_C2IMRx register.

2. EXTI[n] refer to the input event number [n] of the EXTI.