11. System configuration controller (SYSCFG)

11.1 SYSCFG main features

STM32WL5x devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Remapping memory areas
• • Managing the external interrupt line connection to the GPIOs
• • Managing robustness feature
• • Setting SRAM2 write protection and SRAM2 software erase
• • SRAM1, SRAM2 and PKA SRAM erase busy flags
• • Enabling /disabling I ² C Fast-mode Plus driving capability on some I/Os and voltage booster for I/Os analog switches.
• • Interrupt pre-masking

11.2 SYSCFG registers

11.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap.

Address offset: 0x000

Reset value: 0x0000 000X

MEM_MODE[2:0] is the memory mode selected by the BOOT0 pin and BOOT1 option bit.

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 MEM_MODE[2:0] : memory mapping selection

These bits control the memory internal mapping at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT mode setting. After reset, these bits take the value selected by BOOT0 (pin or option bit depending on nSWBOOT0 option bit) and BOOT1 option bit.

000: Main flash memory mapped at CPU1 0x00000000

001: System flash memory mapped at CPU1 0x00000000

010: Reserved

011: SRAM1 mapped at CPU1 0x00000000

100: Reserved

101: Reserved

110: Reserved

111: Reserved

11.2.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x004

Reset value: 0x7C00 0001

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 I2C3_FMP : I2C3 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.

Bit 21 I2C2_FMP : I2C2 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C2 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.

Bit 20 I2C1_FMP : I2C1 Fast-mode Plus driving capability activation

This bit enables the Fm+ driving mode on I2C1 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.

Bit 19 I2C_PB9_FMP : Fast-mode Plus (Fm+) driving capability activation on PB9

This bit enables the Fm+ driving mode for PB9.

0: PB9 pin operates in standard mode.

1: Fm+ mode enabled on PB9 pin, and the speed control is bypassed.

Bit 18 I2C_PB8_FMP : Fast-mode Plus (Fm+) driving capability activation on PB8

This bit enables the Fm+ driving mode for PB8.

0: PB8 pin operates in standard mode.

1: Fm+ mode enabled on PB8 pin, and the speed control is bypassed.

Bit 17 I2C_PB7_FMP : Fast-mode Plus (Fm+) driving capability activation on PB7

This bit enables the Fm+ driving mode for PB7.

0: PB7 pin operates in standard mode.

1: Fm+ mode enabled on PB7 pin, and the speed control is bypassed.

Bit 16 I2C_PB6_FMP : Fast-mode Plus (Fm+) driving capability activation on PB6

This bit enables the Fm+ driving mode for PB6.

0: PB6 pin operates in standard mode.

1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed.

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 BOOSTEN : I/O analog switch voltage booster enable

0: I/O analog switches are supplied by \( V_{DDA} \) voltage. This is the recommended configuration when using the ADC in high \( V_{DDA} \) voltage operation.

1: I/O analog switches are supplied by a dedicated voltage booster (supplied by \( V_{DD} \) ). This is the recommended configuration when using the ADC in low \( V_{DDA} \) voltage operation.

Bits 7:0 Reserved, must be kept at reset value.

11.2.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI3[2:0] : EXTI3 configuration bits

These bits are written by software to select the source input for the EXTI3 external interrupt.

000: PA3 pin

001: PB3 pin

010: PC3 pin

111: PH3 pin

Others: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI2[2:0] : EXTI2 configuration bits

These bits are written by software to select the source input for the EXTI2 external interrupt.

000: PA2 pin

001: PB2 pin

010: PC2 pin

Others: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI1[2:0] : EXTI1 configuration bits

These bits are written by software to select the source input for the EXTI1 external interrupt.

000: PA1 pin

001: PB1 pin

010: PC1 pin

Others: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI0[2:0] : EXTI0 configuration bits

These bits are written by software to select the source input for the EXTI0 external interrupt.

000: PA0 pin

001: PB0 pin

010: PC0 pin

Others: Reserved

Note: Some of the I/O pins mentioned in this register may not be available on small packages.

11.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x00C

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI7[2:0] : EXTI7 configuration bits

These bits are written by software to select the source input for the EXTI7 external interrupt.

000: PA7 pin

001: PB7 pin

Others: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI6[2:0] : EXTI6 configuration bits

These bits are written by software to select the source input for the EXTI6 external interrupt.

000: PA6 pin

001: PB6 pin

010: PC6 pin

Others: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI5[2:0] : EXTI5 configuration bits

These bits are written by software to select the source input for the EXTI5 external interrupt.

000: PA5 pin

001: PB5 pin

010: PC5 pin

Others: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI4[2:0] : EXTI4 configuration bits

These bits are written by software to select the source input for the EXTI4 external interrupt.

000: PA4 pin

001: PB4 pin

010: PC4 pin

Others: Reserved

Note: Some of the I/O pins mentioned in this register may not be available on small packages.

11.2.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI11[2:0] : EXTI11 configuration bits

These bits are written by software to select the source input for the EXTI11 external interrupt.

000: PA11 pin

001: PB11 pin

Others: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI10[2:0] : EXTI10 configuration bits

These bits are written by software to select the source input for the EXTI10 external interrupt.

000: PA10 pin

001: PB10 pin

Others: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI9[2:0] : EXTI9 configuration bits

These bits are written by software to select the source input for the EXTI9 external interrupt.

000: PA9 pin

001: PB9 pin

Others: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI8[2:0] : EXTI8 configuration bits

These bits are written by software to select the source input for the EXTI8 external interrupt.

000: PA8 pin

001: PB8 pin

Others: Reserved

Note: Some of the I/O pins mentioned in this register may not be available on small packages.

11.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 EXTI15[2:0] : EXTI15 configuration bits

These bits are written by software to select the source input for the EXTI15 external interrupt.

000: PA15 pin

001: PB15 pin

010: PC15 pin

Others: Reserved

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 EXTI14[2:0] : EXTI14 configuration bits

These bits are written by software to select the source input for the EXTI14 external interrupt.

000: PA14 pin

001: PB14 pin

010: PC14 pin

Others: Reserved

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 EXTI13[2:0] : EXTI13 configuration bits

These bits are written by software to select the source input for the EXTI13 external interrupt.

000: PA13 pin

001: PB13 pin

010: PC13 pin

Others: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 EXTI12[2:0] : EXTI12 configuration bits

These bits are written by software to select the source input for the EXTI12 external interrupt.

000: PA12 pin

001: PB12 pin

Others: Reserved

Note: Some of the I/O pins mentioned in this register may not be available on small packages.

11.2.7 SYSCFG SRAM control and status register (SYSCFG_SCSR)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 PKASRAMBSY : PKA SRAM busy by erase operation

0: No PKA SRAM erase operation is ongoing.

1: PKA SRAM erase operation is ongoing.

See Section 2.4: SRAM erase for more information on SRAM erase conditions

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 SRAMBSY : SRAM1 or SRAM2 busy by erase operation

0: No SRAM1 or SRAM2 erase operation is ongoing.

1: SRAM1 or SRAM2 erase operation is ongoing.

See Section 2.4: SRAM erase for more information on SRAM erase conditions

Bit 0 SRAM2ER : SRAM2 erase

Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation.

Note: This bit is write-protected: setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.

11.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x01C

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SPF : SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing '1'.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 ECCL : ECC lock

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the flash ECC error connection to TIM1/16/17 break input.

0: ECC error disconnected from TIM1/16/17 break input.

1: ECC error connected to TIM1/16/17 break input.

Bit 2 PVDL : PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PLS[2:0] in the PWR_CR2R register.

0: PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only.

Bit 1 SPL : SRAM2 parity lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.

0: SRAM2 parity error signal disconnected from TIM1/16/17 break inputs

1: SRAM2 parity error signal connected to TIM1/16/17 break inputs

Bit 0 CLL : CPU1 LOCKUP (Hardfault) output enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of CPU1 LOCKUP (Hardfault) output to TIM1/16/17 break inputs.

0: CPU1 LOCKUP output disconnected from TIM1/16/17 break inputs

1: CPU1 LOCKUP output connected to TIM1/16/17 break inputs

11.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:0 PxWP : SRAM2 1 Kbyte page x write protection (x = 31 to 0)

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1 Kbyte page x is disabled.

1: Write protection of SRAM2 1 Kbyte page x is enabled.

11.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x024

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0] : SRAM2 write protection key for software erase

The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_SCSR register.

1. 1. Write 0xCA into Key[7:0].
2. 2. Write 0x53 into Key[7:0].

Writing a wrong key reactivates the write protection.

11.2.11 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)

Address offset: 0x100

Reset value: 0x0000 0000

Bits 31:21 EXTIxIM : EXTIx interrupt mask to CPU1 (x = 15 to 5)

• 0: EXTIx interrupt forwarded to CPU1
• 1: EXTIx interrupt to CPU1 masked

Bits 20:3 Reserved, must be kept at reset value.

Bit 2 RTCSSRUIM : RTC SSRU interrupt mask to CPU1

• 0: RTC SSRU interrupt forwarded to CPU1
• 1: RTC SSRU interrupt to CPU1 masked

Bit 1 Reserved, must be kept at reset value.

Bit 0 RTCSTAMPTAMPLSECSSIM : RTCSTAMPTAMPLSECSS interrupt mask to CPU1

• 0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU1
• 1: RTCSTAMPTAMPLSECSS interrupt to CPU1 masked

11.2.12 SYSCFG CPU1 interrupt mask register 2 (SYSCFG_IMR2)

Address offset: 0x104

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 PVDIM : PVD interrupt mask to CPU1

0: PVD interrupt forwarded to CPU1

1: PVD interrupt to CPU1 masked

Bit 19 Reserved, must be kept at reset value.

Bit 18 PVM3IM : PVM3 interrupt mask to CPU1

0: PVM3 interrupt forwarded to CPU1

1: PVM3 interrupt to CPU1 masked

Bits 17:0 Reserved, must be kept at reset value.

11.2.13 SYSCFG CPU2 interrupt mask register 1 (SYSCFG_C2IMR1)

Address offset: 0x108

Reset value: 0x0000 0000

Bits 31:16 EXTIxIM : EXTIx interrupt mask to CPU2 (x = 15 to 0)

0: EXTIx interrupt forwarded to CPU2

1: EXTIx interrupt to CPU2 masked

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 DACIM : DAC interrupt mask to CPU2

0: DAC interrupt forwarded to CPU2

1: DAC interrupt to CPU2 masked

1. Bit 12 ADCIM : ADC interrupt mask to CPU2
   0: ADC interrupt forwarded to CPU2
   1: ADC interrupt to CPU2 masked
2. Bit 11 COMPIM : COMP interrupt mask to CPU2
   0: COMP interrupt forwarded to CPU2
   1: COMP interrupt to CPU2 masked.
3. Bit 10 AESIM : AES interrupt mask to CPU2
   0: AES interrupt forwarded to CPU2
   1: AES interrupt to CPU2 masked
4. Bit 9 Reserved, must be kept at reset value.
5. Bit 8 PKAIM : PKA interrupt mask to CPU2
   0: PKA interrupt forwarded to CPU2
   1: PKA interrupt to CPU2 masked
6. Bit 7 Reserved, must be kept at reset value.
7. Bit 6 FLASHIM : FLASH interrupt mask to CPU2
   0: FLASH interrupt forwarded to CPU2
   1: FLASH interrupt to CPU2 masked
8. Bit 5 RCCIM : RCC interrupt mask to CPU2
   0: RCC interrupt forwarded to CPU2
   1: RCC interrupt to CPU2 masked
9. Bit 4 Reserved, must be kept at reset value.
10. Bit 3 RTCWKUPIM : RTCWKUP interrupt mask to CPU2
    0: RTCWKUP interrupt forwarded to CPU2
    1: RTCWKUP interrupt to CPU2 masked
11. Bit 2 RTCSSRUI : RTC SSRU interrupt mask to CPU2
    0: RTC SSRU interrupt forwarded to CPU2
    1: RTC SSRU interrupt to CPU2 masked
12. Bit 1 RTCALARMIM : RTCALARM interrupt mask to CPU2
    0: RTCALARM interrupt forwarded to CPU2
    1: RTCALARM interrupt to CPU2 masked
13. Bit 0 RTCSTAMPTAMPLSECSSIM : RTCSTAMPTAMPLSECSS interrupt mask to CPU2
    0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU2
    1: RTCSTAMPTAMPLSECSS interrupt to CPU2 masked

11.2.14 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)

Address offset: 0x10C

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 PVDIM : PVD interrupt mask to CPU2

• 0: PVD interrupt forwarded to CPU2
• 1: PVD interrupt to CPU2 masked

Bit 19 Reserved, must be kept at reset value.

Bit 18 PVM3IM : PVM3 interrupt mask to CPU2

• 0: PVM3 interrupt forwarded to CPU2
• 1: PVM3 interrupt to CPU2 masked.

Bits 17:16 Reserved, must be kept at reset value.

Bit 15 DMAMUX1IM : DMAMUX1 interrupt mask to CPU2

• 0: DMAMUX1 interrupt forwarded to CPU2
• 1: DMAMUX1 interrupt to CPU2 masked

Bits 14:8 DMA2CHxIM : DMA2CHx interrupt mask to CPU2 (x = 7 to 1)

• 0: DMA2CHx interrupt forwarded to CPU2
• 1: DMA2CHx interrupt to CPU2 masked

Bit 7 Reserved, must be kept at reset value.

Bits 6:0 DMA1CHxIM : DMA1CHx interrupt mask to CPU2 (x = 7 to 1)

• 0: DMA1CHx interrupt forwarded to CPU2
• 1: DMA1CHx interrupt to CPU2 masked

11.2.15 SYSCFG radio debug control register (SYSCFG_RFDCR)

Address offset: 0x208

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 RFTBSEL : radio debug test bus selection

0 Digital test bus selected on RF_ADTB[3:0]

1: Analog test bus selected on RF_ADTB[3:0]

11.2.16 SYSCFG register map

Table 75. SYSCFG register map and reset values

Refer to Section 2.6 for the register boundary addresses.