2. Memory and bus architecture

The following definitions are used in this section:

• • CPU1 = Arm Cortex-M4 with MPU and DSP
• • CPU2 = Arm Cortex-M0+ with MPU

When ESE = 0, CPU2 is non-secure. When ESE = 1, CPU2 is secure.

2.1 System architecture

The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the following masters and slaves:

• • Six masters:
  • – CPU1 core I-bus
  • – CPU1 core D-bus
  • – CPU1 core S-bus
  • – CPU2 core S-bus
  • – DMA1
  • – DMA2
• • Eight slaves:
  • – Internal flash memory on the CPU1 Code bus
  • – Internal flash memory on CPU1 DCode bus
  • – Internal flash memory on CPU2 S bus
  • – Internal SRAM1 (32 Kbytes)
  • – Internal SRAM2 (32 Kbytes)
  • – AHB1 peripherals including AHB to APB bridges and APB peripherals (connected to APB1 and APB2)
  • – AHB2 peripherals
  • – AHB3 peripherals including AHB to APB bridges and APB peripherals (connected to APB3)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously.

This architecture is shown in the figure below.

Figure 1. System architecture

2.1.1 S0: CPU1 I-bus

This bus connects the instruction bus of the CPU1 core to the bus matrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal flash memory, SRAM1 and SRAM2.

2.1.2 S1: CPU1 D-bus

This bus connects the data bus of the CPU1 core to the bus matrix. This bus is used by the core for literal load and debug access. The targets of this bus are the internal flash memory, SRAM1 and SRAM2.

2.1.3 S2: CPU1 S-bus

This bus connects the system bus of the CPU1 core to the bus matrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the SRAM1, SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3.

2.1.4 S3: CPU2 S-bus

This bus connects the system bus of the CPU2 core to the bus matrix. This bus is used by the core to fetch instructions, for literal load and debug access, and access data located in a peripheral or SRAM area. The targets of this bus are the internal flash memory, SRAM1,

SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3 peripherals.

2.1.5 S4, S5: DMA-bus

These buses connect the AHB master interface of the DMAs to the bus matrix. The targets of this bus are the internal flash memory, SRAM1, SRAM2 the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the AHB3 peripherals including the APB3 peripherals.

AHB/APB bridges

The two bridges AHB to APB1 and AHB to APB2 provide full synchronous connections between the AHB1 and the two APB buses, allowing flexible selection of the peripheral frequency.

The bridge AHB to APB3 provides full synchronous connections between the AHB and the APB bus, allowing flexible selection of the frequency between the AHB and peripherals.

Refer to Section 2.6.2: Memory map and register boundary addresses for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled, except for the SRAM1/2 and the flash memory interface. Before using a peripheral, its clock must be enabled in the RCC_AHBxENR and RCC_APBxENR registers.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Boot configuration

Three different CPU1 boot modes and one CPU2 boot mode can be selected through the BOOT0 pin and nBOOT1 bit in the user options.

Boot is furthermore conditioned by the CPU1 boot lock enable, CPU2 boot lock enable and the user flash memory empty check, as shown in the table below.

Table 1. Device boot mode

Table 1. Device boot mode (continued)

1. 1. When engi bytes are invalid or PKA or AES is not available in the product, the SFI/RSS boot firmware installation is not available.
2. 2. Since CPU1 is kept in hold at reset boot, the system is not able to enter low-power modes (Stop, Standby or Shutdown).
3. 3. Warning: If one of the user options FSD, BRSD, or NBRSD are set to "Security enable" or when RDP is not set to Level 0, the device must not be boot in SFI/RSS mode.

Values on BOOT0 and BOOT1 are latched after a reset. It is up to the user to provide the correct value for the required boot mode.

BOOT0 and BOOT1 are also re-sampled when exiting Standby mode. Consequently they must be kept in the required boot mode. After the startup delay, the CPU1 fetches the top-of-stack from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, main flash memory, system flash memory and SRAM1 are accessible as follows:

• • Boot from main flash memory

The main flash memory is aliased in the CPU1 boot memory space at address 0x0000 0000 and is also still accessible from its physical address 0x0800 0000. In other words,

the flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.

• • Boot from system flash memory

The system flash memory is aliased in the CPU1 or CPU2 boot memory space at address 0x0000 0000 and is also still accessible from its physical address 0x1FFF 0000.

• • Boot from SRAM memory

The SRAM memory is aliased in the CPU1 boot memory space at address 0x0000 0000 and is also still accessible from its physical address 0x2000 0000.

CPU1 SRAM physical remap

Following CPU1 boot, the application software can modify the memory map at address 0x0000 0000. This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.

The following memories can be remapped:

• • Main flash memory
• • System flash memory
• • SRAM memory

Embedded bootloader

The embedded bootloader is located in the system flash memory, programmed by STMicroelectronics during production. It is used to program the flash memory using one of the following device interfaces:

• • USART1 on pins PA9 and PA10
• • USART2 on pins PA2 and PA3
• • SPI1 on pins PA4, PA5, PA6 and PA7
• • SPI2S2 on pins PB12, PB13, PB14 and PB15

The embedded bootloader runs on the CPU1 and can be used to load content in non-secure memory areas.

Embedded secure firmware install and root security services

The embedded secure firmware install and root security services (SFI/RSS) are located in the system flash memory, programmed by STMicroelectronics during production. They allow programming of the flash memory with the same device interfaces than the ones used by the embedded bootloader. The embedded SFI/RSS run on the CPU2 and can be used to load content in secure and non-secure memory areas.

2.3 CPU2 boot

Following a device reset when CPU1 boots, CPU2 only boots after CPU1 has set the C2BOOT bit in the power control register 4 (PWR_CR4). The C2BOOT value is retained in Standby modes and CPU2 boots accordingly when exit from Standby.

CPU2 boots from its boot reset vector as defined by the flash memory user option C2OPT and SBRV. CPU2 may boot from anywhere in user flash memory, SRAM1 or SRAM2.

CPU2 system flash boot

CPU2 system flash memory SFI/RSS boot can be selected via BOOT0 and BOOT1.

If, after a reset, the user options are not valid and BOOT0/BOOT1 select CPU1 to boot from the main flash memory, CPU2 boots instead from the system flash memory SFI/RSS.

Note: When Engi bytes are not valid, or PKA or AES is not available in the product, the SFI/RSS boot firmware install is not available.

2.4 SRAM erase

SRAM1, SRAM2 and PKA SRAM provide an SRAM erase feature.

These SRAMs are erased under the conditions detailed in the table below.

Table 2. SRAM erase conditions

1. 1. An ongoing SRAM1 or SRAM2 erase can be monitored by SYSCFG_SCSR.SRAMBSY flag.
2. 2. An ongoing PKA SRAM erase can be monitored by SYSCFG_SCSR.PKASRAMBSY flag.
3. 3. POR, NRST, and wake-up from Standby.
4. 4. For more details, see Table 19: RDP regression from level 1 to level 0 and memory erase .
5. 5. To be able to debug without SRAM erase on tamper, especially ITAM6 debug access, the tamper erase must be disabled in the TAMP by firmware.

2.5 Memory protection

System memory protection (security, privilege, and hide protection) is only available when the system is secure (ESE = 1).

Flash memory, SRAM1 and SRAM2 can be protected by security and privilege at system level in addition to any privilege protection in the CPUs MPU. Security is defined in flash memory user options and privilege is defined in GTZC_TZSC registers.

The security and privilege definition protects the memory areas from being accessed by any non authorized bus master.

The memory protection allows the following areas to be defined within a memory:

• • When memory unprivileged address offset > secure address offset
  • – Secure privileged
  • – Flash memory only: secure privileged and unprivileged read execute only (non base thread mode)
  • – Secure unprivileged
  • – Non-secure unprivileged

Or

• • When memory security address offset > unprivileged address offset
  • – Secure privileged
  • – Flash memory only: non-secure privileged and unprivileged read execute only (non base thread mode)
  • – Non-secure privileged
  • – Non-secure unprivileged

For more information see Section 3.1: GTZC introduction .

Further more a hide protection area can be defined in the flash memory by the hide protection area address offset defined in HDPSA user option.

When enabled, the flash memory area starting from the HDPSA address offset up to the end of the flash memory is hide protected. This means that the area is accessible from device reset or wake up from Standby mode, and can be protected from any access by disabling the hide protection area with the HDPADIS bit in flash memory access control register 2 (FLASF_ACR2).

Memory protection is controlled by the parameters as listed below:

• • Flash memory security address offset is defined in SFSA user option.
  The unprivileged watermark address offset is defined in GTZC_TZSC_MPCWM0.UPWM1LGTH and the privileged and unprivileged, read and execute watermark in address offset defined in GTZC_TZSC_MPCWM0.UPWWM1LGTH.
  • – Flash memory privileged is only available when the flash memory is secure (ESE = 1).
• • SRAM1 security address offset is defined in SNBRSA user option.
  The unprivileged watermark address offset is defined in GTZC_TZSC_MPCWM1.UPWM1LGTH.
  • – SRAM1 security is optional and privilege can be enabled without having security.
• • SRAM2 security address offset is defined in SBRSA user option
  The unprivileged watermark address offset is defined in GTZC_TZSC_MPCWM2.UPWM1LGTH.
  • – SRAM2 security is optional and privilege can be enabled without having security.

When enabled, the memory area starting from the security address offset up to the end of the memory is secure.

When enabled, the unprivileged area starts from the memory base address up to the watermark address offset, and the area above the watermark up to the end of the memory is privileged.

A memory protection example with all different areas is given in Figure 2: Memory protection example . In this example the secure privileged hide protection area is only accessible read, write, execute by the secure privileged bus masters when hide protection area access is enabled in HDPADIS bit.

The secure privileged areas is only accessible read, write, execute by the secure privileged bus masters.

The secure privileged write area is only accessible write by the secure privileged bus masters, and read and execute by the privileged and unprivileged bus masters.

The secure unprivileged areas are accessible read, write, execute by the secure privileged and unprivileged bus masters.

The non-secure unprivileged areas are accessible read write by the secure and non-secure privileged and unprivileged bus masters, and are only accessible execute by the non-secure privileged and unprivileged bus masters.

The secure bus masters are CPU2 and a secure DMA channel.

The non-secure bus masters are CPU1 and non-secure DMA channels.

Figure 2. Memory protection example

This example show only a secure and privileged protected memory map. The security and unprivileged parameters can freely be programmed in any order as detailed below:

• • When HDPSA > SFSA > unprivileged watermark > unprivileged write watermark, the areas appear in the following order:
  • – Secure privileged hide protection area at the top
  • – Secure privileged area
  • – Non-secure privileged area
  • – Non-secure unprivileged read only area
  • – Non-secure unprivileged area starting from the memory base address.
• • unprivileged write watermark >= unprivileged watermark, the areas appear in the following order:
  • – privileged area at the top
  • – Unprivileged area starting from the memory base address (no unprivileged read only area in this case)

Memory access protection overview

The secure area of the memories have exclusively read, write, execute access only from the secure CPU2 and secure DMA channels. CPU1 and non-secure DMA channels have no execute, read, nor write access to these areas.

The non-secure area of the memories grants full read, write, execute access to CPU1 and all DMA channels. CPU2 has only read and write access to the non-secure areas. CPU2 is prevented from executing from non-secure areas.

Access rules from the different bus masters and secure, non-secure, privileged and unprivileged access types to the different memory areas is given in the table below.

Table 3. Memory security and privilege access

Table 3. Memory security and privilege access (continued)

1. 1. Access to the hide protection secure privileged area is disabled by flash memory hide protection secure privileged HDPADIS bit.
2. 2. Read access returns a zero value, write access is ignored and, in both cases, an illegal access event is generated.
3. 3. The secure privileged and unprivileged, read and execute protected pages cannot be written by a secure unprivileged access. However it can be erased by a secure unprivileged page erase.
4. 4. Privileged area start address < secure area start address.
5. 5. Execution from SRAM1 and SRAM2 can be disabled by the execute never feature available from the MPU in the respective CPU.
6. 6. Read access returns a zero value, write access is ignored and, in both cases, an illegal access event is generated. When RDP level is 1 and CPU1 boots from SRAM1, SRAM2 is locked and no illegal access event is generated.

2.6 Memory organization

2.6.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.6.2 Memory map and register boundary addresses

Figure 3. Memory map

Any memory area not allocated to on-chip memories and peripherals is considered “Reserved”.

The table below details the boundary addresses of peripherals available in the device.

Table 4. Memory map and peripheral register boundary addresses

Table 4. Memory map and peripheral register boundary addresses (continued)

Table 4. Memory map and peripheral register boundary addresses (continued)

1. This address corresponds to the maximum flash memory. For products with smaller flash memory size (128 and 64 Kbytes), the end address is lower.

2. Bus depends on the selected CPU1n boot area.

2.6.3 CPU1 bit banding

The CPU1 map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

The AHB1, APB1, APB2 peripheral registers and the SRAM1 and SRAM2 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The operations are only available for CPU1 accesses and not from other bus masters (such as DMA).

The peripheral bit-band alias is located from address 0x4200 0000 to 0x425F FFFF.

The SRAM bit-band alias is located from address 0x2200 0000 to 0x221F FFFF.

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region.

The mapping formula is the following:

where:

• • bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
• • bit_band_base is the starting address of the alias region.
• • byte_offset is the number of the byte in the bit_band region that contains the targeted bit.
• • bit_number is the bit position (0-7) of the targeted bit.

Example

The following example shows how to map bit [2] of the byte located at SRAM1 address 0x2000 0300 to the alias region. The formula is then:

Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit [2] of the byte at SRAM1 address 0x2000 0300.

Reading address 0x2200 6008 returns the value 0x01 or 0x00 of bit [2] of the byte at SRAM1 address 0x2000 0300.

For more information on bit-band, refer to the Cortex-M4 programming manual.