RM0453-STM32WL5x

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WL5x microcontrollers memory and peripherals.

STM32WL5x MCUs with integrated sub-GHz radio operating in the 150 - 960 MHz ISM band, belong to a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -Mx cores, refer to the corresponding Arm ® Technical Reference Manuals available on http://infocenter.arm.com .

STM32WL5x microcontrollers include ST state-of-the-art patented technology.

For information on the device errata with respect to the datasheet and reference manual, refer to the STM32WL55xx STM32WL54xx errata sheet (ES0500).

Contents

3.4.7Interrupts .....86
3.5GTZC TZSC registers .....86
3.5.1GTZC TZSC control register (GTZC_TZSC_CR) .....86
3.5.2GTZC TZSC security configuration register
(GTZC_TZSC_SECCFGR1) .....		87
3.5.3GTZC TZSC privileged configuration register
(GTZC_TZSC_PRIVCFGR1) .....		88
3.5.4GTZC TZSC unprivileged watermark 1 register
(GTZC_TZSC_MPCWM1_UPWMR) .....		89
3.5.5GTZC TZSC unprivileged writable watermark 1 register
(GTZC_TZSC_MPCWM1_UPWWMR) .....		90
3.5.6GTZC TZSC unprivileged watermark 2 register
(GTZC_TZSC_MPCWM2_UPWMR) .....		91
3.5.7GTZC TZSC unprivileged watermark 3 register
(GTZC_TZSC_MPCWM3_UPWMR) .....		92
3.5.8GTZC TZSC register map .....93
3.6GTZC TZIC registers .....94
3.6.1GTZC TZIC interrupt enable register 1 (GTZC_TZIC_IER1) .....94
3.6.2GTZC TZIC status register 1 (GTZC_TZIC_MISR1) .....95
3.6.3GTZC TZIC interrupt status clear register 1 (GTZC_TZIC_ICR1) .....97
3.6.4GTZC TZIC register map .....98
4Embedded flash memory (FLASH) .....99
4.1FLASH introduction .....99
4.2FLASH main features .....99
4.3FLASH functional description .....99
4.3.1Flash memory organization .....99
4.3.2Empty check .....100
4.3.3Error code correction (ECC) .....101
4.3.4Read access latency .....101
4.3.5Adaptive real-time memory accelerator (ART Accelerator) .....102
4.3.6Flash program and erase operations .....106
4.3.7Flash main memory erase sequences .....107
4.3.8Flash main memory programming sequences .....109
4.4FLASH option bytes .....114
4.4.1Option bytes description .....114
4.4.2Option bytes programming .....115
4.4.3Sub-GHz radio SPI security .....118
4.5Secure system memory . . . . .118
4.5.1Introduction . . . . .118
4.5.2RSSLIB functions . . . . .118
4.6Flash memory protection . . . . .119
4.6.1Readout protection (RDP) . . . . .119
4.6.2Proprietary code readout protection (PCROP) . . . . .123
4.6.3Write protection (WRP) . . . . .124
4.6.4CPU2 security (ESE) . . . . .125
4.6.5Hide protection area (HDPAD) . . . . .127
4.6.6CPU1 boot lock chain of trust . . . . .127
4.6.7CPU2 boot lock chain of trust . . . . .127
4.7FLASH program erase suspension . . . . .127
4.8FLASH interrupts . . . . .128
4.8.1Illegal access interrupts . . . . .128
4.9Register access protection . . . . .129
4.10FLASH registers . . . . .130
4.10.1FLASH access control register (FLASH_ACR) . . . . .130
4.10.2FLASH access control register 2 (FLASH_ACR2) . . . . .131
4.10.3FLASH key register (FLASH_KEYR) . . . . .132
4.10.4FLASH option key register (FLASH_OPTKEYR) . . . . .132
4.10.5FLASH status register (FLASH_SR) . . . . .132
4.10.6FLASH control register (FLASH_CR) . . . . .135
4.10.7FLASH ECC register (FLASH_ECCR) . . . . .136
4.10.8FLASH option register (FLASH_OPTR) . . . . .137
4.10.9FLASH PCROP zone A start address register
(FLASH_PCROP1ASR) . . . . .		140
4.10.10FLASH PCROP zone A end address register
(FLASH_PCROP1AER) . . . . .		140
4.10.11FLASH WRP area A address register (FLASH_WRP1AR) . . . . .141
4.10.12FLASH WRP area B address register (FLASH_WRP1BR) . . . . .142
4.10.13FLASH PCROP zone B start address register
(FLASH_PCROP1BSR) . . . . .		142
4.10.14FLASH PCROP zone B end address register
(FLASH_PCROP1BER) . . . . .		143
4.10.15FLASH IPCC mailbox data buffer address register
(FLASH_IPCCBR) . . . . .		144
4.10.16FLASH CPU2 access control register (FLASH_C2ACR) . . . . .144
4.10.17FLASH CPU2 status register (FLASH_C2SR) . . . . .145
4.10.18FLASH CPU2 control register (FLASH_C2CR) . . . . .147
4.10.19FLASH secure flash start address register (FLASH_SFR) . . . . .148
4.10.20FLASH secure SRAM start address and CPU2 reset vector register
(FLASH_SRRVR) . . . . .		150
4.10.21FLASH register map . . . . .152
5Sub-GHz radio (SUBGHZ) . . . . .154
5.1Sub-GHz radio introduction . . . . .154
5.2Sub-GHz radio main features . . . . .154
5.3Sub-GHz radio functional description . . . . .155
5.3.1General description . . . . .155
5.3.2Sub-GHz radio signals . . . . .155
5.3.3Transmitter . . . . .156
5.3.4Receiver . . . . .157
5.3.5RF-PLL . . . . .158
5.3.6Intermediate frequencies . . . . .158
5.4Sub-GHz radio clocks . . . . .159
5.4.1Internal oscillators . . . . .159
5.4.2HSE32 reference clock . . . . .159
5.5Sub-GHz radio modems . . . . .160
5.5.1LoRa modem . . . . .160
5.5.2LoRa framing . . . . .162
5.5.3FSK modem . . . . .164
5.5.4MSK modem . . . . .165
5.5.5Generic framing . . . . .165
5.5.6BPSK modem . . . . .167
5.5.7BPSK framing . . . . .168
5.6Sub-GHz radio data buffer . . . . .168
5.6.1Receive data buffer operation . . . . .169
5.6.2Transmit data buffer operation . . . . .169
5.7Sub-GHz radio operating modes . . . . .169
5.7.1Startup mode . . . . .171
5.7.2Sleep mode . . . . .171
5.7.3Calibration mode . . . . .171
5.7.4Standby mode . . . . .172
5.7.5Frequency synthesis mode (FS) . . . . .172
5.7.6Transmit mode (TX) . . . . .172
5.7.7Receive mode (RX) .....173
5.7.8Active mode switching time .....173
5.8Sub-GHz radio SPI interface .....174
5.8.1Sub-GHz radio command structure .....175
5.8.2Register and buffer access commands .....175
5.8.3Operating mode commands .....177
5.8.4Sub-GHz radio configuration commands .....182
5.8.5Communication status information commands .....193
5.8.6IRQ interrupt commands .....196
5.8.7Miscellaneous commands .....198
5.8.8Set_TcxoMode command .....201
5.8.9Sub-GHz radio commands overview .....202
5.9Sub-GHz radio application configuration .....204
5.9.1Basic sequence for LoRa, (G)MSK and (G)FSK transmit operation ..204
5.9.2Basic sequence for LoRa and (G)FSK receive operation .....205
5.9.3Basic sequence for BPSK transmit operation .....206
5.10Sub-GHz radio registers .....206
5.10.1Sub-GHz radio ramp-up MSB register (SUBGHZ_RAM_RAMPUPH) .....206
5.10.2Sub-GHz radio ramp-up LSB register (SUBGHZ_RAM_RAMPUPL) .....207
5.10.3Sub-GHz radio ramp-down MSB register
(SUBGHZ_RAM_RAMPDNH) .....		207
5.10.4Sub-GHz radio ramp-down LSB register
(SUBGHZ_RAM_RAMPDNL) .....		207
5.10.5Sub-GHz radio frame limit MSB register
(SUBGHZ_RAM_FRAMELIMH) .....		207
5.10.6Sub-GHz radio frame limit LSB register
(SUBGHZ_RAM_FRAMELIML) .....		208
5.10.7Sub-GHz radio generic bit synchronization register
(SUBGHZ_GBSYNCR) .....		208
5.10.8Sub-GHz radio generic CFO MSB register (SUBGHZ_GCFORH) .....208
5.10.9Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL) .....209
5.10.10Sub-GHz radio generic packet control 1 register
(SUBGHZ_GPKTCTL1R) .....		209
5.10.11Sub-GHz radio generic packet control 1A register
(SUBGHZ_GPKTCTL1AR) .....		209
5.10.12Sub-GHz radio generic whitening LSB register
(SUBGHZ_GWHITEINIRL) .....		210
5.10.13Sub-GHz radio generic payload length register
(SUBGHZ_GRTXPLDLEN) .....		210
5.10.14Sub-GHz radio generic CRC initial MSB register (SUBGHZ_GCRCINIRH) .....210
5.10.15Sub-GHz radio generic CRC initial LSB register (SUBGHZ_GCRCINIRL) .....211
5.10.16Sub-GHz radio generic CRC polynomial MSB register (SUBGHZ_GCRCPOLRH) .....211
5.10.17Sub-GHz radio generic CRC polynomial LSB register (SUBGHZ_GCRCPOLRL) .....211
5.10.18Sub-GHz radio generic synchronization word control register 0 (SUBGHZ_GSYNCR0) .....212
5.10.19Sub-GHz radio generic synchronization word control register 1 (SUBGHZ_GSYNCR1) .....212
5.10.20Sub-GHz radio generic synchronization word control register 2 (SUBGHZ_GSYNCR2) .....212
5.10.21Sub-GHz radio generic synchronization word control register 3 (SUBGHZ_GSYNCR3) .....212
5.10.22Sub-GHz radio generic synchronization word control register 4 (SUBGHZ_GSYNCR4) .....213
5.10.23Sub-GHz radio generic synchronization word control register 5 (SUBGHZ_GSYNCR5) .....213
5.10.24Sub-GHz radio generic synchronization word control register 6 (SUBGHZ_GSYNCR6) .....213
5.10.25Sub-GHz radio generic synchronization word control register 7 (SUBGHZ_GSYNCR7) .....213
5.10.26Sub-GHz radio generic node address register (SUBGHZ_GNODEADR) .....214
5.10.27Sub-GHz radio generic broadcast address register (SUBGHZ_GBCASTADDR) .....214
5.10.28Sub-GHz radio generic AFC register (SUBGHZ_GAFCR) .....214
5.10.29Sub-GHz radio LoRa payload length register (SUBGHZ_LPLDLENR) .....214
5.10.30Sub-GHz radio synchro timeout register (SUBGHZ_LSYNCTIMEOUTR) .....215
5.10.31Sub-GHz radio LoRa IQ polarity MSB register (SUBGHZ_LIQPOLR) .....215
5.10.32Sub-GHz radio LoRa IQ polarity LSB register (SUBGHZ_LIQPOLR) .....215
5.10.33Sub-GHz radio LoRa synchronization word MSB register (SUBGHZ_LSYNCRH) .....215
5.10.34Sub-GHz radio LoRa synchronization word LSB register (SUBGHZ_LSYNCR) .....216
5.10.35Sub-GHz radio Tx address pointer register (SUBGHZ_TXADRPTR) .....216
5.10.36Sub-GHz radio Rx address pointer register (SUBGHZ_RXADPTRR) .....216
5.10.37Sub-GHz radio bandwidth select register (SUBGHZ_BWSELR) .....217
5.10.38Sub-GHz radio random number register 3 (SUBGHZ_RNGR3) . . . . .217
5.10.39Sub-GHz radio random number register 2 (SUBGHZ_RNGR2) . . . . .217
5.10.40Sub-GHz radio random number register 1 (SUBGHZ_RNGR1) . . . . .217
5.10.41Sub-GHz radio random number register 0 (SUBGHZ_RNGR0) . . . . .218
5.10.42Sub-GHz radio SD resolution register (SUBGHZ_SDCFG0R) . . . . .218
5.10.43Sub-GHz radio AGC RSSI control register
(SUBGHZ_AGCRSSICTL0R) . . . . .		218
5.10.44Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR)218
5.10.45Sub-GHz radio AGC reset configuration register
(SUBGHZ_AGCGFORSTCFGGR) . . . . .		219
5.10.46Sub-GHz radio AGC reset power threshold register
(SUBGHZ_AGCGFORSTPOWTHR) . . . . .		219
5.10.47Sub-GHz radio Tx clamp register (SUBGHZ_TXCLAMPR) . . . . .219
5.10.48Sub-GHz radio disable LNA register (REG_ANA_LNA) . . . . .220
5.10.49Sub-GHz radio disable mixer register (REG_ANA_MIXER) . . . . .220
5.10.50Sub-GHz radio PA over current protection register
(SUBGHZ_PAOCPR) . . . . .		220
5.10.51Sub-GHz radio RTC control register (SUBGHZ_RTCCTLR) . . . . .220
5.10.52Sub-GHz radio RTC period MSB register (SUBGHZ_RTCPRDR2) . . . . .221
5.10.53Sub-GHz radio RTC period mid-byte register
(SUBGHZ_RTCPRDR1) . . . . .		221
5.10.54Sub-GHz radio RTC period LSB register (SUBGHZ_RTCPRDR0) . . . . .221
5.10.55Sub-GHz radio HSE32 OSC_IN capacitor trim register
(SUBGHZ_HSEINTRIMR) . . . . .		222
5.10.56Sub-GHz radio HSE32 OSC_OUT capacitor trim register
(SUBGHZ_HSEOUTTRIMR) . . . . .		222
5.10.57Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R) . . . . .223
5.10.58Sub-GHz radio power control register (SUBGHZ_PCR) . . . . .223
5.10.59Sub-GHz radio regulator drive control register
(SUBGHZ_REGDRVCR) . . . . .		224
5.10.60Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R) . . . . .224
5.10.61Sub-GHz radio register map . . . . .225
6Power control (PWR) . . . . .227
6.1Power supplies . . . . .227
6.1.1Independent analog peripherals supply . . . . .230
6.1.2Battery backup domain . . . . .230
6.1.3Voltage regulator . . . . .232
6.1.4Dynamic voltage scaling management . . . . .232
6.2Power supply supervisor . . . . .233
6.2.1Power-on reset (POR)/power-down reset (PDR)
/Brownout reset (BOR) . . . . .		233
6.2.2Programmable voltage detector (PVD) . . . . .234
6.2.3Peripheral voltage monitoring (PVM) . . . . .235
6.2.4Radio end of life (EOL) . . . . .236
6.3Radio busy management . . . . .236
6.4CPU2 boot . . . . .238
6.5Low-power modes . . . . .240
6.5.1Run mode . . . . .248
6.5.2Low-power run mode (LPRun) . . . . .248
6.5.3Enter low-power mode . . . . .249
6.5.4Exit low-power mode . . . . .249
6.5.5Sleep mode . . . . .251
6.5.6Low-power sleep mode (LPSleep) . . . . .252
6.5.7Stop 0 mode . . . . .253
6.5.8Stop 1 mode . . . . .255
6.5.9Stop 2 mode . . . . .256
6.5.10Standby mode . . . . .258
6.5.11Shutdown mode . . . . .260
6.5.12Auto-wake-up from low-power mode . . . . .261
6.6PWR registers . . . . .262
6.6.1PWR control register 1 (PWR_CR1) . . . . .262
6.6.2PWR control register 2 (PWR_CR2) . . . . .264
6.6.3PWR control register 3 (PWR_CR3) . . . . .265
6.6.4PWR control register 4 (PWR_CR4) . . . . .266
6.6.5PWR status register 1 (PWR_SR1) . . . . .267
6.6.6Power status register 2 (PWR_SR2) . . . . .268
6.6.7PWR status clear register (PWR_SCR) . . . . .270
6.6.8PWR control register 5 (PWR_CR5) . . . . .271
6.6.9PWR port A pull-up control register (PWR_PUCRA) . . . . .272
6.6.10PWR port A pull-down control register (PWR_PDCRA) . . . . .272
6.6.11PWR port B pull-up control register (PWR_PUCRB) . . . . .273
6.6.12PWR port B pull-down control register (PWR_PDCRB) . . . . .273
6.6.13PWR port C pull-up control register (PWR_PUCRC) . . . . .273
6.6.14PWR port C pull-down control register (PWR_PDCRC) . . . . .274
6.6.15PWR port H pull-up control register (PWR_PUCRH) . . . . .275
6.6.16PWR port H pull-down control register (PWR_PDCRH) . . . . .275
6.6.17PWR CPU2 control register 1 (PWR_C2CR1) . . . . .276
6.6.18PWR CPU2 control register 3 (PWR_C2CR3) . . . . .277
6.6.19PWR extended status and status clear register (PWR_EXTSCR) . . . . .278
6.6.20PWR security configuration register (PWR_SECCFGR) . . . . .279
6.6.21PWR sub-GHz SPI control register (PWR_SUBGHZSPICR) . . . . .280
6.6.22PWR RSS command register (PWR_RSSCMDR) . . . . .280
6.6.23PWR register map . . . . .281
7Reset and clock control (RCC) . . . . .283
7.1Reset . . . . .283
7.1.1Power reset . . . . .283
7.1.2System reset . . . . .283
7.1.3Backup domain reset . . . . .285
7.1.4Sub-GHz radio reset . . . . .285
7.1.5PKA SRAM reset . . . . .285
7.2Clocks . . . . .285
7.2.1HSE32 clock with trimming . . . . .288
7.2.2HSI16 clock . . . . .291
7.2.3MSI clock . . . . .291
7.2.4PLL . . . . .292
7.2.5LSE clock . . . . .293
7.2.6LSI clock . . . . .294
7.2.7Clock source stabilization time . . . . .294
7.2.8System clock (SYSCLK) selection . . . . .294
7.2.9Clock source frequency versus voltage scaling . . . . .295
7.2.10Clock security system on HSE32 (CSS) . . . . .295
7.2.11Clock security system on LSE (LSECSS) . . . . .296
7.2.12SPI2S2 clock . . . . .296
7.2.13Sub-GHz radio SPI clock . . . . .296
7.2.14ADC clock . . . . .297
7.2.15RTC clock . . . . .297
7.2.16Timer clock . . . . .297
7.2.17Watchdog clock . . . . .298
7.2.18True RNG clock . . . . .298
7.2.19Clock-out capability . . . . .298
7.2.20Internal/external clock measurement with TIM16/TIM17 . . . . .299
7.2.21Peripheral clocks enable .....301
7.3Low-power modes .....302
7.4RCC registers .....304
7.4.1RCC clock control register (RCC_CR) .....304
7.4.2RCC internal clock sources calibration register (RCC_ICSCR) .....307
7.4.3RCC clock configuration register (RCC_CFGR) .....308
7.4.4RCC PLL configuration register (RCC_PLLCFGR) .....310
7.4.5RCC clock interrupt enable register (RCC_CIER) .....313
7.4.6RCC clock interrupt flag register (RCC_CIFR) .....315
7.4.7RCC clock interrupt clear register (RCC_CICR) .....316
7.4.8RCC AHB1 peripheral reset register (RCC_AHB1RSTR) .....317
7.4.9RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .....318
7.4.10RCC AHB3 peripheral reset register (RCC_AHB3RSTR) .....318
7.4.11RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) .....319
7.4.12RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) .....321
7.4.13RCC APB2 peripheral reset register (RCC_APB2RSTR) .....321
7.4.14RCC APB3 peripheral reset register (RCC_APB3RSTR) .....322
7.4.15RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) .....323
7.4.16RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) .....324
7.4.17RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) .....324
7.4.18RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) .....325
7.4.19RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) .....327
7.4.20RCC APB2 peripheral clock enable register (RCC_APB2ENR) .....328
7.4.21RCC APB3 peripheral clock enable register (RCC_APB3ENR) .....329
7.4.22RCC AHB1 peripheral clock enable in Sleep mode register
(RCC_AHB1SMENR) .....		329
7.4.23RCC AHB2 peripheral clock enable in Sleep mode register
(RCC_AHB2SMENR) .....		330
7.4.24RCC AHB3 peripheral clock enable in Sleep and Stop mode register
(RCC_AHB3SMENR) .....		331
7.4.25RCC APB1 peripheral clock enable in Sleep mode register 1
(RCC_APB1SMENR1) .....		332
7.4.26RCC APB1 peripheral clock enable in Sleep mode register 2
(RCC_APB1SMENR2) .....		334
7.4.27RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR) .....		335
7.4.28RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR) .....		336

8.3.3HSEM lock procedures . . . . .366
8.3.4HSEM write/read/read lock register address . . . . .368
8.3.5HSEM unlock procedures . . . . .368
8.3.6HSEM COREID semaphore clear . . . . .369
8.3.7HSEM interrupts . . . . .369
8.3.8AHB bus master ID verification . . . . .371
8.4HSEM registers . . . . .372
8.4.1HSEM register semaphore x (HSEM_Rx) . . . . .372
8.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .373
8.4.3HSEM interrupt enable register (HSEM_CnIER) . . . . .374
8.4.4HSEM interrupt clear register (HSEM_CnICR) . . . . .374
8.4.5HSEM interrupt status register (HSEM_CnISR) . . . . .374
8.4.6HSEM interrupt status register (HSEM_CnMISR) . . . . .375
8.4.7HSEM clear register (HSEM_CR) . . . . .375
8.4.8HSEM clear semaphore key register (HSEM_KEYR) . . . . .376
8.4.9HSEM register map . . . . .377
9Inter-processor communication controller (IPCC) . . . . .379
9.1Introduction . . . . .379
9.2IPCC main features . . . . .379
9.3IPCC functional description . . . . .379
9.3.1IPCC block diagram . . . . .380
9.3.2IPCC Simplex channel mode . . . . .380
9.3.3IPCC Half-duplex channel mode . . . . .383
9.3.4IPCC interrupts . . . . .386
9.4IPCC registers . . . . .387
9.4.1IPCC processor 1 control register (IPCC_C1CR) . . . . .387
9.4.2IPCC processor 1 mask register (IPCC_C1MR) . . . . .387
9.4.3IPCC processor 1 status set clear register (IPCC_C1SCR) . . . . .388
9.4.4IPCC processor 1 to processor 2 status register
(IPCC_C1TOC2SR) . . . . .		388
9.4.5IPCC processor 2 control register (IPCC_C2CR) . . . . .389
9.4.6IPCC processor 2 mask register (IPCC_C2MR) . . . . .389
9.4.7IPCC processor 2 status set clear register (IPCC_C2SCR) . . . . .390
9.4.8IPCC processor 2 to processor 1 status register
(IPCC_C2TOC1SR) . . . . .		391
9.4.9IPCC register map . . . . .392
10General-purpose I/Os (GPIO) . . . . .393
10.1GPIO introduction . . . . .393
10.2GPIO main features . . . . .393
10.3GPIO functional description . . . . .393
10.3.1General purpose I/O (GPIO) . . . . .396
10.3.2I/O pin alternate function multiplexer and mapping . . . . .396
10.3.3I/O port control registers . . . . .397
10.3.4I/O port data registers . . . . .397
10.3.5I/O data bitwise handling . . . . .397
10.3.6GPIO locking mechanism . . . . .398
10.3.7I/O alternate function input/output . . . . .398
10.3.8External interrupt/wake-up lines . . . . .398
10.3.9Input configuration . . . . .399
10.3.10Output configuration . . . . .399
10.3.11Alternate function configuration . . . . .400
10.3.12Analog configuration . . . . .401
10.3.13Using the LSE oscillator pins as GPIOs . . . . .401
10.3.14Using the GPIO pins in the RTC supply domain . . . . .401
10.3.15Using PH3 as GPIO . . . . .402
10.4GPIO registers . . . . .402
10.4.1GPIOx mode register (GPIOx_MODER) (x = A to B) . . . . .402
10.4.2GPIOx output type register (GPIOx_OTYPER) (x = A to B) . . . . .402
10.4.3GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B) . . . . .403
10.4.4GPIOx pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) . . . . .403
10.4.5GPIOx input data register (GPIOx_IDR) (x = A to B) . . . . .404
10.4.6GPIOx output data register (GPIOx_ODR) (x = A to B) . . . . .404
10.4.7GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B) . . . . .405
10.4.8GPIOx configuration lock register (GPIOx_LCKR) (x = A to B) . . . . .405
10.4.9GPIOx alternate function low register (GPIOx_AFRL) (x = A to B) . . . . .406
10.4.10GPIOx alternate function high register (GPIOx_AFRH) (x = A to B) . . . . .407
10.4.11GPIOx bit reset register (GPIOx_BRR) (x = A to B) . . . . .407
10.4.12GPIOC mode register (GPIOC_MODER) . . . . .408
10.4.13GPIOC output type register (GPIOC_OTYPER) . . . . .408
10.4.14GPIOC output speed register (GPIOC_OSPEEDR) . . . . .409
10.4.15GPIOC pull-up/pull-down register (GPIOC_PUPDR) . . . . .410
10.4.16GPIOC input data register (GPIOC_IDR) . . . . .410
10.4.17GPIOC output data register (GPIOC_ODR) . . . . .411
10.4.18GPIOC bit set/reset register (GPIOC_BSRR) . . . . .411
10.4.19GPIOC configuration lock register (GPIOC_LCKR) . . . . .412
10.4.20GPIOC alternate function low register (GPIOC_AFRL) . . . . .413
10.4.21GPIOC alternate function high register (GPIOC_AFRH) . . . . .414
10.4.22GPIOC bit reset register (GPIOC_BRR) . . . . .414
10.4.23GPIOH mode register (GPIOH_MODER) . . . . .415
10.4.24GPIO H output type register (GPIOH_OTYPER) . . . . .415
10.4.25GPIOH output speed register (GPIOH_OSPEEDR) . . . . .416
10.4.26GPIOH pull-up/pull-down register (GPIOH_PUPDR) . . . . .416
10.4.27GPIOH input data register (GPIOH_IDR) . . . . .417
10.4.28GPIOH output data register (GPIOH_ODR) . . . . .417
10.4.29GPIO H bit set/reset register (GPIOH_BSRR) . . . . .417
10.4.30GPIOH configuration lock register (GPIOH_LCKR) . . . . .418
10.4.31GPIOH alternate function low register (GPIOH_AFRL) . . . . .419
10.4.32GPIOH bit reset register (GPIOH_BRR) . . . . .420
10.4.33GPIOA register map . . . . .420
10.4.34GPIOB register map . . . . .421
10.4.35GPIOC register map . . . . .422
10.4.36GPIOH register map . . . . .423
11System configuration controller (SYSCFG) . . . . .424
11.1SYSCFG main features . . . . .424
11.2SYSCFG registers . . . . .424
11.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .424
11.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .425
11.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		426
11.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		427
11.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		428
11.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		429
11.2.7SYSCFG SRAM control and status register (SYSCFG_SCSR) . . . . .430
11.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .430
11.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . .431
11.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .432
13.4.2DMA pins and internal signals . . . . .449
13.4.3DMA transfers . . . . .449
13.4.4DMA arbitration . . . . .450
13.4.5DMA channels . . . . .451
13.4.6DMA data width, alignment and endianness . . . . .456
13.4.7DMA error management . . . . .457
13.5DMA interrupts . . . . .458
13.6DMA registers . . . . .458
13.6.1DMA interrupt status register (DMA_ISR) . . . . .458
13.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .461
13.6.3DMA channel x configuration register (DMA_CCRx) . . . . .462
13.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .467
13.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .468
13.6.6DMA channel x memory address register (DMA_CMARx) . . . . .468
13.6.7DMA register map . . . . .469
14DMA request multiplexer (DMAMUX) . . . . .472
14.1Introduction . . . . .472
14.2DMAMUX main features . . . . .473
14.3DMAMUX implementation . . . . .473
14.3.1DMAMUX1 instantiation . . . . .473
14.3.2DMAMUX1 mapping . . . . .474
14.4DMAMUX functional description . . . . .476
14.4.1DMAMUX block diagram . . . . .476
14.4.2DMAMUX signals . . . . .477
14.4.3DMAMUX channels . . . . .477
14.4.4DMAMUX secure/non-secure channels . . . . .478
14.4.5DMAMUX privileged / unprivileged channels . . . . .478
14.4.6DMAMUX request line multiplexer . . . . .478
14.4.7DMAMUX request generator . . . . .481
14.5DMAMUX interrupts . . . . .482
14.6DMAMUX registers . . . . .484
14.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		484
14.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		485
16.6.13EXTI register map .....515
17Cyclic redundancy check calculation unit (CRC) .....517
17.1Introduction .....517
17.2CRC main features .....517
17.3CRC functional description .....518
17.3.1CRC block diagram .....518
17.3.2CRC internal signals .....518
17.3.3CRC operation .....518
17.4CRC registers .....520
17.4.1CRC data register (CRC_DR) .....520
17.4.2CRC independent data register (CRC_IDR) .....520
17.4.3CRC control register (CRC_CR) .....521
17.4.4CRC initial value (CRC_INIT) .....522
17.4.5CRC polynomial (CRC_POL) .....522
17.4.6CRC register map .....523
18Analog-to-digital converter (ADC) .....524
18.1Introduction .....524
18.2ADC main features .....525
18.3ADC functional description .....526
18.3.1ADC pins and internal signals .....526
18.3.2ADC voltage regulator (ADVREGEN) .....527
18.3.3Calibration (ADCAL) .....528
18.3.4ADC on-off control (ADEN, ADDIS, ADRDY) .....530
18.3.5ADC clock (CKMODE, PRESC[3:0]) .....531
18.3.6ADC connectivity .....533
18.3.7Configuring the ADC .....534
18.3.8Channel selection (CHSEL, SCANDIR, CHSELRMOD) .....534
18.3.9Programmable sampling time (SMPx[2:0]) .....535
18.3.10Single conversion mode (CONT = 0) .....536
18.3.11Continuous conversion mode (CONT = 1) .....536
18.3.12Starting conversions (ADSTART) .....537
18.3.13Timings .....538
18.3.14Stopping an ongoing conversion (ADSTP) .....539
18.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .539
18.4.1Discontinuous mode (DISCEN) . . . . .540
18.4.2Programmable resolution (RES) - Fast conversion mode . . . . .540
18.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .541
18.4.4End of conversion sequence (EOS flag) . . . . .541
18.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		542
18.4.6Low frequency trigger mode . . . . .544
18.5Data management . . . . .544
18.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .544
18.5.2ADC overrun (OVR, OVRMOD) . . . . .544
18.5.3Managing a sequence of data converted without using the DMA . . . . .546
18.5.4Managing converted data without using the DMA without overrun . . . . .546
18.5.5Managing converted data using the DMA . . . . .546
18.6Low-power features . . . . .547
18.6.1Wait mode conversion . . . . .547
18.6.2Auto-off mode (AUTOFF) . . . . .548
18.7Analog window watchdogs . . . . .549
18.7.1Description of analog watchdog 1 . . . . .550
18.7.2Description of analog watchdog 2 and 3 . . . . .551
18.7.3ADC_AWDx_OUT output signal generation . . . . .551
18.7.4Analog watchdog threshold control . . . . .553
18.8Oversampler . . . . .554
18.8.1ADC operating modes supported when oversampling . . . . .555
18.8.2Analog watchdog . . . . .556
18.8.3Triggered mode . . . . .556
18.9Temperature sensor and internal reference voltage . . . . .556
18.10Battery voltage monitoring . . . . .559
18.11ADC interrupts . . . . .560
18.12ADC registers . . . . .561
18.12.1ADC interrupt and status register (ADC_ISR) . . . . .561
18.12.2ADC interrupt enable register (ADC_IER) . . . . .562
18.12.3ADC control register (ADC_CR) . . . . .564
18.12.4ADC configuration register 1 (ADC_CFGR1) . . . . .566
18.12.5ADC configuration register 2 (ADC_CFGR2) . . . . .569
18.12.6ADC sampling time register (ADC_SMPR) . . . . .570
18.12.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .571
18.12.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .572
18.12.9ADC channel selection register (ADC_CHSELR) . . . . .572
18.12.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .573
18.12.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .575
18.12.12ADC data register (ADC_DR) . . . . .576
18.12.13ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .576
18.12.14ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .576
18.12.15ADC calibration factor (ADC_CALFACT) . . . . .577
18.12.16ADC common configuration register (ADC_CCR) . . . . .578
18.13ADC register map . . . . .579
19Digital-to-analog converter (DAC) . . . . .581
19.1Introduction . . . . .581
19.2DAC main features . . . . .581
19.3DAC implementation . . . . .582
19.4DAC functional description . . . . .582
19.4.1DAC block diagram . . . . .582
19.4.2DAC pins and internal signals . . . . .583
19.4.3DAC channel enable . . . . .584
19.4.4DAC data format . . . . .584
19.4.5DAC conversion . . . . .585
19.4.6DAC output voltage . . . . .585
19.4.7DAC trigger selection . . . . .585
19.4.8DMA requests . . . . .586
19.4.9Noise generation . . . . .586
19.4.10Triangle-wave generation . . . . .588
19.4.11DAC channel modes . . . . .589
19.4.12DAC channel buffer calibration . . . . .592
19.4.13DAC channel conversion modes . . . . .593
19.5DAC in low-power modes . . . . .594
19.6DAC interrupts . . . . .595
19.7DAC registers . . . . .595
19.7.1DAC control register (DAC_CR) . . . . .595
19.7.2DAC software trigger register (DAC_SWTRGR) . . . . .597
19.7.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		597
19.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .598
19.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .598
19.7.6DAC channel1 data output register (DAC_DOR1) . . . . .599
19.7.7DAC status register (DAC_SR) . . . . .599
19.7.8DAC calibration control register (DAC_CCR) . . . . .600
19.7.9DAC mode control register (DAC_MCR) . . . . .600
19.7.10DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .601
19.7.11DAC sample and hold time register (DAC_SHHR) . . . . .601
19.7.12DAC sample and hold refresh time register (DAC_SHRR) . . . . .602
19.7.13DAC register map . . . . .603
20Voltage reference buffer (VREFBUF) . . . . .605
20.1Introduction . . . . .605
20.2VREFBUF functional description . . . . .605
20.3VREFBUF registers . . . . .606
20.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .606
20.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .606
20.3.3VREFBUF register map . . . . .607
21Comparator (COMP) . . . . .608
21.1COMP introduction . . . . .608
21.2COMP main features . . . . .608
21.3COMP functional description . . . . .609
21.3.1COMP block diagram . . . . .609
21.3.2COMP pins and internal signals . . . . .609
21.3.3COMP reset and clocks . . . . .611
21.3.4Comparator LOCK mechanism . . . . .611
21.3.5Window comparator . . . . .611
21.3.6Hysteresis . . . . .612
21.3.7Comparator output blanking function . . . . .613
21.3.8COMP power and speed modes . . . . .613
21.4COMP low-power modes . . . . .614
21.5COMP interrupts . . . . .614
21.6COMP registers . . . . .615
21.6.1COMP1 control and status register (COMP1_CSR) . . . . .615
21.6.2COMP2 control and status register (COMP2_CSR) . . . . .617
21.6.3COMP register map . . . . .619
22True random number generator (RNG) . . . . .620
22.1Introduction . . . . .620
22.2RNG main features . . . . .620
22.3RNG functional description . . . . .621
22.3.1RNG block diagram . . . . .621
22.3.2RNG internal signals . . . . .621
22.3.3Random number generation . . . . .621
22.3.4RNG initialization . . . . .624
22.3.5RNG operation . . . . .625
22.3.6RNG clocking . . . . .627
22.3.7Error management . . . . .627
22.3.8RNG low-power use . . . . .628
22.4RNG interrupts . . . . .628
22.5RNG processing time . . . . .629
22.6RNG entropy source validation . . . . .629
22.6.1Introduction . . . . .629
22.6.2Validation conditions . . . . .629
22.6.3Data collection . . . . .630
22.7RNG registers . . . . .630
22.7.1RNG control register (RNG_CR) . . . . .630
22.7.2RNG status register (RNG_SR) . . . . .632
22.7.3RNG data register (RNG_DR) . . . . .633
22.7.4RNG health test control register (RNG_HTCR) . . . . .634
22.7.5RNG register map . . . . .634
23AES hardware accelerator (AES) . . . . .635
23.1Introduction . . . . .635
23.2AES main features . . . . .635
23.3AES implementation . . . . .635
23.4AES functional description . . . . .636
23.4.1AES block diagram . . . . .636
23.4.2AES internal signals . . . . .636
23.4.3AES cryptographic core . . . . .636
23.4.4AES procedure to perform a cipher operation . . . . .642
23.4.5AES decryption round key preparation . . . . .645
23.4.6AES ciphertext stealing and data padding . . . . .645
23.4.7AES task suspend and resume . . . . .646
23.4.8AES basic chaining modes (ECB, CBC) . . . . .646
23.4.9AES counter (CTR) mode . . . . .651
23.4.10AES Galois/counter mode (GCM) . . . . .653
23.4.11AES Galois message authentication code (GMAC) . . . . .658
23.4.12AES counter with CBC-MAC (CCM) . . . . .660
23.4.13AES data registers and data swapping . . . . .665
23.4.14AES key registers . . . . .667
23.4.15AES initialization vector registers . . . . .667
23.4.16AES DMA interface . . . . .668
23.4.17AES error management . . . . .669
23.5AES interrupts . . . . .670
23.6AES processing latency . . . . .670
23.7AES registers . . . . .671
23.7.1AES control register (AES_CR) . . . . .671
23.7.2AES status register (AES_SR) . . . . .673
23.7.3AES data input register (AES_DINR) . . . . .675
23.7.4AES data output register (AES_DOUTR) . . . . .675
23.7.5AES key register 0 (AES_KEYR0) . . . . .676
23.7.6AES key register 1 (AES_KEYR1) . . . . .676
23.7.7AES key register 2 (AES_KEYR2) . . . . .677
23.7.8AES key register 3 (AES_KEYR3) . . . . .677
23.7.9AES initialization vector register 0 (AES_IVR0) . . . . .677
23.7.10AES initialization vector register 1 (AES_IVR1) . . . . .678
23.7.11AES initialization vector register 2 (AES_IVR2) . . . . .678
23.7.12AES initialization vector register 3 (AES_IVR3) . . . . .678
23.7.13AES key register 4 (AES_KEYR4) . . . . .679
23.7.14AES key register 5 (AES_KEYR5) . . . . .679
23.7.15AES key register 6 (AES_KEYR6) . . . . .679
23.7.16AES key register 7 (AES_KEYR7) . . . . .680
23.7.17AES suspend registers (AES_SUSPxR) . . . . .680
23.7.18AES register map . . . . .681
24Public key accelerator (PKA) . . . . .683
24.1Introduction . . . . .683
24.2PKA main features . . . . .683
24.3PKA functional description . . . . .683
24.3.1PKA block diagram . . . . .683
24.3.2PKA internal signals . . . . .684
24.3.3PKA reset and clocks . . . . .684
24.3.4PKA public key acceleration . . . . .684
24.3.5Typical applications for PKA . . . . .686
24.3.6PKA procedure to perform an operation . . . . .688
24.3.7PKA error management . . . . .689
24.4PKA operating modes . . . . .689
24.4.1Introduction . . . . .689
24.4.2Montgomery parameter computation . . . . .690
24.4.3Modular addition . . . . .691
24.4.4Modular subtraction . . . . .691
24.4.5Modular and Montgomery multiplication . . . . .691
24.4.6Modular exponentiation . . . . .692
24.4.7Modular inversion . . . . .693
24.4.8Modular reduction . . . . .694
24.4.9Arithmetic addition . . . . .694
24.4.10Arithmetic subtraction . . . . .694
24.4.11Arithmetic multiplication . . . . .695
24.4.12Arithmetic comparison . . . . .695
24.4.13RSA CRT exponentiation . . . . .695
24.4.14Point on elliptic curve Fp check . . . . .696
24.4.15ECC Fp scalar multiplication . . . . .697
24.4.16ECDSA sign . . . . .698
24.4.17ECDSA verification . . . . .700
24.5Example of configurations and processing times . . . . .701
24.5.1Supported elliptic curves . . . . .701
24.5.2Computation times . . . . .703
24.6PKA interrupts . . . . .704
24.7PKA registers . . . . .705
24.7.1PKA control register (PKA_CR) . . . . .705
24.7.2PKA status register (PKA_SR) . . . . .706

25.4TIM1 registers . . . . .770
25.4.1TIM1 control register 1 (TIM1_CR1) . . . . .770
25.4.2TIM1 control register 2 (TIM1_CR2) . . . . .771
25.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		774
25.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		776
25.4.5TIM1 status register (TIM1_SR) . . . . .778
25.4.6TIM1 event generation register (TIM1_EGR) . . . . .780
25.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .781
25.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		782
25.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .785
25.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		786
25.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		788
25.4.12TIM1 counter (TIM1_CNT) . . . . .791
25.4.13TIM1 prescaler (TIM1_PSC) . . . . .791
25.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .791
25.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .792
25.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		792
25.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		793
25.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		793
25.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		794
25.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		794
25.4.21TIM1 DMA control register
(TIM1_DCR) . . . . .		798
25.4.22TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . .		799
25.4.23TIM1 option register 1 (TIM1_OR1) . . . . .800
25.4.24TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . .		800
25.4.25TIM1 capture/compare register 5
(TIM1_CCR5) . . . . .		801
25.4.26TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .802
25.4.27TIM1 alternate function option register 1 (TIM1_AF1) . . . . .803
25.4.28TIM1 Alternate function register 2 (TIM1_AF2) . . . . .804
25.4.29TIM1 timer input selection register (TIM1_TISEL) . . . . .806
25.4.30TIM1 register map . . . . .807
26General-purpose timer (TIM2) . . . . .810
26.1TIM2 introduction . . . . .810
26.2TIM2 main features . . . . .810
26.3TIM2 functional description . . . . .812
26.3.1Time-base unit . . . . .812
26.3.2Counter modes . . . . .814
26.3.3Clock selection . . . . .824
26.3.4Capture/Compare channels . . . . .828
26.3.5Input capture mode . . . . .830
26.3.6PWM input mode . . . . .831
26.3.7Forced output mode . . . . .832
26.3.8Output compare mode . . . . .832
26.3.9PWM mode . . . . .833
26.3.10Asymmetric PWM mode . . . . .837
26.3.11Combined PWM mode . . . . .837
26.3.12Clearing the OCxREF signal on an external event . . . . .838
26.3.13One-pulse mode . . . . .840
26.3.14Retriggerable one pulse mode . . . . .841
26.3.15Encoder interface mode . . . . .842
26.3.16UIF bit remapping . . . . .844
26.3.17Timer input XOR function . . . . .844
26.3.18Timers and external trigger synchronization . . . . .845
26.3.19Timer synchronization . . . . .848
26.3.20DMA burst mode . . . . .853
26.3.21Debug mode . . . . .854
26.4TIM2 registers . . . . .855
26.4.1TIM2 control register 1 (TIM2_CR1) . . . . .855
26.4.2TIM2 control register 2 (TIM2_CR2) . . . . .856
26.4.3TIM2 slave mode control register (TIM2_SMCR) . . . . .858
26.4.4TIM2 DMA/Interrupt enable register (TIM2_DIER) . . . . .861
26.4.5TIM2 status register (TIM2_SR) .....862
26.4.6TIM2 event generation register (TIM2_EGR) .....864
26.4.7TIM2 capture/compare mode register 1 (TIM2_CCMR1) .....865
26.4.8TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) ..867
26.4.9TIM2 capture/compare mode register 2 (TIM2_CCMR2) .....869
26.4.10TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) ..870
26.4.11TIM2 capture/compare enable register
(TIM2_CCER) .....		871
26.4.12TIM2 counter (TIM2_CNT) .....872
26.4.13TIM2 counter [alternate] (TIM2_CNT) .....873
26.4.14TIM2 prescaler (TIM2_PSC) .....873
26.4.15TIM2 auto-reload register (TIM2_ARR) .....874
26.4.16TIM2 capture/compare register 1 (TIM2_CCR1) .....874
26.4.17TIM2 capture/compare register 2 (TIM2_CCR2) .....874
26.4.18TIM2 capture/compare register 3 (TIM2_CCR3) .....875
26.4.19TIM2 capture/compare register 4 (TIM2_CCR4) .....875
26.4.20TIM2 DMA control register (TIM2_DCR) .....876
26.4.21TIM2 DMA address for full transfer (TIM2_DMAR) .....877
26.4.22TIM2 option register 1 (TIM2_OR1) .....877
26.4.23TIM2 alternate function option register 1 (TIM2_AF1) .....877
26.4.24TIM2 timer input selection register (TIM2_TISEL) .....878
26.4.25TIMx register map .....879
27General-purpose timers (TIM16/TIM17) .....882
27.1TIM16/TIM17 introduction .....882
27.2TIM16/TIM17 main features .....882
27.3TIM16/TIM17 functional description .....884
27.3.1Time-base unit .....884
27.3.2Counter modes .....886
27.3.3Repetition counter .....890
27.3.4Clock selection .....891
27.3.5Capture/compare channels .....893
27.3.6Input capture mode .....895
27.3.7Forced output mode .....896
27.3.8Output compare mode .....896
27.3.9PWM mode .....898
27.3.10Complementary outputs and dead-time insertion .....899
27.3.11Using the break function . . . . .901
27.3.12Bidirectional break inputs . . . . .904
27.3.136-step PWM generation . . . . .905
27.3.14One-pulse mode . . . . .907
27.3.15UIF bit remapping . . . . .908
27.3.16Slave mode – combined reset + trigger mode . . . . .908
27.3.17DMA burst mode . . . . .908
27.3.18Using timer output as trigger for other timers (TIM16/TIM17) . . . . .909
27.3.19Debug mode . . . . .910
27.4TIM16/TIM17 registers . . . . .911
27.4.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .911
27.4.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .912
27.4.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .913
27.4.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .914
27.4.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .915
27.4.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		916
27.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		917
27.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .919
27.4.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .921
27.4.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .922
27.4.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .922
27.4.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .923
27.4.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .923
27.4.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .924
27.4.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .926
27.4.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .927
27.4.17TIM16 option register 1 (TIM16_OR1) . . . . .928
27.4.18TIM16 alternate function register 1 (TIM16_AF1) . . . . .928
27.4.19TIM16 input selection register (TIM16_TISEL) . . . . .929
27.4.20TIM17 option register 1 (TIM17_OR1) . . . . .930
27.4.21TIM17 alternate function register 1 (TIM17_AF1) . . . . .930
27.4.22TIM17 input selection register (TIM17_TISEL) . . . . .931
27.4.23TIM16/TIM17 register map . . . . .932
28Low-power timer (LPTIM) . . . . .934
28.1Introduction . . . . .934
28.2LPTIM main features . . . . .934
28.3LPTIM implementation . . . . .934
28.4LPTIM functional description . . . . .935
28.4.1LPTIM block diagram . . . . .935
28.4.2LPTIM pins and internal signals . . . . .935
28.4.3LPTIM input and trigger mapping . . . . .936
28.4.4LPTIM reset and clocks . . . . .938
28.4.5Glitch filter . . . . .938
28.4.6Prescaler . . . . .939
28.4.7Trigger multiplexer . . . . .939
28.4.8Operating mode . . . . .940
28.4.9Timeout function . . . . .942
28.4.10Waveform generation . . . . .942
28.4.11Register update . . . . .943
28.4.12Counter mode . . . . .944
28.4.13Timer enable . . . . .944
28.4.14Timer counter reset . . . . .945
28.4.15Encoder mode . . . . .945
28.4.16Repetition counter . . . . .947
28.4.17Debug mode . . . . .948
28.5LPTIM low-power modes . . . . .949
28.6LPTIM interrupts . . . . .949
28.7LPTIM registers . . . . .950
28.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .950
28.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .951
28.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .952
28.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .953
28.7.5LPTIM control register (LPTIM_CR) . . . . .956
28.7.6LPTIM compare register (LPTIM_CMP) . . . . .957
28.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .957
28.7.8LPTIM counter register (LPTIM_CNT) . . . . .958
28.7.9LPTIM1 option register (LPTIM1_OR) . . . . .958
28.7.10LPTIM2 option register (LPTIM2_OR) . . . . .959
28.7.11LPTIM3 option register (LPTIM3_OR) . . . . .959
28.7.12LPTIM repetition register (LPTIM_RCR) . . . . .960
31.5.3WWDG status register (WWDG_SR) .....977
31.5.4WWDG register map .....977
32Real-time clock (RTC) .....978
32.1Introduction .....978
32.2RTC main features .....978
32.3RTC functional description .....979
32.3.1RTC block diagram .....979
32.3.2RTC pins and internal signals .....980
32.3.3GPIOs controlled by the RTC and TAMP .....981
32.3.4Clock and prescalers .....983
32.3.5Real-time clock and calendar .....985
32.3.6Calendar ultra-low power mode .....985
32.3.7Programmable alarms .....985
32.3.8Periodic auto-wake-up .....986
32.3.9RTC initialization and configuration .....987
32.3.10Reading the calendar .....989
32.3.11Resetting the RTC .....990
32.3.12RTC synchronization .....990
32.3.13RTC reference clock detection .....991
32.3.14RTC smooth digital calibration .....992
32.3.15Timestamp function .....994
32.3.16Calibration clock output .....995
32.3.17Tamper and alarm output .....995
32.4RTC low-power modes .....996
32.5RTC interrupts .....997
32.6RTC registers .....998
32.6.1RTC time register (RTC_TR) .....998
32.6.2RTC date register (RTC_DR) .....999
32.6.3RTC sub second register (RTC_SSR) .....1000
32.6.4RTC initialization control and status register (RTC_ICSR) .....1000
32.6.5RTC prescaler register (RTC_PRER) .....1002
32.6.6RTC wake-up timer register (RTC_WUTR) .....1003
32.6.7RTC control register (RTC_CR) .....1003
32.6.8RTC write protection register (RTC_WPR) .....1007
32.6.9RTC calibration register (RTC_CALR) .....1007
32.6.10RTC shift control register (RTC_SHIFTR) . . . . .1008
32.6.11RTC timestamp time register (RTC_TSTR) . . . . .1009
32.6.12RTC timestamp date register (RTC_TSDR) . . . . .1010
32.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .1010
32.6.14RTC alarm A register (RTC_ALRMAR) . . . . .1011
32.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1012
32.6.16RTC alarm B register (RTC_ALRMBR) . . . . .1013
32.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1014
32.6.18RTC status register (RTC_SR) . . . . .1015
32.6.19RTC masked interrupt status register (RTC_MISR) . . . . .1016
32.6.20RTC status clear register (RTC_SCR) . . . . .1017
32.6.21RTC alarm A binary mode register (RTC_ALRABINR) . . . . .1018
32.6.22RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .1018
32.6.23RTC register map . . . . .1019
33Tamper and backup registers (TAMP) . . . . .1021
33.1Introduction . . . . .1021
33.2TAMP main features . . . . .1021
33.3TAMP functional description . . . . .1022
33.3.1TAMP block diagram . . . . .1022
33.3.2TAMP pins and internal signals . . . . .1023
33.3.3TAMP register write protection . . . . .1024
33.3.4Tamper detection . . . . .1024
33.4TAMP low-power modes . . . . .1026
33.5TAMP interrupts . . . . .1026
33.6TAMP registers . . . . .1027
33.6.1TAMP control register 1 (TAMP_CR1) . . . . .1027
33.6.2TAMP control register 2 (TAMP_CR2) . . . . .1028
33.6.3TAMP control register 3 (TAMP_CR3) . . . . .1029
33.6.4TAMP filter control register (TAMP_FLTCR) . . . . .1030
33.6.5TAMP interrupt enable register (TAMP_IER) . . . . .1031
33.6.6TAMP status register (TAMP_SR) . . . . .1032
33.6.7TAMP masked interrupt status register (TAMP_MISR) . . . . .1033
33.6.8TAMP status clear register (TAMP_SCR) . . . . .1034
33.6.9TAMP monotonic counter register (TAMP_COUNTR) . . . . .1036
33.6.10TAMP backup x register (TAMP_BKPxR) . . . . .1036
33.6.11TAMP register map .....1037
34Inter-integrated circuit interface (I2C) .....1038
34.1Introduction .....1038
34.2I2C main features .....1038
34.3I2C implementation .....1039
34.4I2C functional description .....1039
34.4.1I2C block diagram .....1040
34.4.2I2C pins and internal signals .....1040
34.4.3I2C clock requirements .....1041
34.4.4I2C mode selection .....1041
34.4.5I2C initialization .....1042
34.4.6I2C reset .....1046
34.4.7I2C data transfer .....1047
34.4.8I2C slave mode .....1049
34.4.9I2C master mode .....1058
34.4.10I2C_TIMINGR register configuration examples .....1069
34.4.11SMBus specific features .....1071
34.4.12SMBus initialization .....1073
34.4.13SMBus I2C_TIMEOUTR register configuration examples .....1075
34.4.14SMBus slave mode .....1076
34.4.15SMBus master mode .....1079
34.4.16Wake-up from Stop mode on address match .....1082
34.4.17Error conditions .....1083
34.5I2C in low-power modes .....1085
34.6I2C interrupts .....1085
34.7I2C DMA requests .....1086
34.7.1Transmission using DMA .....1086
34.7.2Reception using DMA .....1086
34.8I2C debug modes .....1087
34.9I2C registers .....1087
34.9.1I2C control register 1 (I2C_CR1) .....1087
34.9.2I2C control register 2 (I2C_CR2) .....1090
34.9.3I2C own address 1 register (I2C_OAR1) .....1092
34.9.4I2C own address 2 register (I2C_OAR2) .....1093
34.9.5I2C timing register (I2C_TIMINGR) .....1094
34.9.6I2C timeout register (I2C_TIMEOUTR) .....1095
34.9.7I2C interrupt and status register (I2C_ISR) .....1096
34.9.8I2C interrupt clear register (I2C_ICR) .....1098
34.9.9I2C PEC register (I2C_PECR) .....1099
34.9.10I2C receive data register (I2C_RXDR) .....1099
34.9.11I2C transmit data register (I2C_TXDR) .....1100
34.9.12I2C register map .....1101
35Universal synchronous/asynchronous receiver transmitter (USART/UART) .....1102
35.1USART introduction .....1102
35.2USART main features .....1103
35.3USART extended features .....1104
35.4USART implementation .....1104
35.5USART functional description .....1105
35.5.1USART block diagram .....1105
35.5.2USART signals .....1106
35.5.3USART character description .....1107
35.5.4USART FIFOs and thresholds .....1109
35.5.5USART transmitter .....1109
35.5.6USART receiver .....1113
35.5.7USART baud rate generation .....1120
35.5.8Tolerance of the USART receiver to clock deviation .....1121
35.5.9USART auto baud rate detection .....1123
35.5.10USART multiprocessor communication .....1125
35.5.11USART Modbus communication .....1127
35.5.12USART parity control .....1128
35.5.13USART LIN (local interconnection network) mode .....1129
35.5.14USART synchronous mode .....1131
35.5.15USART single-wire half-duplex communication .....1135
35.5.16USART receiver timeout .....1135
35.5.17USART smartcard mode .....1136
35.5.18USART IrDA SIR ENDEC block .....1140
35.5.19Continuous communication using USART and DMA .....1143
35.5.20RS232 hardware flow control and RS485 Driver Enable .....1145
35.5.21USART low-power management .....1148
35.6USART in low-power modes .....1151
35.7USART interrupts . . . . .1152
35.8USART registers . . . . .1153
35.8.1USART control register 1 (USART_CR1) . . . . .1153
35.8.2USART control register 1 [alternate] (USART_CR1) . . . . .1156
35.8.3USART control register 2 (USART_CR2) . . . . .1160
35.8.4USART control register 3 (USART_CR3) . . . . .1164
35.8.5USART baud rate register (USART_BRR) . . . . .1168
35.8.6USART guard time and prescaler register (USART_GTPR) . . . . .1168
35.8.7USART receiver timeout register (USART_RTOR) . . . . .1169
35.8.8USART request register (USART_RQR) . . . . .1170
35.8.9USART interrupt and status register (USART_ISR) . . . . .1171
35.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .1177
35.8.11USART interrupt flag clear register (USART_ICR) . . . . .1182
35.8.12USART receive data register (USART_RDR) . . . . .1184
35.8.13USART transmit data register (USART_TDR) . . . . .1184
35.8.14USART prescaler register (USART_PRESC) . . . . .1185
35.8.15USART register map . . . . .1186
36Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1188
36.1LPUART introduction . . . . .1188
36.2LPUART main features . . . . .1189
36.3LPUART implementation . . . . .1190
36.4LPUART functional description . . . . .1191
36.4.1LPUART block diagram . . . . .1191
36.4.2LPUART signals . . . . .1192
36.4.3LPUART character description . . . . .1193
36.4.4LPUART FIFOs and thresholds . . . . .1194
36.4.5LPUART transmitter . . . . .1195
36.4.6LPUART receiver . . . . .1198
36.4.7LPUART baud rate generation . . . . .1202
36.4.8Tolerance of the LPUART receiver to clock deviation . . . . .1203
36.4.9LPUART multiprocessor communication . . . . .1204
36.4.10LPUART parity control . . . . .1206
36.4.11LPUART single-wire half-duplex communication . . . . .1207
36.4.12Continuous communication using DMA and LPUART . . . . .1207
36.4.13RS232 hardware flow control and RS485 Driver Enable . . . . .1210
36.4.14LPUART low-power management . . . . .1212
36.5LPUART in low-power modes . . . . .1215
36.6LPUART interrupts . . . . .1216
36.7LPUART registers . . . . .1217
36.7.1LPUART control register 1 (LPUART_CR1) . . . . .1217
36.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1220
36.7.3LPUART control register 2 (LPUART_CR2) . . . . .1223
36.7.4LPUART control register 3 (LPUART_CR3) . . . . .1225
36.7.5LPUART baud rate register (LPUART_BRR) . . . . .1228
36.7.6LPUART request register (LPUART_RQR) . . . . .1228
36.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .1229
36.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1233
36.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .1236
36.7.10LPUART receive data register (LPUART_RDR) . . . . .1237
36.7.11LPUART transmit data register (LPUART_TDR) . . . . .1237
36.7.12LPUART prescaler register (LPUART_PRESC) . . . . .1238
36.7.13LPUART register map . . . . .1239
37Serial peripheral interface / integrated interchip sound (SPI/I2S) . . . . .1241
37.1Introduction . . . . .1241
37.2SPI main features . . . . .1241
37.3I2S main features . . . . .1242
37.4SPI/I2S implementation . . . . .1242
37.5SPI functional description . . . . .1243
37.5.1General description . . . . .1243
37.5.2Communications between one master and one slave . . . . .1244
37.5.3Standard multislave communication . . . . .1246
37.5.4Multimaster communication . . . . .1247
37.5.5Slave select (NSS) pin management . . . . .1248
37.5.6Communication formats . . . . .1249
37.5.7Configuration of SPI . . . . .1251
37.5.8Procedure for enabling SPI . . . . .1252
37.5.9Data transmission and reception procedures . . . . .1252
37.5.10SPI status flags . . . . .1262
37.5.11SPI error flags . . . . .1263
37.5.12NSS pulse mode . . . . .1264
37.5.13TI mode1264
37.5.14CRC calculation1265
37.6SPI interrupts1267
37.7I2S functional description1268
37.7.1I2S general description1268
37.7.2Supported audio protocols1269
37.7.3Start-up description1276
37.7.4Clock generator1278
37.7.5I 2 S master mode1281
37.7.6I 2 S slave mode1282
37.7.7I2S status flags1284
37.7.8I2S error flags1285
37.7.9DMA features1286
37.8I2S interrupts1286
37.9SPI and I2S registers1287
37.9.1SPI control register 1 (SPIx_CR1)1287
37.9.2SPI control register 2 (SPIx_CR2)1289
37.9.3SPI status register (SPIx_SR)1291
37.9.4SPI data register (SPIx_DR)1293
37.9.5SPI CRC polynomial register (SPIx_CRCPR)1293
37.9.6SPI Rx CRC register (SPIx_RXCRCR)1293
37.9.7SPI Tx CRC register (SPIx_TXCRCR)1294
37.9.8SPIx_I2S configuration register (SPIx_I2SCFGR)1294
37.9.9SPIx_I2S prescaler register (SPIx_I2SPR)1296
37.9.10SPI/I2S register map1298
38Debug support (DBG)1299
38.1DBG introduction and main features1299
38.2DBG use cases1300
38.3DBG functional description1300
38.3.1DBG block diagram1300
38.3.2DBG pins and internal signals1301
38.3.3DBG interface control1301
38.3.4DBG reset and clocks1302
38.3.5DBG power domains1302
38.3.6DBG low-power modes1302
38.3.7Serial-wire and JTAG debug port . . . . .1302
38.3.8JTAG debug port . . . . .1303
38.3.9Serial-wire debug port . . . . .1306
38.4Debug port (DP) registers . . . . .1307
38.4.1DP identification register (DP_PIDR) . . . . .1309
38.4.2DP abort register (DP_ABORTR) . . . . .1309
38.4.3DP control and status register (DP_CTRLSTATR) . . . . .1310
38.4.4DP data link control register (DP_DLCR) . . . . .1312
38.4.5DP target identification register (DP_TARGETIDR) . . . . .1313
38.4.6DP data link protocol identification register (DP_DLPIDR) . . . . .1313
38.4.7DP resend register (DP_RESENR) . . . . .1314
38.4.8DP access port select register (DP_SELECTR) . . . . .1314
38.4.9DP read buffer register (DP_BUFFR) . . . . .1315
38.4.10DP target identification register (DP_TARGETSELR) . . . . .1315
38.4.11DP register map and reset values . . . . .1316
38.5Access ports . . . . .1317
38.5.1AP control/status word register (AP_CSWR) . . . . .1321
38.5.2AP transfer address register (AP_TAR) . . . . .1322
38.5.3AP data read/write register (AP_DRWR) . . . . .1322
38.5.4AP banked data registers x (AP_BDxR) . . . . .1323
38.5.5AP base address register (AP_BASER) . . . . .1323
38.5.6AP identification register (AP_IDR) . . . . .1324
38.5.7AP register map and reset values . . . . .1324
38.6Data watchpoint and trace unit (DWT) . . . . .1325
38.6.1DWT control register (DWT_CTRLR) . . . . .1326
38.6.2DWT cycle count register (DWT_CYCCNTR) . . . . .1328
38.6.3DWT CPI count register (DWT_CPICNTR) . . . . .1328
38.6.4DWT exception count register (DWT_EXCCNTR) . . . . .1328
38.6.5DWT sleep count register (DWT_SLP CNTR) . . . . .1329
38.6.6DWT LSU count register (DWT_LSUCNTR) . . . . .1329
38.6.7DWT fold count register (DWT_FOLDCNTR) . . . . .1329
38.6.8DWT program counter sample register (DWT_PCSR) . . . . .1330
38.6.9DWT comparator register x (DWT_COMPxR) . . . . .1330
38.6.10DWT mask register x (DWT_MASKxR) . . . . .1330
38.6.11DWT function register x (DWT_FUNCTxR) . . . . .1331
38.6.12DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1332
38.6.13DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1332
38.6.14DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1333
38.6.15DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1333
38.6.16DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1334
38.6.17DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1334
38.6.18DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1334
38.6.19DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1335
38.6.20DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1335
38.6.21DWT register map . . . . .1336
38.7Cross trigger interface (CTI) and cross trigger matrix (CTM) . . . . .1338
38.7.1CTI registers . . . . .1342
38.8CPU1 ROM table . . . . .1358
38.8.1CPU1 ROM memory type register (ROM_MEMTYPE) . . . . .1360
38.8.2CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4) . . . . .1361
38.8.3CPU1 ROM CoreSight peripheral identity register 0 (ROM_PIDR0) . . . . .1361
38.8.4CPU1 ROM CoreSight peripheral identity register 1 (ROM_PIDR1) . . . . .1362
38.8.5CPU1 ROM CoreSight peripheral identity register 2 (ROM_PIDR2) . . . . .1362
38.8.6CPU1 ROM CoreSight peripheral identity register 3 (ROM_PIDR3) . . . . .1363
38.8.7CPU1 ROM CoreSight component identity register 0 (ROM_CIDR0) . . . . .1363
38.8.8CPU1 ROM CoreSight peripheral identity register 1 (ROM_CIDR1) . . . . .1364
38.8.9CPU1 ROM CoreSight component identity register 2 (ROM_CIDR2) . . . . .1364
38.8.10CPU1 ROM CoreSight component identity register 3 (ROM_CIDR3) . . . . .1365
38.8.11CPU1 ROM table register map . . . . .1365
38.9CPU1 breakpoint unit (FPB) . . . . .1366
38.9.1FPB control register (FPB_CTRLR) . . . . .1366
38.9.2FPB remap register (FPB_REMAPR) . . . . .1367
38.9.3FPB comparator register x (FPB_COMPxR) . . . . .1367
38.9.4FPB CoreSight peripheral identity register 4 (FPB_PIDR4) . . . . .1368
38.9.5FPB CoreSight peripheral identity register 0 (FPB_PIDR0) . . . . .1369
38.9.6FPB CoreSight peripheral identity register 1 (FPB_PIDR1) . . . . .1369
38.9.7FPB CoreSight peripheral identity register 2 (FPB_PIDR2) . . . . .1370
38.9.8FPB CoreSight peripheral identity register 3 (FPB_PIDR3) . . . . .1370
38.9.9FPB CoreSight component identity register 0 (FPB_CIDR0) . . . . .1371
38.9.10FPB CoreSight peripheral identity register 1 (FPB_CIDR1) . . . . .1371
38.9.11FPB CoreSight component identity register 2 (FPB_CIDR2) . . . . .1372
38.9.12FPB CoreSight component identity register 3 (FPB_CIDR3) . . . . .1372
38.9.13CPU1 FPB register map . . . . .1372
38.10CPU1 instrumentation trace macrocell (ITM) . . . . .1374
38.10.1ITM stimulus register x (ITM_STIMRx)1374
38.10.2ITM trace enable register (ITM_TER)1375
38.10.3ITM trace privilege register (ITM_TPR)1375
38.10.4ITM trace control register (ITM_TCR)1376
38.10.5ITM CoreSight peripheral identity register 4 (ITM_PIDR4)1377
38.10.6ITM CoreSight peripheral identity register 0 (ITM_PIDR0)1377
38.10.7ITM CoreSight peripheral identity register 1 (ITM_PIDR1)1378
38.10.8ITM CoreSight peripheral identity register 2 (ITM_PIDR2)1378
38.10.9ITM CoreSight peripheral identity register 3 (ITM_PIDR3)1379
38.10.10ITM CoreSight component identity register 0 (ITM_CIDR0)1379
38.10.11ITM CoreSight peripheral identity register 1 (ITM_CIDR1)1380
38.10.12ITM CoreSight component identity register 2 (ITM_CIDR2)1380
38.10.13ITM CoreSight component identity register 3 (ITM_CIDR3)1381
38.10.14CPU1 ITM register map1381
38.11CPU1 trace port interface unit (TPIU)1382
38.11.1TPIU supported port size register (TPIU_SSPSR)1383
38.11.2TPIU current port size register (TPIU_CSPSR)1383
38.11.3TPIU asynchronous clock prescaler register (TPIU_ACPR)1383
38.11.4TPIU selected pin protocol register (TPIU_SPPR)1384
38.11.5TPIU formatter and flush status register (TPIU_FFSR)1384
38.11.6TPIU formatter and flush control register (TPIU_FFCR)1385
38.11.7TPIU formatter synchronization counter register (TPIU_FSCR)1386
38.11.8TPIU claim tag set register (TPIU_CLAIMSETR)1386
38.11.9TPIU claim tag clear register (TPIU_CLAIMCLR)1387
38.11.10TPIU device configuration register (TPIU_DEVIDR)1387
38.11.11TPIU device type identifier register (TPIU_DEVTYPE)1388
38.11.12TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4)1388
38.11.13TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0)1389
38.11.14TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1)1389
38.11.15TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2)1390
38.11.16TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3)1390
38.11.17TPIU CoreSight component identity register 0 (TPIU_CIDR0)1391
38.11.18TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1)1391
38.11.19TPIU CoreSight component identity register 2 (TPIU_CIDR2)1392
38.11.20TPIU CoreSight component identity register 3 (TPIU_CIDR3)1392
38.11.21CPU 1 TPIU register map1392
38.12Microcontroller debug unit (DBGMCU)1394
38.12.1DBGMCU identity code register (DBGMCU_IDCODER) . . . . .1395
38.12.2DBGMCU configuration register (DBGMCU_CR) . . . . .1395
38.12.3DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . .		1396
38.12.4DBGMCU CPU2 APB1 peripheral freeze register 1
(DBGMCU_C2APB1FZR1) . . . . .		1397
38.12.5DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2) . . . . .		1398
38.12.6DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2) . . . . .		1398
38.12.7DBGMCU CPU1 APB2 peripheral freeze register
(DBGMCU_APB2FZR) . . . . .		1399
38.12.8DBGMCU CPU2 APB2 peripheral freeze register
(DBGMCU_C2APB2FZR) . . . . .		1400
38.12.9DBGMCU register map . . . . .1400
38.13CPU2 ROM tables . . . . .1402
38.13.1CPU2 ROM1 memory type register (C2ROM1_MEMTYPER) . . . . .1403
38.13.2CPU2 ROM1 CoreSight peripheral identity register 4
(C2ROM1_PIDR4) . . . . .		1404
38.13.3CPU2 ROM1 CoreSight peripheral identity register 0
(C2ROM1_PIDR0) . . . . .		1404
38.13.4CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_PIDR1) . . . . .		1405
38.13.5CPU2 ROM1 CoreSight peripheral identity register 2
(C2ROM1_PIDR2) . . . . .		1405
38.13.6CPU2 ROM1 CoreSight peripheral identity register 3
(C2ROM1_PIDR3) . . . . .		1406
38.13.7CPU2 ROM1 CoreSight component identity register 0
(C2ROM1_CIDR0) . . . . .		1406
38.13.8CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_CIDR1) . . . . .		1407
38.13.9CPU2 ROM1 CoreSight component identity register 2
(C2ROM1_CIDR2) . . . . .		1407
38.13.10CPU2 ROM1 CoreSight component identity register 3
(C2ROM1_CIDR3) . . . . .		1408
38.13.11CPU2 ROM1 register map . . . . .1408
38.13.12CPU2 ROM2 memory type register (C2ROM2_MEMTYPER) . . . . .1409
38.13.13CPU2 ROM2 CoreSight peripheral identity register 4
(C2ROM2_PIDR4) . . . . .		1409
38.13.14CPU2 ROM2 CoreSight peripheral identity register 0
(C2ROM2_PIDR0) . . . . .		1410
38.13.15 CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_PIDR1) . . . . .1410
38.13.16 CPU2 ROM2 CoreSight peripheral identity register 2 (C2ROM2_PIDR2) . . . . .1411
38.13.17 CPU2 ROM2 CoreSight peripheral identity register 3 (C2ROM2_PIDR3) . . . . .1411
38.13.18 CPU2 ROM2 CoreSight component identity register 0 (C2ROM2_CIDR0) . . . . .1412
38.13.19 CPU2 ROM2 CoreSight peripheral identity register 1 (C2ROM2_CIDR1) . . . . .1412
38.13.20 CPU2 ROM2 CoreSight component identity register 2 (C2ROM2_CIDR2) . . . . .1413
38.13.21 CPU2 ROM2 CoreSight component identity register 3 (C2ROM2_CIDR3) . . . . .1413
38.13.22 CPU2 ROM2 register map . . . . .1413
38.14 CPU2 breakpoint unit (BPU) . . . . .1415
38.14.1 BPU control register (BPU_CTRLR) . . . . .1415
38.14.2 BPU remap register (BPU_REMAPR) . . . . .1415
38.14.3 BPU comparator register x (BPU_COMPxR) . . . . .1416
38.14.4 BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . .1417
38.14.5 BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .1417
38.14.6 BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .1418
38.14.7 BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .1418
38.14.8 BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .1419
38.14.9 BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .1419
38.14.10 BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .1420
38.14.11 BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .1420
38.14.12 BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .1421
38.14.13 CPU2 BPU register map . . . . .1421
38.15 References . . . . .1422
39 Device electronic signature . . . . .1423
39.1 Device electronic signature registers . . . . .1423
39.1.1 Unique device ID register (UID) . . . . .1423
39.1.2 FLASH size data register (FLASHSIZE) . . . . .1424
39.1.3 Package data register (PKG) . . . . .1425
39.1.4 IEEE 64-bit unique device ID register (UID64) . . . . .1425
40 Important security notice . . . . .1427

41      Revision history ..... 1428

List of tables

Table 1. Device boot mode . . . . . 64

Table 2. SRAM erase conditions . . . . . 67

Table 3. Memory security and privilege access . . . . . 70

Table 4. Memory map and peripheral register boundary addresses . . . . . 74

Table 5. GTZC internal signals . . . . . 81

Table 6. Memory access error generation . . . . . 83

Table 7. Peripheral access error generation . . . . . 84

Table 8. TZSC privileged MPCWMn register memory allocation . . . . . 86

Table 9. GTZC TZSC register map and reset values . . . . . 93

Table 10. TZIC register map and reset values . . . . . 98

Table 11. Flash memory - Single bank organization . . . . . 100

Table 12. Number of wait states according to flash clock (HCLK3) frequency . . . . . 102

Table 13. Page erase overview . . . . . 107

Table 14. Mass erase overview . . . . . 108

Table 15. Errors in page-based row programming . . . . . 113

Table 16. Option bytes organization . . . . . 114

Table 17. Option loading control . . . . . 117

Table 18. Flash memory readout protection status . . . . . 119

Table 19. RDP regression from level 1 to level 0 and memory erase . . . . . 121

Table 20. Access status versus protection level and execution modes . . . . . 122

Table 23. Flash interrupt requests . . . . . 128

Table 25. Flash interface register map and reset values . . . . . 152

Table 26. Sub-GHz internal input/output signals . . . . . 155

Table 27. Sub-GHz radio transmit high output power . . . . . 157

Table 28. FSK mode intermediate frequencies . . . . . 158

Table 29. LoRa mode intermediate frequencies . . . . . 159

Table 30. Spreading factor, chips/symbol and LoRa SNR . . . . . 161

Table 31. LoRa bandwidth setting . . . . . 161

Table 32. Coding rate and overhead ratio . . . . . 162

Table 33. Operation mode transition BUSY switching time . . . . . 174

Table 34. Command structure . . . . . 175

Table 35. PA optimal setting and operating modes . . . . . 184

Table 36. Recommended CAD configuration settings . . . . . 186

Table 37. IRQ bit mapping and definition . . . . . 196

Table 38. Image calibration for ISM bands . . . . . 199

Table 39. Command format Set_TcxoMode() . . . . . 201

Table 40. RegTcxoTrim and Timeout bytes definition . . . . . 202

Table 41. Sub-GHz radio SPI commands overview . . . . . 202

Table 42. SUBGHZ register map and reset values . . . . . 225

Table 43. PVM features . . . . . 235

Table 44. Low-power mode summary . . . . . 244

Table 45. Functionalities depending on system operating mode . . . . . 245

Table 46. MCU and sub-GHz radio operating modes . . . . . 247

Table 47. LPRun . . . . . 249

Table 48. CPU wake-up versus system operating mode . . . . . 251

Table 49. Sleep mode . . . . . 252

Table 50. LPSleep . . . . . 253

Table 51. Stop 0 mode . . . . . 255

Table 52.Stop 1 mode . . . . .256
Table 53.Stop 2 mode . . . . .258
Table 54.Standby mode . . . . .260
Table 55.Shutdown mode . . . . .261
Table 56.PWR register map and reset values . . . . .281
Table 57.Clock source stabilization times . . . . .294
Table 58.Clock source frequency . . . . .295
Table 59.SPI2S2 I2S clock PLL configurations . . . . .296
Table 60.Sub-GHz radio SPI clock configurations . . . . .297
Table 61.Peripheral clock enable . . . . .301
Table 62.Low-power debug configurations . . . . .302
Table 63.RCC register map and reset values . . . . .359
Table 64.HSEM internal input/output signals . . . . .366
Table 65.Authorized AHB bus master IDs . . . . .371
Table 66.HSEM register map and reset values . . . . .377
Table 67.IPCC interface signals . . . . .380
Table 68.Bits used for the communication . . . . .381
Table 69.IPCC register map and reset values . . . . .392
Table 70.Port bit configurations . . . . .395
Table 71.GPIOA register map and reset values . . . . .420
Table 72.GPIOB register map and reset values . . . . .421
Table 73.GPIOC register map and reset values . . . . .422
Table 74.GPIOH register map and reset values . . . . .423
Table 75.SYSCFG register map and reset values . . . . .436
Table 76.STM32WL5x peripherals interconnect matrix . . . . .438
Table 77.DMA1 and DMA2 implementation . . . . .447
Table 78.DMA internal input/output signals . . . . .449
Table 79.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .456
Table 80.DMA interrupt requests . . . . .458
Table 81.DMA register map and reset values . . . . .469
Table 82.DMAMUX instantiation . . . . .473
Table 83.DMAMUX1: assignment of multiplexer inputs to resources . . . . .474
Table 84.DMAMUX1: assignment of trigger inputs to resources . . . . .475
Table 85.DMAMUX1: assignment of synchronization inputs to resources . . . . .475
Table 86.DMAMUX signals . . . . .477
Table 87.DMAMUX interrupts . . . . .482
Table 88.DMAMUX register map and reset values . . . . .489
Table 89.CPU1 vector table . . . . .492
Table 90.CPU2 vector table . . . . .495
Table 91.EXTI pin overview . . . . .499
Table 92.EVG pin overview . . . . .499
Table 93.Wake-up interrupts . . . . .500
Table 94.EXTI event input configurations and register control . . . . .503
Table 95.Masking functionality . . . . .504
Table 96.EXTI register map sections . . . . .505
Table 97.EXTI register map and reset values . . . . .515
Table 98.CRC internal input/output signals . . . . .518
Table 99.CRC register map and reset values . . . . .523
Table 100.ADC input/output pins . . . . .526
Table 101.ADC internal input/output signals . . . . .527
Table 102.External triggers . . . . .527
Table 103.Latency between trigger and start of conversion . . . . .532
Table 104.Configuring the trigger polarity . . . . .539
Table 105.tSAR timings depending on resolution . . . . .541
Table 106.Analog watchdog comparison . . . . .550
Table 107.Analog watchdog 1 channel selection . . . . .550
Table 108.Maximum output results vs N and M. Grayed values indicates truncation . . . . .555
Table 109.ADC interrupts . . . . .560
Table 110.ADC register map and reset values . . . . .579
Table 111.DAC features . . . . .582
Table 112.DAC input/output pins . . . . .583
Table 113.DAC internal input/output signals . . . . .583
Table 114.DAC interconnection . . . . .583
Table 115.Sample and refresh timings . . . . .590
Table 116.Channel output modes summary . . . . .591
Table 117.Effect of low-power modes on DAC . . . . .594
Table 118.DAC interrupts . . . . .595
Table 119.DAC register map and reset values . . . . .603
Table 120.VREF buffer modes . . . . .605
Table 121.VREFBUF register map and reset values . . . . .607
Table 122.COMP1 input plus assignment . . . . .609
Table 123.COMP1 input minus assignment . . . . .610
Table 124.COMP2 input plus assignment . . . . .610
Table 125.COMP2 input minus assignment . . . . .610
Table 126.Comparator behavior in the low-power modes . . . . .614
Table 127.Interrupt control bits . . . . .614
Table 128.COMP register map and reset values . . . . .619
Table 129.RNG internal input/output signals . . . . .621
Table 130.RNG interrupt requests . . . . .628
Table 131.RNG configurations . . . . .629
Table 132.Configuration selection . . . . .630
Table 133.RNG register map and reset map . . . . .634
Table 134.AES internal input/output signals . . . . .636
Table 135.CTR mode initialization vector definition . . . . .652
Table 136.GCM last block definition . . . . .654
Table 137.Initialization of AES_IVRx registers in GCM mode . . . . .655
Table 138.Initialization of AES_IVRx registers in CCM mode . . . . .662
Table 139.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .667
Table 140.AES interrupt requests . . . . .670
Table 141.Processing latency for ECB, CBC and CTR . . . . .670
Table 142.Processing latency for GCM and CCM (in clock cycles) . . . . .671
Table 143.AES register map and reset values . . . . .681
Table 144.Internal input/output signals . . . . .684
Table 145.PKA integer arithmetic functions list . . . . .685
Table 146.PKA prime field (Fp) elliptic curve functions list . . . . .685
Table 147.Montgomery parameter computation . . . . .690
Table 148.Modular addition . . . . .691
Table 149.Modular subtraction . . . . .691
Table 150.Montgomery multiplication . . . . .692
Table 151.Modular exponentiation (normal mode) . . . . .693
Table 152.Modular exponentiation (fast mode) . . . . .693
Table 153.Modular inversion . . . . .693
Table 154.Modular reduction . . . . .694
Table 155.Arithmetic addition . . . . .694
Table 156.Arithmetic subtraction . . . . .694
Table 157.Arithmetic multiplication . . . . .695
Table 158.Arithmetic comparison . . . . .695
Table 159.CRT exponentiation . . . . .696
Table 160.Point on elliptic curve Fp check . . . . .697
Table 161.ECC Fp scalar multiplication. . . . .697
Table 162.ECC Fp scalar multiplication (Fast Mode) . . . . .698
Table 163.ECDSA sign - Inputs. . . . .699
Table 164.ECDSA sign - Outputs . . . . .699
Table 165.Extended ECDSA sign (extra outputs) . . . . .700
Table 166.ECDSA verification (inputs) . . . . .700
Table 167.ECDSA verification (outputs) . . . . .700
Table 168.Family of supported curves for ECC operations . . . . .701
Table 169.Modular exponentiation computation times . . . . .703
Table 170.ECC scalar multiplication computation times . . . . .703
Table 171.ECDSA signature average computation times . . . . .703
Table 172.ECDSA verification average computation times . . . . .704
Table 173.Point on elliptic curve Fp check average computation times . . . . .704
Table 174.Montgomery parameters average computation times. . . . .704
Table 175.PKA interrupt requests . . . . .704
Table 176.PKA register map and reset values . . . . .708
Table 177.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .751
Table 178.Break protection disarming conditions . . . . .753
Table 179.Counting direction versus encoder signals. . . . .759
Table 180.TIM1 internal trigger connection . . . . .776
Table 181.Output control bits for complementary OCx and OCxN channels with break feature. . . . .790
Table 182.TIM1 register map and reset values . . . . .807
Table 183.Counting direction versus encoder signals. . . . .843
Table 184.TIM2 internal trigger connection . . . . .861
Table 185.Output control bit for standard OCx channels. . . . .872
Table 186.TIM2 register map and reset values . . . . .879
Table 187.Break protection disarming conditions . . . . .904
Table 188.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .921
Table 189.TIM16/TIM17 register map and reset values . . . . .932
Table 190.STM32WL5x LPTIM features . . . . .934
Table 191.LPTIM input/output pins . . . . .935
Table 192.LPTIM internal signals . . . . .936
Table 193.LPTIM1 external trigger connections . . . . .936
Table 194.LPTIM2 external trigger connections . . . . .936
Table 195.LPTIM3 external trigger connections . . . . .937
Table 196.LPTIM1 input 1 connections . . . . .937
Table 197.LPTIM1 input 2 connections . . . . .937
Table 198.LPTIM2 input 1 connections . . . . .937
Table 199.LPTIM3 input 1 connections . . . . .937
Table 200.Prescaler division ratios . . . . .939
Table 201.Encoder counting scenarios . . . . .946
Table 202.Effect of low-power modes on the LPTIM. . . . .949
Table 203.Interrupt events. . . . .949
Table 204.LPTIM register map and reset values. . . . .960
Table 205.IWDG register map and reset values . . . . .971
Table 206.WWDG internal input/output signals. . . . .973
Table 207.WWDG register map and reset values . . . . .977
Table 208.RTC input/output pins . . . . .980
Table 209.RTC internal input/output signals . . . . .980
Table 210.RTC interconnection . . . . .981
Table 211.PC13 configuration . . . . .981
Table 212.RTC_OUT mapping . . . . .983
Table 213.Effect of low-power modes on RTC . . . . .996
Table 214.RTC pins functionality over modes . . . . .996
Table 215.Interrupt requests . . . . .997
Table 216.RTC register map and reset values . . . . .1019
Table 217.TAMP input/output pins . . . . .1023
Table 218.TAMP internal input/output signals . . . . .1023
Table 219.TAMP interconnection . . . . .1023
Table 220.Effect of low-power modes on TAMP . . . . .1026
Table 221.Interrupt requests . . . . .1026
Table 222.TAMP register map and reset values . . . . .1037
Table 223.I2C implementation . . . . .1039
Table 224.I2C input/output pins . . . . .1040
Table 225.I2C internal input/output signals . . . . .1041
Table 226.Comparison of analog and digital filters . . . . .1043
Table 227.I 2 C-bus and SMBus specification data setup and hold times . . . . .1045
Table 228.I2C configuration . . . . .1049
Table 229.I 2 C-bus and SMBus specification clock timings . . . . .1060
Table 230.Timing settings for f I2CCLK of 8 MHz . . . . .1070
Table 231.Timing settings for f I2CCLK of 16 MHz . . . . .1070
Table 232.SMBus timeout specifications . . . . .1072
Table 233.SMBus with PEC configuration . . . . .1074
Table 234.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1075
Table 235.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1075
Table 236.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1075
Table 237.Effect of low-power modes to I2C . . . . .1085
Table 238.I2C interrupt requests . . . . .1085
Table 239.I2C register map and reset values . . . . .1101
Table 240.USART / LPUART features . . . . .1104
Table 241.USART/UART input/output pins . . . . .1107
Table 242.USART internal input/output signals . . . . .1107
Table 243.Noise detection from sampled data . . . . .1119
Table 244.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1122
Table 245.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1123
Table 246.USART frame formats . . . . .1128
Table 247.Effect of low-power modes on the USART . . . . .1151
Table 248.USART interrupt requests . . . . .1152
Table 249.USART register map and reset values . . . . .1186
Table 250.USART / LPUART features . . . . .1190
Table 251.LPUART input/output pins . . . . .1192
Table 252.LPUART internal input/output signals . . . . .1192
Table 253.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .1202
Table 254.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .1203
Table 255.Tolerance of the LPUART receiver . . . . .1204
Table 257.Effect of low-power modes on the LPUART . . . . .1215
Table 258.LPUART interrupt requests . . . . .1216
Table 259.LPUART register map and reset values . . . . .1239
Table 260.STM32WL5x SPI and SPI/I2S implementation. . . . .1242
Table 261.SPI interrupt requests . . . . .1267
Table 262.Audio-frequency precision using 48 MHz clock derived from HSE. . . . .1280
Table 263.I2S interrupt requests . . . . .1286
Table 264.SPI/I2S register map and reset values . . . . .1298
Table 265.JTAG/Serial-wire debug port pins. . . . .1301
Table 266.Single-wire trace port pins . . . . .1301
Table 267.Debug access control overview . . . . .1301
Table 268.JTAG-DP data registers . . . . .1305
Table 269.Packet request . . . . .1306
Table 270.ACK response. . . . .1307
Table 271.Data transfer. . . . .1307
Table 272.Debug port registers . . . . .1308
Table 273.DP register map and reset values . . . . .1316
Table 274.MEM-AP registers. . . . .1318
Table 275.AP register map and reset values. . . . .1324
Table 276.DWT register map and reset values . . . . .1336
Table 277.CPU2 CTI inputs. . . . .1338
Table 278.CPU2 CTI outputs. . . . .1339
Table 279.CPU1 CTI inputs. . . . .1339
Table 280.CPU1 CTI outputs. . . . .1339
Table 281.CTI register map and reset values . . . . .1355
Table 282.CPU1 ROM table . . . . .1359
Table 283.CPU1 ROM table register map and reset values . . . . .1365
Table 284.CPU1 FPB register map and reset values . . . . .1372
Table 285.CPU1 ITM register map and reset values. . . . .1381
Table 286.TPIU register map and reset values . . . . .1392
Table 287.DBGMCU register map and reset values . . . . .1400
Table 288.ROM1 table. . . . .1402
Table 289.ROM2 table. . . . .1402
Table 290.CPU2 processor ROM table register map and reset values. . . . .1408
Table 291.CPU2 ROM table register map and reset values . . . . .1413
Table 292.CPU2 BPU register map and reset values . . . . .1421
Table 293.Document revision history . . . . .1428

List of figures

Figure 1.System architecture . . . . .63
Figure 2.Memory protection example . . . . .69
Figure 3.Memory map . . . . .73
Figure 4.GTZC security architecture . . . . .80
Figure 5.GTZC block diagram. . . . .81
Figure 6.Memory protection control water mark . . . . .85
Figure 7.Sequential 16 bits instructions execution . . . . .104
Figure 8.Changing the RDP level . . . . .122
Figure 9.Sub-GHz radio system block diagram . . . . .155
Figure 10.High output power PA. . . . .156
Figure 11.Low output power PA . . . . .157
Figure 12.LoRa packet frames format . . . . .163
Figure 13.Generic packet frames format . . . . .166
Figure 14.Sub-GHz RAM data buffer operation . . . . .168
Figure 15.Sub-GHz radio operating modes . . . . .170
Figure 16.Sub-GHz radio BUSY timing. . . . .174
Figure 17.Receiver listening mode timing . . . . .180
Figure 18.Power supply overview . . . . .228
Figure 19.Supply configurations . . . . .229
Figure 20.Brownout reset waveform . . . . .234
Figure 21.PVD thresholds . . . . .235
Figure 22.EOL thresholds . . . . .236
Figure 23.Radio busy management . . . . .237
Figure 24.CPU2 boot options . . . . .239
Figure 25.CPUs low-power modes possible transitions . . . . .243
Figure 26.Simplified diagram of the reset circuit. . . . .284
Figure 27.Clock tree . . . . .288
Figure 28.HSE32 clock sources . . . . .289
Figure 29.HSE32 TCXO control . . . . .290
Figure 30.LSE clock sources . . . . .293
Figure 31.Frequency measurement with TIM16 in capture mode. . . . .299
Figure 32.Frequency measurement with TIM17 in capture mode. . . . .299
Figure 33.HSEM block diagram . . . . .366
Figure 34.Procedure state diagram . . . . .367
Figure 35.Interrupt state diagram . . . . .370
Figure 36.IPCC block diagram . . . . .380
Figure 37.IPCC Simplex channel mode transfer timing . . . . .381
Figure 38.IPCC Simplex - Send procedure state diagram . . . . .382
Figure 39.IPCC Simplex - Receive procedure state diagram . . . . .383
Figure 40.IPCC Half-duplex channel mode transfer timing. . . . .384
Figure 41.IPCC Half-duplex - Send procedure state diagram . . . . .384
Figure 42.IPCC Half-duplex - Receive procedure state diagram . . . . .385
Figure 43.Basic structure of a standard I/O port bit . . . . .394
Figure 44.Basic structure of a 5V-tolerant I/O port bit. . . . .395
Figure 45.Input floating/pull-up/pull-down configurations . . . . .399
Figure 46.Output configuration . . . . .400
Figure 47.Alternate function configuration . . . . .400
Figure 48.High impedance analog configuration . . . . .401
Figure 49.DMA block diagram .....448
Figure 50.DMAMUX block diagram .....476
Figure 51.Synchronization mode of the DMAMUX request line multiplexer channel .....480
Figure 52.Event generation of the DMA request line multiplexer channel .....480
Figure 53.Interrupt block diagram .....492
Figure 54.EXTI block diagram .....499
Figure 55.Configurable event trigger logic CPU wake-up .....503
Figure 56.Direct event trigger logic CPU wake-up .....504
Figure 57.CRC calculation unit block diagram .....518
Figure 58.ADC block diagram .....526
Figure 59.ADC calibration .....529
Figure 60.Calibration factor forcing .....529
Figure 61.Enabling/disabling the ADC .....530
Figure 62.ADC clock scheme .....531
Figure 63.ADC connectivity .....533
Figure 64.Analog-to-digital conversion time .....538
Figure 65.ADC conversion timings .....538
Figure 66.Stopping an ongoing conversion .....539
Figure 67.Single conversions of a sequence, software trigger .....542
Figure 68.Continuous conversion of a sequence, software trigger .....542
Figure 69.Single conversions of a sequence, hardware trigger .....543
Figure 70.Continuous conversions of a sequence, hardware trigger .....543
Figure 71.Data alignment and resolution (oversampling disabled: OVSE = 0) .....544
Figure 72.Example of overrun (OVR) .....545
Figure 73.Wait mode conversion (continuous mode, software trigger) .....548
Figure 74.Behavior with WAIT = 0, AUTOFF = 1 .....549
Figure 75.Behavior with WAIT = 1, AUTOFF = 1 .....549
Figure 76.Analog watchdog guarded area .....550
Figure 77.ADC_AWDx_OUT signal generation .....552
Figure 78.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) .....552
Figure 79.ADC_AWDx_OUT signal generation (on a single channel) .....553
Figure 80.Analog watchdog threshold update .....553
Figure 81.20-bit to 16-bit result truncation .....554
Figure 82.Numerical example with 5-bit shift and rounding .....554
Figure 83.Triggered oversampling mode (TOVS bit = 1) .....556
Figure 84.Temperature sensor and VREFINT channel block diagram .....557
Figure 85.VBAT channel block diagram .....559
Figure 86.DAC block diagram .....582
Figure 87.Data registers in single DAC channel mode .....584
Figure 88.Timing diagram for conversion with trigger disabled TEN = 0 .....585
Figure 89.DAC LFSR register calculation algorithm .....587
Figure 90.DAC conversion (SW trigger enabled) with LFSR wave generation .....587
Figure 91.DAC triangle wave generation .....588
Figure 92.DAC conversion (SW trigger enabled) with triangle wave generation .....588
Figure 93.DAC sample and hold mode phase diagram .....591
Figure 94.Comparator block diagram .....609
Figure 95.Window mode .....612
Figure 96.Comparator hysteresis .....612
Figure 97.Comparator output blanking .....613
Figure 98.RNG block diagram .....621
Figure 99.NIST SP800-90B entropy source model .....622
Figure 100.RNG initialization overview .....625
Figure 101. AES block diagram . . . . .636
Figure 102. ECB encryption and decryption principle . . . . .638
Figure 103. CBC encryption and decryption principle . . . . .639
Figure 104. CTR encryption and decryption principle . . . . .640
Figure 105. GCM encryption and authentication principle . . . . .641
Figure 106. GMAC authentication principle . . . . .641
Figure 107. CCM encryption and authentication principle . . . . .642
Figure 108. Example of suspend mode management . . . . .646
Figure 109. ECB encryption . . . . .647
Figure 110. ECB decryption . . . . .647
Figure 111. CBC encryption . . . . .648
Figure 112. CBC decryption . . . . .648
Figure 113. ECB/CBC encryption (Mode 1) . . . . .649
Figure 114. ECB/CBC decryption (Mode 3) . . . . .650
Figure 115. Message construction in CTR mode . . . . .651
Figure 116. CTR encryption . . . . .652
Figure 117. CTR decryption . . . . .652
Figure 118. Message construction in GCM . . . . .654
Figure 119. GCM authenticated encryption . . . . .655
Figure 120. Message construction in GMAC mode . . . . .659
Figure 121. GMAC authentication mode . . . . .659
Figure 122. Message construction in CCM mode . . . . .660
Figure 123. CCM mode authenticated encryption . . . . .662
Figure 124. 128-bit block construction with respect to data swap . . . . .666
Figure 125. DMA transfer of a 128-bit data block during input phase . . . . .668
Figure 126. DMA transfer of a 128-bit data block during output phase . . . . .669
Figure 127. PKA block diagram . . . . .684
Figure 128. Advanced-control timer block diagram . . . . .711
Figure 129. Counter timing diagram with prescaler division change from 1 to 2 . . . . .713
Figure 130. Counter timing diagram with prescaler division change from 1 to 4 . . . . .713
Figure 131. Counter timing diagram, internal clock divided by 1 . . . . .715
Figure 132. Counter timing diagram, internal clock divided by 2 . . . . .715
Figure 133. Counter timing diagram, internal clock divided by 4 . . . . .716
Figure 134. Counter timing diagram, internal clock divided by N . . . . .716
Figure 135. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .717
Figure 136. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .717
Figure 137. Counter timing diagram, internal clock divided by 1 . . . . .719
Figure 138. Counter timing diagram, internal clock divided by 2 . . . . .719
Figure 139. Counter timing diagram, internal clock divided by 4 . . . . .720
Figure 140. Counter timing diagram, internal clock divided by N . . . . .720
Figure 141. Counter timing diagram, update event when repetition counter is not used . . . . .721
Figure 142. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .722
Figure 143. Counter timing diagram, internal clock divided by 2 . . . . .723
Figure 144. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .723
Figure 145. Counter timing diagram, internal clock divided by N . . . . .724
Figure 146. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .724
Figure 147. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .725
Figure 148. Update rate examples depending on mode and TIMx_RCR register settings . . . . .726
Figure 149. External trigger input block . . . . .727
Figure 150. TIM1 ETR input circuitry . . . . .727
Figure 151. Control circuit in normal mode, internal clock divided by 1 . . . . .728
Figure 152. TI2 external clock connection example . . . . .729
Figure 153. Control circuit in external clock mode 1 . . . . .730
Figure 154. External trigger input block . . . . .730
Figure 155. Control circuit in external clock mode 2 . . . . .731
Figure 156. Capture/compare channel (example: channel 1 input stage) . . . . .732
Figure 157. Capture/compare channel 1 main circuit . . . . .732
Figure 158. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .733
Figure 159. Output stage of capture/compare channel (channel 4). . . . .733
Figure 160. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .734
Figure 161. PWM input mode timing . . . . .736
Figure 162. Output compare mode, toggle on OC1 . . . . .738
Figure 163. Edge-aligned PWM waveforms (ARR=8) . . . . .739
Figure 164. Center-aligned PWM waveforms (ARR=8). . . . .740
Figure 165. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .742
Figure 166. Combined PWM mode on channel 1 and 3 . . . . .743
Figure 167. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .744
Figure 168. Complementary output with dead-time insertion . . . . .745
Figure 169. Dead-time waveforms with delay greater than the negative pulse . . . . .745
Figure 170. Dead-time waveforms with delay greater than the positive pulse. . . . .746
Figure 171. Break and Break2 circuitry overview . . . . .748
Figure 172. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .750
Figure 173. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .751
Figure 174. PWM output state following BRK assertion (OSSI=0) . . . . .752
Figure 175. Output redirection (BRK2 request not represented) . . . . .753
Figure 176. Clearing TIMx OCxREF . . . . .754
Figure 177. 6-step generation, COM example (OSSR=1) . . . . .755
Figure 178. Example of one pulse mode. . . . .756
Figure 179. Retriggerable one pulse mode . . . . .758
Figure 180. Example of counter operation in encoder interface mode. . . . .759
Figure 181. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .760
Figure 182. Measuring time interval between edges on 3 signals . . . . .761
Figure 183. Example of Hall sensor interface . . . . .763
Figure 184. Control circuit in reset mode . . . . .764
Figure 185. Control circuit in Gated mode . . . . .765
Figure 186. Control circuit in trigger mode . . . . .766
Figure 187. Control circuit in external clock mode 2 + trigger mode . . . . .767
Figure 188. General-purpose timer block diagram . . . . .811
Figure 189. Counter timing diagram with prescaler division change from 1 to 2 . . . . .813
Figure 190. Counter timing diagram with prescaler division change from 1 to 4 . . . . .813
Figure 191. Counter timing diagram, internal clock divided by 1 . . . . .814
Figure 192. Counter timing diagram, internal clock divided by 2 . . . . .815
Figure 193. Counter timing diagram, internal clock divided by 4 . . . . .815
Figure 194. Counter timing diagram, internal clock divided by N. . . . .816
Figure 195. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .816
Figure 196. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .817
Figure 197. Counter timing diagram, internal clock divided by 1 . . . . .818
Figure 198. Counter timing diagram, internal clock divided by 2 . . . . .818
Figure 199. Counter timing diagram, internal clock divided by 4 . . . . .819
Figure 200. Counter timing diagram, internal clock divided by N. . . . .819
Figure 201. Counter timing diagram, Update event . . . . .820
Figure 202. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .821
Figure 203. Counter timing diagram, internal clock divided by 2 . . . . .822
Figure 204. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .822
Figure 205. Counter timing diagram, internal clock divided by N . . . . .823
Figure 206. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .823
Figure 207. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .824
Figure 208. Control circuit in normal mode, internal clock divided by 1 . . . . .825
Figure 209. TI2 external clock connection example. . . . .825
Figure 210. Control circuit in external clock mode 1 . . . . .826
Figure 211. External trigger input block . . . . .827
Figure 212. Control circuit in external clock mode 2 . . . . .828
Figure 213. Capture/Compare channel (example: channel 1 input stage) . . . . .828
Figure 214. Capture/Compare channel 1 main circuit . . . . .829
Figure 215. Output stage of Capture/Compare channel (channel 1) . . . . .829
Figure 216. PWM input mode timing . . . . .831
Figure 217. Output compare mode, toggle on OC1 . . . . .833
Figure 218. Edge-aligned PWM waveforms (ARR=8) . . . . .834
Figure 219. Center-aligned PWM waveforms (ARR=8) . . . . .836
Figure 220. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .837
Figure 221. Combined PWM mode on channels 1 and 3 . . . . .838
Figure 222. Clearing TIMx_OCxREF . . . . .839
Figure 223. Example of one-pulse mode. . . . .840
Figure 224. Retriggerable one-pulse mode . . . . .842
Figure 225. Example of counter operation in encoder interface mode . . . . .843
Figure 226. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .844
Figure 227. Control circuit in reset mode . . . . .845
Figure 228. Control circuit in gated mode . . . . .846
Figure 229. Control circuit in trigger mode . . . . .847
Figure 230. Control circuit in external clock mode 2 + trigger mode . . . . .848
Figure 231. Master/Slave timer example . . . . .849
Figure 232. Master/slave connection example with 1 channel only timers . . . . .849
Figure 233. Gating TIM2 with OC1REF of TIM1 . . . . .850
Figure 234. Gating TIM2 with Enable of TIM1 . . . . .851
Figure 235. Triggering TIM2 with update of TIM1 . . . . .852
Figure 236. Triggering TIM2 with Enable of TIM1 . . . . .852
Figure 237. TIM16/TIM17 block diagram . . . . .883
Figure 238. Counter timing diagram with prescaler division change from 1 to 2 . . . . .885
Figure 239. Counter timing diagram with prescaler division change from 1 to 4 . . . . .885
Figure 240. Counter timing diagram, internal clock divided by 1 . . . . .887
Figure 241. Counter timing diagram, internal clock divided by 2 . . . . .887
Figure 242. Counter timing diagram, internal clock divided by 4 . . . . .888
Figure 243. Counter timing diagram, internal clock divided by N . . . . .888
Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .889
Figure 245. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .889
Figure 246. Update rate examples depending on mode and TIMx_RCR register settings . . . . .891
Figure 247. Control circuit in normal mode, internal clock divided by 1 . . . . .892
Figure 248. TI2 external clock connection example. . . . .892
Figure 249. Control circuit in external clock mode 1 . . . . .893
Figure 250. Capture/compare channel (example: channel 1 input stage) . . . . .894
Figure 251. Capture/compare channel 1 main circuit . . . . .894
Figure 252. Output stage of capture/compare channel (channel 1) . . . . .895
Figure 253. Output compare mode, toggle on OC1 . . . . .898
Figure 254. Edge-aligned PWM waveforms (ARR=8) . . . . .899
Figure 255.Complementary output with dead-time insertion. . . . .900
Figure 256.Dead-time waveforms with delay greater than the negative pulse. . . . .900
Figure 257.Dead-time waveforms with delay greater than the positive pulse. . . . .901
Figure 258.Output behavior in response to a break . . . . .903
Figure 259.Output redirection . . . . .905
Figure 260.6-step generation, COM example (OSSR=1) . . . . .906
Figure 261.Example of one pulse mode . . . . .907
Figure 262.Low-power timer block diagram . . . . .935
Figure 263.Glitch filter timing diagram . . . . .939
Figure 264.LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		940
Figure 265.LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		941
Figure 266.LPTIM output waveform, Continuous counting mode configuration . . . . .941
Figure 267.Waveform generation . . . . .943
Figure 268.Encoder mode counting sequence . . . . .947
Figure 269.Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		948
Figure 270.IRTIM internal hardware connections with TIM16 and TIM17 . . . . .962
Figure 271.Independent watchdog block diagram . . . . .963
Figure 272.Watchdog block diagram . . . . .973
Figure 273.Window watchdog timing diagram . . . . .974
Figure 274.RTC block diagram . . . . .979
Figure 275.TAMP block diagram . . . . .1022
Figure 276.Block diagram . . . . .1040
Figure 277.I 2 C-bus protocol . . . . .1042
Figure 278.Setup and hold timings . . . . .1044
Figure 279.I2C initialization flow . . . . .1046
Figure 280.Data reception . . . . .1047
Figure 281.Data transmission . . . . .1048
Figure 282.Slave initialization flow . . . . .1051
Figure 283.Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . .1053
Figure 284.Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . .1054
Figure 285.Transfer bus diagrams for I2C slave transmitter (mandatory events only). . . . .1055
Figure 286.Transfer sequence flow for I2C slave receiver, NOSTRETCH = 0 . . . . .1056
Figure 287.Transfer sequence flow for I2C slave receiver, NOSTRETCH = 1 . . . . .1057
Figure 288.Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . .		1057
Figure 289.Master clock generation . . . . .1059
Figure 290.Master initialization flow . . . . .1061
Figure 291.10-bit address read access with HEAD10R = 0 . . . . .1061
Figure 292.10-bit address read access with HEAD10R = 1 . . . . .1062
Figure 293.Transfer sequence flow for I2C master transmitter, N ≤ 255 bytes. . . . .1063
Figure 294.Transfer sequence flow for I2C master transmitter, N > 255 bytes . . . . .1064
Figure 295.Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . .		1065
Figure 296.Transfer sequence flow for I2C master receiver, N ≤ 255 bytes . . . . .1067
Figure 297.Transfer sequence flow for I2C master receiver, N > 255 bytes. . . . .1068
Figure 298.Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . .		1069
Figure 299.Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1073
Figure 300.Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . .1076
Figure 301.Transfer bus diagram for SMBus slave transmitter (SBC = 1) . . . . .1077
Figure 302.Transfer sequence flow for SMBus slave receiver N bytes + PEC . . . . .1078
Figure 303.Bus transfer diagrams for SMBus slave receiver (SBC = 1) . . . . .1079
Figure 304.Bus transfer diagrams for SMBus master transmitter . . . . .1080
Figure 305.Bus transfer diagrams for SMBus master receiver . . . . .1082
Figure 306.USART block diagram . . . . .1105
Figure 307.Word length programming . . . . .1108
Figure 308.Configurable stop bits . . . . .1110
Figure 309.TC/TXE behavior when transmitting . . . . .1113
Figure 310.Start bit detection when oversampling by 16 or 8 . . . . .1114
Figure 311.usart_ker_ck clock divider block diagram . . . . .1117
Figure 312.Data sampling when oversampling by 16 . . . . .1118
Figure 313.Data sampling when oversampling by 8 . . . . .1119
Figure 314.Mute mode using Idle line detection . . . . .1126
Figure 315.Mute mode using address mark detection . . . . .1127
Figure 316.Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .1130
Figure 317.Break detection in LIN mode vs. Framing error detection. . . . .1131
Figure 318.USART example of synchronous master transmission. . . . .1132
Figure 319.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1132
Figure 320.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1133
Figure 321.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1134
Figure 322.ISO 7816-3 asynchronous protocol . . . . .1136
Figure 323.Parity error detection using the 1.5 stop bits . . . . .1138
Figure 324.IrDA SIR ENDEC block diagram. . . . .1142
Figure 325.IrDA data modulation (3/16) - normal mode . . . . .1142
Figure 326.Transmission using DMA . . . . .1144
Figure 327.Reception using DMA . . . . .1145
Figure 328.Hardware flow control between 2 USARTs . . . . .1145
Figure 329.RS232 RTS flow control . . . . .1146
Figure 330.RS232 CTS flow control . . . . .1147
Figure 331.Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1150
Figure 332.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1150
Figure 333.LPUART block diagram . . . . .1191
Figure 334.LPUART word length programming . . . . .1194
Figure 335.Configurable stop bits . . . . .1196
Figure 336.TC/TXE behavior when transmitting . . . . .1198
Figure 337.lpuart_ker_ck clock divider block diagram . . . . .1201
Figure 338.Mute mode using Idle line detection . . . . .1205
Figure 339.Mute mode using address mark detection . . . . .1206
Figure 340.Transmission using DMA . . . . .1208
Figure 341.Reception using DMA . . . . .1209
Figure 342.Hardware flow control between 2 LPUARTs . . . . .1210
Figure 343.RS232 RTS flow control . . . . .1210
Figure 344.RS232 CTS flow control . . . . .1211
Figure 345.Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		1214
Figure 346.Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		1214
Figure 347. SPI block diagram. . . . .1243
Figure 348. Full-duplex single master/ single slave application. . . . .1244
Figure 349. Half-duplex single master/ single slave application . . . . .1245
Figure 350. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1246
Figure 351. Master and three independent slaves. . . . .1247
Figure 352. Multimaster application. . . . .1248
Figure 353. Hardware/software slave select management . . . . .1249
Figure 354. Data clock timing diagram . . . . .1250
Figure 355. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1251
Figure 356. Packing data in FIFO for transmission and reception. . . . .1255
Figure 357. Master full-duplex communication . . . . .1258
Figure 358. Slave full-duplex communication . . . . .1259
Figure 359. Master full-duplex communication with CRC . . . . .1260
Figure 360. Master full-duplex communication in packed mode . . . . .1261
Figure 361. NSSP pulse generation in Motorola SPI master mode. . . . .1264
Figure 362. TI mode transfer . . . . .1265
Figure 363. I2S block diagram . . . . .1268
Figure 364. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .1270
Figure 365. I 2 S Philips standard waveforms (24-bit frame) . . . . .1270
Figure 366. Transmitting 0x8EAA33 . . . . .1271
Figure 367. Receiving 0x8EAA33 . . . . .1271
Figure 368. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .1271
Figure 369. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1271
Figure 370. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .1272
Figure 371. MSB justified 24-bit frame length . . . . .1272
Figure 372. MSB justified 16-bit extended to 32-bit packet frame . . . . .1273
Figure 373. LSB justified 16-bit or 32-bit full-accuracy . . . . .1273
Figure 374. LSB justified 24-bit frame length. . . . .1273
Figure 375. Operations required to transmit 0x3478AE. . . . .1274
Figure 376. Operations required to receive 0x3478AE . . . . .1274
Figure 377. LSB justified 16-bit extended to 32-bit packet frame . . . . .1274
Figure 378. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1275
Figure 379. PCM standard waveforms (16-bit) . . . . .1275
Figure 380. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1276
Figure 381. Start sequence in master mode . . . . .1277
Figure 382. Audio sampling frequency definition . . . . .1278
Figure 383. I 2 S clock generator architecture . . . . .1278
Figure 384. Block diagram of debug support infrastructure . . . . .1300
Figure 385. JTAG TAP state machine . . . . .1304
Figure 386. Debug and access port connections . . . . .1317
Figure 387. Debugger connection to debug components . . . . .1320
Figure 388. Embedded cross trigger . . . . .1338
Figure 389. Mapping trigger inputs to outputs . . . . .1340
Figure 390. Cross trigger configuration example. . . . .1341
Figure 391. CPU1 CoreSight topology . . . . .1360
Figure 392. TPIU architecture . . . . .1382
Figure 393. CPU2 CoreSight topology. . . . .1403

Chapters