13. Analog-to-digital converter (ADC)

13.1 Introduction

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 17 multiplexed channels allowing it to measure signals from 16 external and 1 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined higher or lower thresholds.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

A built-in hardware oversampler allows analog performances to be improved while off-loading the related computational burden from the CPU.

13.2 ADC main features

• High performance
- – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
- – ADC conversion time: 0.87 µs for 12-bit resolution (1.14 MHz), 0.81 µs conversion time for 10-bit resolution, faster conversion times can be obtained by lowering resolution.
- – Self-calibration
- – Programmable sampling time
- – Data alignment with built-in data coherency
- – DMA support
• Low-power
- – The application can reduce PCLK frequency for low-power operation while still keeping optimum ADC performance. For example, 0.87 µs conversion time is kept, whatever the PCLK frequency
- – Wait mode: prevents ADC overrun in applications with low PCLK frequency
- – Auto off mode: ADC is automatically powered off except during the active conversion phase. This dramatically reduces the power consumption of the ADC.
• Analog input channels
- – 16 external analog inputs
- – Three fast channels connected to PA0, PA4 and PA5, and up to 13 standard channels (refer to the device datasheet for details on the corresponding GPIOs)
- – 1 channel for internal reference voltage ( $V_{REFINT}$ )
• Start-of-conversion can be initiated:
- – By software
- – By hardware triggers with configurable polarity (timer events or GPIO input events)
• Conversion modes
- – Can convert a single channel or can scan a sequence of channels.
- – Single mode converts selected inputs once per trigger
- – Continuous mode converts selected inputs continuously
- – Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence conversion, and in case of analog watchdog or overrun events
• Analog watchdog
• Oversampler
- – 16-bit data register
- – Oversampling ratio adjustable from 2 to 256x
- – Programmable data shift up to 8-bits
• ADC input range: $V_{SSA} \leq V_{IN} \leq V_{DDA}$

13.3 ADC functional description

Figure 28 shows the ADC block diagram and Table 52 gives the ADC pin description.

Figure 28. ADC block diagram

The block diagram illustrates the internal architecture of the ADC. At the core is the SAR ADC block, which receives analog input from the ADC_IN[15:0] pins through an input selection and scan control block. This block also manages the VREFINT and V_IN pins. The SAR ADC is connected to a Bias & Ref. block and a DATA[15:0] output bus. The DATA bus connects to an Over-sampler, which in turn connects to an AWDx_OUT output for an analog watchdog. The SAR ADC also receives control signals from a Start & stop control block, which includes WAIT, ADSTART (SW trigger), and ADSTP (stop conversion) signals. The Start & stop control block is connected to a Trigger selection and edge selection block, which receives external triggers TRG0 through TRG7. The Trigger selection block also includes EXTSEL[2:0] and EXTEN[1:0] signals. The SAR ADC is connected to an APB interface, which is part of a system including a CPU and DMA. The APB interface includes signals like AREADY, EOSMP, EOSEQ, EOC, OVR, and AWD. The CPU and DMA are connected to the APB interface via an AHB to APB bridge. The ADC also features an AUTOOFF (Auto-off mode) and ADEN/ADDIS signals. The overall system includes power supply connections (ADC VREF+, Analog supply 1.8 to 3.6V) and various configuration registers like CH_SEL[18:0], CONT (single/cont.), SMP[2:0] (sampling time), DISCEN (Discontinuous mode), TOVS, OVSS[3:0], OVSR[2:0], and OVSE.

ADC block diagram showing internal components like SAR ADC, Bias & Ref., and external connections for triggers, power, and data interfaces.

1. TRGi are mapped at product level. Refer to Table External triggers in Section 13.3.1: ADC pins and internal signals .

13.3.1 ADC pins and internal signals

Table 52. ADC input/output pins

Name	Signal type	Remarks
VDDA	Input, analog power supply	Analog power supply and positive reference voltage for the ADC
VSSA	Input, analog supply ground	Ground for analog power supply
ADC_INx	Analog input signals	Up to 16 external analog input channels

Table 53. ADC internal input/output signals

Internal signal name	Signal type	Description
V _IN[x]	Analog Input channels	Connected either to internal channels or to ADC_INi external channels
TRGx	Input	ADC conversion triggers
V _REFINT	Input	Internal voltage reference output voltage
ADC_AWDx_OUT	Output	Internal analog watchdog output signal connected to on-chip timers (x = Analog watchdog number = 1)

Table 54. External triggers

Name	Source	EXTSEL[2:0]
TRG0	Reserved	000
TRG1	TIM21_CH2	001
TRG2	TIM2_TRGO	010
TRG3	TIM2_CH4	011
TRG4	TIM22_TRGO ⁽¹⁾	100
TRG5	TIM2_CH3	101
TRG6	Reserved	110
TRG7	EXTI11	111

1. TIM21_TRGO is available only in category 1 devices.

13.3.2 ADC voltage regulator (ADVREGEN)

The ADC has a specific internal voltage regulator which must be enabled and stable before using the ADC.

The ADC voltage regulator stabilization time is entirely managed by the hardware and software does not need to care about it.

After ADC operations are complete, the ADC can be disabled (ADEN = 0). To keep power consumption low, it is important to disable the ADC voltage regulator before entering low-power mode (LPRun, LPSleep or Stop mode). Refer to Section : ADVREG disable sequence .

Note: When the internal voltage regulator is disabled, the internal analog calibration is kept.

Analog reference for the ADC internal voltage regulator

The internal ADC voltage regulator uses a buffered copy of the internal voltage reference. This buffer is always enabled when the main voltage regulator is in normal Run mode (MR mode, with the device operating either in Run or Sleep mode). When the main voltage regulator is in low-power mode (with the device operating in LPRun, LPSleep or Stop mode), the voltage reference is disabled and the ADC cannot be used anymore.

The software must follow the procedure described below to manage the ADC in low-power mode:

1. Make sure that the ADC is disabled (ADEN = 0).
2. Write ADVREGEN = 0.
3. Enter low-power mode.
4. Resume from low-power mode.
5. Check that REGLPF = 0.
6. Enable the ADC voltage regulator by using the sequence described in Section : ADVREG enable sequence (ADVREGEN = 1 in ADC_CR).
7. Write ADC_CR ADEN = 1 and wait until ADC_CR ADRDY = 1.
8. Write ADRDY = 1 to clear it.

ADVREG enable sequence

There are three ways to enable the voltage regulator:

• by writing ADVREGEN = 1.
• by launching the calibration by writing by ADCAL = 1 (the ADVREGEN bit is automatically set).
• by enabling the ADC by writing ADEN = 1.

ADVREG disable sequence

To disable the ADC voltage regulator, perform the sequence below:

1. Ensure that the ADC is disabled (ADEN = 0).
2. Write ADVREGEN = 0.

13.3.3 Calibration (ADCAL)

The ADC has a calibration feature. During the procedure, the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power-off. The application must not use the ADC during calibration and must wait until it is complete.

Calibration should be performed before starting A/D conversion. It removes the offset error which may vary from chip to chip due to process variation.

The calibration is initiated by software by setting bit ADCAL = 1. Calibration can only be initiated when the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. After this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).

The internal analog calibration is kept if the ADC is disabled (ADEN = 0) or if the ADC voltage reference is disabled (ADVREGEN = 0). When the ADC operating conditions change ( $V_{DDA}$ changes are the main contributor to ADC offset variations change to a lesser extend), it is recommended to re-run a calibration cycle.

The calibration factor is lost in the following cases:

• The product is in Standby mode (power supply removed from the ADC)
• The ADC peripheral is reset.

The calibration factor is maintained in the following low-power modes: LPRun, LPSleep and Stop.

It is still possible to save and restore the calibration factor by software to save time when re-starting the ADC (as long as temperature and voltage are stable during the ADC power down).

The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion.

Software calibration procedure

1. Ensure that ADEN = 0 and DMAEN = 0.
2. Set ADCAL = 1.
3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the interrupt is enabled by setting the EOCALIE bit in the ADC_IER register. The ADCAL bit can remain set for some time even after EOCAL has been set. As a result, the software must wait for ADCAL = 0 after EOCAL = 1 to be able to set ADEN = 1 for next ADC conversions.
4. The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT registers.

For code example, refer to A.8.1: Calibration code example .

Figure 29. ADC calibration

Timing diagram for ADC calibration showing the relationship between the ADCAL bit, ADC State, and calibration factor registers.

The diagram illustrates the timing of the ADC calibration process. It consists of three horizontal timelines:

ADCAL: A signal that is set high (1) by software (indicated by an upward arrow labeled 'by S/W') and returns low (0) by hardware (indicated by a downward arrow labeled 'by H/W'). The duration of the high state is labeled $t_{CAB}$ .
ADC State: Shows the state of the ADC. It starts in the 'OFF' state, transitions to 'Startup' when ADCAL goes high, then to 'CALIBRATE' when ADCAL goes low, and finally returns to 'OFF' when the calibration factor is written.
ADC_DR[6:0] and ADC_CALFACT[6:0]: These registers are shown to contain '0x00' during the 'CALIBRATE' state. When the ADC returns to the 'OFF' state, they are updated with the 'CALIBRATION FACTOR'.

MS33703V1

Timing diagram for ADC calibration showing the relationship between the ADCAL bit, ADC State, and calibration factor registers.

If the ADC voltage regulator was not previously set, it is automatically enabled when setting ADCAL = 1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC calibration time is longer to take into account the stabilization time of the ADC voltage regulator.

At the end of the calibration, the ADC voltage regulator remains enabled.

Calibration factor forcing software procedure

1. Ensure that ADEN= 1 and ADSTART = 0 (ADC started with no conversion ongoing)
2. Write ADC_CALFACT with the saved calibration factor
3. The calibration factor is used as soon as a new conversion is launched.

Figure 30. Calibration factor forcing

Timing diagram for calibration factor forcing showing ADC state, internal calibration factor, start conversion, write ADC_CALFACT, and CALFACT[6:0] signals.

sequenceDiagram
    Note over ADC state: Ready (not converting)
    Note over ADC state: Converting channel (Single ended)
    Note over ADC state: Ready
    Note over ADC state: Converting channel (Single ended)
    Note over Internal calibration factor: F1
    Note over Internal calibration factor: Updating calibration
    Note over Internal calibration factor: F2
    Note over Start conversion: S/W or H/W trigger
    Note over WRITE ADC_CALFACT: Pulse by S/W
    Note over CALFACT[6:0]: F2 written

The diagram illustrates the timing for forcing a calibration factor. It shows the ADC state transitioning from Ready to Converting. During the first conversion, a software write to ADC_CALFACT occurs. The internal calibration factor updates from F1 to F2. The new factor F2 is applied at the start of the subsequent conversion. A legend indicates that rising edges are software-driven (by S/W) and falling edges are hardware-driven (by H/W).

Timing diagram for calibration factor forcing showing ADC state, internal calibration factor, start conversion, write ADC_CALFACT, and CALFACT[6:0] signals.

13.3.4 ADC on-off control (ADEN, ADDIS, ADRDY)

At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).

As shown in Figure 31 , the ADC needs a stabilization time of $t_{STAB}$ before it starts converting accurately.

Two control bits are used to enable or disable the ADC:

• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation.
• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled.

If the ADC voltage regulator was not previously set, it is automatically enabled when setting ADEN=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC stabilization time $t_{STAB}$ is longer to take into account the stabilization time of the ADC voltage regulator.

Conversion can then start either by setting ADSTART to 1 (refer to Section 13.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) on page 266 ) or when an external trigger event occurs if triggers are enabled.

Follow this procedure to enable the ADC:

1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2. Set ADEN = 1 in the ADC_CR register.
3. Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup time). This can be handled by interrupt if the interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register.

For code example, refer to A.8.2: ADC enable sequence code example .

Follow this procedure to disable the ADC:

1. Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the ADC_CR register and waiting until this bit is read at 0.
2. Set ADDIS = 1 in the ADC_CR register.
3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).

For code example, refer to A.8.3: ADC disable sequence code example .

Figure 31. Enabling/disabling the ADC

The diagram illustrates the timing for enabling and disabling the ADC.
- ADEN : Set by S/W (rising edge), cleared by H/W (falling edge).
- ADRDY : Set by H/W (rising edge) after ADEN rises, cleared by S/W (falling edge). The time from ADEN rise to ADRDY rise is $t_{STAB}$ .
- ADDIS : Set by S/W (rising edge), cleared by H/W (falling edge).
- ADC stat : Shows states OFF, Startup, RDY, CONVERTING CH, RDY, REQ-OF, OFF. The transition from OFF to Startup occurs when ADEN rises. The transition from REQ-OF to OFF occurs when ADEN falls.

Timing diagram for enabling/disabling the ADC showing signals ADEN, ADRDY, ADDIS, and ADC status states (OFF, Startup, RDY, CONVERTING CH, RDY, REQ-OF, OFF).

Note: In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by hardware and the ADRDY flag is not set.

13.3.5 ADC clock (CKMODE, PRESC[3:0], LFMEN)

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 32. ADC clock scheme

The diagram shows the clock architecture for the ADC.
- RCC (Reset & Clock Controller) provides two clocks: PCLK and ADC asynchronous clock .
- PCLK is connected to the ADITF block, specifically to the APB interface and a prescaler ( /1 or /2 or /4 ) controlled by Bits CKMODE[1:0] of ADC_CFGR2 .
- The ADC asynchronous clock is connected to another prescaler ( /1,2,4,6,8,10,12,16,32,64,128,256 ) controlled by Bits PRESC[3:0] of ADC_CCR .
- Both prescalers feed into a multiplexer controlled by Bits CKMODE[1:0] of ADC_CFGR2 . The multiplexer selects between the PCLK-derived clock (labeled 'Others') and the asynchronous clock (labeled '00').
- The output of the multiplexer is Analog ADC_CK , which is connected to the Analog ADC block.

Block diagram of the ADC clock scheme showing RCC providing PCLK and ADC asynchronous clock, passing through prescalers and a multiplexer to generate Analog ADC_CK.

1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are enabled.

The input clock of the analog ADC can be selected between two different clock sources (see Figure 32: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock are enabled):

a) The ADC clock can be a specific clock source, named “ADC asynchronous clock” which is independent and asynchronous with the APB clock.

Refer to RCC Section for more information on generating this clock source.

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be reset.

b) The ADC clock can be derived from the APB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be different from “00”.

For code example, refer to A.8.4: ADC clock selection code example .

In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR register).

Option a) has the advantage of reaching the maximum ADC clock frequency whatever the APB clock scheme selected.

Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains).

Table 55. Latency between trigger and start of conversion ⁽¹⁾

ADC clock source	CKMODE[1:0]	Latency between the trigger event and the start of conversion
HSI16 MHz clock	00	Latency is not deterministic (jitter)
PCLK divided by 2	01	Latency is deterministic (no jitter) and equal to 4.25 ADC clock cycles
PCLK divided by 4	10	Latency is deterministic (no jitter) and equal to 4.125 ADC clock cycles
PCLK divided by 1	11	Latency is deterministic (no jitter) and equal to 4.5 ADC clock cycles

1. Refer to the device datasheet for the maximum ADC_CLK frequency.

Caution: When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and clock controller section). If an internal source clock is selected, the AHB and APB prescalers do not divide the clock.

Low frequency

When selecting an analog ADC clock frequency lower than 3.5 MHz, it is mandatory to first enable the Low Frequency Mode by setting bit LFMEN = 1 into the ADC_CCR register

13.3.6 ADC connectivity

ADC inputs are connected to the external channels as well as internal sources as described in Figure 33.

Figure 33. ADC connectivity

The diagram illustrates the internal architecture of the ADC for the STM32L0x0 microcontroller. On the left, external pins are labeled ADC_IN0 through ADC_IN15. These are connected to internal channel lines labeled VIN[0] through VIN[15]. Above the channel lines, the text 'ADC' and 'Channel selection' is present. Channels VIN[0], VIN[4], and VIN[5] are specifically labeled as 'Fast channel'. Below VIN[15], there are additional channel lines: VIN[16] (labeled 'Reserved'), VIN[17] (labeled 'VREFINT'), and VIN[18] (labeled 'Reserved'). All 19 channel lines (VIN[0] to VIN[18]) are connected to a common bus that feeds into a SAR ADC1 block. The SAR ADC1 block also has inputs for VREF+ and VREF-.

Schematic diagram of ADC connectivity for STM32L0x0. It shows 19 channels (VIN[0] to VIN[18]) connected to a SAR ADC1. Channels 0, 4, and 5 are marked as 'Fast channel'. Channel 17 is labeled VREFINT. Channels 16 and 18 are marked as 'Reserved'. External inputs ADC_IN0 through ADC_IN15 are connected to channels 0 through 15 respectively. The SAR ADC1 has VREF+ and VREF- inputs, and a VIN input connected to the channel selection bus.

13.3.7 Configuring the ADC

The software must write the ADCAL and ADEN bits in the ADC_CR register and configure the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must be cleared).

The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).

For all the other control bits in the ADC_IER, ADC_SMPR, ADC_TR, ADC_CHSELR and ADC_CCR registers, refer to the description of the corresponding control bit in Section 13.11: ADC registers .

The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled (and possibly converting) and there is no pending request to disable the ADC (ADSTART = 1 and ADDIS = 0).

Note: There is no hardware protection preventing software from making write operations forbidden by the above rules. If such a forbidden write access occurs, the ADC may enter an undefined state. To recover correct operation in this case, the ADC must be disabled (clear ADEN = 0 and all the bits in the ADC_CR register).

13.3.8 Channel selection (CHSEL, SCANDIR)

There are up to 17 multiplexed channels:

• 16 analog inputs from GPIO pins (ADC_INx)
• 1 internal analog inputs (Internal Reference Voltage)

It is possible to convert a single channel or a sequence of channels.

The sequence of the channels to be converted can be programmed in the ADC_CHSELR channel selection register: each analog input channel has a dedicated selection bit (CHSELx).

The order in which the channels is scanned can be configured by programming the bit SCANDIR bit in the ADC_CFGR1 register:

• SCANDIR = 0: forward scan Channel 0 to Channel 17
• SCANDIR = 1: backward scan Channel 17 to Channel 0

V _REFINTinternal channel

The internal voltage reference V _REFINTis connected to channel ADC V _IN[17].

13.3.9 Programmable sampling time (SMP)

Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level.

Having a programmable sampling time allows the conversion speed to be trimmed according to the input resistance of the input voltage source.

Refer to the device datasheet to select the correct sampling time depending on the type of channel you are using (fast or standard).

The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR register.

This programmable sampling time is common to all channels. If required by the application, the software can change and adapt this sampling time between each conversions.

The total conversion time is calculated as follows:

t_{\text{CONV}} = \text{Sampling time} + 12.5 \times \text{ADC clock cycles}

Example:

With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles:

t_{\text{CONV}} = 1.5 + 12.5 = 14 \text{ ADC clock cycles} = 0.875 \mu\text{s}

The ADC indicates the end of the sampling phase by setting the EOSMP flag.

13.3.10 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again.

Note: To convert a single channel, program a sequence with a length of 1.

13.3.11 Continuous conversion mode (CONT = 1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

Note: To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

13.3.12 Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART = 1.

When ADSTART is set, the conversion:

• Starts immediately if EXTEN = 00 (software trigger)
• At the next active edge of the selected hardware trigger if EXTEN ≠ 00

The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.

The ADSTART bit is cleared by hardware:

• In single mode with software trigger (CONT = 0, EXTEN = 00)
- – At any end of conversion sequence (EOS = 1)
• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
- – At end of conversion (EOC = 1)
• In all cases (CONT = x, EXTEN = XX)
- – After execution of the ADSTP procedure invoked by software (see Section 13.3.14: Stopping an ongoing conversion (ADSTP) on page 266 )

Note: In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the EOS flag is set because the sequence is automatically relaunched.

When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed.

13.3.13 Timings

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution:

t_{CONV} = t_{SMPL} + t_{SAR} = [ 1.5 \text{ } |_{min} + 12.5 \text{ } |_{12bit} ] \times t_{ADC\_CLK}

t_{CONV} = t_{SMPL} + t_{SAR} = 93.8 \text{ ns } |_{min} + 781.3 \text{ ns } |_{12bit} = 0.875 \text{ } \mu\text{s } |_{min} \text{ (for } f_{ADC\_CLK} = 16 \text{ MHz)}

Figure 34. Analog to digital conversion time

The diagram shows the timing of an ADC conversion. The 'ADC state' line transitions from 'RDY' to 'SAMPLING CH(N)', then to 'CONVERTING CH(N)', and finally to 'SAMPLING CH(N+1)'. The 'Analog channel' line shows 'CH(N)' being sampled and 'CH(N+1)' being prepared. The 'Internal S/H' line shows 'Sample AIN(N+1)' and 'Hold AIN(N)' phases. The 'ADSTART' signal is set by software. The 'EOSMP' signal is set by hardware and cleared by software. The 'EOC' signal is set by hardware and cleared by software. The 'ADC_DR' line shows 'DATA N-1' and 'DATA N' being output. Notes: (1) $t_{SMPL}$ depends on SMP[2:0]; (2) $t_{SAR}$ depends on RES[2:0]. MS30336V1

Timing diagram for Figure 34 showing ADC state, Analog channel, Internal S/H, ADSTART, EOSMP, EOC, and ADC_DR signals over time. It illustrates the sampling and converting phases for channels CH(N) and CH(N+1).

Figure 35. ADC conversion timings

The diagram shows the timing of ADC conversions. The 'ADSTART' signal is shown with a trigger latency $t_{LATENCY}$ . The 'ADC state' line shows a sequence of 'Ready', 'S0', 'Conversion 0', 'S1', 'Conversion 1', 'S2', 'Conversion 2', 'S3', and 'Conversion 3'. The 'ADC_DR' line shows 'Data 0', 'Data 1', and 'Data 2' being output with a write latency $W_{LATENCY}$ . Notes: 1. EXTEN = 00 or EXTEN ≠ 00; 2. Trigger latency (refer to datasheet for more details); 3. ADC_DR register write latency (refer to datasheet for more details). MSV33174V1

Timing diagram for Figure 35 showing ADSTART, ADC state, and ADC_DR signals. It illustrates the latency from ADSTART to the start of conversion and the write latency for the ADC_DR register.

1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)

13.3.14 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register.

This resets the ADC operation and the ADC is idle, ready for a new operation.

When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).

The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).

Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 36. Stopping an ongoing conversion

The diagram illustrates the sequence of events for stopping an ongoing conversion. The ADC state starts at RDY, transitions to SAMPLING CH(N) when ADSTART is set by software, then to CONVERTING CH(N). When ADSTOP is set by software, the conversion is aborted, and the state returns to RDY. Both ADSTART and ADSTOP are cleared by hardware upon returning to the RDY state. The ADC_DR register contains DATA N-1 during the conversion.

Timing diagram showing ADC state transitions from RDY to SAMPLING CH(N) to CONVERTING CH(N) and back to RDY. It shows the setting of ADSTART by software and its clearing by hardware, and the setting of ADSTOP by software and its clearing by hardware. The ADC_DR register is shown with DATA N-1.

13.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)

A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to “0b00”, then external events are able to trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit ADSTART = 1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

If bit ADSTART = 0, any hardware triggers which occur are ignored.

Table 56 provides the correspondence between the EXTEN[1:0] values and the trigger polarity.

Table 56. Configuring the trigger polarity

Source	EXTEN[1:0]
Trigger detection disabled	00
Detection on rising edge	01
Detection on falling edge	10
Detection on both rising and falling edges	11

Note: The polarity of the external trigger can be changed only when the ADC is not converting (ADSTART = 0).

The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger conversions.

Refer to Table 54: External triggers in Section 13.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion.

The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.

Note: The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

13.4.1 Discontinuous mode (DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.

In this mode (DISCEN = 1), a hardware or software trigger event is required to start each conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or software trigger event successively starts all the conversions defined in the sequence.

Example:

• DISCEN = 1, channels to be converted = 0, 3, 7, 10
- – 1st trigger: channel 0 is converted and an EOC event is generated
- – 2nd trigger: channel 3 is converted and an EOC event is generated
- – 3rd trigger: channel 7 is converted and an EOC event is generated
- – 4th trigger: channel 10 is converted and both EOC and EOS events are generated.
- – 5th trigger: channel 0 is converted an EOC event is generated
- – 6th trigger: channel 3 is converted and an EOC event is generated
- – ...
• DISCEN = 0, channels to be converted = 0, 3, 7, 10
- – 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each conversion generates an EOC event and the last one also generates an EOS event.
- – Any subsequent trigger events restarts the complete sequence.

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

13.4.2 Programmable resolution (RES) - Fast conversion mode

It is possible to obtain faster conversion times ( $t_{SAR}$ ) by reducing the ADC resolution.

The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times for applications where high data precision is not required.

Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.

The result of the conversion is always 12 bits wide and any unused LSB bits are read as zeros.

Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table 57 .

Table 57.

t_{SAR}

timings depending on resolution

RES[1:0] bits	$t_{SAR}$ (ADC clock cycles)	$t_{SAR}$ (ns) at $f_{ADC} = 16$ MHz	$t_{SMPL}$ (min) (ADC clock cycles)	$t_{CONV}$ (ADC clock cycles) (with min. $t_{SMPL}$ )	$t_{CONV}$ (ns) at $f_{ADC} = 16$ MHz
12	12.5	781 ns	1.5	14	875 ns
10	11.5	719 ns	1.5	13	812 ns
8	9.5	594 ns	1.5	11	688 ns
6	7.5	469 ns	1.5	9	562 ns

13.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

The ADC indicates each end of conversion (EOC) event.

The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.

The ADC also indicates the end of sampling phase by setting the EOSMP flag in the ADC_ISR register. The EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if the EOSMPIE bit is set in the ADC_IER register.

The aim of this interrupt is to allow the processing to be synchronized with the conversions. Typically, an analog multiplexer can be accessed in hidden time during the conversion phase, so that the multiplexer is positioned when the next sampling starts.

Note: As there is only a very short time left between the end of the sampling and the end of the conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt and a WFI instruction.

13.4.4 End of conversion sequence (EOS flag)

The ADC notifies the application of each end of sequence (EOS) event.

The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a conversion sequence is available in the ADC_DR register. An interrupt can be generated if the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing 1 to it.

13.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)

Figure 37. Single conversions of a sequence, software trigger

MSV30338V3

Timing diagram for single conversions of a sequence with software trigger. The diagram shows five signal lines over time: ADSTART(1), EOC, EOS, SCANDIR, and ADC state(2). ADSTART is a software trigger (S/W) that goes high to start a sequence and low to stop it. EOC (End of Conversion) pulses for each conversion. EOS (End of Sequence) goes high when the last conversion (CH17) is complete. SCANDIR indicates the current channel being converted. ADC state shows the sequence of channels: RDY, CH0, CH9, CH10, CH17, RDY, CH17, CH10, CH9, CH0, RDY. ADC_DR shows the corresponding digital values: D0, D9, D10, D17, D17, D10, D9, D0. A legend indicates 'by S/W' with a rising edge symbol and 'by H/W' with a falling edge symbol.

1. EXTEN = 00, CONT = 0
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

For code example, refer to A.8.5: Single conversion sequence code example - Software trigger .

Figure 38. Continuous conversion of a sequence, software trigger

MSV30339V2

Timing diagram for continuous conversion of a sequence with software trigger. The diagram shows six signal lines: ADSTART(1), EOC, EOS, ADSTP, SCANDIR, and ADC state(2). ADSTART is a software trigger. EOC pulses for each conversion. EOS goes high when the last conversion (CH17) is complete. ADSTP (ADC Stop) goes high to stop continuous mode. SCANDIR indicates the current channel. ADC state shows the sequence: RDY, CH0, CH9, CH10, CH17, CH0, CH9, CH10, STP, RDY, CH17, CH10. ADC_DR shows digital values: D0, D9, D10, D17, D0, D9, D17. A legend indicates 'by S/W' with a rising edge symbol and 'by H/W' with a falling edge symbol.

1. EXTEN = 00, CONT = 1,
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

For code example, refer to A.8.6: Continuous conversion sequence code example - Software trigger .

Figure 39. Single conversions of a sequence, hardware trigger

The diagram illustrates the timing for single conversions. ADSTART ⁽¹⁾is a software-started signal (upward arrow). TRGx ⁽¹⁾is a hardware trigger (rising edge, blue line). The ADC state transitions from RDY to a sequence of CH0, CH1, CH2, CH3, then back to RDY, repeating once more. EOC signals are generated after each conversion. ADC_DR registers are updated with data D0, D1, D2, D3 corresponding to the channels. A legend defines the signal types: by S/W (upward arrow), by H/W (upward arrow with triangle), triggered (blue line), and ignored (line with X).

Timing diagram for single conversions of a sequence with hardware trigger. It shows signal transitions for ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR over time. A legend indicates signal types: by S/W, by H/W, triggered, and ignored.

MSv30340V2

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

Figure 40. Continuous conversions of a sequence, hardware trigger

The diagram illustrates the timing for continuous conversions. ADSTART ⁽¹⁾is a software-started signal (upward arrow). TRGx ⁽¹⁾is a hardware trigger (falling edge, blue line). The ADC state transitions from RDY to a sequence of CH0, CH1, CH2, CH3, CH0, CH1, CH2, CH3, CH0, then STOP, and back to RDY. EOC signals are generated after each conversion. ADC_DR registers are updated with data D0, D1, D2, D3. ADSTP is a software-stop signal (downward arrow). A legend defines the signal types: by S/W (upward arrow), by H/W (upward arrow with triangle), triggered (blue line), and ignored (line with X).

Timing diagram for continuous conversions of a sequence with hardware trigger. It shows signal transitions for ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR over time. A legend indicates signal types: by S/W, by H/W, triggered, and ignored.

MSv30341V2

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

13.5 Data management

13.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide.

The format of the ADC_DR depends on the configured data alignment and resolution.

The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in Figure 41.

Figure 41. Data alignment and resolution (oversampling disabled: OVSE = 0)

ALIGN	RES	15	5	2	0
0	0x0	0x0	DR[11:0]
	0x1	0x00	DR[9:0]
	0x2	0x00	DR[7:0]
	0x3	0x00	DR[5:0]
1	0x0	DR[11:0]		0x0
	0x1	DR[9:0]		0x00
	0x2	DR[7:0]		0x00
	0x3	0x00	DR[5:0]		0x0

MS30342V1

13.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the CPU or the DMA, before the data from a new conversion is available.

The OVR flag is set in the ADC_ISR register if the EOC flag is still at '1' at the time when a new conversion completes. An interrupt can be generated if the OVRIE bit is set in the ADC_IER register.

When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register.

The OVR flag is cleared by software by writing 1 to it.

It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register:

• OVRMOD = 0
- – An overrun event preserves the data register from being overwritten: the old data is maintained and the new conversion is discarded. If OVR remains at 1, further conversions can be performed but the resulting data is discarded.
• OVRMOD = 1
- – The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, further conversions can be performed and the ADC_DR register always contains the data from the latest conversion.

Figure 42. Example of overrun (OVR)

Timing diagram showing ADC signals: ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR values for OVRMOD=0 and OVRMOD=1. It illustrates an overrun condition where a new conversion starts before the previous one is read.

The diagram illustrates the timing of an ADC overrun event. The signals shown are:

ADSTART ⁽¹⁾: Software-initiated start of conversion. It goes high at the beginning and low at the end of the sequence.
EOC : End of Conversion flag. It pulses high when each conversion in the sequence is complete.
EOS : End of Sequence flag. It goes high when the last conversion in the sequence (CH2) is complete.
OVR : Overrun flag. It goes high when a new conversion starts before the previous data in the ADC_DR register has been read.
ADSTP : Stop conversion. It goes high to stop the current sequence.
TRGx ⁽¹⁾: Hardware trigger. It goes high to start the conversion sequence.
ADC state ⁽²⁾: Shows the sequence of states: RDY, CH0, CH1, CH2, CH0, CH1, CH2, CH0, STOP, RDY. An overrun occurs when a new conversion (CH0) starts while the previous data (CH2) is still unread.
ADC_DR read access : Shows software reading the data register. An 'OVERRUN' label indicates the period where the data is stale because a new conversion has occurred.
ADC_DR (OVRMOD=0) : Data register values when overrun mode is disabled. The values are D0, D1, D2, D0. The second D0 is incorrect because it was overwritten by the third conversion (CH2) before being read.
ADC_DR (OVRMOD=1) : Data register values when overrun mode is enabled. The values are D0, D1, D2, D0, D1, D2. In this mode, the ADC continues to convert, and the register always holds the latest result.

Legend for signal transitions:

by S/W (Software): solid line with upward arrow
by H/W (Hardware): dashed line with upward arrow
triggered: dashed line with downward arrow

MSV30343V3

Timing diagram showing ADC signals: ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR values for OVRMOD=0 and OVRMOD=1. It illustrates an overrun condition where a new conversion starts before the previous one is read.

13.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register should be configured to 0 to manage overrun events as an error.

13.5.4 Managing converted data without using the DMA without overrun

It may be useful to let the ADC convert one or more channels without reading the data after each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent the ADC from continuing to convert and the ADC_DR register always contains the latest conversion data.

13.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use DMA when converting more than one channel. This avoids losing the conversion data results stored in the ADC_DR register.

When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request is generated after the conversion of each channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.

Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section 13.5.2: ADC overrun (OVR, OVRMOD) on page 271 ).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG in the ADC_CFGR1 register:

• DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed number of data words.
• DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when a DMA_EOT interrupt occurs, see Section 10: Direct memory access controller (DMA) on page 216 ) even if a conversion has been started again.

For code example, refer to A.8.9: DMA one shot mode sequence code example .

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted and its partial result discarded
• No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available in the data register, even if the DMA has reached the last DMA transfer. This allows the DMA to be configured in circular mode to handle a continuous analog input data stream.

For code example, refer to A.8.10: DMA circular mode sequence code example .

13.6 Low-power features

13.6.1 Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the performance of applications clocked at low frequency where there might be a risk of ADC overrun occurring.

When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared.

This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.

Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the read access are ignored.

Figure 43. Wait mode conversion (continuous mode, software trigger)

Timing diagram for Figure 43 showing ADSTART, EOC, EOS, ADSTP, ADC_DR Read access, ADC state, and ADC_DR signals over time. The diagram illustrates the sequence of events in continuous mode with a software trigger. ADSTART is a rising edge (S/W) that starts the conversion. EOC pulses high for each conversion (CH1, CH2, CH3) and returns low after CH3. EOS goes high after the third conversion. ADSTP goes high after EOS. ADC_DR Read access pulses occur when data (D1, D2, D3) is ready. The ADC state sequence is RDY -> CH1 -> DLY -> CH2 -> DLY -> CH3 -> DLY -> CH1 -> DLY -> STOP -> RDY. A legend indicates 'by S/W' for rising edges and 'by H/W' for falling edges.

1. EXTEN = 00, CONT = 1
2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0

For code example, refer to A.8.11: Wait mode sequence code example .

13.6.2 Auto-off mode (AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.

When AUTOFF = 1, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger). A startup-time is automatically inserted between the trigger event which starts the conversion and the sampling time of the ADC. The ADC is then automatically disabled once the sequence of conversions is complete.

Auto-off mode can cause a dramatic reduction in the power consumption of applications which need relatively few conversions or when conversion requests are timed far enough apart (for example with a low frequency hardware trigger) to justify the extra power and extra time used for switching the ADC on and off.

Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications clocked at low frequency. This combination can provide significant power savings if the ADC is automatically powered-off during the wait phase and restarted as soon as the ADC_DR register is read by the application (see Figure 45: Behavior with WAIT = 1, AUTOFF = 1 ).

Note: Refer to the Section Reset and clock control (RCC) for the description of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch ON/OFF the 14 MHz internal oscillator to save power.

Figure 44. Behavior with WAIT = 0, AUTOFF = 1

Timing diagram showing the behavior of the ADC in auto-off mode (AUTOFF = 1) with no wait mode (WAIT = 0). The diagram illustrates the sequence of events from trigger to data read, including the ADC state transitions between Ready, Startup, Conversion, and Off.

The timing diagram shows the following signals and states over time:

TRGx: Trigger signal. It shows two rising edges. The first rising edge is labeled 'by S/W triggered' and the second 'by H/W triggered'.
EOC (End of Conversion): A signal that pulses high when each conversion is complete. It has four pulses corresponding to conversions CH1, CH2, CH3, and CH4.
EOS (End of Sequence): A signal that goes high after the last conversion (CH4) is complete.
ADC_DR Read access: A signal showing the application reading the data register. It has four pulses, each following an EOC pulse.
ADC state: Shows the state of the ADC. It starts in 'RDY' (Ready), goes to 'Startup' upon the first trigger, then cycles through 'CH1', 'CH2', 'CH3', and 'CH4' (Conversion). After the last conversion, it goes to 'OFF' (Off). Upon the second trigger, it returns to 'Startup'.
ADC_DR: The data register content. It shows four data values: D1, D2, D3, and D4, each appearing after its corresponding conversion is complete.

A legend at the bottom left indicates:

by S/W triggered: Software trigger (rising edge).
by H/W triggered: Hardware trigger (rising edge).

MSv30345V2

Timing diagram showing the behavior of the ADC in auto-off mode (AUTOFF = 1) with no wait mode (WAIT = 0). The diagram illustrates the sequence of events from trigger to data read, including the ADC state transitions between Ready, Startup, Conversion, and Off.

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 1

For code example, refer to A.8.12: Auto off and no wait mode sequence code example .

Figure 45. Behavior with WAIT = 1, AUTOFF = 1

Timing diagram showing the behavior of an ADC with WAIT=1 and AUTOFF=1. It displays signals for TRGx (trigger), EOC (end of conversion), EOS (end of sequence), ADC_DR Read access, ADC state (RDY, Startup, CH1, OFF, CH2, CH3), and ADC_DR (data registers D1, D2, D3, D4). The diagram shows a sequence of conversions triggered by TRGx rising edges, with delays (DLY) between them. A legend indicates that solid arrows represent software (S/W) triggers and dashed arrows represent hardware (H/W) triggers.

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1

For code example, refer to A.8.13: Auto off and wait mode sequence code example .

13.7 Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR)

13.7.1 Description of the analog watchdog

The AWD analog watchdog is enabled by setting the AWDEN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 59: Analog watchdog channel selection ) remain within a configured voltage range (window) as shown in Figure 46 .

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in HT[11:0] and LT[11:0] bit of ADC_TR register. An interrupt can be enabled by setting the AWDIE bit in the ADC_IER register.

The AWD flag is cleared by software by programming it to it.

When converting data with a resolution of less than 12-bit (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

For code example, refer to A.8.14: Analog watchdog code example .

Table 58 describes how the comparison is performed for all the possible resolutions.

Table 58. Analog watchdog comparison

Resolution bits RES[1:0]	Analog Watchdog comparison between:		Comments
Resolution bits RES[1:0]	Raw converted data, left aligned ⁽¹⁾	Thresholds	Comments
00: 12-bit	DATA[11:0]	LT[11:0] and HT[11:0]	-
01: 10-bit	DATA[11:2],00	LT[11:0] and HT[11:0]	The user must configure LT1[1:0] and HT1[1:0] to "00"
10: 8-bit	DATA[11:4],0000	LT[11:0] and HT[11:0]	The user must configure LT1[3:0] and HT1[3:0] to "0000"
11: 6-bit	DATA[11:6],000000	LT[11:0] and HT[11:0]	The user must configure LT1[5:0] and HT1[5:0] to "000000"

1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 59 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1 register to enable the analog watchdog on one or more channels.

Figure 46. Analog watchdog guarded area

Figure 46: Analog watchdog guarded area diagram. A vertical axis represents 'Analog voltage'. Two horizontal lines mark the 'Higher threshold' (HTx) and 'Lower threshold' (LTx). The region between these two thresholds is shaded and labeled 'Guarded area'. The diagram is labeled MS45396V1 in the bottom right corner.

Table 59. Analog watchdog channel selection

Channels guarded by the analog watchdog	AWDSGL bit	AWDEN bit
None	x	0
All channels	0	1
Single ⁽¹⁾channel	1	1

1. Selected by the AWDCH[4:0] bits

13.7.2 ADC_AWD1_OUT output signal generation

The analog watchdog is associated to an internal hardware signal, ADC_AWD1_OUT that is directly connected to the ETR input (external trigger) of some on-chip timers (refer to the timers section for details on how to select the ADC_AWD1_OUT signal as ETR).

ADC_AWD1_OUT is activated when the analog watchdog is enabled:

• ADC_AWD1_OUT is set when a guarded conversion is outside the programmed thresholds.
• ADC_AWD1_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds. It remains at 1 if the next guarded conversions are still outside the programmed thresholds.
• ADC_AWD1_OUT is also reset when disabling the ADC (when setting ADDIS to 1). Note that stopping conversions (ADSTP set), might clear the ADC_AWD1_OUT state.
• ADC_AWD1_OUT state does not change when the ADC converts the none-guarded channel (see Figure 47 )

AWD flag is set by hardware and reset by software: AWD flag has no influence on the generation of ADC_AWD1_OUT (as an example, ADC_AWD1_OUT can toggle while AWD flag remains at 1 if the software has not cleared the flag).

The ADC_AWD1_OUT signal is generated by the ADC_CLK domain. This signal can be generated even the APB clock is stopped.

The AWD comparison is performed at the end of each ADC conversion. The ADC_AWD1_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison.

As ADC_AWD1_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized.

Figure 47. ADC_AWD1_OUT signal generation

Timing diagram showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over a series of conversions (Conversion1 to Conversion7).

The diagram illustrates the timing relationship between the ADC state, End of Conversion (EOC) flag, Analog Watchdog (AWD) flag, and the ADC_AWD1_OUT signal across seven conversions. The ADC state starts in 'RDY' and then cycles through 'Conversion1' to 'Conversion7'. Each conversion is labeled as either 'inside' or 'outside' the programmed thresholds. The EOC flag pulses high at the end of each conversion. The AWD flag is set (goes high) when a conversion is 'outside' the thresholds and is cleared by software (labeled 'Cleared by SW') when the next conversion is 'inside' the thresholds. The ADC_AWD1_OUT signal is shown toggling based on these conditions. A legend at the bottom indicates that converted channels are 1,2,3,4,5,6,7 and guarded converted channels are 1,2,3,4,5,6,7.

ADC STATE	RDY	Conversion1 inside	Conversion2 outside	Conversion3 inside	Conversion4 outside	Conversion5 outside	Conversion6 outside	Conversion7 inside
EOC FLAG	Low	Pulse	Pulse	Pulse	Pulse	Pulse	Pulse	Pulse
AWD FLAG	Low	Low	High	Low (Cleared by SW)	High	Low (Cleared by SW)	High	Low (Cleared by SW)
ADC_AWD1_OUT	Low	Low	High	Low	High	High	High	Low

- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

MSV65326V1

Timing diagram showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over a series of conversions (Conversion1 to Conversion7).

Figure 48. ADC_AWD1_OUT signal generation (AWD flag not cleared by software)

Timing diagram for Figure 48 showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over seven conversions. The AWD FLAG is set at the end of Conversion3 and remains high because it is not cleared by software. The ADC_AWD1_OUT signal goes high at the end of Conversion3 and stays high until the end of Conversion7.

EOC FLAG: Pulses at the end of each conversion.

AWD FLAG: Goes high at the end of Conversion3 and remains high (not cleared by SW).

ADC_AWD1_OUT: Goes high at the end of Conversion3 and stays high until the end of Conversion7.

- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

MSV65327V1

Timing diagram for Figure 48 showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over seven conversions. The AWD FLAG is set at the end of Conversion3 and remains high because it is not cleared by software. The ADC_AWD1_OUT signal goes high at the end of Conversion3 and stays high until the end of Conversion7.

Figure 49. ADC1_AWD_OUT signal generation (on a single channel)

Timing diagram for Figure 49 showing ADC STATE, EOC FLAG, EOS FLAG, AWD FLAG, and ADCy_AWD1_OUT signals over four conversion pairs. Only channel 1 is guarded. The AWD FLAG is cleared by software. The ADCy_AWD1_OUT signal goes high when Conversion1 is 'inside' and low when it is 'outside'.

EOC FLAG: Pulses at the end of each conversion.

EOS FLAG: Pulses at the end of each pair of conversions. It is labeled 'Cleared by SW'.

AWD FLAG: Pulses when Conversion1 is 'inside' and is cleared by software. It is labeled 'Cleared by SW'.

ADCy_AWD1_OUT: Goes high when Conversion1 is 'inside' and low when it is 'outside'.

- Converted channels: 1 and 2
- Only channel 1 is guarded

MSV65328V1

Timing diagram for Figure 49 showing ADC STATE, EOC FLAG, EOS FLAG, AWD FLAG, and ADCy_AWD1_OUT signals over four conversion pairs. Only channel 1 is guarded. The AWD FLAG is cleared by software. The ADCy_AWD1_OUT signal goes high when Conversion1 is 'inside' and low when it is 'outside'.

13.7.3 Analog watchdog threshold control

LT[11:0] and HT[11:0] can be changed during an analog-to-digital conversion (that is between the start of the conversion and the end of conversion of the ADC internal state). If LT and HT bits are programmed during the ADC guarded channel conversion, the watchdog function is masked for this conversion. This mask is cleared when starting a new conversion, and the resulting new AWD threshold is applied starting the next ADC conversion result. AWD comparison is performed at each end of conversion. If the current ADC data are out of the new threshold interval, this does not generate any interrupt or an ADC_AWD1_OUT signal. The Interrupt and the ADC_AWD1_OUT generation only occurs at the end of the ADC conversion that started after the threshold update. If ADC_AWD1_OUT is already asserted, programming the new threshold does not deactivate the ADC_AWD1_OUT signal.

Figure 50. Analog watchdog threshold update

Timing diagram showing ADC state, LT/HT threshold levels, and Comparison status over time. The diagram shows four 'Conversion' blocks in the ADC state. Below, the LT, HT threshold levels are shown as XXXX, XXXY, and XXXZ. An arrow labeled 'Threshold updated' points to the transition between XXXX and XXXY. The Comparison status is shown as Active, Masked, and Active. The diagram is labeled MSV65329V1.

13.8 Oversampler

The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit.

It provides a result with the following form, where N and M can be adjusted:

\text{Result} = \frac{1}{M} \times \sum_{n=0}^{n=N-1} \text{Conversion}(t_n)

It allows the following functions to be performed by hardware: averaging, data rate reduction, SNR improvement, basic filtering.

The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits. It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.

For code example, refer to A.8.15: Oversampling code example .

The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register.

Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated.

Figure 51. 20-bit to 16-bit result truncation

Diagram illustrating 20-bit to 16-bit result truncation. It shows three rows: 'Raw 20-bit data' with bits 19-0, 'Shifting' with a right arrow, and 'Truncation and rounding' resulting in a 16-bit value. Bit positions 19, 15, 11, 7, 3, and 0 are marked. The source identifier MS31928V2 is in the bottom right.

The Figure 52 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.

Figure 52. Numerical example with 5-bits shift and rounding

Numerical example of 20-bit to 16-bit conversion with a 5-bit shift and rounding. Raw data: 3 B 7 D 7 (bits 19-3). Final result: 1 D B F (bits 15-0). Source identifier MS31929V1 is in the bottom right.

The Table 60 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.

Table 60. Maximum output results vs N and M. Grayed values indicates truncation

Oversampling ratio	Max Raw data	No-shift OVSS = 0000	1-bit shift OVSS = 0001	2-bit shift OVSS = 0010	3-bit shift OVSS = 0011	4-bit shift OVSS = 0100	5-bit shift OVSS = 0101	6-bit shift OVSS = 0110	7-bit shift OVSS = 0111	8-bit shift OVSS = 1000
2x	0x1FFE	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040	0x0020
4x	0x3FFC	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080	0x0040
8x	0x7FF8	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100	0x0080
16x	0xFFF0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200	0x0100
32x	0x1FFE0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400	0x0200
64x	0x3FFC0	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800	0x0400
128x	0x7FF80	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF	0x0800
256x	0xFFF00	0xFF00	0xFF80	0xFFC0	0xFFE0	0xFFF0	0x7FF8	0x3FFC	0x1FFE	0x0FFF

The conversion timings in oversampled mode do not change compared to standard conversion mode: the sample time is maintained equal during the whole oversampling

sequence. New data are provided every N conversion, with an equivalent delay equal to $N \times t_{\text{CONV}} = N \times (t_{\text{SMP}} + t_{\text{SAR}})$ . The flags features are raised as following:

• the end of the sampling phase (EOSMP) is set after each sampling phase
• the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available
• the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is completed (i.e. after $N \times$ sequence length conversions total)

13.8.1 ADC operating modes supported when oversampling

In oversampling mode, most of the ADC operating modes are available:

• Single or continuous mode conversions, forward or backward scanned sequences
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (WAIT, AUTOFF)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are

Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in ADC_CFGR1 is ignored and the data are always provided right-aligned.

13.8.2 Analog watchdog

The analog watchdog functionality is available (AWDSGL, AWDEN bits), with the following differences:

• the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits values HT[11:0] and LT[11:0]
• the comparison is performed on the most significant 12 bits of the 16 bits oversampled results ADC_DR[15:4]

Note: Care must be taken when using high shifting values. This reduces the comparison range. For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data right-aligned, the affective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[7:0] / LT[7:0], and HT[11:8] / LT[11:8] must be kept reset.

13.8.3 Triggered mode

The averager can also be used for basic filtering purposes. Although not a very efficient filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself.

Figure 53 below shows how conversions are started in response to triggers in discontinuous mode.

If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

Figure 53. Triggered oversampling mode (TOVS bit = 1)

Figure 53: Triggered oversampling mode (TOVS bit = 1) diagram. The diagram compares two configurations. Top: CONT = 0, (DISCEN = 1)*, TOVS = 0. A single 'Trigger' arrow points to a block of four conversions: Ch(N) 0, 1, 2, 3. After the fourth conversion, an arrow points down to 'EOC flag set'. Bottom: CONT = 0, (DISCEN = 1)*, TOVS = 1. Here, each conversion (Ch(N) 0, 1, 2, 3, 0, 1, 2) has its own 'Trigger' arrow above it. After the seventh conversion, an arrow points down to 'EOC flag set'. A note at the bottom states: (DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set. Labeled MS33700V1.

13.9 Internal reference voltage

The internal voltage reference ( $V_{REFINT}$ ) provides a stable (bandgap) voltage output for the ADC. $V_{REFINT}$ is internally connected to the ADC $V_{IN}[17]$ input channel. The precise voltage of $V_{REFINT}$ is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Figure 54 shows the block diagram of connection between the internal voltage reference and the ADC.

VREFEN bit must be set to enable the conversion of ADC $V_{IN}[17]$ ( $V_{REFINT}$ ).

During the manufacturing process, the calibration data of the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the internal reference. Refer to the electrical characteristics section of the device datasheet for additional information.

Main features

• Linearity: $\pm 2$ °C max., precision depending on calibration

Figure 54.

V_{REFINT}

channel block diagram

Figure 54: V_REFINT channel block diagram. A block labeled 'Internal power block' feeds into a multiplexer. The multiplexer is controlled by 'VREFEN control bit'. The output of the multiplexer, labeled V_REFINT, goes into an 'ADC' block at the 'ADC V_IN[17]' input. The ADC block outputs 'converted data' to an 'Address/data bus'. Labeled MSV48804V2.

Calculating the actual $V_{DDA}$ voltage using the internal reference voltage

The $V_{DDA}$ power supply voltage applied to the device may be subject to variation or not precisely known. The embedded internal voltage reference ( $V_{REFINT}$ ) and its calibration data, acquired by the ADC during the manufacturing process at $V_{DDA\_Charac}$ , can be used to evaluate the actual $V_{DDA}$ voltage level.

The following formula gives the actual $V_{DDA}$ voltage supplying the device:

V_{DDA} = V_{DDA\_Charac} \times VREFINT\_CAL / VREFINT\_DATA

Where:

• $V_{DDA\_Charac}$ is the value of $V_{DDA}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.
• $VREFINT\_CAL$ is the $$ VREFINT $$ calibration value
• $VREFINT\_DATA$ is the actual $$ VREFINT $$ output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of $V_{DDA}$ . For applications where $V_{DDA}$ is known and ADC converted values are right-aligned you can use the following formula to get this absolute value:

V_{CHANNELx} = \frac{V_{DDA}}{FULL\_SCALE} \times ADC\_DATA_x

For applications where $V_{DDA}$ value is not known, you must use the internal voltage reference and $V_{DDA}$ can be replaced by the expression provided in Section : Calculating the actual $V_{DDA}$ voltage using the internal reference voltage , resulting in the following formula:

V_{CHANNELx} = \frac{V_{DDA\_Charac} \times VREFINT\_CAL \times ADC\_DATA_x}{VREFINT\_DATA \times FULL\_SCALE}

Where:

• $V_{DDA\_Charac}$ is the value of $V_{DDA}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.
• $VREFINT\_CAL$ is the $$ VREFINT $$ calibration value
• $ADC\_DATA_x$ is the value measured by the ADC on channelx (right-aligned)
• $VREFINT\_DATA$ is the actual $$ VREFINT $$ output value converted by the ADC
• $full\_SCALE$ is the maximum digital value of the ADC output. For example with 12-bit resolution, it is $2^{12} - 1 = 4095$ or with 8-bit resolution, $$ 2^8 - 1 = 255 $$ .

Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

13.10 ADC interrupts

An interrupt can be generated by any of the following events:

• End Of Calibration (EOCAL flag)
• ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
• End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD flag)
• When the end of sampling phase occurs (EOSMP flag)
• when a data overrun occurs (OVR flag)

Separate interrupt enable bits are available for flexibility.

Table 61. ADC interrupts

Interrupt event	Event flag	Enable control bit
End Of Calibration	EOCAL	EOCALIE
ADC ready	ADRDY	ADRDYIE
End of conversion	EOC	EOCIE
End of sequence of conversions	EOS	EOSIE
Analog watchdog status bit is set	AWD	AWDIE
End of sampling phase	EOSMP	EOSMPIE
Overrun	OVR	OVRIE

13.11 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

13.11.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	EOCAL	Res.	Res.	Res.	AWD	Res.	Res.	OVR	EOS	EOC	EOSMP	ADRDY
				rc_w1				rc_w1			rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCAL : End Of Calibration flag

This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.

0: Calibration is not complete

1: Calibration is complete

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 AWD : Analog watchdog flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR register. It is cleared by software by programming it to 1.

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog event occurred

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVR : ADC overrun

This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS : End of sequence flag

This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.

0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Conversion sequence complete

Bit 2 EOC : End of conversion flag

This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)

1: Channel conversion complete

Bit 1 EOSMP : End of sampling flag

This bit is set by hardware during the conversion, at the end of the sampling phase. It is cleared by software by programming it to '1'.

0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)

1: End of sampling phase reached

Bit 0 ADRDY : ADC ready

This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)

1: ADC is ready to start conversion

13.11.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	EOCALIE	Res.	Res.	Res.	AWDIE	Res.	Res.	OVRIE	EOSIE	EOCIE	EOSMP IE	ADRDY IE
				rw				rw			rw	rw	rw	rw	rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCALIE : End of calibration interrupt enable

This bit is set and cleared by software to enable/disable the end of calibration interrupt.

0: End of calibration interrupt disabled

1: End of calibration interrupt enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 AWDIE: Analog watchdog interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled

1: Analog watchdog interrupt enabled

Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the overrun interrupt.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 3 EOSIE: End of conversion sequence interrupt enable

This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 2 EOCIE: End of conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of conversion interrupt.

0: EOC interrupt disabled

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 1 EOSMPIE: End of sampling flag interrupt enable

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 0 ADRDYIE: ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled.

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

13.11.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL	Res.	Res.	ADVREGEN	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rs			rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ADSTP	Res.	ADSTART	ADDIS	ADEN
											rs		rs	rs	rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC.

It is cleared by hardware after calibration is complete.

0: Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.

Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).

Bits 30:29 Reserved, must be kept at reset value.

Bit 28 ADVREGEN: ADC Voltage Regulator Enable

This bit can be set:

– by software, to enable the ADC internal voltage regulator.
– by hardware, when launching the calibration (setting ADCAL = 1) or when enabling the ADC (setting ADEN = 1)

It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is cleared.

0: ADC voltage regulator disabled

1: ADC voltage regulator enabled

Note: The software can program this bit field only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 27:5 Reserved, must be kept at reset value.

Bit 4 ADSTP: ADC stop conversion command

This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command.

0: No ADC stop conversion command ongoing

1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.

Note: Setting ADSTP to '1' is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)

Bit 3 Reserved, must be kept at reset value.

Bit 2 ADSTART: ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode (CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware.

0: No ADC conversion is ongoing.

1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.

Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC).

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: No ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: Setting ADDIS to '1' is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)

Bit 0 ADEN: ADC enable command

This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

13.11.4 ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C

Reset value: 0x0000 0000

The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	AWDCH[4:0]					Res.	Res.	AWDEN	AWDSGL	Res.	Res.	Res.	Res.	Res.	DISCEN
	rw	rw	rw	rw	rw			rw	rw						rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AUTOFF	WAIT	CONT	OVRMOD	EXTEN[1:0]		Res.	EXTSEL[2:0]			ALIGN	RES[1:0]		SCANDIR	DMACFG	DMAEN
rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWDCH[4:0] : Analog watchdog channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input Channel 0 monitored by AWD

00001: ADC analog input Channel 1 monitored by AWD

.....

10001: ADC analog input Channel 17 monitored by AWD

Others: Reserved

Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). The software is allowed to write this bit only when ADEN bit is cleared.

Bits 25:24 Reserved, must be kept at reset value.

Bit 23 AWDEN : Analog watchdog enable

This bit is set and cleared by software.

0: Analog watchdog disabled

1: Analog watchdog enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). The software is allowed to write this bit only when ADEN bit is cleared.

Bit 22 AWDSGL : Enable the watchdog on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels

0: Analog watchdog enabled on all channels

1: Analog watchdog enabled on a single channel

Bits 21:17 Reserved, must be kept at reset value.

Bit 16 DISCEN : Discontinuous mode

This bit is set and cleared by software to enable/disable discontinuous mode.

0: Discontinuous mode disabled

1: Discontinuous mode enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). The software is allowed to write this bit only when ADEN bit is cleared.

Bit 15 AUTOFF : Auto-off mode

This bit is set and cleared by software to enable/disable auto-off mode.

0: Auto-off mode disabled

1: Auto-off mode enabled

Bit 14 WAIT : Wait conversion mode

This bit is set and cleared by software to enable/disable wait conversion mode.

0: Wait conversion mode off

1: Wait conversion mode on

Bit 13 CONT : Single / continuous conversion mode

This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). The software is allowed to write this bit only when ADEN bit is cleared.

Bit 12 OVRMOD : Overrun management mode

This bit is set and cleared by software and configure the way data overruns are managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Bits 11:10 EXTEN[1:0] : External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable the trigger.

00: Hardware trigger detection disabled (conversions can be started by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Bit 9 Reserved, must be kept at reset value.

Bits 8:6 EXTSEL[2:0] : External trigger selection

These bits select the external event used to trigger the start of conversion (refer to Table 54: External triggers for details):

000: TRG0

001: TRG1

010: TRG2

011: TRG3

100: TRG4

101: TRG5

110: TRG6

111: TRG7

Bit 5 ALIGN : Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to Figure 41: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 271

0: Right alignment

1: Left alignment

Bits 4:3 RES[1:0] : Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12 bits

01: 10 bits

10: 8 bits

11: 6 bits

Note: The software is allowed to write these bits only when ADEN is cleared.

Bit 2 SCANDIR: Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence.

0: Upward scan (from CHSEL0 to CHSEL17)

1: Backward scan (from CHSEL17 to CHSEL0)

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1.

0: DMA one shot mode selected

1: DMA circular mode selected

For more details, refer to Section 13.5.5: Managing converted data using the DMA on page 272

Bit 0 DMAEN: Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section 13.5.5: Managing converted data using the DMA on page 272 .

0: DMA disabled

1: DMA enabled

13.11.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10

Reset value: 0x0000 0000

The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKMODE[1:0]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	TOVS	OVSS[3:0]			OVSR[2:0]			Res.	OVSE
						rw	rw	rw	rw	rw	rw	rw	rw		rw

Bits 31:30 CKMODE[1:0] : ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:

00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)

01: PCLK/2 (Synchronous clock mode)

10: PCLK/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 29:10 Reserved, must be kept at reset value.

Bit 9 TOVS : Triggered Oversampling

This bit is set and cleared by software.

0: All oversampled conversions for a channel are done consecutively after a trigger

1: Each oversampled conversion for a channel needs a trigger

Bits 8:5 OVSS[3:0] : Oversampling shift

This bit is set and cleared by software.

0000: No shift

0001: Shift 1-bit

0010: Shift 2-bits

0011: Shift 3-bits

0100: Shift 4-bits

0101: Shift 5-bits

0110: Shift 6-bits

0111: Shift 7-bits

1000: Shift 8-bits

Others: Reserved

Bits 4:2 OVSR[2:0] : Oversampling ratio

This bit field defines the number of oversampling ratio.

000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x

Bit 1 Reserved, must be kept at reset value.

Bit 0 OVSE : Oversampler Enable

This bit is set and cleared by software.

0: Oversampler disabled
1: Oversampler enabled

13.11.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SMP[2:0]
													rw	rw	rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 SMP[2:0] : Sampling time selection

These bits are written by software to select the sampling time that applies to all channels.

000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

13.11.7 ADC watchdog threshold register (ADC_TR)

Address offset: 0x20

Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT[11:0] : Analog watchdog higher threshold

These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 13.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on page 276

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT[11:0] : Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 13.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on page 276 .

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

13.11.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res	CHSEL 17	CHSEL 16
														rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 CHSELx : Channel-x selection

These bits are written by software and define which channels are part of the sequence of channels to be converted. Refer to Figure 33: ADC connectivity for ADC inputs connected to external channels and internal sources.

0: Input Channel-x is not selected for conversion

1: Input Channel-x is selected for conversion

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

13.11.9 ADC data register (ADC_DR)

Address offset: 0x40

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0] : Converted data

These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 41: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 271 .

Just after a calibration is complete, DATA[6:0] contains the calibration factor.

13.11.10 ADC Calibration factor (ADC_CALFACT)

Address offset: 0xB4

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CALFACT[6:0]
									rw	rw	rw	rw	rw	rw	rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT[6:0] : Calibration factor

These bits are written by hardware or by software.

– Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended conversion is launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.

Note: Software can write these bits only when ADEN=1 and ADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

13.11.11 ADC common configuration register (ADC_CCR)

Address offset: 0x308

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	LFMEN	Res.	Res.	VREF EN	PRESC[3:0]				Res.	Res.
						rw			rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LFMEN : Low Frequency Mode enable

This bit is set and cleared by software to enable/disable the Low Frequency Mode.

It is mandatory to enable this mode the user selects an ADC clock frequency lower than 3.5 MHz

0: Low Frequency Mode disabled

1: Low Frequency Mode enabled

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 24 Reserved, must be kept at reset value.

Bit 23 Reserved, must be kept at reset value.

Bit 22 VREFEN : V _REFINTenable

This bit is set and cleared by software to enable/disable the V _REFINT.

0: V _REFINTdisabled

1: V _REFINTenabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 21:18 PRESC[3:0] : ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADC.

0000: input ADC clock not divided

0001: input ADC clock divided by 2

0010: input ADC clock divided by 4

0011: input ADC clock divided by 6

0100: input ADC clock divided by 8

0101: input ADC clock divided by 10

0110: input ADC clock divided by 12

0111: input ADC clock divided by 16

1000: input ADC clock divided by 32

1001: input ADC clock divided by 64

1010: input ADC clock divided by 128

1011: input ADC clock divided by 256

Other: Reserved

Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 17:0 Reserved, must be kept at reset value.

13.12 ADC register map

The following table summarizes the ADC registers.

Table 62. ADC register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	ADC_ISR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	EOCAL	Res.	Res.	Res.	AWD	Res.	Res.	OVR	EOS	EOC	EOSMP	ADRDY
0x00	Reset value																					0				0			0	0	0	0	0
0x04	ADC_IER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	EOCALIE	Res.	Res.	Res.	AWDIE	Res.	Res.	OVRIE	EOSIE	EOCIE	EOSMPIE	ADRDYIE
0x04	Reset value																					0				0			0	0	0	0	0
0x08	ADC_CR	ADCAL	Res.	Res.	ADVREGEN	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ADSTP	Res.	ADSTART	ADDIS	ADEN
0x08	Reset value	0			0																								0		0	0	0
0x0C	ADC_CFGR1	Res.	AWDCH[4:0]					Res.	Res.	AWDEN	AWDSGL	Res.	Res.	Res.	Res.	Res.	DISCEN	AUTOFF	WAIT	CONT	OVRMOD	EXTEN[1:0]		Res.	EXTSEL [2:0]			ALIGN	RES [1:0]		SCANDIR	DMACFG	DMAEN
0x0C	Reset value		0	0	0	0	0			0	0						0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0

Table 62. ADC register map and reset values (continued)

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x10	ADC_CFGR2	CKMODE[1:0]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TOVS	OVSS[3:0]			OVSR[2:0]			Res.	OVSE
0x10	Reset value	0	0																					0	0	0	0	0	0	0	0	0	0
0x14	ADC_SMPR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SMP[2:0]
0x14	Reset value																															0	0	0
0x18	Reserved	Reserved
0x1C	Reserved	Reserved
0x20	ADC_TR	Res.	Res.	Res.	Res.	HT[11:0]																										LT[11:0]
0x20	Reset value					1	1	1	1	1	1	1	1	1	1	1	1					0	0	0	0	0	0	0	0	0	0	0	0
0x24	Reserved	Reserved
0x28	ADC_CHSELR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CHSEL17	CHSEL16	CHSEL15	CHSEL14	CHSEL13	CHSEL12	CHSEL11	CHSEL10	CHSEL9	CHSEL8	CHSEL7	CHSEL6	CHSEL5	CHSEL4	CHSEL3	CHSEL2	CHSEL1	CHSEL0
0x28	Reset value															0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C 0x30 0x34 0x38 0x3C	Reserved	Reserved
0x40	ADC_DR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DATA[15:0]
0x40	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
...	Reserved	Reserved
...	Reserved	Reserved
0xB4	ADC_CALFACT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CALFACT[6:0]
0xB4	Reset value																											0	0	0	0	0	0
...	Reserved	Reserved
0x308	ADC_CCR	Res.	Res.	Res.	Res.	Res.	Res.	LFMEN	Res.	Res.	VREFEN	PRES3	PRES2	PRES1	PRES0	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
0x308	Reset value							0			0	0	0	0	0

Refer to Section 2.2 on page 39 for the register boundary addresses.

13. Analog-to-digital converter (ADC)

13.1 Introduction

13.2 ADC main features

13.3 ADC functional description

13.3.1 ADC pins and internal signals

13.3.2 ADC voltage regulator (ADVREGEN)

Analog reference for the ADC internal voltage regulator

ADVREG enable sequence

ADVREG disable sequence

13.3.3 Calibration (ADCAL)

Software calibration procedure

13.3.5 ADC clock (CKMODE, PRESC[3:0], LFMEN)

Low frequency

13.3.6 ADC connectivity

13.3.7 Configuring the ADC

13.3.8 Channel selection (CHSEL, SCANDIR)

V REFINT internal channel

13.3.9 Programmable sampling time (SMP)

13.3.10 Single conversion mode (CONT = 0)

13.3.11 Continuous conversion mode (CONT = 1)

13.3.12 Starting conversions (ADSTART)

13.3.13 Timings

13.3.14 Stopping an ongoing conversion (ADSTP)

13.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)

13.4.1 Discontinuous mode (DISCEN)

13.4.2 Programmable resolution (RES) - Fast conversion mode

13.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

13.4.4 End of conversion sequence (EOS flag)

13.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)

13.5 Data management

13.5.1 Data register and data alignment (ADC_DR, ALIGN)

13.5.2 ADC overrun (OVR, OVRMOD)

13.5.3 Managing a sequence of data converted without using the DMA

13.5.4 Managing converted data without using the DMA without overrun

13.5.5 Managing converted data using the DMA

DMA one shot mode (DMACFG = 0)

DMA circular mode (DMACFG = 1)

13.6 Low-power features

13.6.1 Wait mode conversion

13.6.2 Auto-off mode (AUTOFF)

13.7 Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR)

13.7.1 Description of the analog watchdog

13.7.2 ADC_AWD1_OUT output signal generation

13.7.3 Analog watchdog threshold control

13.8 Oversampler

13.8.1 ADC operating modes supported when oversampling

13.8.2 Analog watchdog

13.8.3 Triggered mode

13.9 Internal reference voltage

Main features

Calculating the actual \( V_{DDA} \) voltage using the internal reference voltage

Converting a supply-relative ADC measurement to an absolute voltage value

13.10 ADC interrupts

13.11 ADC registers

13.11.1 ADC interrupt and status register (ADC_ISR)

13.11.2 ADC interrupt enable register (ADC_IER)

13.11.3 ADC control register (ADC_CR)

13.11.4 ADC configuration register 1 (ADC_CFGR1)

13.11.5 ADC configuration register 2 (ADC_CFGR2)

13.11.6 ADC sampling time register (ADC_SMPR)

13.11.7 ADC watchdog threshold register (ADC_TR)

13.11.8 ADC channel selection register (ADC_CHSELR)

13.11.9 ADC data register (ADC_DR)

13.11.10 ADC Calibration factor (ADC_CALFACT)

13.11.11 ADC common configuration register (ADC_CCR)

13.12 ADC register map

V _REFINTinternal channel

Calculating the actual $V_{DDA}$ voltage using the internal reference voltage