1. Documentation conventions

1.1 General information

The STM32L010xx devices have an Arm ®(a) Cortex ® -M0+ core.

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1.2 List of abbreviations for registers

The following abbreviations (b) are used in register descriptions:

read/write (rw)Software can read and write to this bit.
read-only (r)Software can only read this bit.
write-only (w)Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0)Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value.
read/clear write1 (rc_w1)Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value.
read/clear write (rc_w)Software can read as well as clear this bit by writing to the register. The value written to this bit is not important.
read/clear by read (rc_r)Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit has no effect on the bit value.
read/set by read (rs_r)Software can read this bit. Reading this bit automatically sets it to 1. Writing this bit has no effect on the bit value.
read/set (rs)Software can read as well as set this bit. Writing 0 has no effect on the bit value.
read/write once (rwo)Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value.
toggle (t)The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1)Software can read this bit. Writing 1 triggers an event but has no effect on the bit value.
Reserved (Res.)Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.

1.3 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular device datasheet.

1.5 Product category definition

Table 1 gives an overview of memory density versus product line.

The present reference manual describes the superset of features for each product category. Refer to Table 2 for the list of features per category.

Table 1. STM32L010 memory density

Memory densityCategory 1Category 2Category 3Category 5
8 KbytesSTM32L010x3---
16 KbytesSTM32L010x4---
32 Kbytes-STM32L010x6--
64 Kbytes--STM32L010x8-
128 Kbytes---STM32L010xB

Table 2. Overview of features per category

FeatureCategory 1Category 2Category 3Category 5
NVMfull-featured, single bankfull-featured, single bankfull-featured, single bankfull-featured, single bank
Cyclic redundancy check calculation unit (CRC)full-featuredfull-featuredfull-featuredfull-featured
Firewall (FW)--full-featuredfull-featured
Power control (PWR)full-featuredfull-featuredfull-featuredfull-featured
Reset and clock control (RCC)HSE supports bypass only, no CSS on HSEfull-featuredfull-featuredfull-featured
GPIOAfull-featuredfull-featuredfull-featuredfull-featured

Table 2. Overview of features per category (continued)

FeatureCategory 1Category 2Category 3Category 5
GPIOB[0:9], BOOT0/PB9 sharing the same pinfull-featuredfull-featuredfull-featured
GPIOC[14:15][0][13:15]full-featuredfull-featured
GPIOD--[2]full-featured
GPIOE---full-featured
GPIOH-[0:1][0:1][0:1][9:10]
System configuration controller (SYSCFG)full-featuredfull-featuredfull-featuredfull-featured
Direct memory access controller (DMA1)full-featuredfull-featuredfull-featuredfull-featured
Nested vectored interrupt controller (NVIC)full-featuredfull-featuredfull-featuredfull-featured
Extended interrupt and event controller (EXTI)full-featuredfull-featuredfull-featuredfull-featured
Analog-to-digital converter (ADC1)full-featuredfull-featuredfull-featuredfull-featured
General-purpose timers (TIM2)full-featuredfull-featuredfull-featuredfull-featured
General-purpose timers (TIM21)full-featuredfull-featuredfull-featuredfull-featured
General-purpose timers (TIM22)---full-featured
Low power timer (LPTIM1)full-featuredfull-featuredfull-featuredfull-featured
Independent watchdog (IWDG)full-featuredfull-featuredfull-featuredfull-featured
System window watchdog (WWDG)full-featuredfull-featuredfull-featuredfull-featured
Real-time clock (RTC)full-featuredfull-featuredfull-featuredfull-featured
Inter-integrated circuit (I2C1) interfaceup to 400 kHz, no Fast-mode Plusup to 400 kHz, no Fast-mode Plusup to 400 kHz, no Fast-mode Plusup to 400 kHz, no Fast-mode Plus
Universal synchronous asynchronous receiver transmitter (USART2)no synchronous mode, no LIN mode, no dual clock, no receiver timeout, no ModBus, no autobaudrate, no Smartcard modeno synchronous mode, no LIN mode, no dual clock, no receiver timeout, no ModBus, no autobaudrate, no Smartcard modeno LIN modeno LIN mode
Table 2. Overview of features per category (continued)
FeatureCategory 1Category 2Category 3Category 5
Low-power universal asynchronous receiver transmitter (LPUART1)full-featuredfull-featuredfull-featuredfull-featured
Serial peripheral interface(SPI1)no I2Sno I2Sno I2Sno I2S
Debug support (DBG)full-featuredfull-featuredfull-featuredfull-featured
Device electronic signaturefull-featuredfull-featuredfull-featuredfull-featured