RM0451-STM32L0x0
Introduction
This reference manual targets application developers. It provides complete information on how to use the STM32L0x0 microcontroller memory and peripherals.
The STM32L0x0 is a line of microcontrollers with different memory sizes, packages and peripherals. It includes STM32L010xx part numbers.
For ordering information, mechanical, and electrical device characteristics please refer to the corresponding datasheets.
For information on the Arm ® Cortex ® -M0+ core, please refer to the Cortex ® -M0+ Technical Reference Manual .
The STM32L0x0 microcontrollers include state-of-the-art patented technology.
Related documents
- • Cortex ® -M0+ Technical Reference Manual, available from www.arm.com .
- • STM32L0 Series Cortex ® -M0+ programming manual (PM0223).
- • STM32L010xx datasheets.
- • STM32L0x0 erratasheet.
Contents
- 1 Documentation conventions . . . . . 33
- 1.1 General information . . . . . 33
- 1.2 List of abbreviations for registers . . . . . 33
- 1.3 Glossary . . . . . 34
- 1.4 Availability of peripherals . . . . . 34
- 1.5 Product category definition . . . . . 34
- 2 System and memory overview . . . . . 37
- 2.1 System architecture . . . . . 37
- 2.1.1 S0: Cortex®-bus . . . . . 38
- 2.1.2 S1: DMA-bus . . . . . 38
- 2.1.3 BusMatrix . . . . . 38
- 2.2 Memory organization . . . . . 39
- 2.2.1 Introduction . . . . . 39
- 2.2.2 Memory map and register boundary addresses . . . . . 40
- 2.3 Embedded SRAM . . . . . 43
- 2.4 Boot configuration . . . . . 44
- 2.1 System architecture . . . . . 37
- 3 Flash program memory and data EEPROM (FLASH) . . . . . 46
- 3.1 Introduction . . . . . 46
- 3.2 NVM main features . . . . . 46
- 3.3 NVM functional description . . . . . 46
- 3.3.1 NVM organization . . . . . 46
- 3.3.2 Reading the NVM . . . . . 50
- 3.3.3 Writing/erasing the NVM . . . . . 58
- 3.4 Memory protection . . . . . 72
- 3.4.1 RDP (Read Out Protection) . . . . . 73
- 3.4.2 PcROP (Proprietary Code Read-Out Protection) . . . . . 74
- 3.4.3 Protections against unwanted write/erase operations . . . . . 76
- 3.4.4 Write/erase protection management . . . . . 77
- 3.4.5 Protection errors . . . . . 78
- 3.5 NVM interrupts . . . . . 78
- 3.5.1 Hard fault . . . . . 79
| 3.6 | Memory interface management . . . . . | 79 |
| 3.6.1 | Operation priority and evolution . . . . . | 79 |
| 3.6.2 | Sequence of operations . . . . . | 80 |
| 3.6.3 | Change the number of wait states while reading . . . . . | 81 |
| 3.6.4 | Power-down . . . . . | 81 |
| 3.7 | Flash register description . . . . . | 82 |
| 3.7.1 | Access control register (FLASH_ACR) . . . . . | 83 |
| 3.7.2 | Program and erase control register (FLASH_PECR) . . . . . | 84 |
| 3.7.3 | Power-down key register (FLASH_PDKEYR) . . . . . | 87 |
| 3.7.4 | PECR unlock key register (FLASH_PEKEYR) . . . . . | 87 |
| 3.7.5 | Program and erase key register (FLASH_PRGKEYR) . . . . . | 87 |
| 3.7.6 | Option bytes unlock key register (FLASH_OPTKEYR) . . . . . | 88 |
| 3.7.7 | Status register (FLASH_SR) . . . . . | 89 |
| 3.7.8 | Option bytes register (FLASH_OPTR) . . . . . | 91 |
| 3.7.9 | Write protection register 1 (FLASH_WRPROT1) . . . . . | 93 |
| 3.7.10 | Write protection register 2 (FLASH_WRPROT2) . . . . . | 94 |
| 3.7.11 | Flash register map . . . . . | 95 |
| 3.8 | Option bytes . . . . . | 96 |
| 3.8.1 | Option bytes description . . . . . | 96 |
| 3.8.2 | Mismatch when loading protection flags . . . . . | 97 |
| 3.8.3 | Reloading Option bytes by software . . . . . | 97 |
| 4 | Cyclic redundancy check calculation unit (CRC) . . . . . | 98 |
| 4.1 | Introduction . . . . . | 98 |
| 4.2 | CRC main features . . . . . | 98 |
| 4.3 | CRC functional description . . . . . | 99 |
| 4.3.1 | CRC block diagram . . . . . | 99 |
| 4.3.2 | CRC internal signals . . . . . | 99 |
| 4.3.3 | CRC operation . . . . . | 99 |
| 4.4 | CRC registers . . . . . | 101 |
| 4.4.1 | CRC data register (CRC_DR) . . . . . | 101 |
| 4.4.2 | CRC independent data register (CRC_IDR) . . . . . | 101 |
| 4.4.3 | CRC control register (CRC_CR) . . . . . | 102 |
| 4.4.4 | CRC initial value (CRC_INIT) . . . . . | 103 |
| 4.4.5 | CRC polynomial (CRC_POL) . . . . . | 103 |
| 4.4.6 | CRC register map . . . . . | 104 |
| 5 | Firewall (FW) . . . . . | 105 |
| 5.1 | Introduction . . . . . | 105 |
| 5.2 | Firewall main features . . . . . | 105 |
| 5.3 | Firewall functional description . . . . . | 106 |
| 5.3.1 | Firewall AMBA bus snoop . . . . . | 106 |
| 5.3.2 | Functional requirements . . . . . | 106 |
| 5.3.3 | Firewall segments . . . . . | 107 |
| 5.3.4 | Segment accesses and properties . . . . . | 108 |
| 5.3.5 | Firewall initialization . . . . . | 109 |
| 5.3.6 | Firewall states . . . . . | 110 |
| 5.4 | Firewall registers . . . . . | 112 |
| 5.4.1 | Code segment start address (FW_CSSA) . . . . . | 112 |
| 5.4.2 | Code segment length (FW_CSL) . . . . . | 112 |
| 5.4.3 | Non-volatile data segment start address (FW_NVDSSA) . . . . . | 113 |
| 5.4.4 | Non-volatile data segment length (FW_NVDLSL) . . . . . | 113 |
| 5.4.5 | Volatile data segment start address (FW_VDSSA) . . . . . | 114 |
| 5.4.6 | Volatile data segment length (FW_VDSL) . . . . . | 114 |
| 5.4.7 | Configuration register (FW_CR) . . . . . | 115 |
| 5.4.8 | Firewall register map . . . . . | 116 |
| 6 | Power control (PWR) . . . . . | 117 |
| 6.1 | Power supplies . . . . . | 117 |
| 6.1.1 | Independent A/D converter supply . . . . . | 118 |
| 6.1.2 | RTC and RTC backup registers . . . . . | 118 |
| 6.1.3 | Voltage regulator . . . . . | 118 |
| 6.1.4 | Dynamic voltage scaling management . . . . . | 119 |
| 6.1.5 | Dynamic voltage scaling configuration . . . . . | 120 |
| 6.1.6 | Voltage regulator and clock management when modifying the VCORE range . . . . . | 120 |
| 6.1.7 | Voltage range and limitations when VDD ranges from 1.8 V to 2.0 V . . . . . | 121 |
| 6.2 | Power supply supervisor . . . . . | 121 |
| 6.2.1 | Power-on reset (POR)/power-down reset (PDR) . . . . . | 122 |
| 6.2.2 | Brownout reset (BOR) . . . . . | 123 |
| 6.2.3 | Internal voltage reference (VREFINT) . . . . . | 124 |
| 6.3 | Low-power modes . . . . . | 125 |
| 6.3.1 | Behavior of clocks in low-power modes . . . . . | 126 |
| 6.3.2 | Slowing down system clocks . . . . . | 127 |
| 6.3.3 | Peripheral clock gating . . . . . | 127 |
| 6.3.4 | Low-power run mode (LP run) . . . . . | 127 |
| 6.3.5 | Entering low-power mode . . . . . | 128 |
| 6.3.6 | Exiting low-power mode . . . . . | 128 |
| 6.3.7 | Sleep mode . . . . . | 129 |
| 6.3.8 | Low-power sleep mode (LP sleep) . . . . . | 130 |
| 6.3.9 | Stop mode . . . . . | 132 |
| 6.3.10 | Standby mode . . . . . | 135 |
| 6.3.11 | Waking up the device from Stop and Standby modes using the RTC . . . . . | 136 |
| 6.4 | Power control registers . . . . . | 138 |
| 6.4.1 | PWR power control register (PWR_CR) . . . . . | 138 |
| 6.4.2 | PWR power control/status register (PWR_CSR) . . . . . | 141 |
| 6.4.3 | PWR register map . . . . . | 143 |
| 7 | Reset and clock control (RCC) . . . . . | 144 |
| 7.1 | Reset . . . . . | 144 |
| 7.1.1 | System reset . . . . . | 144 |
| 7.1.2 | Power reset . . . . . | 145 |
| 7.1.3 | RTC and backup registers reset . . . . . | 145 |
| 7.2 | Clocks . . . . . | 146 |
| 7.2.1 | HSE clock . . . . . | 149 |
| 7.2.2 | HSI16 clock . . . . . | 151 |
| 7.2.3 | MSI clock . . . . . | 151 |
| 7.2.4 | PLL . . . . . | 152 |
| 7.2.5 | LSE clock . . . . . | 153 |
| 7.2.6 | LSI clock . . . . . | 153 |
| 7.2.7 | System clock (SYSCLK) selection . . . . . | 154 |
| 7.2.8 | System clock source frequency versus voltage range . . . . . | 154 |
| 7.2.9 | HSE clock security system (CSS) . . . . . | 154 |
| 7.2.10 | LSE Clock Security System . . . . . | 155 |
| 7.2.11 | RTC clock . . . . . | 155 |
| 7.2.12 | Watchdog clock . . . . . | 156 |
| 7.2.13 | Clock-out capability . . . . . | 156 |
| 7.2.14 | Internal/external clock measurement using TIM21 . . . . . | 156 |
| 7.2.15 | Clock-independent system clock sources for TIM2/TIM21/TIM22 . . . . . | 157 |
| 7.3 | RCC registers . . . . . | 158 |
| 7.3.1 | Clock control register (RCC_CR) . . . . . | 158 |
| 7.3.2 | Internal clock sources calibration register (RCC_ICSCR) . . . . . | 161 |
| 7.3.3 | Clock configuration register (RCC_CFGR) . . . . . | 162 |
| 7.3.4 | Clock interrupt enable register (RCC_CIER) . . . . . | 164 |
| 7.3.5 | Clock interrupt flag register (RCC_CIFR) . . . . . | 166 |
| 7.3.6 | Clock interrupt clear register (RCC_CICR) . . . . . | 167 |
| 7.3.7 | GPIO reset register (RCC_IOPRSTR) . . . . . | 168 |
| 7.3.8 | AHB peripheral reset register (RCC_AHBRSTR) . . . . . | 169 |
| 7.3.9 | APB2 peripheral reset register (RCC_APB2RSTR) . . . . . | 170 |
| 7.3.10 | APB1 peripheral reset register (RCC_APB1RSTR) . . . . . | 171 |
| 7.3.11 | GPIO clock enable register (RCC_IOPENR) . . . . . | 172 |
| 7.3.12 | AHB peripheral clock enable register (RCC_AHBENR) . . . . . | 174 |
| 7.3.13 | APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . | 175 |
| 7.3.14 | APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . | 177 |
| 7.3.15 | GPIO clock enable in Sleep mode register (RCC_IOPSMENR) . . . . . | 179 |
| 7.3.16 | AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . . . . . | 180 |
| 7.3.17 | APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) . . . . . | 181 |
| 7.3.18 | APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR) . . . . . | 182 |
| 7.3.19 | Clock configuration register (RCC_CCIPR) . . . . . | 183 |
| 7.3.20 | Control/status register (RCC_CSR) . . . . . | 184 |
| 7.3.21 | RCC register map . . . . . | 188 |
| 8 | General-purpose I/Os (GPIO) . . . . . | 191 |
| 8.1 | Introduction . . . . . | 191 |
| 8.2 | GPIO main features . . . . . | 191 |
| 8.3 | GPIO functional description . . . . . | 191 |
| 8.3.1 | General-purpose I/O (GPIO) . . . . . | 193 |
| 8.3.2 | I/O pin alternate function multiplexer and mapping . . . . . | 194 |
| 8.3.3 | I/O port control registers . . . . . | 195 |
| 8.3.4 | I/O port data registers . . . . . | 195 |
| 8.3.5 | I/O data bitwise handling . . . . . | 195 |
| 8.3.6 | GPIO locking mechanism . . . . . | 195 |
| 8.3.7 | I/O alternate function input/output . . . . . | 196 |
| 8.3.8 | External interrupt/wakeup lines . . . . . | 196 |
| 8.3.9 | Input configuration . . . . . | 196 |
| 8.3.10 | Output configuration . . . . . | 197 |
| 8.3.11 | Alternate function configuration . . . . . | 198 |
| 8.3.12 | Analog configuration . . . . . | 199 |
| 8.3.13 | Using the HSE or LSE oscillator pins as GPIOs . . . . . | 199 |
| 8.3.14 | Using the GPIO pins in the RTC supply domain . . . . . | 199 |
| 8.3.15 | BOOT0/GPIO pin sharing . . . . . | 200 |
| 8.4 | GPIO registers . . . . . | 200 |
| 8.4.1 | GPIO port mode register (GPIOx_MODER) (x =A to E and H) . . . . . | 200 |
| 8.4.2 | GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) . . . . . | 200 |
| 8.4.3 | GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) . . . . . | 201 |
| 8.4.4 | GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) . . . . . | 201 |
| 8.4.5 | GPIO port input data register (GPIOx_IDR) (x = A to E and H) . . . . . | 202 |
| 8.4.6 | GPIO port output data register (GPIOx_ODR) (x = A to E and H) . . . . . | 202 |
| 8.4.7 | GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) . . . . . | 203 |
| 8.4.8 | GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) . . . . . | 203 |
| 8.4.9 | GPIO alternate function low register (GPIOx_AFRL) (x = A to E and H) . . . . . | 204 |
| 8.4.10 | GPIO alternate function high register (GPIOx_AFRH) (x = A to E and H) . . . . . | 205 |
| 8.4.11 | GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . | 205 |
| 8.4.12 | GPIO register map . . . . . | 206 |
| 9 | System configuration controller (SYSCFG) . . . . . | 208 |
| 9.1 | Introduction . . . . . | 208 |
| 9.2 | SYSCFG registers . . . . . | 209 |
| 9.2.1 | SYSCFG memory remap register (SYSCFG_CFGR1) . . . . . | 209 |
| 9.2.2 | SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) . . . . . | 210 |
| 9.2.3 | Reference control and status register (SYSCFG_CFGR3) . . . . . | 210 |
| 9.2.4 | SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . | 211 |
| 9.2.5 | SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . | 213 |
- 9.2.6 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) ..... 213
- 9.2.7 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) ..... 214
- 9.2.8 SYSCFG register map ..... 215
- 10 Direct memory access controller (DMA) ..... 216
- 10.1 Introduction ..... 216
- 10.2 DMA main features ..... 216
- 10.3 DMA implementation ..... 217
- 10.3.1 DMA ..... 217
- 10.3.2 DMA request mapping ..... 217
- 10.4 DMA functional description ..... 219
- 10.4.1 DMA block diagram ..... 219
- 10.4.2 DMA transfers ..... 220
- 10.4.3 DMA arbitration ..... 220
- 10.4.4 DMA channels ..... 221
- 10.4.5 DMA data width, alignment and endianness ..... 224
- 10.4.6 DMA error management ..... 226
- 10.5 DMA interrupts ..... 226
- 10.6 DMA registers ..... 226
- 10.6.1 DMA interrupt status register (DMA_ISR) ..... 227
- 10.6.2 DMA interrupt flag clear register (DMA_IFCR) ..... 229
- 10.6.3 DMA channel x configuration register (DMA_CCRx) ..... 230
- 10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) ..... 233
- 10.6.5 DMA channel x peripheral address register (DMA_CPARx) ..... 234
- 10.6.6 DMA channel x memory address register (DMA_CMARx) ..... 234
- 10.6.7 DMA channel selection register (DMA_CSELR) ..... 236
- 10.6.8 DMA register map ..... 236
- 11 Nested vectored interrupt controller (NVIC) ..... 239
- 11.1 Main features ..... 239
- 11.2 SysTick calibration value register ..... 239
- 11.3 Interrupt and exception vectors ..... 239
- 12 Extended interrupt and event controller (EXTI) ..... 242
- 12.1 Introduction ..... 242
| 12.2 | EXTI main features . . . . . | 242 |
| 12.3 | EXTI functional description . . . . . | 242 |
| 12.3.1 | EXTI block diagram . . . . . | 243 |
| 12.3.2 | Wakeup event management . . . . . | 243 |
| 12.3.3 | Peripherals asynchronous interrupts . . . . . | 244 |
| 12.3.4 | Hardware interrupt selection . . . . . | 244 |
| 12.3.5 | Hardware event selection . . . . . | 244 |
| 12.3.6 | Software interrupt/event selection . . . . . | 244 |
| 12.4 | EXTI interrupt/event line mapping . . . . . | 245 |
| 12.5 | EXTI registers . . . . . | 247 |
| 12.5.1 | EXTI interrupt mask register (EXTI_IMR) . . . . . | 247 |
| 12.5.2 | EXTI event mask register (EXTI_EMR) . . . . . | 247 |
| 12.5.3 | EXTI rising edge trigger selection register (EXTI_RTSR) . . . . . | 248 |
| 12.5.4 | Falling edge trigger selection register (EXTI_FTSR) . . . . . | 249 |
| 12.5.5 | EXTI software interrupt event register (EXTI_SWIER) . . . . . | 249 |
| 12.5.6 | EXTI pending register (EXTI_PR) . . . . . | 250 |
| 12.5.7 | EXTI register map . . . . . | 251 |
| 13 | Analog-to-digital converter (ADC) . . . . . | 252 |
| 13.1 | Introduction . . . . . | 252 |
| 13.2 | ADC main features . . . . . | 253 |
| 13.3 | ADC functional description . . . . . | 254 |
| 13.3.1 | ADC pins and internal signals . . . . . | 254 |
| 13.3.2 | ADC voltage regulator (ADVREGEN) . . . . . | 255 |
| 13.3.3 | Calibration (ADCAL) . . . . . | 256 |
| 13.3.4 | ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . | 258 |
| 13.3.5 | ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . . | 259 |
| 13.3.6 | ADC connectivity . . . . . | 261 |
| 13.3.7 | Configuring the ADC . . . . . | 262 |
| 13.3.8 | Channel selection (CHSEL, SCANDIR) . . . . . | 262 |
| 13.3.9 | Programmable sampling time (SMP) . . . . . | 262 |
| 13.3.10 | Single conversion mode (CONT = 0) . . . . . | 263 |
| 13.3.11 | Continuous conversion mode (CONT = 1) . . . . . | 263 |
| 13.3.12 | Starting conversions (ADSTART) . . . . . | 264 |
| 13.3.13 | Timings . . . . . | 265 |
| 13.3.14 | Stopping an ongoing conversion (ADSTP) . . . . . | 266 |
| 13.4 | Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . | 266 |
| 13.4.1 | Discontinuous mode (DISCEN) . . . . . | 267 |
| 13.4.2 | Programmable resolution (RES) - Fast conversion mode . . . . . | 267 |
| 13.4.3 | End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . . | 268 |
| 13.4.4 | End of conversion sequence (EOS flag) . . . . . | 268 |
| 13.4.5 | Example timing diagrams (single/continuous modes hardware/software triggers) . . . . . | 269 |
| 13.5 | Data management . . . . . | 271 |
| 13.5.1 | Data register and data alignment (ADC_DR, ALIGN) . . . . . | 271 |
| 13.5.2 | ADC overrun (OVR, OVRMOD) . . . . . | 271 |
| 13.5.3 | Managing a sequence of data converted without using the DMA . . . . . | 272 |
| 13.5.4 | Managing converted data without using the DMA without overrun . . . . . | 272 |
| 13.5.5 | Managing converted data using the DMA . . . . . | 272 |
| 13.6 | Low-power features . . . . . | 274 |
| 13.6.1 | Wait mode conversion . . . . . | 274 |
| 13.6.2 | Auto-off mode (AUTOFF) . . . . . | 275 |
| 13.7 | Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) . . . . . | 276 |
| 13.7.1 | Description of the analog watchdog . . . . . | 276 |
| 13.7.2 | ADC_AWD1_OUT output signal generation . . . . . | 277 |
| 13.7.3 | Analog watchdog threshold control . . . . . | 279 |
| 13.8 | Oversampler . . . . . | 280 |
| 13.8.1 | ADC operating modes supported when oversampling . . . . . | 282 |
| 13.8.2 | Analog watchdog . . . . . | 282 |
| 13.8.3 | Triggered mode . . . . . | 282 |
| 13.9 | Internal reference voltage . . . . . | 283 |
| 13.10 | ADC interrupts . . . . . | 285 |
| 13.11 | ADC registers . . . . . | 286 |
| 13.11.1 | ADC interrupt and status register (ADC_ISR) . . . . . | 286 |
| 13.11.2 | ADC interrupt enable register (ADC_IER) . . . . . | 287 |
| 13.11.3 | ADC control register (ADC_CR) . . . . . | 289 |
| 13.11.4 | ADC configuration register 1 (ADC_CFGR1) . . . . . | 291 |
| 13.11.5 | ADC configuration register 2 (ADC_CFGR2) . . . . . | 295 |
| 13.11.6 | ADC sampling time register (ADC_SMPR) . . . . . | 296 |
| 13.11.7 | ADC watchdog threshold register (ADC_TR) . . . . . | 297 |
| 13.11.8 | ADC channel selection register (ADC_CHSELR) . . . . . | 297 |
| 13.11.9 | ADC data register (ADC_DR) . . . . . | 298 |
| 13.11.10 | ADC Calibration factor (ADC_CALFACT) . . . . . | 298 |
| 13.11.11 | ADC common configuration register (ADC_CCR) . . . . . | 299 |
| 13.12 | ADC register map . . . . . | 300 |
| 14 | General-purpose timer (TIM2) . . . . . | 302 |
| 14.1 | TIM2 introduction . . . . . | 302 |
| 14.2 | TIM2 main features . . . . . | 302 |
| 14.3 | TIM2 functional description . . . . . | 304 |
| 14.3.1 | Time-base unit . . . . . | 304 |
| 14.3.2 | Counter modes . . . . . | 306 |
| 14.3.3 | Clock selection . . . . . | 316 |
| 14.3.4 | Capture/compare channels . . . . . | 320 |
| 14.3.5 | Input capture mode . . . . . | 322 |
| 14.3.6 | PWM input mode . . . . . | 324 |
| 14.3.7 | Forced output mode . . . . . | 325 |
| 14.3.8 | Output compare mode . . . . . | 325 |
| 14.3.9 | PWM mode . . . . . | 326 |
| 14.3.10 | One-pulse mode . . . . . | 330 |
| 14.3.11 | Clearing the OCxREF signal on an external event . . . . . | 331 |
| 14.3.12 | Encoder interface mode . . . . . | 332 |
| 14.3.13 | Timer input XOR function . . . . . | 334 |
| 14.3.14 | Timers and external trigger synchronization . . . . . | 335 |
| 14.3.15 | Timer synchronization . . . . . | 339 |
| 14.3.16 | Debug mode . . . . . | 345 |
| 14.4 | TIM2 registers . . . . . | 346 |
| 14.4.1 | TIMx control register 1 (TIMx_CR1) . . . . . | 346 |
| 14.4.2 | TIMx control register 2 (TIMx_CR2) . . . . . | 348 |
| 14.4.3 | TIMx slave mode control register (TIMx_SMCR) . . . . . | 349 |
| 14.4.4 | TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . | 351 |
| 14.4.5 | TIMx status register (TIMx_SR) . . . . . | 352 |
| 14.4.6 | TIMx event generation register (TIMx_EGR) . . . . . | 354 |
| 14.4.7 | TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 355 |
| 14.4.8 | TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . | 358 |
| 14.4.9 | TIMx capture/compare enable register (TIMx_CCER) . . . . . | 359 |
| 14.4.10 | TIMx counter (TIMx_CNT) . . . . . | 361 |
| 14.4.11 | TIMx prescaler (TIMx_PSC) . . . . . | 361 |
| 14.4.12 | TIMx auto-reload register (TIMx_ARR) . . . . . | 361 |
| 14.4.13 | TIMx capture/compare register 1 (TIMx_CCR1) . . . . . | 362 |
| 14.4.14 | TIMx capture/compare register 2 (TIMx_CCR2) . . . . . | 362 |
| 14.4.15 | TIMx capture/compare register 3 (TIMx_CCR3) . . . . . | 363 |
| 14.4.16 | TIMx capture/compare register 4 (TIMx_CCR4) . . . . . | 363 |
| 14.4.17 | TIMx DMA control register (TIMx_DCR) . . . . . | 364 |
| 14.4.18 | TIMx DMA address for full transfer (TIMx_DMAR) . . . . . | 364 |
| 14.4.19 | TIM2 option register (TIM2_OR) . . . . . | 366 |
| 14.5 | TIMx register map . . . . . | 367 |
| 15 | General-purpose timers (TIM21/22) . . . . . | 369 |
| 15.1 | Introduction . . . . . | 369 |
| 15.2 | TIM21/22 main features . . . . . | 369 |
| 15.2.1 | TIM21/22 main features . . . . . | 369 |
| 15.3 | TIM21/22 functional description . . . . . | 371 |
| 15.3.1 | Timebase unit . . . . . | 371 |
| 15.3.2 | Counter modes . . . . . | 373 |
| 15.3.3 | Clock selection . . . . . | 384 |
| 15.3.4 | Capture/compare channels . . . . . | 387 |
| 15.3.5 | Input capture mode . . . . . | 389 |
| 15.3.6 | PWM input mode . . . . . | 391 |
| 15.3.7 | Forced output mode . . . . . | 392 |
| 15.3.8 | Output compare mode . . . . . | 392 |
| 15.3.9 | PWM mode . . . . . | 393 |
| 15.3.10 | Clearing the OCxREF signal on an external event . . . . . | 396 |
| 15.3.11 | One-pulse mode . . . . . | 397 |
| 15.3.12 | Encoder interface mode . . . . . | 399 |
| 15.3.13 | TIM21/22 external trigger synchronization . . . . . | 401 |
| 15.3.14 | Timer synchronization (TIM21/22) . . . . . | 404 |
| 15.3.15 | Debug mode . . . . . | 404 |
| 15.4 | TIM21/22 registers . . . . . | 405 |
| 15.4.1 | TIM21/22 control register 1 (TIMx_CR1) . . . . . | 405 |
| 15.4.2 | TIM21/22 control register 2 (TIMx_CR2) . . . . . | 407 |
| 15.4.3 | TIM21/22 slave mode control register (TIMx_SMCR) . . . . . | 408 |
| 15.4.4 | TIM21/22 Interrupt enable register (TIMx_DIER) . . . . . | 410 |
| 15.4.5 | TIM21/22 status register (TIMx_SR) . . . . . | 411 |
| 15.4.6 | TIM21/22 event generation register (TIMx_EGR) . . . . . | 413 |
| 15.4.7 | TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 414 |
| 15.4.8 | TIM21/22 capture/compare enable register (TIMx_CCER) . . . . . | 417 |
| 15.4.9 | TIM21/22 counter (TIMx_CNT) . . . . . | 418 |
| 15.4.10 | TIM21/22 prescaler (TIMx_PSC) . . . . . | 418 |
| 15.4.11 | TIM21/22 auto-reload register (TIMx_ARR) . . . . . | 418 |
| 15.4.12 | TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . . | 419 |
| 15.4.13 | TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . . | 419 |
| 15.4.14 | TIM21 option register (TIM21_OR) . . . . . | 420 |
| 15.4.15 | TIM22 option register (TIM22_OR) . . . . . | 421 |
| 15.4.16 | TIM21/22 register map . . . . . | 422 |
| 16 | Low-power timer (LPTIM) . . . . . | 424 |
| 16.1 | Introduction . . . . . | 424 |
| 16.2 | LPTIM main features . . . . . | 424 |
| 16.3 | LPTIM implementation . . . . . | 425 |
| 16.4 | LPTIM functional description . . . . . | 425 |
| 16.4.1 | LPTIM block diagram . . . . . | 425 |
| 16.4.2 | LPTIM trigger mapping . . . . . | 426 |
| 16.4.3 | LPTIM reset and clocks . . . . . | 426 |
| 16.4.4 | Glitch filter . . . . . | 426 |
| 16.4.5 | Prescaler . . . . . | 427 |
| 16.4.6 | Trigger multiplexer . . . . . | 428 |
| 16.4.7 | Operating mode . . . . . | 428 |
| 16.4.8 | Timeout function . . . . . | 430 |
| 16.4.9 | Waveform generation . . . . . | 430 |
| 16.4.10 | Register update . . . . . | 431 |
| 16.4.11 | Counter mode . . . . . | 432 |
| 16.4.12 | Timer enable . . . . . | 433 |
| 16.4.13 | Encoder mode . . . . . | 433 |
| 16.4.14 | Debug mode . . . . . | 434 |
| 16.5 | LPTIM low-power modes . . . . . | 434 |
| 16.6 | LPTIM interrupts . . . . . | 435 |
| 16.7 | LPTIM registers . . . . . | 435 |
| 16.7.1 | LPTIM interrupt and status register (LPTIM_ISR) . . . . . | 436 |
| 16.7.2 | LPTIM interrupt clear register (LPTIM_ICR) . . . . . | 437 |
| 16.7.3 | LPTIM interrupt enable register (LPTIM_IER) . . . . . | 437 |
| 16.7.4 | LPTIM configuration register (LPTIM_CFGR) . . . . . | 438 |
| 16.7.5 | LPTIM control register (LPTIM_CR) . . . . . | 441 |
| 16.7.6 | LPTIM compare register (LPTIM_CMP) . . . . . | 442 |
| 16.7.7 | LPTIM autoreload register (LPTIM_ARR) . . . . . | 443 |
| 16.7.8 | LPTIM counter register (LPTIM_CNT) . . . . . | 443 |
| 16.7.9 | LPTIM register map . . . . . | 444 |
| 17 | Independent watchdog (IWDG) . . . . . | 445 |
| 17.1 | Introduction . . . . . | 445 |
| 17.2 | IWDG main features . . . . . | 445 |
| 17.3 | IWDG functional description . . . . . | 445 |
| 17.3.1 | IWDG block diagram . . . . . | 445 |
| 17.3.2 | Window option . . . . . | 446 |
| 17.3.3 | Hardware watchdog . . . . . | 447 |
| 17.3.4 | Register access protection . . . . . | 447 |
| 17.3.5 | Debug mode . . . . . | 447 |
| 17.4 | IWDG registers . . . . . | 448 |
| 17.4.1 | IWDG key register (IWDG_KR) . . . . . | 448 |
| 17.4.2 | IWDG prescaler register (IWDG_PR) . . . . . | 449 |
| 17.4.3 | IWDG reload register (IWDG_RLR) . . . . . | 450 |
| 17.4.4 | IWDG status register (IWDG_SR) . . . . . | 451 |
| 17.4.5 | IWDG window register (IWDG_WINR) . . . . . | 452 |
| 17.4.6 | IWDG register map . . . . . | 453 |
| 18 | System window watchdog (WWDG) . . . . . | 454 |
| 18.1 | Introduction . . . . . | 454 |
| 18.2 | WWDG main features . . . . . | 454 |
| 18.3 | WWDG functional description . . . . . | 454 |
| 18.3.1 | WWDG block diagram . . . . . | 455 |
| 18.3.2 | Enabling the watchdog . . . . . | 455 |
| 18.3.3 | Controlling the down-counter . . . . . | 455 |
| 18.3.4 | How to program the watchdog timeout . . . . . | 455 |
| 18.3.5 | Debug mode . . . . . | 457 |
| 18.4 | WWDG interrupts . . . . . | 457 |
| 18.5 | WWDG registers . . . . . | 457 |
| 18.5.1 | WWDG control register (WWDG_CR) . . . . . | 457 |
| 18.5.2 | WWDG configuration register (WWDG_CFR) . . . . . | 458 |
| 18.5.3 | WWDG status register (WWDG_SR) ..... | 458 |
| 18.5.4 | WWDG register map ..... | 459 |
| 19 | Real-time clock (RTC) ..... | 460 |
| 19.1 | Introduction ..... | 460 |
| 19.2 | RTC main features ..... | 461 |
| 19.3 | RTC implementation ..... | 461 |
| 19.4 | RTC functional description ..... | 462 |
| 19.4.1 | RTC block diagram ..... | 462 |
| 19.4.2 | GPIOs controlled by the RTC ..... | 463 |
| 19.4.3 | Clock and prescalers ..... | 464 |
| 19.4.4 | Real-time clock and calendar ..... | 465 |
| 19.4.5 | Programmable alarms ..... | 466 |
| 19.4.6 | Periodic auto-wakeup ..... | 466 |
| 19.4.7 | RTC initialization and configuration ..... | 467 |
| 19.4.8 | Reading the calendar ..... | 468 |
| 19.4.9 | Resetting the RTC ..... | 469 |
| 19.4.10 | RTC synchronization ..... | 470 |
| 19.4.11 | RTC reference clock detection ..... | 470 |
| 19.4.12 | RTC smooth digital calibration ..... | 471 |
| 19.4.13 | Time-stamp function ..... | 473 |
| 19.4.14 | Tamper detection ..... | 474 |
| 19.4.15 | Calibration clock output ..... | 476 |
| 19.4.16 | Alarm output ..... | 476 |
| 19.5 | RTC low-power modes ..... | 477 |
| 19.6 | RTC interrupts ..... | 477 |
| 19.7 | RTC registers ..... | 478 |
| 19.7.1 | RTC time register (RTC_TR) ..... | 478 |
| 19.7.2 | RTC date register (RTC_DR) ..... | 479 |
| 19.7.3 | RTC control register (RTC_CR) ..... | 480 |
| 19.7.4 | RTC initialization and status register (RTC_ISR) ..... | 483 |
| 19.7.5 | RTC prescaler register (RTC_PRER) ..... | 486 |
| 19.7.6 | RTC wakeup timer register (RTC_WUTR) ..... | 487 |
| 19.7.7 | RTC alarm A register (RTC_ALRMAR) ..... | 488 |
| 19.7.8 | RTC alarm B register (RTC_ALRMBR) ..... | 489 |
| 19.7.9 | RTC write protection register (RTC_WPR) ..... | 490 |
- 19.7.10 RTC sub second register (RTC_SSR) . . . . . 490
- 19.7.11 RTC shift control register (RTC_SHIFTR) . . . . . 491
- 19.7.12 RTC timestamp time register (RTC_TSTR) . . . . . 492
- 19.7.13 RTC timestamp date register (RTC_TSDR) . . . . . 493
- 19.7.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . 494
- 19.7.15 RTC calibration register (RTC_CALR) . . . . . 495
- 19.7.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . 496
- 19.7.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . 499
- 19.7.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . 500
- 19.7.19 RTC option register (RTC_OR) . . . . . 501
- 19.7.20 RTC backup registers (RTC_BKPxR) . . . . . 502
- 19.7.21 RTC register map . . . . . 502
- 20 Inter-integrated circuit (I2C) interface . . . . . 505
- 20.1 Introduction . . . . . 505
- 20.2 I2C main features . . . . . 505
- 20.3 I2C implementation . . . . . 506
- 20.4 I2C functional description . . . . . 506
- 20.4.1 I2C1 block diagram . . . . . 507
- 20.4.2 I2C pins and internal signals . . . . . 508
- 20.4.3 I2C clock requirements . . . . . 508
- 20.4.4 Mode selection . . . . . 508
- 20.4.5 I2C initialization . . . . . 509
- 20.4.6 Software reset . . . . . 514
- 20.4.7 Data transfer . . . . . 515
- 20.4.8 I2C slave mode . . . . . 517
- 20.4.9 I2C master mode . . . . . 526
- 20.4.10 I2C_TIMINGR register configuration examples . . . . . 538
- 20.4.11 SMBus specific features . . . . . 539
- 20.4.12 SMBus initialization . . . . . 542
- 20.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . 544
- 20.4.14 SMBus slave mode . . . . . 544
- 20.4.15 Wakeup from Stop mode on address match . . . . . 552
- 20.4.16 Error conditions . . . . . 552
- 20.4.17 DMA requests . . . . . 554
- 20.4.18 Debug mode . . . . . 555
- 20.5 I2C low-power modes . . . . . 555
| 20.6 | I2C interrupts . . . . . | 556 |
| 20.7 | I2C registers . . . . . | 557 |
| 20.7.1 | I2C control register 1 (I2C_CR1) . . . . . | 557 |
| 20.7.2 | I2C control register 2 (I2C_CR2) . . . . . | 560 |
| 20.7.3 | I2C own address 1 register (I2C_OAR1) . . . . . | 562 |
| 20.7.4 | I2C own address 2 register (I2C_OAR2) . . . . . | 563 |
| 20.7.5 | I2C timing register (I2C_TIMINGR) . . . . . | 564 |
| 20.7.6 | I2C timeout register (I2C_TIMEOUTR) . . . . . | 565 |
| 20.7.7 | I2C interrupt and status register (I2C_ISR) . . . . . | 566 |
| 20.7.8 | I2C interrupt clear register (I2C_ICR) . . . . . | 568 |
| 20.7.9 | I2C PEC register (I2C_PECR) . . . . . | 569 |
| 20.7.10 | I2C receive data register (I2C_RXDR) . . . . . | 570 |
| 20.7.11 | I2C transmit data register (I2C_TXDR) . . . . . | 570 |
| 20.7.12 | I2C register map . . . . . | 571 |
| 21 | Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . | 573 |
| 21.1 | Introduction . . . . . | 573 |
| 21.2 | USART main features . . . . . | 573 |
| 21.3 | USART extended features . . . . . | 574 |
| 21.4 | USART implementation . . . . . | 575 |
| 21.5 | USART functional description . . . . . | 575 |
| 21.5.1 | USART character description . . . . . | 578 |
| 21.5.2 | USART transmitter . . . . . | 580 |
| 21.5.3 | USART receiver . . . . . | 583 |
| 21.5.4 | USART baud rate generation . . . . . | 588 |
| 21.5.5 | Tolerance of the USART receiver to clock deviation . . . . . | 590 |
| 21.5.6 | USART auto baud rate detection . . . . . | 592 |
| 21.5.7 | Multiprocessor communication using USART . . . . . | 593 |
| 21.5.8 | Modbus communication using USART . . . . . | 595 |
| 21.5.9 | USART parity control . . . . . | 596 |
| 21.5.10 | USART LIN (local interconnection network) mode . . . . . | 597 |
| 21.5.11 | USART synchronous mode . . . . . | 599 |
| 21.5.12 | USART Single-wire Half-duplex communication . . . . . | 602 |
| 21.5.13 | USART Smartcard mode . . . . . | 602 |
| 21.5.14 | USART IrDA SIR ENDEC block . . . . . | 607 |
| 21.5.15 | USART continuous communication in DMA mode . . . . . | 609 |
| 21.5.16 | RS232 hardware flow control and RS485 driver enable using USART . . . . . | 611 |
| 21.5.17 | Wakeup from Stop mode using USART . . . . . | 613 |
| 21.6 | USART in low-power modes . . . . . | 615 |
| 21.7 | USART interrupts . . . . . | 615 |
| 21.8 | USART registers . . . . . | 617 |
| 21.8.1 | USART control register 1 (USART_CR1) . . . . . | 617 |
| 21.8.2 | USART control register 2 (USART_CR2) . . . . . | 620 |
| 21.8.3 | USART control register 3 (USART_CR3) . . . . . | 624 |
| 21.8.4 | USART baud rate register (USART_BRR) . . . . . | 628 |
| 21.8.5 | USART guard time and prescaler register (USART_GTPR) . . . . . | 628 |
| 21.8.6 | USART receiver timeout register (USART_RTOR) . . . . . | 629 |
| 21.8.7 | USART request register (USART_RQR) . . . . . | 630 |
| 21.8.8 | USART interrupt and status register (USART_ISR) . . . . . | 631 |
| 21.8.9 | USART interrupt flag clear register (USART_ICR) . . . . . | 636 |
| 21.8.10 | USART receive data register (USART_RDR) . . . . . | 638 |
| 21.8.11 | USART transmit data register (USART_TDR) . . . . . | 638 |
| 21.8.12 | USART register map . . . . . | 639 |
| 22 | Low-power universal asynchronous receiver transmitter (LPUART) . . . . . | 641 |
| 22.1 | Introduction . . . . . | 641 |
| 22.2 | LPUART main features . . . . . | 642 |
| 22.3 | LPUART implementation . . . . . | 642 |
| 22.4 | LPUART functional description . . . . . | 643 |
| 22.4.1 | LPUART character description . . . . . | 646 |
| 22.4.2 | LPUART transmitter . . . . . | 648 |
| 22.4.3 | LPUART receiver . . . . . | 650 |
| 22.4.4 | LPUART baud rate generation . . . . . | 653 |
| 22.4.5 | Tolerance of the LPUART receiver to clock deviation . . . . . | 655 |
| 22.4.6 | Multiprocessor communication using LPUART . . . . . | 656 |
| 22.4.7 | LPUART parity control . . . . . | 658 |
| 22.4.8 | Single-wire Half-duplex communication using LPUART . . . . . | 659 |
| 22.4.9 | Continuous communication in DMA mode using LPUART . . . . . | 659 |
| 22.4.10 | RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . . | 662 |
| 22.4.11 | Wakeup from Stop mode using LPUART . . . . . | 665 |
| 22.5 | LPUART in low-power mode . . . . . | 667 |
| 22.6 | LPUART interrupts . . . . . | 667 |
| 22.7 | LPUART registers . . . . . | 669 |
| 22.7.1 | Control register 1 (LPUART_CR1) . . . . . | 669 |
| 22.7.2 | Control register 2 (LPUART_CR2) . . . . . | 672 |
| 22.7.3 | Control register 3 (LPUART_CR3) . . . . . | 674 |
| 22.7.4 | Baud rate register (LPUART_BRR) . . . . . | 676 |
| 22.7.5 | Request register (LPUART_RQR) . . . . . | 676 |
| 22.7.6 | Interrupt & status register (LPUART_ISR) . . . . . | 677 |
| 22.7.7 | Interrupt flag clear register (LPUART_ICR) . . . . . | 680 |
| 22.7.8 | Receive data register (LPUART_RDR) . . . . . | 681 |
| 22.7.9 | Transmit data register (LPUART_TDR) . . . . . | 681 |
| 22.7.10 | LPUART register map . . . . . | 683 |
| 23 | Serial peripheral interface (SPI) . . . . . | 684 |
| 23.1 | Introduction . . . . . | 684 |
| 23.1.1 | SPI main features . . . . . | 684 |
| 23.1.2 | SPI extended features . . . . . | 685 |
| 23.2 | SPI implementation . . . . . | 685 |
| 23.3 | SPI functional description . . . . . | 686 |
| 23.3.1 | General description . . . . . | 686 |
| 23.3.2 | Communications between one master and one slave . . . . . | 687 |
| 23.3.3 | Standard multi-slave communication . . . . . | 690 |
| 23.3.4 | Multi-master communication . . . . . | 691 |
| 23.3.5 | Slave select (NSS) pin management . . . . . | 691 |
| 23.3.6 | Communication formats . . . . . | 693 |
| 23.3.7 | SPI configuration . . . . . | 695 |
| 23.3.8 | Procedure for enabling SPI . . . . . | 695 |
| 23.3.9 | Data transmission and reception procedures . . . . . | 696 |
| 23.3.10 | Procedure for disabling the SPI . . . . . | 698 |
| 23.3.11 | Communication using DMA (direct memory addressing) . . . . . | 699 |
| 23.3.12 | SPI status flags . . . . . | 701 |
| 23.3.13 | SPI error flags . . . . . | 702 |
| 23.4 | SPI special features . . . . . | 703 |
| 23.4.1 | TI mode . . . . . | 703 |
| 23.4.2 | CRC calculation . . . . . | 704 |
| 23.5 | SPI interrupts . . . . . | 706 |
| 23.6 | SPI registers . . . . . | 707 |
| 23.6.1 | SPI control register 1 (SPI_CR1) . . . . . | 707 |
| 23.6.2 | SPI control register 2 (SPI_CR2) . . . . . | 709 |
| 23.6.3 | SPI status register (SPI_SR) . . . . . | 710 |
| 23.6.4 | SPI data register (SPI_DR) . . . . . | 712 |
| 23.6.5 | SPI CRC polynomial register (SPI_CRCPR) . . . . . | 712 |
| 23.6.6 | SPI RX CRC register (SPI_RXCRCR) . . . . . | 713 |
| 23.6.7 | SPI TX CRC register (SPI_TXCRCR) . . . . . | 713 |
| 23.6.8 | SPI register map . . . . . | 714 |
| 24 | Debug support (DBG) . . . . . | 715 |
| 24.1 | Overview . . . . . | 715 |
| 24.2 | Reference Arm® documentation . . . . . | 716 |
| 24.3 | Pinout and debug port pins . . . . . | 716 |
| 24.3.1 | SWD port pins . . . . . | 716 |
| 24.3.2 | SW-DP pin assignment . . . . . | 716 |
| 24.3.3 | Internal pull-up & pull-down on SWD pins . . . . . | 717 |
| 24.4 | ID codes and locking mechanism . . . . . | 717 |
| 24.4.1 | MCU device ID code . . . . . | 717 |
| 24.5 | SWD port . . . . . | 718 |
| 24.5.1 | SWD protocol introduction . . . . . | 718 |
| 24.5.2 | SWD protocol sequence . . . . . | 718 |
| 24.5.3 | SW-DP state machine (reset, idle states, ID code) . . . . . | 719 |
| 24.5.4 | DP and AP read/write accesses . . . . . | 720 |
| 24.5.5 | SW-DP registers . . . . . | 720 |
| 24.5.6 | SW-AP registers . . . . . | 721 |
| 24.6 | Core debug . . . . . | 722 |
| 24.7 | BPU (Break Point Unit) . . . . . | 722 |
| 24.7.1 | BPU functionality . . . . . | 722 |
| 24.8 | DWT (Data Watchpoint) . . . . . | 723 |
| 24.8.1 | DWT functionality . . . . . | 723 |
| 24.8.2 | DWT Program Counter Sample Register . . . . . | 723 |
| 24.9 | MCU debug component (DBG) . . . . . | 723 |
| 24.9.1 | Debug support for low-power modes . . . . . | 723 |
| 24.9.2 | Debug support for timers, watchdog and I 2 C . . . . . | 724 |
| 24.9.3 | Debug MCU configuration register (DBG_CR) . . . . . | 724 |
| 24.9.4 | Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . . | 726 |
| 24.9.5 | Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . . | 728 |
| 24.10 | DBG register map . . . . . | 729 |
| 25 | Device electronic signature . . . . . | 730 |
| 25.1 | Memory size register . . . . . | 730 |
| 25.1.1 | Flash size register . . . . . | 730 |
| 25.2 | Unique device ID registers (96 bits) . . . . . | 730 |
| Appendix A | Code examples. . . . . | 732 |
| A.1 | Introduction . . . . . | 732 |
| A.2 | NVM/RCC Operation code example . . . . . | 732 |
| A.2.1 | Increasing the CPU frequency preparation sequence code . . . . . | 732 |
| A.2.2 | Decreasing the CPU frequency preparation sequence code . . . . . | 732 |
| A.2.3 | Switch from PLL to HSI16 sequence code . . . . . | 733 |
| A.2.4 | Switch to PLL sequence code. . . . . | 733 |
| A.3 | NVM Operation code example . . . . . | 734 |
| A.3.1 | Unlocking the data EEPROM and FLASH_PECR register code example . . . . . | 734 |
| A.3.2 | Locking data EEPROM and FLASH_PECR register code example . . . . . | 734 |
| A.3.3 | Unlocking the NVM program memory code example . . . . . | 734 |
| A.3.4 | Unlocking the option bytes area code example . . . . . | 735 |
| A.3.5 | Write to data EEPROM code example . . . . . | 735 |
| A.3.6 | Erase to data EEPROM code example . . . . . | 735 |
| A.3.7 | Program Option byte code example . . . . . | 736 |
| A.3.8 | Erase Option byte code example . . . . . | 736 |
| A.3.9 | Program a single word to Flash program memory code example . . . . . | 737 |
| A.3.10 | Program half-page to Flash program memory code example . . . . . | 738 |
| A.3.11 | Erase a page in Flash program memory code example . . . . . | 739 |
| A.3.12 | Mass erase code example . . . . . | 740 |
| A.4 | Clock Controller. . . . . | 741 |
| A.4.1 | HSE start sequence code example . . . . . | 741 |
| A.4.2 | PLL configuration modification code example . . . . . | 742 |
| A.4.3 | MCO selection code example. . . . . | 743 |
| A.5 | GPIOs . . . . . | 743 |
| A.5.1 | Locking mechanism code example. . . . . | 743 |
| A.5.2 | Alternate function selection sequence code example . . . . . | 743 |
| A.5.3 | Analog GPIO configuration code example . . . . . | 743 |
| A.6 | DMA . . . . . | 744 |
| A.6.1 | DMA Channel Configuration sequence code example . . . . . | 744 |
| A.7 | Interrupts and event . . . . . | 744 |
| A.7.1 | NVIC initialization example . . . . . | 744 |
| A.7.2 | Extended interrupt selection code example . . . . . | 744 |
| A.8 | ADC . . . . . | 745 |
| A.8.1 | Calibration code example . . . . . | 745 |
| A.8.2 | ADC enable sequence code example . . . . . | 745 |
| A.8.3 | ADC disable sequence code example . . . . . | 746 |
| A.8.4 | ADC clock selection code example . . . . . | 746 |
| A.8.5 | Single conversion sequence code example - Software trigger . . . . . | 746 |
| A.8.6 | Continuous conversion sequence code example - Software trigger . . . . . | 747 |
| A.8.7 | Single conversion sequence code example - Hardware trigger . . . . . | 747 |
| A.8.8 | Continuous conversion sequence code example - Hardware trigger . . . . . | 748 |
| A.8.9 | DMA one shot mode sequence code example . . . . . | 748 |
| A.8.10 | DMA circular mode sequence code example . . . . . | 749 |
| A.8.11 | Wait mode sequence code example . . . . . | 749 |
| A.8.12 | Auto off and no wait mode sequence code example . . . . . | 749 |
| A.8.13 | Auto off and wait mode sequence code example . . . . . | 750 |
| A.8.14 | Analog watchdog code example . . . . . | 750 |
| A.8.15 | Oversampling code example . . . . . | 751 |
| A.9 | Timers . . . . . | 751 |
| A.9.1 | Upcounter on TI2 rising edge code example . . . . . | 751 |
| A.9.2 | Up counter on each 2 ETR rising edges code example . . . . . | 751 |
| A.9.3 | Input capture configuration code example . . . . . | 752 |
| A.9.4 | Input capture data management code example . . . . . | 752 |
| A.9.5 | PWM input configuration code example . . . . . | 753 |
| A.9.6 | PWM input with DMA configuration code example . . . . . | 753 |
| A.9.7 | Output compare configuration code example . . . . . | 754 |
| A.9.8 | Edge-aligned PWM configuration example . . . . . | 755 |
| A.9.9 | Center-aligned PWM configuration example . . . . . | 755 |
| A.9.10 | ETR configuration to clear OCxREF code example . . . . . | 756 |
| A.9.11 | Encoder interface code example . . . . . | 756 |
| A.9.12 | Reset mode code example . . . . . | 757 |
| A.9.13 | Gated mode code example . . . . . | 757 |
| A.9.14 | Trigger mode code example . . . . . | 758 |
| A.9.15 | External clock mode 2 + trigger mode code example. . . . . | 758 |
| A.9.16 | One-Pulse mode code example . . . . . | 758 |
| A.9.17 | Timer prescaling another timer code example . . . . . | 759 |
| A.9.18 | Timer enabling another timer code example. . . . . | 760 |
| A.9.19 | Master and slave synchronization code example. . . . . | 761 |
| A.9.20 | Two timers synchronized by an external trigger code example . . . . . | 762 |
| A.9.21 | DMA burst feature code example . . . . . | 763 |
| A.10 | Low-power timer (LPTIM) . . . . . | 764 |
| A.10.1 | Pulse counter configuration code example. . . . . | 764 |
| A.11 | IWDG code example . . . . . | 764 |
| A.11.1 | IWDG configuration code example. . . . . | 764 |
| A.11.2 | IWDG configuration with window code example. . . . . | 765 |
| A.12 | WWDG code example. . . . . | 765 |
| A.12.1 | WWDG configuration code example. . . . . | 765 |
| A.13 | RTC code example . . . . . | 765 |
| A.13.1 | RTC calendar configuration code example. . . . . | 765 |
| A.13.2 | RTC alarm configuration code example . . . . . | 766 |
| A.13.3 | RTC WUT configuration code example . . . . . | 766 |
| A.13.4 | RTC read calendar code example . . . . . | 767 |
| A.13.5 | RTC calibration code example . . . . . | 767 |
| A.13.6 | RTC tamper and time stamp configuration code example . . . . . | 768 |
| A.13.7 | RTC tamper and time stamp code example . . . . . | 768 |
| A.13.8 | RTC clock output code example. . . . . | 768 |
| A.14 | I2C code example . . . . . | 769 |
| A.14.1 | I2C configured in slave mode code example . . . . . | 769 |
| A.14.2 | I2C slave transmitter code example . . . . . | 769 |
| A.14.3 | I2C slave receiver code example . . . . . | 769 |
| A.14.4 | I2C configured in master mode to receive code example. . . . . | 770 |
| A.14.5 | I2C configured in master mode to transmit code example . . . . . | 770 |
| A.14.6 | I2C master transmitter code example. . . . . | 770 |
| A.14.7 | I2C master receiver code example. . . . . | 770 |
| A.14.8 | I2C configured in master mode to transmit with DMA code example . . . . . | 771 |
| A.14.9 | I2C configured in slave mode to receive with DMA code example. . . . . | 771 |
| A.15 | USART code example. . . . . | 771 |
| A.15.1 | USART transmitter configuration code example. . . . . | 771 |
- A.15.2 USART transmit byte code example. . . . . 771
- A.15.3 USART transfer complete code example . . . . . 771
- A.15.4 USART receiver configuration code example. . . . . 772
- A.15.5 USART receive byte code example . . . . . 772
- A.15.6 USART LIN mode code example . . . . . 772
- A.15.7 USART synchronous mode code example. . . . . 772
- A.15.8 USART single-wire half-duplex code example . . . . . 773
- A.15.9 USART smartcard mode code example . . . . . 773
- A.15.10 USART DMA code example . . . . . 774
- A.15.11 USART IrDA mode code example . . . . . 774
- A.15.12 USART hardware flow control code example. . . . . 774
- A.16 LPUART code example. . . . . 775
- A.16.1 LPUART receiver configuration code example. . . . . 775
- A.16.2 LPUART receive byte code example . . . . . 775
- A.17 SPI code example . . . . . 775
- A.17.1 SPI master configuration code example. . . . . 775
- A.17.2 SPI slave configuration code example . . . . . 775
- A.17.3 SPI full duplex communication code example . . . . . 776
- A.17.4 SPI master configuration with DMA code example. . . . . 776
- A.17.5 SPI slave configuration with DMA code example . . . . . 776
- A.17.6 SPI interrupt code example . . . . . 776
- A.18 DBG code example . . . . . 776
- A.18.1 DBG read device Id code example. . . . . 776
- A.18.2 DBG debug in LPM code example . . . . . 776
Revision history . . . . . 777
List of tables
| Table 1. | STM32L010 memory density . . . . . | 34 |
| Table 2. | Overview of features per category . . . . . | 34 |
| Table 3. | STM32L010xx peripheral register boundary addresses . . . . . | 41 |
| Table 4. | Boot modes . . . . . | 44 |
| Table 5. | Boot modes . . . . . | 44 |
| Table 6. | NVM organization (category 1 devices) . . . . . | 47 |
| Table 7. | NVM organization (category 2 devices) . . . . . | 47 |
| Table 8. | NVM organization (category 3 devices) . . . . . | 48 |
| Table 9. | NVM organization (category 5 devices) . . . . . | 49 |
| Table 10. | Link between master clock power range and frequencies . . . . . | 50 |
| Table 11. | Delays to memory access and number of wait states . . . . . | 50 |
| Table 12. | Internal buffer management . . . . . | 53 |
| Table 13. | Configurations for buffers and speculative reading . . . . . | 56 |
| Table 14. | Dhrystone performances in all memory interface configurations . . . . . | 57 |
| Table 15. | NVM write/erase timings . . . . . | 70 |
| Table 16. | NVM write/erase duration . . . . . | 70 |
| Table 17. | Protection level and content of RDP Option bytes . . . . . | 74 |
| Table 18. | Link between protection bits of FLASH_WRPPROTx register and protected address in Flash program memory . . . . . | 75 |
| Table 19. | Memory access vs mode, protection and Flash program memory sectors . . . . . | 76 |
| Table 20. | Flash interrupt request . . . . . | 79 |
| Table 21. | Flash interface - register map and reset values . . . . . | 95 |
| Table 22. | Option byte format . . . . . | 96 |
| Table 23. | Option byte organization . . . . . | 96 |
| Table 24. | CRC internal input/output signals . . . . . | 99 |
| Table 25. | CRC register map and reset values . . . . . | 104 |
| Table 26. | Segment accesses according to the Firewall state . . . . . | 108 |
| Table 27. | Segment granularity and area ranges . . . . . | 109 |
| Table 28. | Firewall register map and reset values . . . . . | 116 |
| Table 29. | Performance versus VCORE ranges . . . . . | 119 |
| Table 30. | Summary of low-power modes . . . . . | 125 |
| Table 31. | Sleep-now . . . . . | 129 |
| Table 32. | Sleep-on-exit . . . . . | 130 |
| Table 33. | Sleep-now (Low-power sleep) . . . . . | 131 |
| Table 34. | Sleep-on-exit (Low-power sleep) . . . . . | 132 |
| Table 35. | Stop mode . . . . . | 134 |
| Table 36. | Standby mode . . . . . | 136 |
| Table 37. | PWR - register map and reset values . . . . . | 143 |
| Table 38. | HSE/LSE clock sources . . . . . | 149 |
| Table 39. | System clock source frequency . . . . . | 154 |
| Table 40. | RCC register map and reset values . . . . . | 188 |
| Table 41. | Port bit configuration table . . . . . | 193 |
| Table 42. | GPIO register map and reset values . . . . . | 206 |
| Table 43. | SYSCFG register map and reset values . . . . . | 215 |
| Table 44. | DMA implementation . . . . . | 217 |
| Table 45. | DMA requests for each channel . . . . . | 218 |
| Table 46. | Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . | 225 |
| Table 47. | DMA interrupt requests . . . . . | 226 |
| Table 48. | DMA register map and reset values . . . . . | 236 |
| Table 49. | List of vectors . . . . . | 239 |
| Table 50. | EXTI lines connections . . . . . | 246 |
| Table 51. | Extended interrupt/event controller register map and reset values. . . . . | 251 |
| Table 52. | ADC input/output pins . . . . . | 254 |
| Table 53. | ADC internal input/output signals . . . . . | 255 |
| Table 54. | External triggers . . . . . | 255 |
| Table 55. | Latency between trigger and start of conversion . . . . . | 260 |
| Table 56. | Configuring the trigger polarity . . . . . | 266 |
| Table 57. | tSAR timings depending on resolution . . . . . | 268 |
| Table 58. | Analog watchdog comparison. . . . . | 277 |
| Table 59. | Analog watchdog channel selection . . . . . | 277 |
| Table 60. | Maximum output results vs N and M. Grayed values indicates truncation . . . . . | 281 |
| Table 61. | ADC interrupts . . . . . | 285 |
| Table 62. | ADC register map and reset values . . . . . | 300 |
| Table 63. | Counting direction versus encoder signals. . . . . | 333 |
| Table 64. | TIM2/TIM3 internal trigger connection . . . . . | 350 |
| Table 65. | Output control bit for standard OCx channels. . . . . | 360 |
| Table 66. | TIM2 register map and reset values . . . . . | 367 |
| Table 67. | Counting direction versus encoder signals. . . . . | 400 |
| Table 68. | Output control bit for standard OCx channels. . . . . | 418 |
| Table 69. | TIM21/22 register map and reset values . . . . . | 422 |
| Table 70. | STM32L010xx LPTIM features . . . . . | 425 |
| Table 71. | LPTIM1 external trigger connection . . . . . | 426 |
| Table 72. | Prescaler division ratios . . . . . | 427 |
| Table 73. | Encoder counting scenarios . . . . . | 433 |
| Table 74. | Effect of low-power modes on the LPTIM. . . . . | 434 |
| Table 75. | Interrupt events. . . . . | 435 |
| Table 76. | LPTIM register map and reset values. . . . . | 444 |
| Table 77. | IWDG register map and reset values . . . . . | 453 |
| Table 78. | WWDG register map and reset values . . . . . | 459 |
| Table 79. | RTC implementation . . . . . | 461 |
| Table 80. | RTC pin PC13 configuration. . . . . | 463 |
| Table 81. | RTC_OUT mapping . . . . . | 464 |
| Table 82. | Effect of low-power modes on RTC . . . . . | 477 |
| Table 83. | Interrupt control bits . . . . . | 477 |
| Table 84. | RTC register map and reset values . . . . . | 502 |
| Table 85. | STM32L010xx I2C features . . . . . | 506 |
| Table 86. | I2C input/output pins. . . . . | 508 |
| Table 87. | I2C internal input/output signals . . . . . | 508 |
| Table 88. | Comparison of analog vs. digital filters. . . . . | 510 |
| Table 89. | I2C-SMBUS specification data setup and hold times . . . . . | 513 |
| Table 90. | I2C configuration. . . . . | 517 |
| Table 91. | I2C-SMBUS specification clock timings . . . . . | 528 |
| Table 92. | Examples of timing settings for fI2CCLK = 8 MHz . . . . . | 538 |
| Table 93. | Examples of timings settings for fI2CCLK = 16 MHz . . . . . | 538 |
| Table 94. | SMBus timeout specifications . . . . . | 540 |
| Table 95. | SMBus with PEC configuration. . . . . | 543 |
| Table 96. | Examples of TIMEOUTA settings for various I2CCLK frequencies (max tTIMEOUT = 25 ms) . . . . . | 544 |
| Table 97. | Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . | 544 |
| Table 98. | Examples of TIMEOUTA settings for various I2CCLK frequencies |
| (max \( t_{IDLE} = 50 \mu s \) ) . . . . . | 544 | |
| Table 99. | Effect of low-power modes on the I2C . . . . . | 555 |
| Table 100. | I2C Interrupt requests . . . . . | 556 |
| Table 101. | I2C register map and reset values . . . . . | 571 |
| Table 102. | STM32L010x USART/LPUART features . . . . . | 575 |
| Table 103. | Noise detection from sampled data . . . . . | 587 |
| Table 104. | Error calculation for programmed baud rates at \( f_{CK} = 32 \text{ MHz} \) in both cases of oversampling by 16 or by 8. . . . . | 590 |
| Table 105. | Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . | 591 |
| Table 106. | Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . | 591 |
| Table 107. | Frame formats . . . . . | 596 |
| Table 108. | Effect of low-power modes on the USART . . . . . | 615 |
| Table 109. | USART interrupt requests. . . . . | 615 |
| Table 110. | USART register map and reset values . . . . . | 639 |
| Table 111. | STM32L010x USART/LPUART features . . . . . | 643 |
| Table 112. | Error calculation for programmed baud rates at \( f_{ck} = 32.768 \text{ kHz} \) . . . . . | 654 |
| Table 113. | Error calculation for programmed baud rates at \( f_{ck} = 32 \text{ MHz} \) . . . . . | 654 |
| Table 114. | Tolerance of the LPUART receiver. . . . . | 655 |
| Table 115. | Frame formats . . . . . | 658 |
| Table 116. | Effect of low-power modes on the LPUART . . . . . | 667 |
| Table 117. | LPUART interrupt requests. . . . . | 667 |
| Table 118. | LPUART register map and reset values . . . . . | 683 |
| Table 119. | STM32L010xx SPI implementation . . . . . | 685 |
| Table 120. | SPI interrupt requests . . . . . | 706 |
| Table 121. | SPI register map and reset values . . . . . | 714 |
| Table 122. | SW debug port pins . . . . . | 716 |
| Table 123. | REV_ID values . . . . . | 718 |
| Table 124. | Packet request (8-bits) . . . . . | 718 |
| Table 125. | ACK response (3 bits). . . . . | 719 |
| Table 126. | DATA transfer (33 bits). . . . . | 719 |
| Table 127. | SW-DP registers . . . . . | 720 |
| Table 128. | 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . | 721 |
| Table 129. | Core debug registers . . . . . | 722 |
| Table 130. | DBG register map and reset values . . . . . | 729 |
| Table 131. | Document revision history . . . . . | 777 |
List of figures
| Figure 1. | System architecture . . . . . | 37 |
| Figure 2. | Memory map . . . . . | 40 |
| Figure 3. | Structure of one internal buffer . . . . . | 52 |
| Figure 4. | Timing to fetch and execute instructions with prefetch disabled. . . . . | 54 |
| Figure 5. | Timing to fetch and execute instructions with prefetch enabled . . . . . | 56 |
| Figure 6. | RDP levels . . . . . | 74 |
| Figure 7. | CRC calculation unit block diagram . . . . . | 99 |
| Figure 8. | STM32L010xx firewall connection schematics . . . . . | 106 |
| Figure 9. | Firewall functional states . . . . . | 110 |
| Figure 10. | Power supply overview . . . . . | 117 |
| Figure 11. | Performance versus VDD and VCORE range . . . . . | 120 |
| Figure 12. | Power supply supervisors . . . . . | 122 |
| Figure 13. | Power-on reset/power-down reset waveform . . . . . | 123 |
| Figure 14. | BOR thresholds . . . . . | 124 |
| Figure 15. | Simplified diagram of the reset circuit. . . . . | 145 |
| Figure 16. | Clock tree . . . . . | 148 |
| Figure 17. | Using TIM21 channel 1 input capture to measure frequencies . . . . . | 156 |
| Figure 18. | Basic structure of an I/O port bit . . . . . | 192 |
| Figure 19. | Basic structure of a 5-Volt tolerant I/O port bit . . . . . | 192 |
| Figure 20. | Input floating / pull up / pull down configurations . . . . . | 197 |
| Figure 21. | Output configuration . . . . . | 198 |
| Figure 22. | Alternate function configuration . . . . . | 198 |
| Figure 23. | High impedance-analog configuration . . . . . | 199 |
| Figure 24. | DMA request mapping . . . . . | 218 |
| Figure 25. | DMA block diagram . . . . . | 219 |
| Figure 26. | Extended interrupts and events controller (EXTI) block diagram . . . . . | 243 |
| Figure 27. | Extended interrupt/event GPIO mapping . . . . . | 245 |
| Figure 28. | ADC block diagram . . . . . | 254 |
| Figure 29. | ADC calibration . . . . . | 257 |
| Figure 30. | Calibration factor forcing . . . . . | 258 |
| Figure 31. | Enabling/disabling the ADC . . . . . | 259 |
| Figure 32. | ADC clock scheme . . . . . | 259 |
| Figure 33. | ADC connectivity . . . . . | 261 |
| Figure 34. | Analog to digital conversion time . . . . . | 265 |
| Figure 35. | ADC conversion timings . . . . . | 265 |
| Figure 36. | Stopping an ongoing conversion . . . . . | 266 |
| Figure 37. | Single conversions of a sequence, software trigger . . . . . | 269 |
| Figure 38. | Continuous conversion of a sequence, software trigger . . . . . | 269 |
| Figure 39. | Single conversions of a sequence, hardware trigger . . . . . | 270 |
| Figure 40. | Continuous conversions of a sequence, hardware trigger . . . . . | 270 |
| Figure 41. | Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . | 271 |
| Figure 42. | Example of overrun (OVR) . . . . . | 272 |
| Figure 43. | Wait mode conversion (continuous mode, software trigger). . . . . | 274 |
| Figure 44. | Behavior with WAIT = 0, AUTOFF = 1 . . . . . | 275 |
| Figure 45. | Behavior with WAIT = 1, AUTOFF = 1 . . . . . | 276 |
| Figure 46. | Analog watchdog guarded area . . . . . | 277 |
| Figure 47. | ADC_AWD1_OUT signal generation . . . . . | 278 |
| Figure 48. | ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . . | 279 |
| Figure 49. | ADC1_AWD_OUT signal generation (on a single channel) . . . . . | 279 |
| Figure 50. | Analog watchdog threshold update . . . . . | 280 |
| Figure 51. | 20-bit to 16-bit result truncation . . . . . | 281 |
| Figure 52. | Numerical example with 5-bits shift and rounding . . . . . | 281 |
| Figure 53. | Triggered oversampling mode (TOVS bit = 1) . . . . . | 283 |
| Figure 54. | VREFINT channel block diagram . . . . . | 283 |
| Figure 55. | General-purpose timer block diagram . . . . . | 303 |
| Figure 56. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 305 |
| Figure 57. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 305 |
| Figure 58. | Counter timing diagram, internal clock divided by 1 . . . . . | 306 |
| Figure 59. | Counter timing diagram, internal clock divided by 2 . . . . . | 307 |
| Figure 60. | Counter timing diagram, internal clock divided by 4 . . . . . | 307 |
| Figure 61. | Counter timing diagram, internal clock divided by N . . . . . | 308 |
| Figure 62. | Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 308 |
| Figure 63. | Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 309 |
| Figure 64. | Counter timing diagram, internal clock divided by 1 . . . . . | 310 |
| Figure 65. | Counter timing diagram, internal clock divided by 2 . . . . . | 310 |
| Figure 66. | Counter timing diagram, internal clock divided by 4 . . . . . | 311 |
| Figure 67. | Counter timing diagram, internal clock divided by N . . . . . | 311 |
| Figure 68. | Counter timing diagram, Update event when repetition counter is not used . . . . . | 312 |
| Figure 69. | Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . | 313 |
| Figure 70. | Counter timing diagram, internal clock divided by 2 . . . . . | 314 |
| Figure 71. | Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . | 314 |
| Figure 72. | Counter timing diagram, internal clock divided by N . . . . . | 315 |
| Figure 73. | Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . | 315 |
| Figure 74. | Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . | 316 |
| Figure 75. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 317 |
| Figure 76. | TI2 external clock connection example. . . . . | 317 |
| Figure 77. | Control circuit in external clock mode 1 . . . . . | 318 |
| Figure 78. | External trigger input block . . . . . | 319 |
| Figure 79. | Control circuit in external clock mode 2 . . . . . | 320 |
| Figure 80. | Capture/compare channel (example: channel 1 input stage) . . . . . | 321 |
| Figure 81. | Capture/compare channel 1 main circuit . . . . . | 321 |
| Figure 82. | Output stage of capture/compare channel (channel 1). . . . . | 322 |
| Figure 83. | PWM input mode timing . . . . . | 324 |
| Figure 84. | Output compare mode, toggle on OC1. . . . . | 326 |
| Figure 85. | Edge-aligned PWM waveforms (ARR=8). . . . . | 327 |
| Figure 86. | Center-aligned PWM waveforms (ARR=8). . . . . | 329 |
| Figure 87. | Example of one-pulse mode. . . . . | 330 |
| Figure 88. | Clearing TIMx_OCxREF . . . . . | 332 |
| Figure 89. | Example of counter operation in encoder interface mode . . . . . | 334 |
| Figure 90. | Example of encoder interface mode with TI1FP1 polarity inverted . . . . . | 334 |
| Figure 91. | Control circuit in reset mode . . . . . | 335 |
| Figure 92. | Control circuit in gated mode . . . . . | 336 |
| Figure 93. | Control circuit in trigger mode . . . . . | 337 |
| Figure 94. | Control circuit in external clock mode 2 + trigger mode . . . . . | 339 |
| Figure 95. | Master/Slave timer example . . . . . | 339 |
| Figure 96. | Gating timer y with OC1REF of timer x. . . . . | 341 |
| Figure 97. | Gating timer y with Enable of timer x . . . . . | 342 |
| Figure 98. | Triggering timer y with update of timer x. . . . . | 343 |
| Figure 99. | Triggering timer y with Enable of timer x | 343 |
| Figure 100. | Triggering timer x and y with timer x TI1 input | 344 |
| Figure 101. | General-purpose timer block diagram (TIM21/22) | 370 |
| Figure 102. | Counter timing diagram with prescaler division change from 1 to 2 | 372 |
| Figure 103. | Counter timing diagram with prescaler division change from 1 to 4 | 373 |
| Figure 104. | Counter timing diagram, internal clock divided by 1 | 374 |
| Figure 105. | Counter timing diagram, internal clock divided by 2 | 375 |
| Figure 106. | Counter timing diagram, internal clock divided by 4 | 375 |
| Figure 107. | Counter timing diagram, internal clock divided by N | 376 |
| Figure 108. | Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) | 376 |
| Figure 109. | Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) | 377 |
| Figure 110. | Counter timing diagram, internal clock divided by 1 | 378 |
| Figure 111. | Counter timing diagram, internal clock divided by 2 | 378 |
| Figure 112. | Counter timing diagram, internal clock divided by 4 | 379 |
| Figure 113. | Counter timing diagram, internal clock divided by N | 379 |
| Figure 114. | Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 | 381 |
| Figure 115. | Counter timing diagram, internal clock divided by 2 | 381 |
| Figure 116. | Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 | 382 |
| Figure 117. | Counter timing diagram, internal clock divided by N | 382 |
| Figure 118. | Counter timing diagram, Update event with ARPE=1 (counter underflow) | 383 |
| Figure 119. | Counter timing diagram, Update event with ARPE=1 (counter overflow) | 383 |
| Figure 120. | Control circuit in normal mode, internal clock divided by 1 | 384 |
| Figure 121. | TI2 external clock connection example | 385 |
| Figure 122. | Control circuit in external clock mode 1 | 386 |
| Figure 123. | External trigger input block | 386 |
| Figure 124. | Control circuit in external clock mode 2 | 387 |
| Figure 125. | Capture/compare channel (example: channel 1 input stage) | 388 |
| Figure 126. | Capture/compare channel 1 main circuit | 388 |
| Figure 127. | Output stage of capture/compare channel (channel 1 and 2) | 389 |
| Figure 128. | PWM input mode timing | 391 |
| Figure 129. | Output compare mode, toggle on OC1 | 393 |
| Figure 130. | Edge-aligned PWM waveforms (ARR=8) | 394 |
| Figure 131. | Center-aligned PWM waveforms (ARR=8) | 395 |
| Figure 132. | Clearing TIMx_OCxREF | 397 |
| Figure 133. | Example of one pulse mode | 398 |
| Figure 134. | Example of counter operation in encoder interface mode | 400 |
| Figure 135. | Example of encoder interface mode with TI1FP1 polarity inverted | 401 |
| Figure 136. | Control circuit in reset mode | 402 |
| Figure 137. | Control circuit in gated mode | 403 |
| Figure 138. | Control circuit in trigger mode | 404 |
| Figure 139. | Low-power timer block diagram | 425 |
| Figure 140. | Glitch filter timing diagram | 427 |
| Figure 141. | LPTIM output waveform, single counting mode configuration | 429 |
| Figure 142. | LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) | 429 |
| Figure 143. | LPTIM output waveform, Continuous counting mode configuration | 430 |
| Figure 144. | Waveform generation | 431 |
| Figure 145. | Encoder mode counting sequence | 434 |
| Figure 146. | Independent watchdog block diagram | 445 |
| Figure 147. | Watchdog block diagram | 455 |
| Figure 148. Window watchdog timing diagram ..... | 456 |
| Figure 149. RTC block diagram ..... | 462 |
| Figure 150. I2C1 block diagram ..... | 507 |
| Figure 151. I2C bus protocol ..... | 509 |
| Figure 152. Setup and hold timings ..... | 511 |
| Figure 153. I2C initialization flow ..... | 514 |
| Figure 154. Data reception ..... | 515 |
| Figure 155. Data transmission ..... | 516 |
| Figure 156. Slave initialization flow ..... | 519 |
| Figure 157. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 ..... | 521 |
| Figure 158. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 ..... | 522 |
| Figure 159. Transfer bus diagrams for I2C slave transmitter ..... | 523 |
| Figure 160. Transfer sequence flow for slave receiver with NOSTRETCH = 0 ..... | 524 |
| Figure 161. Transfer sequence flow for slave receiver with NOSTRETCH = 1 ..... | 525 |
| Figure 162. Transfer bus diagrams for I2C slave receiver ..... | 525 |
| Figure 163. Master clock generation ..... | 527 |
| Figure 164. Master initialization flow ..... | 529 |
| Figure 165. 10-bit address read access with HEAD10R = 0 ..... | 529 |
| Figure 166. 10-bit address read access with HEAD10R = 1 ..... | 530 |
| Figure 167. Transfer sequence flow for I2C master transmitter for N≤255 bytes ..... | 531 |
| Figure 168. Transfer sequence flow for I2C master transmitter for N>255 bytes ..... | 532 |
| Figure 169. Transfer bus diagrams for I2C master transmitter ..... | 533 |
| Figure 170. Transfer sequence flow for I2C master receiver for N≤255 bytes ..... | 535 |
| Figure 171. Transfer sequence flow for I2C master receiver for N >255 bytes ..... | 536 |
| Figure 172. Transfer bus diagrams for I2C master receiver ..... | 537 |
| Figure 173. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) ..... | 541 |
| Figure 174. Transfer sequence flow for SMBus slave transmitter N bytes + PEC ..... | 545 |
| Figure 175. Transfer bus diagrams for SMBus slave transmitter (SBC=1) ..... | 546 |
| Figure 176. Transfer sequence flow for SMBus slave receiver N Bytes + PEC ..... | 547 |
| Figure 177. Bus transfer diagrams for SMBus slave receiver (SBC=1) ..... | 548 |
| Figure 178. Bus transfer diagrams for SMBus master transmitter ..... | 549 |
| Figure 179. Bus transfer diagrams for SMBus master receiver ..... | 551 |
| Figure 180. USART block diagram ..... | 577 |
| Figure 181. Word length programming ..... | 579 |
| Figure 182. Configurable stop bits ..... | 581 |
| Figure 183. TC/TXE behavior when transmitting ..... | 582 |
| Figure 184. Start bit detection when oversampling by 16 or 8 ..... | 583 |
| Figure 185. Data sampling when oversampling by 16 ..... | 586 |
| Figure 186. Data sampling when oversampling by 8 ..... | 587 |
| Figure 187. Mute mode using Idle line detection ..... | 594 |
| Figure 188. Mute mode using address mark detection ..... | 595 |
| Figure 189. Break detection in LIN mode (11-bit break length - LBDL bit is set) ..... | 598 |
| Figure 190. Break detection in LIN mode vs. Framing error detection ..... | 599 |
| Figure 191. USART example of synchronous transmission ..... | 600 |
| Figure 192. USART data clock timing diagram (M bits = 00) ..... | 600 |
| Figure 193. USART data clock timing diagram (M bits = 01) ..... | 601 |
| Figure 194. RX data setup/hold time ..... | 601 |
| Figure 195. ISO 7816-3 asynchronous protocol ..... | 603 |
| Figure 196. Parity error detection using the 1.5 stop bits ..... | 604 |
| Figure 197. IrDA SIR ENDEC- block diagram ..... | 608 |
| Figure 198. IrDA data modulation (3/16) -Normal Mode ..... | 609 |
| Figure 199. Transmission using DMA ..... | 610 |
| Figure 200. Reception using DMA . . . . . | 611 |
| Figure 201. Hardware flow control between 2 USARTs . . . . . | 611 |
| Figure 202. RS232 RTS flow control . . . . . | 612 |
| Figure 203. RS232 CTS flow control . . . . . | 613 |
| Figure 204. USART interrupt mapping diagram . . . . . | 616 |
| Figure 205. LPUART block diagram . . . . . | 645 |
| Figure 206. Word length programming . . . . . | 647 |
| Figure 207. Configurable stop bits . . . . . | 648 |
| Figure 208. TC/TXE behavior when transmitting . . . . . | 650 |
| Figure 209. Mute mode using Idle line detection . . . . . | 657 |
| Figure 210. Mute mode using address mark detection . . . . . | 658 |
| Figure 211. Transmission using DMA . . . . . | 661 |
| Figure 212. Reception using DMA . . . . . | 662 |
| Figure 213. Hardware flow control between 2 LPUARTs . . . . . | 662 |
| Figure 214. RS232 RTS flow control . . . . . | 663 |
| Figure 215. RS232 CTS flow control . . . . . | 664 |
| Figure 216. LPUART interrupt mapping diagram . . . . . | 668 |
| Figure 217. SPI block diagram. . . . . | 686 |
| Figure 218. Full-duplex single master/ single slave application. . . . . | 687 |
| Figure 219. Half-duplex single master/ single slave application . . . . . | 688 |
| Figure 220. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . | 689 |
| Figure 221. Master and three independent slaves. . . . . | 690 |
| Figure 222. Multi-master application . . . . . | 691 |
| Figure 223. Hardware/software slave select management . . . . . | 692 |
| Figure 224. Data clock timing diagram . . . . . | 694 |
| Figure 225. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . . | 697 |
| Figure 226. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . . | 698 |
| Figure 227. Transmission using DMA . . . . . | 700 |
| Figure 228. Reception using DMA . . . . . | 701 |
| Figure 229. TI mode transfer . . . . . | 704 |
| Figure 230. Block diagram of STM32L010xx MCU and Cortex ® -M0+-level debug support . . . . . | 715 |
Chapters
- 1. Documentation conventions
- 2. System and memory overview
- 3. Flash program memory and data EEPROM (FLASH)
- 4. Cyclic redundancy check calculation unit (CRC)
- 5. Firewall (FW)
- 6. Power control (PWR)
- 7. Reset and clock control (RCC)
- 8. General-purpose I/Os (GPIO)
- 9. System configuration controller (SYSCFG)
- 10. Direct memory access controller (DMA)
- 11. Nested vectored interrupt controller (NVIC)
- 12. Extended interrupt and event controller (EXTI)
- 13. Analog-to-digital converter (ADC)
- 14. General-purpose timer (TIM2)
- 15. General-purpose timers (TIM21/22)
- 16. Low-power timer (LPTIM)
- 17. Independent watchdog (IWDG)
- 18. System window watchdog (WWDG)
- 19. Real-time clock (RTC)
- 20. Inter-integrated circuit (I2C) interface
- 21. Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 22. Low-power universal asynchronous receiver transmitter (LPUART)
- 23. Serial peripheral interface (SPI)
- 24. Debug support (DBG)
- 25. Device electronic signature
- Index