43. Revision history

• – Section Availability of peripherals
• – Figure Memory map
• – Table STM32G031xx and STM32G041xx memory boundary addresses (added)
• – Section Embedded SRAM
• – Section Boot configuration
• – Section FLASH functional description
• – Table Flash memory organization (title modified)
• – Section Power control (PWR) (indication of bits not available on STM32G031xx and STM32G041xx)
• – Figure Clock tree
• – Section Reset and clock control (RCC) (indication of bits not available on STM32G031xx and STM32G041xx) and Section Timer clock
• – Section System configuration controller (SYSCFG) (indication of bits not available on STM32G031xx and STM32G041xx)
• – Section SYSCFG configuration register 2 (SYSCFG_CFGR2) (clamping diode enable bits added)
• – Section Introduction
• – Table DMA implementation
• – Table DMAMUX instantiation
• – Section Interrupt and exception vectors
• – Section Extended interrupt and event controller (EXTI) (indication of bits not available on STM32G031xx and STM32G041xx)
• – Figure General-purpose timer block diagram and Figure External trigger input block
• – Section Infrared interface (IRTIM)
• – Table USART features
• – Table DEV_ID and REV_ID field values
• – Table DBG APB freeze register 2 (DBG_APB_FZ2)
• – Section Package data register

• – Empty check section
• – Section 3.3.8: FLASH main memory programming sequences
• – User and read protection option bytes section
• – Option byte loading (OBL) section
• – Table 20: Access status versus protection level and execution modes
• – Section 3.5.4: Securable memory area
• – Section 3.7.1: FLASH access control register (FLASH_ACR)
• – Section 3.7.8: FLASH option register (FLASH_OPTR) (BORR_LEV[1:0] swapped with BORF_LEV[1:0])
• – Section 3.7.9: FLASH PCROP area A start address register (FLASH_PCROP1ASR) to Section 3.7.14: FLASH PCROP area B end address register (FLASH_PCROP1BER) : reset values
• – Section 7.3: GPIO functional description : introductory information modified
• – Section 7.3.16: USB PD / Dead battery support : description filled
• – Table 51: Programmable data width and endian behavior (when PINC = MINC = 1) : NDT in the first row corrected from 8 to 4
• – Table 55: DMAMUX: assignment of multiplexer inputs to resources : TIM16/17_TRG_COM corrected to TIM16/17_COM
• – Section 15.2: ADC main features : V _TS corrected to V _SENSE
• – Section 15.3.1: ADC pins and internal signals : tables and their organization ( External triggers table brought to this section)
• – Table 74: Latency between trigger and start of conversion : latency values
• – Section : Calculating the actual V _REF+ voltage using the internal reference voltage - corrected from V _DDA to V _REF+
• – Section 20: AES hardware accelerator (AES) : general update
• – Section 21: Advanced-control timer (TIM1) : general update
• – Figure 187: Capture/Compare channel 1 main circuit and Figure 188: Output stage of Capture/Compare channel (channel 1) updated
• – Figure 205: Master/slave connection example with 1 channel only timers added
• – Table 124: Output control bit for standard OCx channels updated
• – Section 22.4.29: TIM3 timer input selection register (TIM3_TISEL) : removed TI4SEL[3:0] and TI3SEL[3:0]
• – Figure 221: General-purpose timer block diagram (TIM14) : updated
• – Figure 232: Capture/compare channel 1 main circuit and Figure 233: Output stage of capture/compare channel (channel 1) updated
• – Section 24.3.11: Using timer output as trigger for other timers (TIM14) added
• – Figure 251: Capture/compare channel 1 main circuit updated
• – Section 25.4.24: Using timer output as trigger for other timers (TIM16/TIM17) added
• – Former Section 28.3.4 Advanced watchdog interrupt feature moved to Section 29.4: WWDG interrupts
• – Section 32.4.2: I2C pins and internal signals added
• – Section 32.9.3: I2C own address 1 register (I2C_OAR1) and Section 32.9.8: I2C interrupt clear register (I2C_ICR) updated

• – Section 33.4: USART implementation updated - tables reorganized
• – Section 34.3: LPUART implementation updated - tables reorganized
• – Section 38: USB Type-C ^® /USB Power Delivery interface (UCPD) : general update
• – former DAC trigger connection table renamed as Table 85: DAC interconnection and moved to Section 16.4.2: DAC pins and internal signals
• – Table 265: DEV_ID and REV_ID field values
• – Section 40.10.2: DBG configuration register (DBG_CR)

• – Section 1.1: General information
• – Section 1.4: Availability of peripherals
• – Section 2: Memory and bus architecture
• – Section 3: Embedded flash memory (FLASH)
• – Section 4: Power control (PWR)
• – Section 5: Reset and clock control (RCC)
• – Section 8: System configuration controller (SYSCFG)
• – Section 9: Interconnect matrix
• – Section 10: Direct memory access controller (DMA)
• – Section 11: DMA request multiplexer (DMAMUX)
• – Section 12: Nested vectored interrupt controller (NVIC)
• – Section 13: Extended interrupt and event controller (EXTI)
• – Section 15: Analog-to-digital converter (ADC)
• – Section 18: Comparator (COMP)
• – Section 20: AES hardware accelerator (AES)
• – Section 21: Advanced-control timer (TIM1)
• – Section 22: General-purpose timers (TIM2/TIM3/TIM4)
• – Section 24: General-purpose timers (TIM14)
• – Section 25: General-purpose timers (TIM15/TIM16/TIM17)
• – Section 26: Low-power timer (LPTIM)
• – Section 32: Inter-integrated circuit interface (I2C)
• – Section 33: Universal synchronous receiver transmitter (USART)
• – Section 34: Low-power universal asynchronous receiver transmitter (LPUART)
• – Table 31Section 31: Tamper and backup registers (TAMP)
• – Section 35: Serial peripheral interface / integrated interchip sound (SPI/I2S)
• – Section 37: Universal serial bus full-speed host/device interface (USB)
• – Section 36: FD controller area network (FDCAN)
• – Section 41: Device electronic signature

Added errata sheet in the list of reference documents as well as the mention that patents apply to the microcontrollers on document cover page.

Updated DMAMUX register block size in Table 6: STM32G0x1 peripheral register boundary addresses .

Updated parity check in Section 2.3: Embedded SRAM .

Added caution note related to BOOT0 pin in Section 2.5: Boot configuration .

Updated Section 2.5.4: Empty check .

Section 3: Embedded flash memory (FLASH)

Updated main memory block description in Section 3.3.1: FLASH organization .

Modified page numbers corresponding to Bank 2 in Table 10: Flash memory organization for 256 KB dual-bank devices and Table 11: Flash memory organization for 512 KB devices .

Updated Section 3.3.3: FLASH error code correction (ECC) .

Updated conditions in which PGAERR and WRPERR errors can occur in Section : Programming errors .

Updated Section : Modifying user options .

Updated memory areas protected by RDP in Section 3.5.1: FLASH read protection (RDP) .

Updated PNB[9:0] bitfield description of FLASH control register (FLASH_CR) .

Updated SEC_SIZE[7:0] description of FLASH security register (FLASH_SECR) .

Section 4: Power control (PWR)

Replaced “power voltage detector” by “programmable voltage detector” in PVDRT, PVDFT and PVDE bit descriptions of Power control register 2 (PWR_CR2) and PVDO of Power status register 2 (PWR_SR2) .

Section 6: Clock recovery system (CRS)

Updated CRS control register (CRS_CR) .

Section 5: Reset and clock control (RCC)

Updated Section 5.1.2: System reset to indicate the a system reset sets all registers to their reset value unless otherwise specified.

Modified Section : External source (HSE bypass) .

Section 12: Nested vectored interrupt controller (NVIC)

Updated Section 12.2: SysTick calibration value register .

Section 14: Cyclic redundancy check calculation unit (CRC)

Updated Figure 30: CRC calculation unit block diagram .

Added note in Section : Polynomial programmability to clarify what are even and odd polynomials.

Added CRC register access granularity in Section 14.2: CRC main features and Section 14.4: CRC registers .

Section 15: Analog-to-digital converter (ADC)
Removed ADC supply requirements from Section 15.2: ADC main features
Table 71: ADC input/output pins : removed “ \( V_{DDA} \geq V_{DD} \) ” from \( V_{DDA} \) description as well as the recommendation to connect \( V_{SSA} \) to \( V_{SS} \) .
Removed JOFFSETx and JOFFSETx_CH from Figure 31: ADC block diagram since offset control is not available.
Updated software calibration procedure in Section 15.3.3: Calibration (ADCAL) .
Updated note related to ADSTART clearing in Section 15.3.12: Starting conversions (ADSTART) .
Updated formula to calculate the temperature in Section : Reading the temperature .
Changed value of converted digital value to \( V_{BAT}/3 \) and updated Figure 58: VBAT channel block diagram in Section 15.10: Battery voltage monitoring .

Section 16: Digital-to-analog converter (DAC)
Added VREF+ pin availability in Table 82: DAC features

Section 20: AES hardware accelerator (AES)
Corrected IVI[127:0] bitfield split among AES_IVRx registers ( Table 107: CTR mode initialization vector definition ).
Corrected Table 109: Initialization of AES_IVRx registers in GCM mode and Table 110: Initialization of AES_IVRx registers in CCM mode .
Updated text relative to the CCF flag in section DMA operation in different operating modes .

Section 21: Advanced-control timer (TIM1)
Updated Figure 124: Control circuit in normal mode, internal clock divided by 1 .
Added Note in Section 21.3.16: Using the break function .
Updated OC1PE in Section 21.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) .

Section 24: General-purpose timers (TIM14)
Updated OC1PE in TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) .

Section 25: General-purpose timers (TIM15/TIM16/TIM17)
Updated Figure 247: Control circuit in normal mode, internal clock divided by 1 .
Added Note in Section 25.4.13: Using the break function .
Added Section 25.4.15: 6-step PWM generation .
Suppressed CC2DE in TIM15 DMA/interrupt enable register (TIM15_DIER) .
Updated TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) .
Updated TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .

Section 26: Low-power timer (LPTIM)
Updated Section 26.2: LPTIM main features .
Added note to Section 26.4.7: Trigger multiplexer .
Updated Section 26.4.4: LPTIM reset and clocks .
Updated Section 26.4.15: Encoder mode .
Updated LPTIM interrupt and status register (LPTIM_ISR) , LPTIM interrupt clear register (LPTIM_ICR) , LPTIM configuration register (LPTIM_CFGR)

Section 30: Real-time clock (RTC)
Updated Section 30.3.13: RTC smooth digital calibration .
Updated RTC initialization control and status register (RTC_ICSR) and RTC status clear register (RTC_SCR) .

Section 32: Inter-integrated circuit interface (I2C)
Updated Figure 284: Block diagram and Figure 296: Transfer bus diagrams for I2C target receiver (mandatory events only) .

Section 33: Universal synchronous receiver transmitter (USART)
In the whole document renamed SCLK pin into CK, and replaced nCTS and nRTS by CTS and RT, respectively.
Removed mention that usart_wkup interrupt is not mandatory when wake-up event is detected from Section 33.5.21: USART low-power management .
Updated ADD[7:0] bitfield descriptions in USART control register 2 (USART_CR2) .

Section 34: Low-power universal asynchronous receiver transmitter (LPUART)
In the whole document renamed SCLK pin into CK, and replaced nCTS and nRTS by CTS and RT, respectively.
Updated Table 198: Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz .
Removed mention that lpuart_wkup interrupt is not mandatory when wake-up event is detected from Section 34.4.14: LPUART low-power management .
Updated ADD[7:0] bitfield descriptions in LPUART control register 2 (LPUART_CR2) .

Section 35: Serial peripheral interface / integrated interchip sound (SPI/I2S)
Updated Section : Communication using DMA (direct memory addressing) .
Updated Table 207: Audio-frequency precision using 48 MHz clock derived from HSE title.

Section 36: FD controller area network (FDCAN)
Updated Figure 392: CAN subsystem . and Section 36.3.6: Message RAM .

Section 37: Universal serial bus full-speed host/device interface (USB)
Updated Table 228: Bulk double-buffering memory buffers usage (Device mode) , Table 229: Bulk double-buffering memory buffers usage (Host mode) and Table 230: Isochronous memory buffers usage
Updated USB endpoint/channel n register (USB_CHEPnR) .

Section 38: USB Type-C ^® /USB Power Delivery interface (UCPD)
Added table footnote added in Table 249: Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) .
Removed UCPD_CFGR3 register.
Removed CC1VCONNEN and CC2VCONNEN bits from UCPD control register (UCPD_CR) .