18. Comparator (COMP)

18.1 Introduction

The devices embed COMP1, COMP2, and COMP3 (the last on STM32G0B1xx and STM32G0C1xx only) ultra-low-power comparators.

The comparators can be used for a variety of functions including:

• Wake-up from low-power mode triggered by an analog signal,
• Analog signal conditioning,
• Cycle-by-cycle current control loop when combined with a PWM output from a timer.

18.2 COMP main features

• Each comparator has configurable plus and minus inputs used for flexible voltage selection:
- – Multiplexed I/O pins
- – DAC Channel1 and Channel2
- – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider)
• Programmable hysteresis
• Programmable speed / consumption
• The outputs can be redirected to an I/O or to timer inputs for triggering:
- – Break events for fast PWM shutdowns
• Comparator outputs with blanking source
• The two comparators can be combined in a window comparator
• Each comparator has interrupt generation capability with wake-up from Sleep and Stop modes (through the EXTI controller)

18.3 COMP functional description

18.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 68 .

Figure 68. Comparator block diagram

Figure 68. Comparator block diagram. The diagram shows a comparator (COMPx) with its non-inverting input (COMPx_INP) and inverting input (COMPx_INM). The non-inverting input is selected from COMPx_INP I/Os or COMPx_INP via a multiplexer controlled by COMPx_INPSEL. The inverting input is selected from a multiplexer controlled by COMPx_INMSEL, which includes inputs from COMPx_INM I/Os, DAC_CH1, DAC_CH2, VREFINT, 3/4 VREFINT, 1/2 VREFINT, and 1/4 VREFINT. The comparator output is connected to a multiplexer controlled by COMPx_POLARITY. This output is also connected to a logic block consisting of an AND gate (inputs: Blank source, COMPx_VALUE) and an OR gate (inputs: COMPx_VALUE, COMPx_WINOUT). The output of the OR gate is connected to COMPx_OUT, which can be connected to a GPIO alternate function, a Wakeup EXTI line interrupt, or TIMERS. The diagram is labeled MSv42190V1.

18.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.

The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet.

The output can also be internally redirected to a variety of timer input for the following purposes:

• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures

It is possible to have the comparator output simultaneously redirected internally and externally.

Table 93. COMP1 non-inverting input assignment

COMP1_INP	COMP1_INPSEL[1:0]
PC5	00
PB2	01
PA1	10
Open	11

Table 94. COMP1 inverting input assignment

COMP1_INM	COMP1_INMSEL[3:0]
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011
DAC Channel1	0100
DAC Channel2	0101
PB1	0110
PC4	0111
PA0	1000
$\frac{1}{4} V_{REFINT}$	> 1000

Table 95. COMP2 non-inverting input assignment

COMP2_INP	COMP2_INPSEL[1:0]
PB4	00
PB6	01
PA3	10
Open	11

Table 96. COMP2 inverting input assignment

COMP2_INM	COMP2_INMSEL[3:0]
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011
DAC Channel1	0100
DAC Channel2	0101
PB3	0110
PB7	0111
PA2	1000
$\frac{1}{4} V_{REFINT}$	> 1000

Table 97. COMP3 non-inverting input assignment

COMP3_INP	COMP3_INPSEL[1:0]
PB0	00
PC1	01
PE7	10
Open	11

Table 98. COMP3 inverting input assignment

COMP3_INM	COMP3_INMSEL[3:0]
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011
DAC Channel1	0100
DAC Channel2	0101
PB2	0110
PC0	0111
PE8	1000
$\frac{1}{4} V_{REFINT}$	> 1000

18.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the APB2 clock.

There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG.

Important: The polarity selection logic and the output redirection to the port works independently from the APB2 clock. This allows the comparator to work even in Stop mode.

18.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption.

For this purpose, the comparator control and status registers can be write-protected (read-only).

Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPx LOCK bit.

The write protection can only be reset by a MCU reset.

18.3.5 Window comparator

The purpose of window comparator is to monitor the analog voltage if it is within specified voltage range defined by lower and upper threshold.

COMP1 and COMP2 or COMP2 and COMP3 can combine to create a window comparator. The monitored analog voltage is connected to the non-inverting (plus) inputs of comparators connected together and the upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators. Two non-inverting inputs can be connected internally together by enabling WINMODE bit to save one IO for other purposes.

Figure 69. Window mode

Circuit diagram of a window comparator mode. It shows two comparators, COMPx and COMPy. COMPx has WINMODE = 0 and its non-inverting input (COMPx_INP) is connected to the main Input. Its inverting input (COMPx_INM) is connected to the Upper threshold. The output of COMPx (COMPx_VALUE) is connected to one input of an OR gate. COMPy has WINMODE = 1 and its non-inverting input (COMPy_INP) is connected to the main Input. Its inverting input (COMPy_INM) is connected to the Lower threshold. The output of COMPy (COMPy_VALUE) is connected to the other input of the OR gate. The output of the OR gate is COMPx_OUT. Labels indicate COMPx WINOUT = 1 and COMPy WINOUT = 0. The diagram is labeled MSv42191V1.

18.3.6 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.

Figure 70. Comparator hysteresis

Graph illustrating comparator hysteresis. The top graph shows the non-inverting input (INP) as a sinusoidal-like waveform. The inverting input (INM) is a constant reference voltage. Two dashed horizontal lines represent the threshold levels: INM + V_hyst (upper) and INM - V_hyst (lower). The bottom graph shows the output (COMP_OUT) as a digital signal. The output transitions from low to high when INP crosses the upper threshold and from high to low when INP crosses the lower threshold, demonstrating hysteresis. The diagram is labeled MS19984V1.

18.3.7 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It consists of a selection of a blanking window which is a timer output compare signal. The selection is done by software (refer to the comparator register description for possible blanking signals). Then, the complementary of the blanking signal is ANDed with the comparator output to provide the wanted comparator output. See the example provided in the figure below.

Figure 71. Comparator output blanking

The figure contains a timing diagram with the following signals from top to bottom: PWM (square wave), Current (sawtooth wave with sharp spikes at the rising edge of PWM), Raw comp output (pulses whenever Current exceeds Current limit), Blanking window (pulses aligned with the Current spikes), and Final comp output (Raw comp output pulses minus those occurring during the Blanking window). Below the waveforms is a logic diagram showing an AND gate. One input is 'Comp out', and the other is 'Blank' which passes through an inversion bubble before entering the AND gate. The output is labeled 'Comp out (to TIM_BK ...)'.

Timing diagram and logic gate for comparator output blanking.

18.3.8 COMP power and speed modes

COMPx power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.

The PWRMODE[1:0] bitfields of the COMPx_CSR registers allow setting the comparators to high speed with full power or medium speed with medium power. Refer to Section 18.6: COMP registers .

18.4 COMP low-power modes

Table 99. Comparator behavior in the low power modes

Mode	Description
Sleep	No effect on the comparators. Comparator interrupts cause the device to exit the Sleep mode.
Low-power run	No effect.
Low-power sleep	No effect. COMP interrupts cause the device to exit the Low-power sleep mode.
Stop 0	No effect on the comparators.
Stop 1	Comparator interrupts cause the device to exit the Stop mode.
Standby	The COMP registers are powered down and must be reinitialized after exiting Standby or Shutdown mode.
Shutdown

18.5 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes.

Refer to Interrupt and events section for more details.

To enable COMPx interrupt, it is required to follow this sequence:

1. Configure and enable the EXTI line corresponding to the COMPx output event in interrupt mode and select the rising, falling or both edges sensitivity
2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines
3. Enable COMPx.

Table 100. Interrupt control bits

Interrupt event	Enable control bit	Exit from Sleep mode	Exit from Stop modes	Exit from Standby mode
COMP1 output	Through EXTI	Yes	Yes	N/A
COMP2 output	Through EXTI	Yes	Yes	N/A
COMP3 output	Through EXTI	Yes	Yes	N/A

18.6 COMP registers

18.6.1 Comparator 1 control and status register (COMP1_CSR)

Address offset: 0x00

System reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE [1:0]		HYST[1:0]
rw	r						rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]	INMSEL[3:0]				Res.	Res.	Res.	EN
rw	rw			rw		rw	rw	rw	rw	rw	rw				rw

Bit 31 LOCK : COMP1_CSR register lock

This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only.

0: Not locked

1: Locked

Bit 30 VALUE : Comparator 1 output status

This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in Figure 68 .

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : Comparator 1 blanking source selector

This bitfield is controlled by software (if not locked). It selects the blanking source:
00000: None (no blanking)

xxxx1: TIM1 OC4

xx11x: TIM1 OC5

xx1xx: TIM2 OC3

x1xxx: TIM3 OC3

1xxxx: TIM15 OC2

Bits 19:18 PWRMODE[1:0] : Comparator 1 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1:

00: High speed

01: Medium speed

others: Reserved

Bits 17:16 HYST[1:0] : Comparator 1 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1:

00: None

01: Low

10: Medium

11: High

Bit 15 POLARITY : Comparator 1 polarity selector

This bit is controlled by software (if not locked). It selects the comparator 1 output polarity:

0: Non-inverted

1: Inverted

Bit 14 WINOUT : Comparator 1 output selector

This bit is controlled by software (if not locked). It selects the comparator 1 output:

0: COMP1_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 69 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : Comparator 1 non-inverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of the comparator 1:

0: Signal selected with INPSEL[1:0] bitfield of this register

1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure 69 )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : Comparator 1 signal selector for non-inverting input

This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP1_INP of the comparator 1 (also see the WINMODE bit):

00: PC5

01: PB2

10: PA1

11: None (open)

Bits 7:4 INMSEL[3:0] : Comparator 1 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP1_INM of the comparator 1:

0000: 1/4 V _REFINT

0001: 1/2 V _REFINT

0010: 3/4 V _REFINT

0011: V _REFINT

0100: DAC channel 1

0101: DAC channel 2

0110: PB1

0111: PC4

1000: PA0

Other: 1/4 V _REFINT

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : Comparator 1 enable bit

This bit is controlled by software (if not locked). It enables the comparator 1:

0: Disable

1: Enable

18.6.2 Comparator 2 control and status register (COMP2_CSR)

Address offset: 0x04

System reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE [1:0]	HYST[1:0]
rw	r						rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]	INMSEL[3:0]				Res.	Res.	Res.	EN
rw	rw			rw		rw	rw	rw	rw	rw	rw			rw

Bit 31 LOCK : COMP2_CSR register lock

This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only.

0: Not locked

1: Locked

Bit 30 VALUE : Comparator 2 output status

This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in Figure 68 .

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : Comparator 2 blanking source selector

This bitfield is controlled by software (if not locked). It selects the blanking source:

00000: None (no blanking)

xxxx1: TIM1 OC4

xx11x: TIM1 OC5

xx1xx: TIM2 OC3

x1xxx: TIM3 OC3

1xxxx: TIM15 OC2

Bits 19:18 PWRMODE[1:0] : Comparator 2 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2:

00: High speed

01: Medium speed

others: Reserved

Bits 17:16 HYST[1:0] : Comparator 2 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2:

00: None

01: Low

10: Medium

11: High

Bit 15 POLARITY : Comparator 2 polarity selector

This bit is controlled by software (if not locked). It selects the comparator 2 output polarity:

0: Non-inverted

1: Inverted

Bit 14 WINOUT : Comparator 2 output selector

This bit is controlled by software (if not locked). It selects the comparator 2 output:

0: COMP2_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 69 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : Comparator 2 non-inverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for COMP2_INP input of the comparator 2:

0: Signal selected with INPSEL[1:0] bitfield of this register

1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 69 )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : Comparator 2 signal selector for non-inverting input

This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP2_INP of the comparator 2 (also see the WINMODE bit):

00: PB4
01: PB6
10: PA3
11: None (open)

Bits 7:4 INMSEL[3:0] : Comparator 2 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP2_INM of the comparator 2:

0000: 1/4 V _REFINT
0001: 1/2 V _REFINT
0010: 3/4 V _REFINT
0011: V _REFINT
0100: DAC channel 1
0101: DAC channel 2
0110: PB3
0111: PB7
1000: PA2
Other: 1/4 V _REFINT

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : Comparator 2 enable bit

This bit is controlled by software (if not locked). It enables the comparator 2:

0: Disable
1: Enable

18.6.3 Comparator 3 control and status register (COMP3_CSR)

Address offset: 0x08

System reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE [1:0]		HYST[1:0]
rw	r						rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]	INMSEL[3:0]					Res.	Res.	Res.	EN
rw	rw			rw		rw	rw	rw	rw	rw	rw				rw

Bit 31 LOCK : COMP3_CSR register lock

This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only.

0: Not locked
1: Locked

Bit 30 VALUE : Comparator 3 output status

This bit is read-only. It reflects the level of the comparator 3 output after the polarity selector and blanking, as indicated in Figure 68.

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : Comparator 3 blanking source selector

This bitfield is controlled by software (if not locked). It selects the blanking source:

00000: None (no blanking)

xxx1: TIM1 OC4

xx1x: TIM1 OC5

xx1xx: TIM2 OC3

x1xxx: TIM3 OC3

1xxxx: TIM15 OC2

Bits 19:18 PWRMODE[1:0] : Comparator 3 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 3:

00: High speed

01: Medium speed

others: Reserved

Bits 17:16 HYST[1:0] : Comparator 3 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 3:

00: None

01: Low

10: Medium

11: High

Bit 15 POLARITY : Comparator 3 polarity selector

This bit is controlled by software (if not locked). It selects the comparator 3 output polarity:

0: Non-inverted

1: Inverted

Bit 14 WINOUT : Comparator 3 output selector

This bit is controlled by software (if not locked). It selects the comparator 3 output:

0: COMP3_VALUE

1: COMP2_VALUE XOR COMP3_VALUE (required for window mode, see Figure 69 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : Comparator 3 non-inverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for COMP3_INP input of the comparator 3:

0: Signal selected with INPSEL[1:0] bitfield of this register

1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure 69 )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : Comparator 3 signal selector for non-inverting input

This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP3_INP of the comparator 3 (also see the WINMODE bit):

00: PB0

01: PC1

10: PE7

11: None (open)

Bits 7:4 INMSEL[3:0] : Comparator 3 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP3_INM of the comparator 3:

0000: 1/4 V _REFINT

0001: 1/2 V _REFINT

0010: 3/4 V _REFINT

0011: V _REFINT

0100: DAC channel 1

0101: DAC channel 2

0110: PB2

0111: PC0

1000: PE8

Other: 1/4 V _REFINT

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : Comparator 3 enable bit

This bit is controlled by software (if not locked). It enables the comparator 3:

0: Disable

1: Enable

18.6.4 COMP register map

The following table summarizes the comparator registers.

The comparator registers share SYSCFG peripheral register base addresses.

Table 101. COMP register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	COMP1_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST	POL	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]		INMSEL[3:0]				Res.	Res.	Res.	EN
0x00	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0		0		0	0	0	0	0	0	0				0
0x04	COMP2_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST	POL	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]		INMSEL[3:0]				Res.	Res.	Res.	EN
0x04	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0		0		0	0	0	0	0	0	0				0
0x08	COMP3_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST	POL	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]		INMSEL[3:0]				Res.	Res.	Res.	EN
0x08	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0		0		0	0	0	0	0	0	0				0

Refer to Section 2.2 on page 60 for the register boundary addresses.