13. Extended interrupt and event controller (EXTI)

The Extended interrupt and event controller (EXTI) manages the CPU and system wake-up through configurable and direct event inputs (lines). It provides wake-up requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can also be used in Run modes.

The EXTI also includes the EXTI I/O port mux.

13.1 EXTI main features

The EXTI main features are the following:

• • System wake-up upon event on any input
• • Wake-up flag and CPU interrupt generation for events not having a wake-up flag in their source peripheral
• • Configurable events (from I/Os, peripherals not having an associated interrupt pending status bit, or peripherals generating a pulse)
  • – Selectable active trigger edge
  • – Independent rising and falling edge interrupt pending status bits
  • – Individual interrupt and event generation mask, used for conditioning the CPU wake-up, interrupt and event generation
  • – SW trigger possibility
• • Direct events (from peripherals having an associated flag and interrupt pending status bit)
  • – Fixed rising edge active trigger
  • – No interrupt pending status bit in the EXTI
  • – Individual interrupt and event generation mask for conditioning the CPU wake-up and event generation
  • – No SW trigger possibility
• • I/O port selector

13.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger block, the masking block, and EXTI mux as shown in Figure 26 .

The register block contains all the EXTI registers.

The event input trigger block provides an event input edge trigger logic.

The masking block provides the event input distribution to the different wake-up, interrupt and event outputs, and the masking of these.

The EXTI mux provides the I/O port selection on to the EXTI event signal.

Figure 26. EXTI block diagram

Table 62. EXTI signal overview

Table 63. EVG pin overview

13.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wake-up or interrupt events when the system is in Stop mode are connected to the EXTI.

• • Peripheral wake-up signals that generate a pulse or that do not have an interrupt status bits in the peripheral, are connected to an EXTI configurable line. For these events the EXTI provides a status pending bit which requires to be cleared. It is the EXTI interrupt associated with the status bit that interrupts the CPU.
• • Peripheral interrupt and wake-up signals that have a status bit in the peripheral which requires to be cleared in the peripheral, are connected to an EXTI direct line. There is no status pending bit within the EXTI. The interrupt or wake-up is cleared by the CPU in the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
• • All GPIO ports input to the EXTI multiplexer, allowing to select a port to wake up the system via a configurable event.

The EXTI configurable event interrupts are connected to the NVIC(a) of the CPU.

The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.

The EXTI CPU wake-up signals are connected to the PWR block, and are used to wake up the system and CPU sub-system bus clocks.

13.3 EXTI functional description

Depending on the EXTI line type and wake-up target(s), different logic implementations are used. The applicable features and control or status registers are:

• • rising and falling edge event enable through
  • – EXTI rising trigger selection register (EXTI_RTSR1)
  • – EXTI falling trigger selection register 1 (EXTI_FTSR1)
• • software trigger through EXTI software interrupt event register 1 (EXTI_SWIER1)
• • pending interrupt flagging through
  • – EXTI rising edge pending register 1 (EXTI_RPR1)
  • – EXTI falling edge pending register 1 (EXTI_FPR1)
  • – EXTI external interrupt selection register (EXTI_EXTICRx)
• • CPU wake-up and interrupt enable through
  • – EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)
  • – EXTI CPU wake-up with interrupt mask register (EXTI_IMR2)
• • CPU wake-up and event enable through
  • – EXTI CPU wake-up with event mask register (EXTI_EM1)
  • – EXTI CPU wake-up with event mask register (EXTI_EM2)

Table 64. EXTI event input configurations and register control

13.3.1 EXTI configurable event input wake-up

Figure 27 is a detailed representation of the logic associated with configurable event inputs which wake up the CPU sub-system bus clocks and generated an EXTI pending flag and interrupt to the CPU and or a CPU wake-up event.

Figure 27. Configurable event trigger logic CPU wake-up

The software interrupt event register allows triggering configurable events by software, writing the corresponding register bit, irrespective of the edge selection setting.

The rising edge and falling edge selection registers allow to enable and select the configurable event active trigger edge or both edges.

The CPU has its dedicated interrupt mask register and a dedicated event mask registers. The enabled event allows generating an event on the CPU. All events for a CPU are OR-ed together into a single CPU event signal. The event pending registers (EXTI_RPR1 and EXTI_FPR1) is not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers, shared by the CPU. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to the CPU. The configurable event interrupts need to be acknowledged by software in the EXTI_RPR1 and/or EXTI_FPR1 registers.

When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees the wake-up of the EXTI hclk clock before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request can be cleared by the CPU. The system cannot enter low-power modes as long as an interrupt pending request is active.

13.3.2 EXTI direct event input wake-up

Figure 28 is a detailed representation of the logic associated with direct event inputs waking up the system.

The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the system and CPU sub-system clocks and may generate a CPU wake-up event. The peripheral synchronous interrupt, associated with the direct wake-up event wakes up the CPU.

The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU. The CPU event may occur before the interrupt flag of the associated peripheral is set.

Figure 28. Direct event trigger logic CPU wake-up

13.3.3 EXTI mux

The EXTI mux allows selecting GPIOs as interrupts and wake-up. The GPIOs are connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The selection of GPIO port as EXTI mux output is controlled through the EXTI external interrupt selection register (EXTI_EXTICRx) register.

Figure 29. EXTI GPIO mux

The EXTI mux outputs are available as output signals from the EXTI, to trigger other functional blocks. The EXTI mux outputs are available independently of mask setting through the EXTI_IMR and EXTI_EMR registers.

The EXTI lines (event inputs) are connected as shown in the following table.

Table 65. EXTI line connections

Table 65. EXTI line connections (continued)

13.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wake-up event. The configurable events are enabled by enabling at least one of the trigger edges.

Once an event input is enabled, the generation of a CPU wake-up is conditioned by the CPU interrupt mask and CPU event mask.

Table 66. Masking functionality

1. 1. The single exti(n) interrupt goes to the CPU. If no interrupt is required for CPU, the exti(n) interrupt must be masked in the CPU NVIC.
2. 2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.

For configurable event inputs, upon an edge on the event input, an event request is generated if that edge (rising or/and falling) is enabled. When the associated CPU interrupt is unmasked, the corresponding RPIFn and/or FPIFn bit is/are set in the EXTI_RPR or/and EXTI_FPR register, waking up the CPU subsystem and activating CPU interrupt signal. The RPIFn and/or FPIFn pending bit is cleared by writing 1 to it, which clears the CPU interrupt request.

For direct event inputs, when enabled in the associated peripheral, an event request is generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI. When the associated CPU interrupt is unmasked, the corresponding CPU subsystem is woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.

The CPU event must be unmasked to generate an event. Upon an enabled edge occurring on an event input, a CPU event pulse is generated. There is no event pending bit.

For the configurable event inputs, the software can generate an event request by setting the corresponding bit of the software interrupt/event register EXTI_SWIER1, which has the effect of a rising edge on the event input. The pending rising edge event flag is set in the EXTI_RPR1 register, irrespective of the EXTI_RTSR1 register setting.

13.5 EXTI registers

The EXTI register map is divided in the following sections:

Table 67. EXTI register map sections

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

13.5.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 RT20 : Rising trigger event configuration bit of configurable line 20 ⁽¹⁾

This bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.

0: Disable

1: Enable

The RT20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 RTx : Rising trigger event configuration bit of configurable line x (x = 18 to 0) ⁽¹⁾

Each bit enables/disables the rising edge trigger for the event and interrupt on the corresponding line.

0: Disable

1: Enable

The RT18 and RT17 bits are reserved in STM32G031xx and STM32G041xx.

1. 1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
   If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
   Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger.

13.5.2 EXTI falling trigger selection register 1 (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 FT20 : Falling trigger event configuration bit of configurable line 20 ⁽¹⁾ .

This bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0: Disable
1: Enable
The FT20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 FTx : Falling trigger event configuration bit of configurable line x (x = 18 to 0) ⁽¹⁾ .

Each bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.
0: Disable
1: Enable
The FT18 and FT17 bits are reserved in STM32G031xx and STM32G041xx.

1. 1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
   Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger.

13.5.3 EXTI software interrupt event register 1 (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 SWI20 : Software rising edge event trigger on line 20.

Setting this bit by software triggers a rising edge event on the corresponding line, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. This bit is automatically cleared by hardware. Reading this bit always returns 0.

0: No effect

1: Rising edge event generated on the corresponding line, followed by an interrupt

The SWI20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 SWIx : Software rising edge event trigger on line x (x = 18 to 0)

Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. These bits are automatically cleared by HW. Reading of any bit always returns 0.

0: No effect

1: Rising edge event generated on the corresponding line, followed by an interrupt

The SWI18 and SWI17 bits are reserved in STM32G031xx and STM32G041xx.

13.5.4 EXTI rising edge pending register 1 (EXTI_RPR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 RPIF20 : Rising edge event pending for configurable line 20.

This bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. This bit is cleared by writing 1 into it.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

The RPIF20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 RPIFx : Rising edge event pending for configurable line x (x = 18 to 0)

Each bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

The RPIF18 and RPIF17 bits are reserved in STM32G031xx and STM32G041xx.

13.5.5 EXTI falling edge pending register 1 (EXTI_FPR1)

Address offset: 0x010

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 FPIF20 : Falling edge event pending for configurable line 20.

This bit is set upon a falling edge event generated by hardware on the corresponding line.
This bit is cleared by writing 1 into it.
0: No falling edge trigger request occurred
1: Falling edge trigger request occurred
The FPIF20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

Bit 19 Reserved, must be kept at reset value.

Bits 18:0 FPIFx : Falling edge event pending for configurable line x (x = 18 to 0)

Each bit is set upon a falling edge event generated by hardware on the corresponding line.
Each bit is cleared by writing 1 into it.
0: No falling edge trigger request occurred
1: Falling edge trigger request occurred
The FPIF18 and FPIF17 bits are reserved in STM32G031xx and STM32G041xx.

13.5.6 EXTI rising trigger selection register 2 (EXTI_RTSR2)

Address offset: 0x028

Reset value: 0x0000 0000

Contains only register bits for configurable events.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 RT34 : Rising trigger event configuration bit of configurable line 34 ⁽¹⁾

This bit enables/disables the rising edge trigger for the event and interrupt on line 34.

0: Disable

1: Enable

This bit is only available in STM32G0B1xx and STM32G0C1xx. Reserved in all the other devices.

Bits 1:0 Reserved, must be kept at reset value.

1. 1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
   If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
   Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger.

13.5.7 EXTI falling trigger selection register 2 (EXTI_FTSR2)

Address offset: 0x02C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FT34 : Falling trigger event configuration bit of configurable line 34 ⁽¹⁾ .

This bit enables/disables the falling edge trigger for the event and interrupt on the corresponding line.

0: Disable

1: Enable

This bit is only available in STM32G0B1xx and STM32G0C1xx. Reserved in all the other devices.

Bits 1:0 Reserved, must be kept at reset value.

1. 1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
   If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
   Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger.

13.5.8 EXTI software interrupt event register 2 (EXTI_SWIER2)

Address offset: 0x030

Reset value: 0x0000 0000

Contains only register bits for configurable events.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 SWI34 : Software rising edge event trigger on line 34

Setting this bit by software triggers a rising edge event on the line 34, resulting in an interrupt, independently of EXTI_RTSR2 and EXTI_FTSR2 settings. This bit is automatically cleared by hardware. Reading this bit always returns 0.

0: No effect

1: Rising edge event generated on the line 34, followed by an interrupt

This bit is only available in STM32G0B1xx and STM32G0C1xx. Reserved in all the other devices.

Bits 1:0 Reserved, must be kept at reset value.

13.5.9 EXTI rising edge pending register 2 (EXTI_RPR2)

Address offset: 0x034

Reset value: 0x0000 0000

Contains only register bits for configurable events.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 RPIF34 : Rising edge event pending for configurable line 34

This bit is set upon a rising edge event generated by hardware or by software (through the EXTI_SWIER2 register) on line 34. This bit is cleared by writing 1 into it.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is only available in STM32G0B1xx and STM32G0C1xx. Reserved in all the other devices.

Bits 1:0 Reserved, must be kept at reset value.

13.5.10 EXTI falling edge pending register 2 (EXTI_FPR2)

Address offset: 0x038

Reset value: 0x0000 0000

Contains only register bits for configurable events.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FP1F34 : Falling edge event pending for configurable line 34

This bit is set upon a falling edge event generated by hardware on the line 34. This bit is cleared by writing 1 into it.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

This bit is only available in STM32G0B1xx and STM32G0C1xx. Reserved in all the other devices.

Bits 1:0 Reserved, must be kept at reset value.

13.5.11 EXTI external interrupt selection register (EXTI_EXTICRx)

Address offset: 0x060 + 0x4 * (x - 1), (x = 1 to 4)

Reset value: 0x0000 0000

Bits 31:24 EXTIm+3[7:0] : EXTIm+3 GPIO port selection (m = 4 * (x - 1))

These bits are written by software to select the source input for EXTIm+3 external interrupt.

0x00: PA[m+3] pin

0x01: PB[m+3] pin

0x02: PC[m+3] pin

0x03: PD[m+3] pin

0x04: PE[m+3] pin

0x05: PF[m+3] pin

Other: Reserved

Bits 23:16 EXTIm+2[7:0] : EXTIm+2 GPIO port selection ( \( m = 4 * (x - 1) \) )

These bits are written by software to select the source input for EXTIm+2 external interrupt.

0x00: PA[m+2] pin
0x01: PB[m+2] pin
0x02: PC[m+2] pin
0x03: PD[m+2] pin
0x04: PE[m+2] pin
0x05: PF[m+2] pin
Other: Reserved

Bits 15:8 EXTIm+1[7:0] : EXTIm+1 GPIO port selection ( \( m = 4 * (x - 1) \) )

These bits are written by software to select the source input for EXTIm+1 external interrupt.

0x00: PA[m+1] pin
0x01: PB[m+1] pin
0x02: PC[m+1] pin
0x03: PD[m+1] pin
0x04: PE[m+1] pin
0x05: PF[m+1] pin
Other: Reserved

Bits 7:0 EXTIm[7:0] : EXTIm GPIO port selection ( \( m = 4 * (x - 1) \) )

These bits are written by software to select the source input for EXTIm external interrupt.

0x00: PA[m] pin
0x01: PB[m] pin
0x02: PC[m] pin
0x03: PD[m] pin
0x04: PE[m] pin
0x05: PF[m] pin
Other: Reserved

13.5.12 EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0xFFF8 0000

Contains register bits for configurable events and direct events.

The reset value is set such as to, by default, enable interrupt from direct lines, and disable interrupt from configurable lines.

Bits 31:0 IMx : CPU wake-up with interrupt mask on line x (x = 31 to 0)

Setting/clearing each bit unmask/masks the CPU wake-up with interrupt, by an event on the corresponding line.

0: wake-up with interrupt masked

1: wake-up with interrupt unmasked

The IM24, IM22 and IM20 bits are only available in STM32G0B1xx and STM32G0C1xx.

They are reserved in all the other devices.

The IM27 bit is only available in STM32G071xx and STM32G081xx, and in STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

The IM18 and IM17 bits are reserved in STM32G031xx and STM32G041xx.

13.5.13 EXTI CPU wake-up with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

Bits 31:0 EMx : CPU wake-up with event generation mask on line x (x = 31 to 0)

Setting/clearing each bit unmask/masks the CPU wake-up with event generation on the corresponding line.

0: wake-up with event generation masked

1: wake-up with event generation unmasked

The EM24, EM22 and EM20 bits are only available in STM32G0B1xx and STM32G0C1xx.

They are reserved in all other devices.

The EM27 bit is only available in STM32G071xx and STM32G081xx, and STM32G0B1xx and STM32G0C1xx. It is reserved in all the other devices.

The EM18 and EM17 bits are reserved in STM32G031xx and STM32G041xx.

13.5.14 EXTI CPU wake-up with interrupt mask register (EXTI_IMR2)

Address offset: 0x090 (EXTI_IMR2)

Reset value: 0x0x0000 001B

Contains register bits for configurable events and direct events.

The reset value is set such as to, by default, enable interrupt from direct lines, and disable interrupt from configurable lines.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 IMx : CPU wake-up with interrupt mask on line x (x = 36 to 32)

Setting/clearing this bit un.masks/masks the CPU wake-up with interrupt, by an event on the corresponding line.

0: wake-up with interrupt request from Line x is masked

1: wake-up with interrupt request from Line x is unmasked

The IM36, IM35, and IM34 bits are only available in STM32G0B1xx and STM32G0C1xx.

They are reserved in STM32G071xx and STM32G081xx.

13.5.15 EXTI CPU wake-up with event mask register (EXTI_EMR2)

Address offset: 0x094

Reset value: 0x0000 0000

Contains register bits for configurable events and direct events.

The reset value is set such as to, by default, enable interrupt from direct lines, and disable interrupt from configurable lines.

This register is not available in STM32G031xx and STM32G041xx, and in STM32G051xx and STM32G061xx.

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 EMx : CPU wake-up with event generation mask on line x (x = 36 to 32)

Setting/clearing each bit un.masks/masks the CPU wake-up with event generation on the corresponding line.

0: wake-up with event generation masked

1: wake-up with event generation unmasked

The EM36, EM35, and EM34 bits are only available in STM32G0B1xx and STM32G0C1xx.

They are reserved in STM32G071xx and STM32G081xx.

13.5.16 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 68. EXTI controller register map and reset values

Table 68. EXTI controller register map and reset values (continued)

Refer to Section 2.2 on page 60 for the register boundary addresses.