9. Interconnect matrix

9.1 Introduction

Several peripherals have direct connections between them.

This allows autonomous communication and/or synchronization between peripherals, saving CPU resources thus power consumption.

In addition, these hardware connections remove software latency and allow design of predictable systems.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run, Low-power sleep, Stop 0, and Stop 1 modes.

For availability of peripherals on different STM32G0x1 products, refer to Section 1.4: Availability of peripherals .

9.2 Connection summary

Table 48. Interconnect matrix ⁽¹⁾⁽²⁾

1. Numbers in the table are links to corresponding sub-sections in Section 9.3: Interconnection details .

2. The “-” symbol in grayed cells means “no interconnection”.

9.3 Interconnection details

9.3.1 From TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17, to TIM1, TIM2, TIM3, TIM4, and TIM15

Purpose

Some of the TIMx timers are linked together internally for timer synchronization or chaining.

When one timer is configured in master mode, it can reset, start, stop or clock the counter of another timer configured in slave mode.

A description of the feature is provided in: Section 22.3.19: Timer synchronization .

The modes of synchronization are detailed in:

• • Section 21.3.26: Timer synchronization for advanced-control timer TIM1
• • Section 22.3.18: Timers and external trigger synchronization for general-purpose timers TIM2/TIM3/TIM4
• • Section 25.4.20: External trigger synchronization (TIM15 only) for general-purpose timer TIM15

Triggering signals

The output (from master) is on signal TIMx_TRGO (and TIMx_TRGOx), following a configurable timer event.

With TIM14, TIM16, and TIM17 timers that do not have a trigger output, the output compare 1 is used instead.

The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

The input and output signals for TIM1 are shown in Figure 101: Advanced-control timer block diagram .

The possible master/slave connections are given in Table 119: TIM1 internal trigger connection and Table 130: TIMx Internal trigger connection .

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.2 From TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC

Purpose

The general-purpose timers TIM2, TIM3, TIM4, and TIM15, basic timer TIM6, advanced-control timer TIM1, and EXTI can be used to generate an ADC triggering event.

TIMx synchronization is described in: Section 21.3.27: ADC synchronization .

ADC synchronization is described in: Section 15.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on the TRG[7:0] signal.

The connection between timers and ADC is provided in Table 73: External triggers .

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.3 From ADC to TIM1

Purpose

ADC can provide trigger event through watchdog signals to the advanced-control timer TIM1.

A description of the ADC analog watchdog setting is provided in: Section 15.7: Analog window watchdogs .

Trigger settings on the timer are provided in: Section 21.3.4: External trigger input .

Triggering signals

The output (from ADC) is on signals ADC_AWDx_OUT x = 1, 2, 3 (three watchdogs per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Relevant power modes

This interconnection operates in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.4 From TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM15, LPTIM1, LPTIM2, and EXTI, to DAC

Purpose

General-purpose timers TIM2/TIM3/TIM4/TIM15, basic timers TIM6, TIM7, low-power timers LPTIM1/LPTIM2, and advanced control timer TIM1 can trigger a DAC conversion.

Triggering signals

The TIMx_TRGO output of each timer is directly connected to corresponding DAC input.

Selection of DAC triggering input is provided in Section 16.4.7: DAC trigger selection (single and dual mode).

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.5 From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM2, TIM14, TIM16, and TIM17

Purpose

External clocks (HSE, LSE), internal clock (LSI), microcontroller output clock (MCO and MCO2), RTC clock, RTC wake-up interrupt, and GPIO can be selected as inputs to capture channel 1 of some of TIM14/16/TIM17 timers.

The timers allow calibrating or precisely measuring internal clocks such as HSI16 or LSI, using accurate clocks such as LSE or HSE/32 for timing reference. See details in Section 5.2.16: Internal/external clock measurement with TIM14/TIM16/TIM17 .

When low-speed external (LSE) oscillator is used, no additional hardware connections are required.

External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR input, see Section 22.4.25: TIM2 alternate function option register 1 (TIM2_AF1) .

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.6 From RTC, TAMP, COMP1, COMP2, and COMP3 to LPTIM1 and LPTIM2

Purpose

RTC alarm A/B, TAMP1/2 input detection, COMP1/2_OUT and GPIO alternate function can be used as trigger to start LPTIM counters LPTIM1/2.

Triggering signals

This trigger feature is described in Section 26.4.7: Trigger multiplexer (and following sections).

The input selection is described in Table 138: LPTIM1 external trigger connection and Table 139: LPTIM2 external trigger connection .

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, Low-power sleep, Stop 0, and Stop 1 power modes.

9.3.7 From TIM1, TIM2, TIM3, TIM4, and TIM15, to COMP1, COMP2, and COMP3

Purpose

Advanced-control timer TIM1 and general-purpose timers TIM2, TIM3, TIM4, and TIM15 can be used as blanking window input to COMP1, COMP2, and COMP3.

The blanking function is described in Section 18.3.7: Comparator output blanking function .

The blanking sources are given in:

• • Section 18.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0]
• • Section 18.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0]

Triggering signals

Timer output signal TIMx_OCx are the inputs to blanking source of COMP1/COMP2/COMP3.

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.8 From internal analog sources to ADC

Purpose

Internal temperature sensor output voltage \( V_{TS} \) , internal reference voltage \( V_{REFINT} \) and \( V_{BAT} \) monitoring channel are connected to ADC input channels.

More information is in:

• • Section 15.2: ADC main features
• • Section 15.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• • Figure 15.9: Temperature sensor and internal reference voltage
• • Figure 15.10: Battery voltage monitoring

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.9 From COMP1, COMP2, and COMP3 to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17

Purpose

COMP1, COMP2, and COMP3 comparator outputs can be connected to input capture or TIMx_ETR inputs of TIM1, TIM2, TIM3, or TIM4.

The connection to ETR is described in Section 21.3.4: External trigger input .

COMP1, COMP2, and COMP3 comparator outputs can also act as TIMx_BKIN or TIMx_BKIN2 break input signals for TIM1, TIM15, TIM16, and TIM17, through selecting GPIO alternate function using open drain connection of I/O. See Section 21.3.17: Bidirectional break inputs .

The possible connections are given in:

• • Section 21.4.23: TIM1 option register 1 (TIM1_OR1)
• • Section 21.4.28: TIM1 Alternate function register 2 (TIM1_AF2)
• • Section 22.4.22: TIM2 option register 1 (TIM2_OR1)
• • Section 25.3: TIM16/TIM17 main features

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.10 From system errors to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17

Purpose

CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17.

The purpose of the break function is to protect power switches driven by PWM signals from the timers.

List of possible source of break are described in:

• • Section 21.3.16: Using the break function (TIM1)
• • Section 25.4.13: Using the break function (TIM15/TIM16/TIM17)
• • Figure 236: TIM15 block diagram
• • Figure 237: TIM16/TIM17 block diagram

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.11 From TIM16, TIM17, USART1, and USART4, to IRTIM

Purpose

TIMx_OC1 output channel of TIM16 or TIM17 timers, associated with USART1 or USART4 transmission signal, can generate the infrared output waveform.

The functionality is described in Section 27: Infrared interface (IRTIM) .

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.

9.3.12 From TIM14, LPTIM1, and LPTIM2, to DMAMUX

Purpose

TIM14 general-purpose timer, LPTIM1 and LPTIM2 low-power timers, and EXTI, can be used as triggering event to DMAMUX.

Relevant power modes

These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power modes.