8. System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Enabling/disabling I ² C Fast Mode Plus on some I/O ports
• • Enabling/disabling the analog switch booster
• • Configuring the IR modulation signal and its output polarity
• • Remapping of some I/O ports
• • Remapping the memory located at the beginning of the code area
• • Flag pending interrupts from each interrupt line
• • Managing robustness feature

8.1 SYSCFG registers

8.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations of memory remap and to control special I/O features.

Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the hardware BOOT selection. After reset these bits take the value selected by the actual boot mode configuration.

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the actual boot mode configuration)

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 I2C3_FMP : Fast Mode Plus (FM+) enable for I2C3

This bit is set and cleared by software. It enables I ² C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers.

0: Disable

1: Enable

The I2C FM+ driving capability on some I/O ports can also be enabled through their corresponding I2C_xxx_FMP bit. When I2C FM+ is enabled, the speed control is ignored.

Note: Only significant on devices integrating the corresponding peripheral or function, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 23 I2C_PA10_FMP : Fast Mode Plus (FM+) enable for PA10

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PA10 I/O port.

0: Disable

1: Enable

When this I/O port is configured for I2Cx, the I2C FM+ driving capability on this I/O port can also be enabled through the corresponding I2Cx_FMP bit.

Bit 22 I2C_PA9_FMP : Fast Mode Plus (FM+) enable for PA9

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PA9 I/O port.

0: Disable

1: Enable

When this I/O port is configured for I2Cx, the I2C FM+ driving capability on this I/O port can also be enabled through the corresponding I2Cx_FMP bit.

Bit 21 I2C2_FMP : Fast Mode Plus (FM+) enable for I2C2

This bit is set and cleared by software. It enables I ² C FM+ driving capability on I/O ports configured as I2C2 through GPIOx_AFR registers.

0: Disable

1: Enable

The I2C FM+ driving capability on some I/O ports can also be enabled through their corresponding I2C_xxx_FMP bit. When I2C FM+ is enabled, the speed control is ignored.

Bit 20 I2C1_FMP : Fast Mode Plus (FM+) enable for I2C1

This bit is set and cleared by software. It enables I ² C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers.

0: Disable

1: Enable

The I2C FM+ driving capability on some I/O ports can also be enabled through their corresponding I2C_xxx_FMP bit. When I2C FM+ is enabled, the speed control is ignored.

Bit 19 I2C_PB9_FMP : Fast Mode Plus (FM+) enable for PB9

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB9 I/O port.

0: Disable

1: Enable

When this I/O port is configured for I2Cx, the I2C FM+ driving capability on this I/O port can also be enabled through the corresponding I2Cx_FMP bit.

Bit 18 I2C_PB8_FMP : Fast Mode Plus (FM+) enable for PB8

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB8 I/O port.

0: Disable

1: Enable

When this I/O port is configured for I2Cx, the I2C FM+ driving capability on this I/O port can also be enabled through the corresponding I2Cx_FMP bit.

Bit 17 I2C_PB7_FMP : Fast Mode Plus (FM+) enable for PB7

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB7 I/O port.

0: Disable

1: Enable

When this I/O port is configured for I2Cx, the I2C FM+ driving capability on this I/O port can also be enabled through the corresponding I2Cx_FMP bit.

Bit 16 I2C_PB6_FMP : Fast Mode Plus (FM+) enable for PB6

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB6 I/O port.

0: Disable

1: Enable

When this I/O port is configured for I2Cx, the I2C FM+ driving capability on this I/O port can also be enabled through the corresponding I2Cx_FMP bit.

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 UCPD2_STROBE : UCPD2 pull-down configuration strobe

Upon power on, internal pull-down resistors on UCPD2 CC1 and CC2 pins are enabled (connected).

The action of setting this bit has the following “strobing” effect:

- when UCPD2 is disabled: disable UCPD pull-down resistors on CC1 and CC2

- when UCPD2 is enabled, with CC1 and CC2 pin UCPD control bits configured: apply that configuration

See Section 38: USB Type-C ^® /USB Power Delivery interface (UCPD) for details.

Note: Only significant on devices integrating the corresponding peripheral or function, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 9 UCPD1_STROBE : UCPD1 pull-down configuration strobe

Upon power on, internal pull-down resistors on UCPD1 CC1 and CC2 pins are enabled (connected).

The action of setting this bit has the following “strobing” effect:

- when UCPD1 is disabled: disable UCPD pull-down resistors on CC1 and CC2

- when UCPD1 is enabled, with CC1 and CC2 pin UCPD control bits configured: apply that configuration

See Section 38: USB Type-C ^® /USB Power Delivery interface (UCPD) for details.

Note: Only significant on devices integrating the corresponding peripheral or function, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 8 BOOSTEN : I/O analog switch voltage booster enable

This bit selects the way of supplying I/O analog switches:

0: V _DD

1: Dedicated voltage booster (supplied by V _DD )

When using the analog inputs, setting to 0 is recommended for high V _DD , setting to 1 for low V _DD (less than 2.4 V).

Bits 7:6 IR_MOD[1:0] : IR Modulation Envelope signal selection

This bitfield selects the signal for IR modulation envelope:

00: TIM16

01: USART1

10: USART4 on STM32G071xx and STM32G081xx as well as STM32G0B1xx and STM32G0C1xx, USART2 on STM32G031xx and STM32G041xx as well as STM32G051xx and STM32G061xx

11: Reserved

Bit 5 IR_POL : IR output polarity selection

0: Output of IRTIM (IR_OUT) is not inverted

1: Output of IRTIM (IR_OUT) is inverted

Bit 4 PA12_RMP : PA12 pin remapping

This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. In this case, the original PA10 pin (if available) is forced to analog mode.

0: No remap (PA12)

1: Remap (PA10)

Bit 3 PA11_RMP : PA11 pin remapping

This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. In this case, the original PA9 pin (if available) is forced to analog mode.

0: No remap (PA11)

1: Remap (PA9)

Bit 2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE[1:0] : Memory mapping selection bits

These bits are set and cleared by software. They control the memory internal mapping at address 0x0000 0000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section 2.5: Boot configuration for more details.

x0: Main flash memory mapped at 0x0000 0000

01: System flash memory mapped at 0x0000 0000

11: Embedded SRAM mapped at 0x0000 0000

8.1.2 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18

System reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 PB2_CDEN : PB2 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PB2 pin.

0: Disable

1: Enable

Bit 22 PB1_CDEN : PB1 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PB1 pin.

0: Disable

1: Enable

Bit 21 PB0_CDEN : PB0 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PB0 pin.

0: Disable

1: Enable

Bit 20 PA13_CDEN : PA13 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PA13 pin.

0: Disable

1: Enable

Bit 19 PA6_CDEN : PA6 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PA6 pin.

0: Disable

1: Enable

Bit 18 PA5_CDEN : PA5 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PA5 pin.

0: Disable

1: Enable

Bit 17 PA3_CDEN : PA3 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PA3 pin.

0: Disable

1: Enable

Bit 16 PA1_CDEN : PA1 clamping diode enable bit ⁽¹⁾

This bit is set and cleared by software. It enables (connects) a clamping diode to V _DDIOx on PA1 pin.

0: Disable

1: Enable

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 SRAM_PEF : SRAM parity error flag

This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by writing 1.

0: No SRAM parity error detected

1: SRAM parity error detected

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 ECC_LOCK : ECC error lock bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash memory ECC 2-bit error detection signal connection to TIM1/15/16/17 Break input.

0: ECC error disconnected from TIM1/15/16/17 Break input

1: ECC error connected to TIM1/15/16/17 Break input

Bit 2 PVD_LOCK : PVD lock enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.

0: PVD interrupt disconnected from TIM1/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/15/16/17 Break input, PVDE and PLS[2:0] bits are read only.

Bit 1 SRAM_PARITY_LOCK : SRAM parity lock bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM parity error signal connection to TIM1/15/16/17 Break input.

0: SRAM parity error disconnected from TIM1/15/16/17 Break input

1: SRAM parity error connected to TIM1/15/16/17 Break input

Bit 0 LOCKUP_LOCK : Cortex ^® -M0+ LOCKUP bit enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the connection of Cortex ^® -M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.

0: Cortex ^® -M0+ LOCKUP output disconnected from TIM1/15/16/17 Break input

1: Cortex ^® -M0+ LOCKUP output connected to TIM1/15/16/17 Break input

1. 1. Only significant on devices integrating switchable clamping diodes, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.3 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)

A dedicated set of registers is implemented on the device to collect all pending interrupt sources associated with each interrupt line into a single register. This allows users to check by single read which peripheral requires service in case more than one source is associated to the interrupt line.

All bits in those registers are read only, set by hardware when there is corresponding interrupt request pending and cleared by resetting the interrupt source flags in the peripheral registers.

Address offset: 0x80

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 WWDOG : Window watchdog interrupt pending flag

8.1.4 SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1)

Address offset: 0x84

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 PVMOUT : V _DDIO2 supply monitoring interrupt request pending (EXTI line 34).

Bit 0 PVDOUT : PVD supply monitoring interrupt request pending (EXTI line 16).

8.1.5 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)

Address offset: 0x88

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RTC : RTC interrupt request pending (EXTI line 19)

Note: Only significant on devices integrating VDDIO2 monitor, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 0 TAMP : Tamper interrupt request pending (EXTI line 21)

8.1.6 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)

Address offset: 0x8C

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 FLASH_ITF : Flash memory interface interrupt request pending

Bit 0 FLASH_ECC : Flash memory interface ECC interrupt request pending

8.1.7 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)

Address offset: 0x90

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 CRS : CRS interrupt request pending

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 0 RCC : Reset and clock control interrupt request pending

8.1.8 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)

Address offset: 0x94

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 EXTI1 : EXTI line 1 interrupt request pending

Bit 0 EXTI0 : EXTI line 0 interrupt request pending

8.1.9 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)

Address offset: 0x98

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 EXTI3 : EXTI line 3 interrupt request pending

Bit 0 EXTI2 : EXTI line 2 interrupt request pending

8.1.10 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)

Address offset: 0x9C

System reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 EXTI15 : EXTI line 15 interrupt request pending

Bit 10 EXTI14 : EXTI line 14 interrupt request pending

Bit 9 EXTI13 : EXTI line 13 interrupt request pending

Bit 8 EXTI12 : EXTI line 12 interrupt request pending

Bit 7 EXTI11 : EXTI line 11 interrupt request pending

Bit 6 EXTI10 : EXTI line 10 interrupt request pending

Bit 5 EXTI9 : EXTI line 9 interrupt request pending

Bit 4 EXTI8 : EXTI line 8 interrupt request pending

Bit 3 EXTI7 : EXTI line 7 interrupt request pending

Bit 2 EXTI6 : EXTI line 6 interrupt request pending

Bit 1 EXTI5 : EXTI line 5 interrupt request pending

Bit 0 EXTI4 : EXTI line 4 interrupt request pending

8.1.11 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8)

Address offset: 0xA0

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 USB : USB interrupt request pending ⁽¹⁾

Bit 1 UCPD2 : UCPD2 interrupt request pending (EXTI line 33) ⁽¹⁾

Bit 0 UCPD1 : UCPD1 interrupt request pending (EXTI line 32) ⁽¹⁾

1. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.12 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)

Address offset: 0xA4

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 DMA1_CH1 : DMA1 channel 1 interrupt request pending

8.1.13 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)

Address offset: 0xA8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DMA1_CH3 : DMA1 channel 3 interrupt request pending

Bit 0 DMA1_CH2 : DMA1 channel 2 interrupt request pending

8.1.14 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)

Address offset: 0xAC

System reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 DMA2_CH5 : DMA2 channel 5 interrupt request pending ⁽¹⁾

Bit 8 DMA2_CH4 : DMA2 channel 4 interrupt request pending ⁽¹⁾

Bit 7 DMA2_CH3 : DMA2 channel 3 interrupt request pending ⁽¹⁾

Bit 6 DMA2_CH2 : DMA2 channel 2 interrupt request pending ⁽¹⁾

Bit 5 DMA2_CH1 : DMA2 channel 1 interrupt request pending ⁽¹⁾

Bit 4 DMA1_CH7 : DMA1 channel 7 interrupt request pending ⁽¹⁾

Bit 3 DMA1_CH6 : DMA1 channel 6 interrupt request pending ⁽¹⁾

Bit 2 DMA1_CH5 : DMA1 channel 5 interrupt request pending

Bit 1 DMA1_CH4 : DMA1 channel 4 interrupt request pending

Bit 0 DMAMUX : DMAMUX interrupt request pending

1. 1. Only significant on devices integrating the corresponding DMA instance and channel, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.15 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)

Address offset: 0xB0

System reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 COMP3 : Comparator 3 interrupt request pending (EXTI line 20) ⁽¹⁾

Bit 2 COMP2 : Comparator 2 interrupt request pending (EXTI line 18) ⁽¹⁾

Bit 1 COMP1 : Comparator 1 interrupt request pending (EXTI line 17) ⁽¹⁾

Bit 0 ADC : ADC interrupt request pending

1. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.16 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)

Address offset: 0xB4

System reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 TIM1_BRK : Timer 1 break interrupt request pending

Bit 2 TIM1_UPD : Timer 1 update interrupt request pending

Bit 1 TIM1_TRG : Timer 1 trigger interrupt request pending

Bit 0 TIM1_CCU : Timer 1 commutation interrupt request pending

8.1.17 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)

Address offset: 0xB8

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM1_CC : Timer 1 capture compare interrupt request pending

8.1.18 SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15)

Address offset: BCh

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM2 : Timer 2 interrupt request pending

8.1.19 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)

Address offset: 0xC0

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 TIM4 : Timer 4 interrupt request pending

Note: Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 0 TIM3 : Timer 3 interrupt request pending

8.1.20 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)

Address offset: 0xC4

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LPTIM1 : Low-power timer 1 interrupt request pending (EXTI line 29)

Bit 1 DAC : DAC underrun interrupt request pending ⁽¹⁾

Bit 0 TIM6 : Timer 6 interrupt request pending ⁽¹⁾

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.21 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)

Address offset: 0xC8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPTIM2 : Low-power timer 2 interrupt request pending (EXTI line 30)

Bit 0 TIM7 : Timer 7 interrupt request pending

Note: Only significant on devices integrating TIM7, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.22 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)

Address offset: 0xCC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM14 : Timer 14 interrupt request pending

8.1.23 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)

Address offset: 0xD0

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM15 : Timer 15 interrupt request pending

Note: Only significant on devices integrating TIM15, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.24 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)

Address offset: 0xD4

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FDCAN2_IT0 : FDCAN2 interrupt request pending

Note: Only significant on devices integrating FDCAN2, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 1 FDCAN1_IT0 : FDCAN1 interrupt request pending

Note: Only significant on devices integrating FDCAN1, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 0 TIM16 : Timer 16 interrupt request pending

8.1.25 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)

Address offset: 0xD8

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FDCAN2_IT1 : FDCAN2 interrupt request pending

Note: Only significant on devices integrating FDCAN2, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 1 FDCAN1_IT1 : FDCAN1 interrupt request pending

Note: Only significant on devices integrating FDCAN1, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 0 TIM17 : Timer 17 interrupt request pending

8.1.26 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)

Address offset: 0xDC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 I2C1 : I2C1 interrupt request pending, combined with EXTI line 23

8.1.27 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)

Address offset: 0xE0

System reset value: 0x0000 0000

1. Only significant on devices integrating I2C3, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 I2C3 : I2C3 interrupt request pending (EXTI line 22) ⁽¹⁾

Bit 0 I2C2 : I2C2 interrupt request pending

8.1.28 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)

Address offset: 0xE4

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SPI1 : SPI1 interrupt request pending

8.1.29 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)

Address offset: 0xE8

System reset value: 0x0000 0000

1. Only significant on devices integrating SPI3, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SPI3 : SPI3 interrupt request pending ⁽¹⁾

Bit 0 SPI2 : SPI2 interrupt request pending

8.1.30 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)

Address offset: 0xEC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 USART1 : USART1 interrupt request pending, combined with EXTI line 25

8.1.31 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)

Address offset: 0xF0

System reset value: 0x0000 0000

1. Only significant on devices integrating LPUART2, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPUART2 : LPUART2 interrupt request pending ⁽¹⁾

Bit 0 USART2 : USART2 interrupt request pending (EXTI line 26)

8.1.32 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)

Address offset: 0xF4

System reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 USART6 : USART6 interrupt request pending ⁽¹⁾

Bit 3 USART5 : USART5 interrupt request pending ⁽¹⁾

Bit 2 LPUART1 : LPUART1 interrupt request pending (EXTI line 28)

Bit 1 USART4 : USART4 interrupt request pending ⁽¹⁾

Bit 0 USART3 : USART3 interrupt request pending (EXTI line 28) ⁽¹⁾

1. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.33 SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30)

Address offset: 0xF8

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 CEC : CEC interrupt request pending (EXTI line 27)

Note: Only significant on devices integrating CEC, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.34 SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31)

Address offset: 0xFC

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 AES : AES interrupt request pending

Note: Only significant on devices integrating AES, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 0 RNG : RNG interrupt request pending

Note: Only significant on devices integrating RNG, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

8.1.35 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 47. SYSCFG register map and reset values

Table 47. SYSCFG register map and reset values (continued)

Table 47. SYSCFG register map and reset values (continued)