7. General-purpose I/Os (GPIO)

7.1 Introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).

7.2 GPIO main features

• • Output states: push-pull or open drain + pull-up/down
• • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)
• • Speed selection for each I/O
• • Configurable state of each I/O in Standby and Shutdown mode: analog, pull-up/down
• • Input states: floating, pull-up/down, analog
• • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• • Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
• • Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• • Analog function
• • Alternate function selection registers (at most 8 AFs possible per I/O)
• • Fast toggle capable of changing every two clock cycles
• • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

7.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

• • Input floating
• • Input pull-up
• • Input pull-down
• • Analog
• • Output open-drain with pull-up or pull-down capability
• • Output push-pull with pull-up or pull-down capability
• • Alternate function push-pull with pull-up or pull-down capability
• • Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR

registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

Figure 17 shows the basic structures of a standard I/O port bit. Table 44 gives the possible port bit configurations.

Figure 17. Basic structure of an I/O port bit

Table 44. Port bit configuration table ⁽¹⁾

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

7.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode.

The debug pins are in AF pull-up/pull-down after reset:

• • PA14: SWCLK in pull-down
• • PA13: SWDIO in pull-up

Note: PA14 is shared with BOOT0 functionality. Caution is required as the debugging device can manipulate BOOT0 pin value.

Upon reset, the UCPD CCx lines present a pull-down resistor that can be disabled by setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register.

When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

7.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin.

Each I/O pin has a multiplexer with up to eight alternate function inputs (AF0 to AF7) that can be configured through the GPIOx_AFRRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:

• • After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx_MODER register.
• • The specific alternate function assignments for each pin are detailed in the device datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, proceed as follows:

• • Debug function: After each device reset these pins are assigned as alternate function pins immediately usable by the debugger host
• • GPIO: Configure the desired I/O as output, input or analog in the GPIOx_MODER register.
• • Alternate function:
  • – Connect the I/O to the desired AFx in one of the GPIOx_AFRRL or GPIOx_AFRH register.
  • – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
  • – Configure the desired I/O as an alternate function in the GPIOx_MODER register.

Note: The Cortex-M0+ output EVENTOUT signal can be output as alternate function on several I/Os. An event can be signaled through the configured pin after executing SEV instruction.

• • Additional functions:
  • – ADC, DAC, and COMP connection can be enabled in ADC, DAC, or COMP registers, regardless of the configured GPIO mode. When ADC, DAC or COMP uses a GPIO, it is recommended to configure the GPIO in analog mode, through the GPIOx_MODER register.
  • – For the additional functions such as RTC, TAMP, WKUPx and oscillators, configure the required function in the related RTC, TAMP, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers.

Refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins.

7.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.

7.3.4 I/O port state in low-power modes

In Standby and in Shutdown mode, GPIO digital interface is not powered and the configuration of GPIO ports is controlled by PWR instead. Use the PWR_PUCRx and PWR_PDCRx registers, together with the APC bit of the PWR_CR3 register, to configure the GPIO pin states during the deep low-power modes, to prevent disturbing external components, buses, and to optimize power consumption.

Note: Exiting Shutdown mode causes a power reset, which also resets the PWR registers, thus putting the GPIOs to analog mode until reinitialized by the application software.

7.3.5 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register.

See Section 7.5.5: GPIO port input data register (GPIOx_IDR) (x = A to F) and Section 7.5.6: GPIO port output data register (GPIOx_ODR) (x = A to F) for the register descriptions.

7.3.6 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

7.3.7 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).

The LOCK sequence (refer to Section 7.5.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to F) ) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.

For more details refer to LCKR register description in Section 7.5.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to F) .

7.3.8 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.

To know which functions are multiplexed on each GPIO pin refer to the device datasheet.

7.3.9 External interrupt/wake-up lines

All ports have external interrupt capability. To use external interrupt lines, the given pin must not be configured in analog mode or being used as oscillator pin, so the input trigger is kept enabled.

Refer to Section 13: Extended interrupt and event controller (EXTI) .

7.3.10 Input configuration

When the I/O port is programmed as input:

• • The output buffer is disabled
• • The Schmitt trigger input is activated
• • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register provides the I/O state

Figure 18 shows the input configuration of the I/O port bit.

7.3.11 Output configuration

When the I/O port is programmed as output:

• • The output buffer is enabled:
  • – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
  • – Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS
• • The Schmitt trigger input is activated
• • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register gets the I/O state
• • A read access to the output data register gets the last written value

Figure 19 shows the output configuration of the I/O port bit.

Figure 19. Output configuration

7.3.12 Alternate function configuration

When the I/O port is programmed as alternate function:

• • The output buffer can be configured in open-drain or push-pull mode
• • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data)
• • The Schmitt trigger input is activated
• • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register gets the I/O state

Figure 20 shows the Alternate function configuration of the I/O port bit.

Figure 20. Alternate function configuration-

7.3.13 Analog configuration

When the I/O port is programmed as analog configuration:

• • The output buffer is disabled
• • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• • The weak pull-up and pull-down resistors are disabled by hardware
• • Read access to the input data register gets the value “0”

Figure 21 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 21. High impedance-analog configuration

7.3.14 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs.

When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.

When the oscillator is configured in a user external clock mode, only the OSC_IN or OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

7.3.15 Using the GPIO pins in the RTC domain

The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode.

For details about I/O control by the RTC, refer to Section 30.3: RTC functional description .

7.3.16 USB PD / Dead battery support

In the absence of \( V_{DD} \) supply, the device using the Dead battery capability of the USB Type-C standard provides an internal pull-down resistor \( R_d \) on CC lines if the input level on DBCC pins is high. This is to signal VBUS supply request.

To enable this feature, it is necessary to connect UCPD_DBCC1 to UCPD_CC1 and UCPD_DBCC2 to UCPD_CC2. To disable the feature, it is necessary to connect UCPD_DBCC1 and UCPD_DBCC2 to ground. Refer to Section 38: USB Type-C®/USB Power Delivery interface (UCPD) for more detail.

Note: The DBCC pads (GPIOs of FT_d type) present more leakage than standard GPIOs. Refer to product datasheet for values.

In applications that do not use the UCPD peripheral, disable the internal pull-down resistor \( R_d \) at startup through the strobe bits in SYSCFG registers.

In applications that use the UCPD peripheral, first configure the peripheral then load the configuration to the UCPD_CCx GPIOs through the strobe bits in SYSCFG registers.

7.3.17 Reset pin (PF2-NRST) in GPIO mode

The PF2-NRST pin can be configured as reset I/O or as a GPIO.

To configure PF2-NRST as a GPIO (input, output, AF, or analog I/O), set the NRST_MODE bitfield to GPIO mode in the FLASH option bytes. The new setting only takes effect upon the option byte loading (OBL) event following a reset. Until the reset release, PF2-NRST keeps acting as reset I/O.

The user must ensure that, upon power-on or exit from Standby or Shutdown mode, the level on the PF2-NRST pin can exceed the minimum \( V_{IH(NRST)} \) level specified in the device datasheet. Otherwise, the device does not exit the power-on reset. This applies to any PF2-NRST pin configuration set through the NRST_MODE[1:0] bitfield, the GPIO mode inclusive.

When PF2-NRST acts as a GPIO, reset can only be triggered from one of the device internal reset sources and the reset signal cannot be output.

For further information on reset function, refer to the RCC section.

7.4 GPIO in low-power modes

Table 45. Effect of low-power modes on the GPIO

7.5 GPIO registers

This section gives a detailed description of the GPIO registers.

For a summary of register bits, register address offsets and reset values, refer to Table 46 .

The peripheral registers can be written in word, half word or byte mode.

7.5.1 GPIO port mode register (GPIOx_MODER)
(x = A to F)

Address offset: 0x00

Reset value: 0xEBFF FFFF (port A)

Reset value: 0xFFFF FFFF (other ports)

Bits 31:0 MODEy[1:0] : Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)

7.5.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to F)

Address offset: 0x04
Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0] : Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

7.5.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to F)

Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for other ports)

Bits 31:0 OSPEEDy[1:0] : Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.

00: Very low speed

01: Low speed

10: High speed

11: Very high speed

Refer to the device datasheet for frequency specifications, and for power supply and load conditions for each speed.

Note: The FT_c GPIOs cannot be set to high speed and to very high speed. Only very low speed and low speed settings are available, with specific characteristics.

7.5.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to F)

Address offset: 0x0C

Reset value: 0x2400 0000 (for port A)

Reset value: 0x0000 0000 (for other ports)

Bits 31:0 PUPDy[1:0] : Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

7.5.5 GPIO port input data register (GPIOx_IDR)
(x = A to F)

Address offset: 0x10

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0] : Port x input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.

7.5.6 GPIO port output data register (GPIOx_ODR)
(x = A to F)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0] : Port output data I/O pin y (y = 15 to 0)

These bits can be read and written by software.

Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSR register (x = A to D, F).

7.5.7 GPIO port bit set/reset register (GPIOx_BSR)
(x = A to F)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:16 BR[15:0] : Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Resets the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BS[15:0] : Port x set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Sets the corresponding ODRx bit

7.5.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A to F)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the

LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK : Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset.

LOCK key write sequence:

• WR LCKR[16] = '1' + LCKR[15:0]
• WR LCKR[16] = '0' + LCKR[15:0]
• WR LCKR[16] = '1' + LCKR[15:0]
• RD LCKR
• RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns '1' until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0] : Port x lock I/O pin y (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is '0'.

0: Port configuration not locked

1: Port configuration locked

7.5.9 GPIO port alternate function low register (GPIOx_AFRL) (x = A to F)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:0 AFSELy[3:0] : Alternate function selection for port x pin y (y = 7 to 0)

These bits are written by software to configure alternate function I/Os.

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

Other: Reserved

7.5.10 GPIO port alternate function high register (GPIOx_AFRH)
(x = A to F)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:0 AFSELy[3:0] : Alternate function selection for port x pin y (y = 15 to 8)

These bits are written by software to configure alternate function I/Os.

0000: AF0

0001: AF1

0010: AF2

0011: AF3

0100: AF4

0101: AF5

0110: AF6

0111: AF7

Other: Reserved

7.5.11 GPIO port bit reset register (GPIOx_BRR) (x = A to F)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0] : Port x reset IO pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODx bit

1: Reset the corresponding ODx bit

7.5.12 GPIO register map

The following table gives the GPIO register map and reset values.

Table 46. GPIO register map and reset values

Refer to Section 2.2 on page 60 for the register boundary addresses.