5. Reset and clock control (RCC)

5.1 Reset

There are three types of reset, defined as system reset, power reset and RTC domain reset.

5.1.1 Power reset

A power reset is generated when one of the following events occurs:

• • Power-on reset (POR)
• • Exit from Standby mode
• • Exit from Shutdown mode

Power reset sets all registers to their reset values except the registers of the RTC domain.

When exiting Standby mode, all registers in the \( V_{CORE} \) domain are set to their reset value. Registers outside the \( V_{CORE} \) domain (RTC, WKUP, IWDG, and Standby/Shutdown mode control) are not impacted.

When exiting Shutdown mode, the power reset is generated, resetting all registers except those in the RTC domain.

5.1.2 System reset

A system reset sets all registers to their reset value unless otherwise specified in the register descriptions.

System reset is generated when one of the following events occurs:

• • Low level on NRST (external reset)
• • Window watchdog event (WWDG reset)
• • Independent watchdog event (IWDG reset)
• • Software reset (SW reset) (see Software reset )
• • Low-power mode security reset (see Low-power mode security reset )
• • Option byte loader reset (see Option byte loader reset )
• • Power-on reset (POR) or brown-out reset (BOR)

The reset source can be identified by checking the reset flags in the RCC_CSR register (see Section 5.4.24: Control/status register (RCC_CSR) ).

NRST (external reset):

Through specific option bits, the PF2-NRST pin is configurable for operating as:

• • Reset input/output (default at device delivery)

Valid reset signal on the pin is propagated to the internal logic, and each internal reset source is led to a pulse generator the output of which drives this pin. The GPIO functionality (PF2) is not available. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source to be output on the NRST pin. An internal reset holder option can be used, if enabled in the option bytes, to ensure that the pin is pulled low until it is read as low level. This function allows the detection of internal reset sources by external components when the line faces a significant

capacitive load. The BOOT0 pin is sampled on any NRST rising edge, caused by internal or external resets.

• • Reset input

In this mode, any valid reset signal on the NRST pin is propagated to device internal logic, but resets generated internally by the device are not visible on the pin. The GPIO functionality (PF2) is not available. The BOOT0 pin is sampled on POR and any subsequent NRST rising edge, caused by external resets. Other internal resets do not trigger new BOOT0 sampling.

• • GPIO

In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin is not available. Reset is only possible from device internal reset sources and it is not propagated to the pin. The BOOT0 pin is sampled on POR NRST rising edge only. Subsequent internal resets or transitions on the PF2 GPIO do not trigger new BOOT0 sampling. Also refer to Section 7.3.17: Reset pin (PF2-NRST) in GPIO mode for additional considerations for this mode.

Caution: Upon power-on reset or wake-up from Standby or Shutdown mode, the PF2-NRST pin is configured as reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of \( t_{RSTTEMPO} \) .

Figure 9. Simplified diagram of the reset circuit

Software reset

The SYSRESETREQ bit in Cortex®-M0+ Application interrupt and reset control register must be set to force a software reset on the device (refer to the programming manual PM0223).

Low-power mode security reset

To prevent that critical applications mistakenly enter a low-power mode, three low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions:

• • Entering Standby mode

This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.

• • Entering Stop mode

This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

• • Entering Shutdown mode

This type of reset is enabled by resetting nRST_SHDW bit in user option bytes. In this case, whenever a Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown mode.

For further information on the user option bytes, refer to Section 3.4.1: FLASH option byte description .

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the FLASH_CR register. This bit is used to launch the option byte loading by software.

5.1.3 RTC domain reset

The RTC domain has two specific resets.

A RTC domain reset is generated when one of the following events occurs:

• • Software reset , triggered by setting the BDRST bit in the RTC domain control register (RCC_BDCR) .
• • V _DD or V _BAT power on , if both supplies have previously been powered off.

A RTC domain reset only affects the LSE oscillator, the RTC, the backup registers and the RCC RTC domain control register.

5.2 Clocks

The device provides the following clock sources producing primary clocks:

• • HSI16 RC - a high-speed fully-integrated RC oscillator producing HSI16 clock (about 16 MHz)
• • HSI48 RC - a high-speed fully-integrated RC oscillator producing HSI48 clock for USB (about 48 MHz)
• • HSE OSC - a high-speed oscillator with external crystal/ceramic resonator or external clock source, producing HSE clock (4 to 48 MHz)
• • LSI RC - a low-speed fully-integrated RC oscillator producing LSI clock (about 32 kHz)
• • LSE OSC - a low-speed oscillator with external crystal/ceramic resonator or external clock source, producing LSE clock (accurate 32.768 kHz or external clock up to 1 MHz)
• • I2S_CKIN - pin for direct clock input for I2S1 peripheral

Each oscillator can be switched on or off independently when it is not used, to optimize power consumption. Check sub-sections of this section for more functional details. For electrical characteristics of the internal and external clock sources, refer to the device datasheet.

The device produces secondary clocks by dividing or/and multiplying the primary clocks:

• • HSISYS - a clock derived from HSI16 through division by a factor programmable from 1 to 128
• • PLLCLK, PLLQCLK and PLLCLK - clocks output from the PLL block
• • SYSCLK - a clock obtained through selecting one of LSE, LSI, HSE, PLLCLK, and HSISYS clocks
• • HCLK - a clock derived from SYSCLK through division by a factor programmable from 1 to 512
• • HCLK8 - a clock derived from HCLK through division by eight
• • PCLK - a clock derived from HCLK through division by a factor programmable from 1 to 16
• • TIMPCLK - a clock derived from PCLK, running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the PCLK frequency otherwise
• • LPTIMx_IN - clock from LPTIMx_INx pins, selectable for the LPTIM peripheral

More secondary clocks are generated by fixed division of HSE, HSI16 and HCLK clocks.

The HSISYS is used as system clock source after startup from reset, with the division by 1 (producing HSI16 frequency).

The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains, respectively. Their maximum allowed frequency is 64 MHz.

The peripherals are clocked with the clocks from the bus they are attached to (HCLK for AHB, PCLK for APB) except:

• • TIMx , with these clock sources to select from:
  • – TIMPCLK (selectable for all timers) running at PCLK frequency if the APB prescaler division factor is set to 1, or at twice the PCLK frequency otherwise
  • – PLLQCLK selectable for high-speed TIM1 and TIM15 timers
• • LPTIMx , with these clock sources to select from:
  • – LSI
  • – LSE
  • – HSI16
  • – PCLK (APB clock)
  • – LPTIMx_IN selected from LPTIMx_INx pins

The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.

• • UCPD , always clocked with HSI16
• • ADC , with these clock sources to select from:
  • – SYSCLK (system clock)
  • – HSI16
  • – PLLPCLK
• • USARTx / LPUARTx , with these clock sources to select from:
  • – SYSCLK (system clock)
  • – HSI16
  • – LSE
  • – PCLK (APB clock)

  The wake-up from Stop mode is supported only when the clock is HSI16 or LSE.

• • I2Cx , with these clock sources to select from:
  • – SYSCLK (system clock)
  • – HSI16
  • – PCLK (APB clock)

  The wake-up from Stop mode is supported only when the clock is HSI16.

• • I2Sx , with these clock sources to select from:
  • – SYSCLK (system clock)
  • – HSI16
  • – PLLPCLK
  • – I2S_CKIN pin
• • RNG , with these clock sources to select from:
  • – SYSCLK (system clock)
  • – HSI16 clock divided by 8
  • – PLLQCLK

The RNG clock can additionally be divided by 2, 4 or 8, using a dedicated prescaler.

• • CEC , with these clock sources to select from:
  • – HSI16 clock divided by 488
  • – LSE
• • RTC , with these clock sources to select from:
  • – LSE
  • – LSI
  • – HSE clock divided by 32

The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.

• • IWDG , always clocked with LSI clock.
• • USB , with these clocks to select from:
  • – HSE
  • – HSI48
  • – PLLQCLK
• • FDCAN , with these clocks to select from:
  • – HSE
  • – PCLK
  • – PLLQCLK
• • SysTick (Cortex ^® core system timer), with these clock sources to select from:
  • – HCLK (AHB clock)
  • – HCLK clock divided by 8

The selection is done through SysTick control and status register.

HCLK is used as Cortex ^® -M0+ free-running clock (FCLK). For more details, refer to the programming manual PM0223.

Figure 10. Clock tree

1. Only applies to STM32G071xx and STM32G081xx and to STM32G0B1xx and STM32G0C1xx.

2. Only applies to STM32G0B1xx and STM32G0C1xx.

5.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock sources:

• • HSE external crystal/ceramic resonator
• • HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Figure 11. HSE/ LSE clock sources

External crystal/ceramic resonator (HSE crystal)

The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.

The associated hardware configuration is shown in Figure 11 . Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER) .

The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR) .

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR) . The external clock signal (square, sinus or triangle) with ~40-60 % duty cycle depending on the frequency (refer to the datasheet ) must drive the OSC_IN pin (see Figure 11 ).

The OSC_OUT pin can be used as a GPIO or it can be configured as OSC_EN alternate function, to provide an enable signal to external clock synthesizer. The OSC_EN output is high when the external HSE clock is required and low when the external HSE clock can be switched off. It allows stopping the external clock source when the device enters low power modes.

Note: For details on pin availability, refer to the pinout section in the corresponding device datasheet.

To minimize the consumption, it is recommended to use the square signal.

5.2.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator.

The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator. However, even after calibration, it is less accurate than an oscillator using a frequency reference such as quartz crystal or ceramic resonator.

The HSISYS clock derived from HSI16 can be selected as system clock after wake-up from Stop modes (Stop 0 or Stop 1). Refer to Section 5.3: Low-power modes . It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.9: Clock security system (CSS) .

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. To compensate for this variation, each device is factory calibrated to 1 % accuracy at \( T_A=25^\circ\text{C} \) .

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal clock source calibration register (RCC_ICSCR) .

Voltage or temperature variations in the application may affect the HSI16 frequency of the RC oscillator. It can be trimmed using the HSITRIM[6:0] bits in the Internal clock source calibration register (RCC_ICSCR) .

For more details on how to measure the HSI16 frequency variation, refer to Section 5.2.16: Internal/external clock measurement with TIM14/TIM16/TIM17 .

The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.

The HSI16 RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR) .

The HSI16 signal can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.9: Clock security system (CSS) on page 166 .

5.2.3 HSI48 clock

Available on the STM32G0B1xx and STM32G0C1xx devices only, the HSI48 clock signal is generated from an internal 48 MHz RC oscillator. It can be used as clock source for the USB and RNG peripherals.

The internal 48MHz RC oscillator provides a high-precision clock to the USB peripheral thanks to the clock recovery system (CRS). CRS uses the USB SOF signal, LSE clock or an external signal as timing reference to precisely adjust the HSI48 RC oscillator frequency.

HSI48 RC oscillator is disabled as soon as the system enters in Stop or Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its free-run frequency which is subject to manufacturing process variations. The devices are factory-calibrated for ~3 % accuracy at \( T_A = 25^\circ\text{C} \) .

Refer to CRS section for more details on how to configure and use CRS.

The HSI48RDY flag in the RCC_CR register indicates if HSI48 is stable or not. At startup, the HSI48 clock is not released until this flag is set by hardware.

The HSI48 RC oscillator is enabled/disabled through the HSI48ON bit of the RCC_CR register. It is automatically enabled (by hardware setting the HSI48ON bit) when selected as clock source for the USB peripheral, as long as the USB peripheral is enabled.

Furthermore, it is possible to output the HSI48 clock through the MCO and MCO2 multiplexers and use it as a clock source for other application components.

5.2.4 PLL

The internal PLL multiplies the frequency of HSI16- or HSE-based clock fetched on its input, to produce three independent clock outputs. The allowed input frequency range is from 2.66 to 16 MHz. The dedicated divider PLLM with division factor programmable from one to eight allows setting a frequency within the valid PLL input range. Refer to Figure 10: Clock tree and PLL configuration register (RCC_PLLCFGR) .

The PLL configuration (selection of the input clock and multiplication factor) must be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.

To modify the PLL configuration, proceed as follows:

1. 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR) .
2. 2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. 3. Change the desired parameter.
4. 4. Enable the PLL again by setting PLLON to 1.
5. 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL configuration register (RCC_PLLCFGR) .

An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt enable register (RCC_CIER) .

The enable bit of each PLL output clock (PLLPEN, PLLQEN, and PLLREN) can be modified at any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as system clock.

5.2.5 LSE clock

The LSE crystal is a 32.768 kHz crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in RTC domain control register (RCC_BDCR) . The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best compromise between robustness and short start-up time on one side and low-power-consumption on the other side. The LSE drive can be decreased to the lower drive capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the drive capability can not be increased if LSEON=1.

The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER) .

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the AHB peripheral clock enable in Sleep/Stop mode register (RCC_AHBSMENR) . The external clock signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 11 .

OSC32_OUT can be configured as alternate function of OSC32_EN to control the external clock source. OSC32_EN output is high when the external LSE clock is required and low when the external LSE clock can be switched off.

5.2.6 LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For more details, refer to the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR) .

The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER) .

5.2.7 System clock (SYSCLK) selection

One of the following clocks can be selected as system clock (SYSCLK):

• • LSI
• • LSE
• • HSISYS
• • HSE
• • PLLRCLK

The system clock maximum frequency is 64 MHz. Upon system reset, the HSISYS clock derived from HSI16 oscillator is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch occurs when the clock source becomes ready. Status bits in the Clock control register (RCC_CR) indicate which clocks are ready. Status bits in the Clock configuration register (RCC_CFGR) indicate which clock is currently used as a system clock.

5.2.8 Clock source frequency versus voltage scaling

The following table gives the different clock source frequencies depending on the product voltage range.

Table 36. Clock source frequency

1. Maximum VCO frequency is 344 MHz.

2. Maximum VCO frequency is 128 MHz.

5.2.9 Clock security system (CSS)

Clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock:

• • the HSE oscillator is automatically disabled
• • a clock failure event is sent to the break input of TIM1, TIM15, TIM16 and TIM17 timers
• • CSSI (clock security system interrupt) is generated

The CSSI is linked to the Cortex®-M0+ NMI (non-maskable interrupt) exception vector. It makes the software aware of a HSE clock failure to allow it to perform rescue operations.

Note: If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the Clock interrupt clear register (RCC_CICR) .

If HSE is selected directly or indirectly (PLLCLK selected for SYSCLK and HSE selected as PLL input) as system clock, and a failure of HSE clock is detected, the system clock switches automatically to HSISYS and the HSE oscillator is disabled. If the HSE clock (divided or not) is the clock entry of the PLL and PLLCLK is used as system clock when the failure occurs, the PLL is disabled, too.

5.2.10 Clock security system for LSE clock (LSECSS)

A clock security system on LSE can be activated by setting the LSECSSON bit in RTC domain control register (RCC_BDCR) . This bit can be cleared only by a hardware reset or RTC software reset, or after LSE clock failure detection. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after selecting the RTC clock by RTCSEL.

The LSECSS works in all modes except VBAT. It keeps working also under system reset (excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no longer supplied to the RTC but its registers are not impacted.

Note: If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the LSECSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the LSECSSI by setting the LSECSSC bit in the Clock interrupt clear register (RCC_CICR) .

If LSE is used as system clock, and a failure of LSE clock is detected, the system clock switches automatically to LSI. In low-power modes, an LSE clock failure generates a wake-up. The interrupt flag must then be cleared within the RCC registers.

The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by clearing LSEON), and change the RTC clock source (no clock, LSI or HSE, with RTCSEL), or take any appropriate action to secure the application.

Caution: When the LSECSSD bit is set, the LSE oscillator is held under reset and it cannot be restarted. To clear the LSECSSD bit, reset the RTC domain, using BDRST bit.

The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.

5.2.11 ADC clock

The ADC clock is derived from the system clock, or from the PLLPCLK output. It can reach 122 MHz and can be divided by the following prescalers values: 1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB

clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor is configured using the CKMODE bitfields in the ADC1_CCR.

If the programmed factor is 1, the AHB prescaler must be set to 1.

5.2.12 RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR) . This selection cannot be modified without resetting the RTC domain. The system must always be configured so as to get a PCLK frequency greater than or equal to the RTCCLK frequency for a proper operation of the RTC.

The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not. Consequently:

• • If LSE is selected as RTC clock:
  • – The RTC continues to work even if the \( V_{DD} \) supply is switched off, provided the \( V_{BAT} \) supply is maintained.
• • If LSI is selected as the RTC clock:
  • – The RTC state is not guaranteed if the \( V_{DD} \) supply is powered off.
• • If the HSE clock divided by a prescaler is used as the RTC clock:
  • – The RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the internal voltage regulator is powered off (removing power from the \( V_{CORE} \) domain).

When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system reset.

5.2.13 Timer clock

The timer clock TIMPCLK is derived from PCLK (used for APB) as follows:

1. 1. If the APB prescaler is set to 1, TIMPCLK frequency is equal to PCLK frequency.
2. 2. Otherwise, the TIMPCLK frequency is set to twice the PCLK frequency.

For TIM1 and TIM15, PLLQCLK clock can also be selected, if:

• • PCLK is derived from PLLRCLK, and
• • PLLQCLK frequency is an integer multiplication by 2 or more of the PCLK frequency, without exceeding 128 MHz.

5.2.14 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

5.2.15 Clock-out capability

MCO and MCO2

The MCO and MCO2 pins output, independently of each other, the clock selected from:

• • LSI
• • LSE
• • SYSCLK
• • HSI16
• • HSI48
• • HSE
• • PLLPCLK
• • PLLQCLK
• • PLLRCLK
• • RTCCLK
• • RTC WAKEUP

The multiplexers for MCO and MCO2, respectively, are controlled by the MCOSEL[3:0] and MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR) . Their outputs are further divided by a factor set through the MCOPRE[3:0] and MCO2PRE[3:0] bitfields of the Clock configuration register (RCC_CFGR) .

Note: The MCO2 output and the associated MCO2SEL[3:0] and MCO2PRE[3:0] bitfields are only available on the STM32G0B1xx and STM32G0C1xx devices.

The divider ratio (MCOPRE[3:0] bitfield) on the devices other than STM32G0B1xx and STM32G0C1xx is limited to 128. The selectable clock sources here do not include PLLPCLK, PLLQCLK, HSI48, RTCCLK, and RTC WAKEUP.

LSCO

The LSCO pin allows outputting on of low-speed clocks:

• • LSI
• • LSE

The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit of the RTC domain control register (RCC_BDCR) . When this additional function is activated on a GPIO, its input buffer is disabled by hardware.

This function remains available in Stop 0, Stop 1 and Standby modes.

5.2.16 Internal/external clock measurement with TIM14/TIM16/TIM17

It is possible to indirectly measure the frequency of all on-board clock sources with the TIM14, TIM16 and TIM17 channel 1 input capture, as represented in Figure 12 , Figure 13 and Figure 14 .

TIM14

By setting the TI1SEL[3:0] field of the TIM14_TISEL register, the clock selected for the input capture channel1 of TIM14 can be one of:

• • GPIO (refer to the alternate function mapping in the device datasheets)
• • RTC clock (RTCCLK)
• • HSE clock divided by 32
• • MCO (MCU clock output)
• • MCO2 (MCU clock output 2)

The two last options are controlled by the MCOSEL[3:0] and MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR) . All clock sources can be selected for the MCO and MCO2 pins.

Figure 12. Frequency measurement with TIM14 in capture mode

TIM16

By setting the TI1SEL[3:0] field of the TIM16_TISEL register, the clock selected for the input capture channel1 of TIM16 can be one of:

• • GPIO (refer to the alternate function mapping in the device datasheets).
• • LSI clock
• • LSE clock
• • RTC wake-up interrupt signal
• • MCO2 (MCU clock output 2)

The second-last option requires to enable the RTC interrupt.

The last option is controlled through the MCO2SEL[3:0] bitfield of the Clock configuration register (RCC_CFGR) . All clock sources can be selected for the MCO2 pin.

Figure 13. Frequency measurement with TIM16 in capture mode

TIM17

By setting the TI1SEL[3:0] field of the TIM17_TISEL register, the clock selected for the input capture channel1 of TIM17 can be one of:

• • GPIO (refer to the alternate function mapping in the device datasheets)
• • HSI48 divided by 256
• • HSE divided by 32
• • MCO (MCU clock output)
• • MCO2 (MCU clock output 2)

The two last options are controlled by the MCOSEL[3:0] and MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR) . All clock sources can be selected for the MCO and MCO2 pins.

Figure 14. Frequency measurement with TIM17 in capture mode

Calibration of the HSI16 oscillator

For TIM14, TIM15 and TIM17, the primary purpose of connecting the LSE to the channel 1 input capture is to precisely measure HSISYS (derived from HSI16) selected as system clock. Counting HSISYS clock pulses between consecutive edges of the LSE clock (the time reference) allows measuring the HSISYS (and HSI16) clock period. Such measurement can determine the HSI16 oscillator frequency with nearly the same accuracy as the accuracy of the 32.768 kHz quartz crystal used with the LSE oscillator (typically a few tens of ppm). The HSI16 oscillator can then be trimmed to compensate for deviations from target frequency, due to manufacturing, process, temperature and/or voltage variation.

The HSI16 oscillator has dedicated user-accessible calibration bits for this purpose.

The basic concept consists in providing a relative measurement (for example, the HSISYS/LSE ratio): the measurement accuracy is therefore closely related to the ratio between the two clock sources. Increasing the ratio allows improving the measurement accuracy.

Generated by the HSE oscillator, the HSE clock (divided by 32) used as time reference is the second best method for reaching a good HSI16 frequency measurement accuracy. It is recommended in absence of the LSE clock.

In order to further improve the precision of the HSI16 oscillator calibration, it is advised to employ one or a combination of the following measures to increase the frequency measurement accuracy:

• • set the HSISYS divider to 1 for HSISYS frequency to be equal to HSI16 frequency
• • average the results of multiple consecutive measurements
• • use the input capture prescaler of the timer (one capture every up to eight periods)
• • use LSE clock for the RTC and the RTC wake-up interrupt signal as time reference

The last point significantly increases the reference period for HSI16 clock pulse counting, which improves the accuracy of a single measurement. For operation, the RTC wake-up interrupt must be enabled.

Calibration of the HSI48 oscillator

The HSI48 oscillator is factory-calibrated.

Measurement of the LSI oscillator frequency

The measurement of the LSI oscillator frequency uses the same principle as that for calibrating the HSI16 oscillator. TIM16 channel1 input capture must be used for LSI clock, and HSE selected as system clock source. The number of HSE clock pulses between consecutive edges of the LSI signal, counted by TIM16, is then representative of the LSI clock period.

5.2.17 Peripheral clock enable registers

The clock to each peripheral can individually be enabled by the corresponding enable bit of the RCC_AHBENR register or one of the RCC_APBENRx registers. The clocks to I/O ports can individually be enabled through the RCC_IOPENR register.

When the clock to a peripheral or I/O port is not active, the read and write accesses to its registers are not effective.

Caution: The enable bit has a synchronization mechanism to create a glitch-free clock for the peripheral or I/O port. After the enable bit is set, there is a 2-clock-cycle delay before the clock be active, which the software must take into account.

5.3 Low-power modes

• • AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• • Sleep and Low Power Sleep modes stops the CPU clock. The memory interface clocks (flash memory and SRAM interfaces) can be stopped by software during sleep mode.

The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled.

• • Stop modes (Stop 0 and Stop 1) stop all the clocks in the \( V_{\text{CORE}} \) domain and disable the PLL as well as the HSI16, HSI48 and HSE oscillators.

The USART1, USART2, USART3, LPUART1, LPUART2, I2C1, and I2C2 peripherals can enable the HSI16 oscillator even when the MCU is in Stop mode (if HSI16 is selected as clock source for one of those peripherals).

The LPUART1, LPUART2, USART1, USART2, and USART3 peripherals can also operate with the clock from the LSE oscillator when the system is in Stop mode, if LSE is selected as clock source for that peripheral and the LSE oscillator is enabled (LSEON set). In that case, the LSE oscillator remains active when the device enters Stop mode (these peripherals do not have the capability to turn on the LSE oscillator).

• • Standby and Shutdown modes stop all clocks in the \( V_{\text{CORE}} \) domain and disable the PLL, as well as the HSI16, HSI48, and HSE oscillators.

The CPU deepsleep mode can be overridden for debugging, by setting the DBG_STOP or DBG_STANDBY bits in the DBG_CR register.

When leaving the Stop 0 or Stop 1 modes, HSISYS becomes automatically the system clock.

When leaving the Standby and Shutdown modes, HSISYS (with frequency equal to HSI16) becomes automatically the system clock. At wake-up from Standby and Shutdown mode, the user trim is lost.

If a flash memory programming operation is ongoing, Stop, Standby, and Shutdown entry is delayed until the flash memory interface access is finished. If an access to the APB domain is ongoing, the Stop, Standby, and Shutdown entry is delayed until the APB access is finished.

5.4 RCC registers

Unless otherwise specified, the RCC registers support word, half-word, and byte access, without any wait state.

5.4.1 Clock control register (RCC_CR)

Address offset: 0x00

Power-on reset value: 0x0000 0500

Other types of reset: same as power-on reset, except HSEBYP bit that keeps its previous value.

This register only supports word and half-word accesses.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLL RDY : PLL clock ready flag

Set by hardware to indicate that the PLL is locked.

0: PLL unlocked

1: PLL locked

Bit 24 PLLON : PLL enable

Set and cleared by software to enable the PLL.

Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock.

0: PLL OFF

1: PLL ON

Bit 23 HSI48 RDY : HSI48 clock ready flag

The flag is set when the HSI48 clock is ready for use.

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 22 HSI48 ON : HSI48 RC oscillator enable

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 21:20 Reserved, must be kept at reset value.

Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.

0: Clock security system OFF (clock detector OFF)

1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: HSE crystal oscillator not bypassed

1: HSE crystal oscillator bypassed with external clock

Set by hardware to indicate that the HSE oscillator is stable.

0: HSE oscillator not ready

1: HSE oscillator ready

Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.

Set and cleared by software.

Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

0: HSE oscillator OFF

1: HSE oscillator ON

Bits 15:14 Reserved, must be kept at reset value.

This bitfield controlled by software sets division factor of the HSI16 clock divider to produce HSISYS clock:

000: 1

001: 2

010: 4

011: 8

100: 16

101: 32

110: 64

111: 128

Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.

0: HSI16 oscillator not ready

1: HSI16 oscillator ready

Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.

Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value.

0: No effect on HSI16 oscillator.

1: HSI16 oscillator is forced ON even in Stop mode.

Bit 8 HSION : HSI16 clock enable

Set and cleared by software.

Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode.

Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock).

0: HSI16 oscillator OFF
1: HSI16 oscillator ON

Bits 7:0 Reserved, must be kept at reset value.

5.4.2 Internal clock source calibration register (RCC_ICSCR)

Address offset: 0x04

Reset value: 0x0000 40XX (X is factory-programmed)

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:8 HSITRIM[6:0] : HSI16 clock trimming

These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16 clock.

The default value is 64, which, when added to the HSICAL value, trims the HSI16 to 16 MHz \( \pm 1 \% \) .

Bits 7:0 HSICAL[7:0] : HSI16 clock calibration

These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. Refer to DS for the trimming steps granularity. The frequency progression presents discontinuities when HSICAL crosses multiples of 64.

5.4.3 Clock configuration register (RCC_CFGR)

One or two wait states are inserted if this register is accessed during clock source switch, and between zero and 15 wait states are inserted if during an update of APB or AHB prescaler values.

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:28 MCOPRE[3:0] : Microcontroller clock output prescaler

This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:

0000: 1

0001: 2

0010: 4

...

0111: 128

1000: 256*

1001: 512*

1010: 1024*

Other: reserved

It is highly recommended to set this field before the MCO output is enabled.

Note: The MCOPRE[3] bit and so the values marked with * are only significant for STM32G0B1xx and STM32G0C1xx. Reserved on the other devices.

Bits 27:24 MCOSEL[3:0] : Microcontroller clock output clock selector

This bitfield is controlled by software. It sets the clock selector for MCO output as follows:

0000: no clock

0001: SYSCLK

0010: HSI48*

0011: HSI16

0100: HSE

0101: PLLRCLK

0110: LSI

0111: LSE

1000: PLLPCLK*

1001: PLLQCLK*

1010: RTCCLK*

1011: RTC wake-up*

Other: no clock

Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

Values marked with * are only significant for STM32G0B1xx and STM32G0C1xx. Reserved for the other devices.

This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows:

0000: 1

0001: 2

0010: 4

...

0111: 128

1000: 256

1001: 512

1010: 1024

Other: reserved

It is highly recommended to set this field before the MCO2 output is enabled.

Note: These bits are only significant on devices integrating the corresponding output, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:

0000: no clock

0001: SYSCLK

0010: HSI48

0011: HSI16

0100: HSE

0101: PLLRCLK

0110: LSI

0111: LSE

1000: PLLPCLK

1001: PLLQCLK

1010: RTCCLK

1011: RTC wake-up

Other: no clock

Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.

Note: These bits are only significant on devices integrating the corresponding output, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 15 Reserved, must be kept at reset value.

This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows:

0xx: 1

100: 2

101: 4

110: 8

111: 16

This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows:

0xxx: 1
1000: 2
1001: 4
1010: 8
1011: 16
1100: 64
1101: 128
1110: 256
1111: 512

Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section 4.1.4: Dynamic voltage scaling management ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.

Bits 7:6 Reserved, must be kept at reset value.

This bitfield is controlled by hardware to indicate the clock source used as system clock:

000: HSISYS
001: HSE
010: PLLRCLK
011: LSI
100: LSE
Others: Reserved

This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows:

000: HSISYS
001: HSE
010: PLLRCLK
011: LSI
100: LSE
Others: Reserved

The setting is forced by hardware to 000 (HSISYS selected):

• – when the device exits Stop, Standby, or Shutdown mode, or
• – when the HSE oscillator failure is detected while the HSE is selected directly or indirectly (PLLRCLK selected for SYSCLK and HSE selected as PLL input) as system clock source.

The setting is forced by hardware to 011 (LSI selected) when the LSE oscillator failure is detected while the LSE is selected as system clock source.

5.4.4 PLL configuration register (RCC_PLLCFGR)

Address offset: 0x0C

Reset value: 0x0000 1000

This register configures the PLL clock outputs according to the formulas:

• • \( f_{VCO} = f_{PLLIN} \times (N / M) \)

• • \( f_{\text{PLL P}} = f_{\text{VCO}} / P \)
• • \( f_{\text{PLL Q}} = f_{\text{VCO}} / Q \)
• • \( f_{\text{PLL R}} = f_{\text{VCO}} / R \)

where \( f_{\text{PLL IN}} \) is the PLL input clock frequency, \( f_{\text{VCO}} \) is the PLL VCO frequency, and P, Q and R are \( f_{\text{VCO}} \) division factors and \( f_{\text{PLL P}} \) , \( f_{\text{PLL Q}} \) and \( f_{\text{PLL R}} \) the clock frequencies of the PLLPCLK, PLLQCLK and PLLRCLK PLL clock outputs, respectively.

Bits 31:29 PLLR[2:0] : PLL VCO division factor R for PLLRCLK clock output

This bitfield is controlled by software. It sets the PLL VCO division factor R as follows:

000: Reserved

001: 2

010: 3

011: 4

100: 5

101: 6

110: 7

111: 8

The bitfield can be written only when the PLL is disabled.

The PLLRCLK clock can be selected as system clock.

Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.

Bit 28 PLLREN : PLLRCLK clock output enable

This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL:

0: Disable

1: Enable

This bit cannot be written when PLLRCLK output of the PLL is selected for system clock.

Disabling the PLLRCLK clock output, when not used, allows saving power.

Bits 27:25 PLLQ[2:0] : PLL VCO division factor Q for PLLQCLK clock output

This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows:

000: Reserved

001: 2

010: 3

011: 4

100: 5

101: 6

110: 7

111: 8

The bitfield can be written only when the PLL is disabled.

Note: Only significant on devices integrating PLLQCLK, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Caution: The software must set this bitfield so as not to exceed 128 MHz on this clock.

Bit 24 PLLQEN : PLLQCLK clock output enable

This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL:

0: Disable

1: Enable

Disabling the PLLQCLK clock output, when not used, allows saving power.

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:17 PLLP[4:0] : PLL VCO division factor P for PLLPCLK clock output

This bitfield is controlled by software. It sets the PLL VCO division factor P as follows:

00000: Reserved

00001: 2

...

11111: 32

The bitfield can be written only when the PLL is disabled.

Caution: The software must set this bitfield so as not to exceed 122 MHz on this clock.

Bit 16 PLLPEN : PLLPCLK clock output enable

This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL:

0: Disable

1: Enable

Disabling the PLLPCLK clock output, when not used, allows saving power.

Bit 15 Reserved, must be kept at reset value.

Bits 14:8 PLLN[6:0] : PLL frequency multiplication factor N

This bit is controlled by software to set the division factor of the \( f_{VCO} \) feedback divider (that determines the PLL multiplication ratio) as follows:

0000000: Invalid

0000001: Reserved

...

0000111: Reserved

0001000: 8

0001001: 9

...

1010101: 85

1010110: 86

1010111: Reserved

...

1111111: Reserved

The bitfield can be written only when the PLL is disabled.

Caution: The software must set these bits so that the VCO output frequency is between 96 and 344 MHz.

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 PLLM : Division factor M of the PLL input clock divider

This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows:

000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8

The bitfield can be written only when the PLL is disabled.

Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 16 MHz.

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 PLL SRC : PLL input clock source

This bit is controlled by software to select PLL clock source, as follows:

00: No clock
01: Reserved
10: HSI16
11: HSE

The bitfield can be written only when the PLL is disabled.

When the PLL is not used, selecting 00 allows saving power.

5.4.5 RCC clock recovery RC register (RCC_CRRCR)

This register applies to STM32G0B1xx and STM32G0C1xx only. It is reserved otherwise.

Address offset: 0x14

Reset value: 0b0000 0000 0000 0000 0000 000X XXXX XXXX

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 HSI48CAL[8:0] : HSI48 clock calibration

These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.

5.4.6 Clock interrupt enable register (RCC_CIER)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 PLLRDYIE : PLL ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLL lock:

0: Disable

1: Enable

Bit 4 HSERDYIE : HSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:

0: Disable

1: Enable

Bit 3 HSIRDYIE : HSI16 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:

0: Disable

1: Enable

Bit 2 HSI48RDYIE : HSI48 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization:

0: Disable

1: Enable

Bit 1 LSERDYIE : LSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:

0: Disable

1: Enable

Bit 0 LSIRDYIE : LSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:

0: Disable

1: Enable

5.4.7 Clock interrupt flag register (RCC_CIFR)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 LSECSSF : LSE clock security system interrupt flag

Set by hardware when a failure is detected in the LSE oscillator.

Cleared by software by setting the LSECSSC bit.

0: No clock security interrupt caused by LSE clock failure

1: Clock security interrupt caused by LSE clock failure

Bit 8 CSSF : HSE clock security system interrupt flag

Set by hardware when a failure is detected in the HSE oscillator.

Cleared by software setting the CSSC bit.

0: No clock security interrupt caused by HSE clock failure

1: Clock security interrupt caused by HSE clock failure

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 PLL RDYF : PLL ready interrupt flag

Set by hardware when the PLL locks and PLLRDYIE is set.

Cleared by software setting the PLLRDYC bit.

0: No clock ready interrupt caused by PLL lock

1: Clock ready interrupt caused by PLL lock

Bit 4 HSERDYF : HSE ready interrupt flag

Set by hardware when the HSE clock becomes stable and HSERDYIE is set.

Cleared by software setting the HSERDYC bit.

0: No clock ready interrupt caused by the HSE oscillator

1: Clock ready interrupt caused by the HSE oscillator

Bit 3 HSIRDYF : HSI16 ready interrupt flag

Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR) ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.

Cleared by software setting the HSIRDYC bit.

0: No clock ready interrupt caused by the HSI16 oscillator

1: Clock ready interrupt caused by the HSI16 oscillator

Bit 2 HSI48RDYF : HSI48 ready interrupt flag

Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to Clock control register (RCC_CR) ). When HSI48ON is not set but the HSI48 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.

Cleared by software setting the HSI48RDYC bit.

0: No clock ready interrupt caused by the HSI48 oscillator

1: Clock ready interrupt caused by the HSI48 oscillator

Bit 1 LSERDYF : LSE ready interrupt flag

Set by hardware when the LSE clock becomes stable and LSERDYIE is set.

Cleared by software setting the LSERDYC bit.

0: No clock ready interrupt caused by the LSE oscillator

1: Clock ready interrupt caused by the LSE oscillator

Bit 0 LSIRDYF : LSI ready interrupt flag

Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.

Cleared by software setting the LSIRDYC bit.

0: No clock ready interrupt caused by the LSI oscillator

1: Clock ready interrupt caused by the LSI oscillator

5.4.8 Clock interrupt clear register (RCC_CICR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 LSECSSC : LSE Clock security system interrupt clear

This bit is set by software to clear the LSECSSF flag.

0: No effect

1: Clear LSECSSF flag

Bit 8 CSSC : Clock security system interrupt clear

This bit is set by software to clear the HSECSSF flag.

0: No effect

1: Clear CSSF flag

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 PLLRDYC : PLL ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.

0: No effect

1: Clear PLLRDYF flag

Bit 4 HSERDYC : HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.

0: No effect

1: Clear HSERDYF flag

Bit 3 HSIRDYC : HSI16 ready interrupt clear

This bit is set software to clear the HSIRDYF flag.

0: No effect

1: Clear HSIRDYF flag

Bit 2 HSI48RDYC : HSI48 ready interrupt clear

This bit is set software to clear the HSI48RDYF flag.

0: No effect

1: Clear HSI48RDYF flag

Bit 1 LSERDYC : LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.

0: No effect

1: Clear LSERDYF flag

Bit 0 LSIRDYC : LSI ready interrupt clear

This bit is set by software to clear the LSIRDF flag.

0: No effect

1: Clear LSIRDF flag

5.4.9 I/O port reset register (RCC_IOPRSTR)

Address Offset: 0x24

Reset value: 0x0000 0000

1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 GPIOFRST : I/O port F reset

This bit is set and cleared by software.

0: no effect

1: Reset I/O port F

Bit 4 GPIOERST : I/O port E reset ⁽¹⁾

This bit is set and cleared by software.

0: no effect

1: Reset I/O port E

Bit 3 GIODRST : I/O port D reset

This bit is set and cleared by software.

0: no effect

1: Reset I/O port D

Bit 2 GPIOCRST : I/O port C reset

This bit is set and cleared by software.

0: no effect

1: Reset I/O port C

Bit 1 GPIOBRST : I/O port B reset

This bit is set and cleared by software.

0: no effect

1: Reset I/O port B

Bit 0 GPIOARST : I/O port A reset

This bit is set and cleared by software.

0: no effect

1: Reset I/O port A

5.4.10 AHB peripheral reset register (RCC_AHBRSTR)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 RNGRST : Random number generator reset

Set and cleared by software.

0: No effect

1: Reset RNG

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 17 Reserved, must be kept at reset value.

Bit 16 AESRST : AES hardware accelerator reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset AES

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 RCRST : CRC reset

Set and cleared by software.

0: No effect

1: Reset CRC

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLASHRST : Flash memory interface reset

Set and cleared by software.

0: No effect

1: Reset flash memory interface

This bit can only be set when the flash memory is in power down mode.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 DMA2RST : DMA2 and DMAMUX reset

Set and cleared by software.

0: No effect

1: Reset DMA2 and DMAMUX

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals.

Bit 0 DMA1RST : DMA1 and DMAMUX reset

Set and cleared by software.

0: No effect

1: Reset DMA1 and DMAMUX

5.4.11 APB peripheral reset register 1 (RCC_APBHRSTR1)

Address offset: 0x2C

Reset value: 0x0000 0000

Bit 31 LPTIM1RST : Low Power Timer 1 reset

Set and cleared by software.

0: No effect

1: Reset LPTIM1

Bit 30 LPTIM2RST : Low Power Timer 2 reset

Set and cleared by software.

0: No effect

1: Reset LPTIM2

Bit 29 DAC1RST : DAC1 interface reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset DAC1 interface

Bit 28 PWRRST : Power interface reset

Set and cleared by software.

0: No effect

1: Reset PWR

Bit 27 DBGIRST : Debug support reset

Set and cleared by software.

0: No effect

1: Reset DBG

Bit 26 UCPD2RST : UCPD2 reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset UCPD2

Bit 25 UCPD1RST : UCPD1 reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset UCPD1

Bit 24 CECRST : HDMI CEC reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset the HDMI CEC

Bit 23 I2C3RST : I2C3 reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset I2C3

Bit 22 I2C2RST : I2C2 reset

Set and cleared by software.

0: No effect

1: Reset I2C2

Bit 21 I2C1RST : I2C1 reset

Set and cleared by software.

0: No effect

1: Reset I2C1

Bit 20 LPUART1RST : LPUART1 reset

Set and cleared by software.

0: No effect

1: Reset LPUART1

Bit 19 USART4RST : USART4 reset

Set and cleared by software.

0: No effect

1: Reset USART4

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 18 USART3RST : USART3 reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset USART3

Note:

Bit 17 USART2RST : USART2 reset
Set and cleared by software.

0: No effect

1: Reset USART2

Bit 16 CRSRST : CRS reset
Set and cleared by software.

0: No effect

1: Reset CRS

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 15 SPI3RST : SPI3 reset
Set and cleared by software.

0: No effect

1: Reset SPI3

Bit 14 SPI2RST : SPI2 reset
Set and cleared by software.

0: No effect

1: Reset SPI2

Bit 13 USBRST : USB reset ⁽¹⁾
Set and cleared by software.

0: No effect

1: Reset USB

Bit 12 FDCANRST : FDCAN reset ⁽¹⁾
Set and cleared by software.

0: No effect

1: Reset FDCAN

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 USART6RST : USART3 reset ⁽¹⁾
Set and cleared by software.

0: No effect

1: Reset USART6

Bit 8 USART5RST : USART3 reset ⁽¹⁾
Set and cleared by software.

0: No effect

1: Reset USART5

Bit 7 LPUART2RST : LPUART2 reset ⁽¹⁾
Set and cleared by software.

0: No effect

1: Reset LPUART2

Bit 6 Reserved, must be kept at reset value.

Bit 5 TIM7RST : TIM7 timer reset ⁽¹⁾
Set and cleared by software.

0: No effect

1: Reset TIM7

Bit 4 TIM6RST : TIM6 timer reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset TIM6

Bit 3 Reserved, must be kept at reset value.

Bit 2 TIM4RST : TIM3 timer reset ⁽¹⁾

Set and cleared by software.

0: No effect

1: Reset TIM4

Bit 1 TIM3RST : TIM3 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM3

Bit 0 TIM2RST : TIM2 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM2

1. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

5.4.12 APB peripheral reset register 2 (RCC_APBHRSTR2)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADCRST : ADC reset

Set and cleared by software.

0: No effect

1: Reset ADC

Bit 19 Reserved, must be kept at reset value.

Bit 18 TIM17RST : TIM16 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM17 timer

Bit 17 TIM16RST : TIM16 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM16 timer

Bit 16 TIM15RST : TIM15 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM15 timer

Bit 15 TIM14RST : TIM14 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM14 timer

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 14 USART1RST : USART1 reset

Set and cleared by software.

0: No effect

1: Reset USART1

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1RST : SPI1 reset

Set and cleared by software.

0: No effect

1: Reset SPI1

Bit 11 TIM1RST : TIM1 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM1 timer

Bits 10:1 Reserved, must be kept at reset value.

Bit 0 SYSCFGRST : SYSCFG, COMP and VREFBUF reset

Set and cleared by software.

0: No effect

1: Reset SYSCFG + COMP + VREFBUF

5.4.13 I/O port clock enable register (RCC_IOPENR)

Address Offset: 0x34

Reset value: 0x0000 0000

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 GPIOFEN : I/O port F clock enable

This bit is set and cleared by software.

0: Disable

1: Enable

Bit 4 GPIOEEN : I/O port E clock enable

This bit is set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 3 GPIODEN : I/O port D clock enable

This bit is set and cleared by software.

0: Disable

1: Enable

Bit 2 GPIOCEN : I/O port C clock enable

This bit is set and cleared by software.

0: Disable

1: Enable

Bit 1 GPIOBEN : I/O port B clock enable

This bit is set and cleared by software.

0: Disable

1: Enable

Bit 0 GPIOAEN : I/O port A clock enable

This bit is set and cleared by software.

0: Disable

1: Enable

5.4.14 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x38

Reset value: 0x0000 0100

This register individually enables clocks to AHB peripherals. In Sleep and Stop modes, a clock enabled through this register is only supplied to the peripheral if the corresponding bit of the RCC_AHBSMENR register is also set.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 RNGEN : Random number generator clock enable

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 17 Reserved, must be kept at reset value.

Bit 16 AESEN : AES hardware accelerator

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CRCEN : CRC clock enable

Set and cleared by software.

0: Disable

1: Enable

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLASHEN : Flash memory interface clock enable

Set and cleared by software.

0: Disable

1: Enable

This bit can only be cleared when the flash memory is in power down mode.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 DMA2EN : DMA2 and DMAMUX clock enable

Set and cleared by software.

0: Disable

1: Enable

DMAMUX is enabled as long as at least one DMA peripheral is enabled.

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 0 DMA1EN : DMA1 and DMAMUX clock enable

Set and cleared by software.

0: Disable

1: Enable

DMAMUX is enabled as long as at least one DMA peripheral is enabled.

5.4.15 APB peripheral clock enable register 1 (RCC_APBENR1)

Address offset: 0x3C

Reset value: 0x0000 0000

This register individually enables clocks to APB peripherals. In Sleep and Stop modes, a clock enabled through this register is only supplied to the peripheral if the corresponding bit of the RCC_APBSMENR1 register is also set.

Bit 31 LPTIM1EN : LPTIM1 clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 30 LPTIM2EN : LPTIM2 clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 29 DAC1EN : DAC1 interface clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 28 PWREN : Power interface clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 27 DBGEN : Debug support clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 26 UCPD2EN : UCPD2 clock enable ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

Bit 25 UCPD1EN : UCPD1 clock enable ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

Bit 24 CECEN : HDMI CEC clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 23 I2C3EN : I2C3 clock enable ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

1. Bit 22 I2C2EN : I2C2 clock enable
   Set and cleared by software.
   0: Disable
   1: Enable
2. Bit 21 I2C1EN : I2C1 clock enable
   Set and cleared by software.
   0: Disable
   1: Enable
3. Bit 20 LPUART1EN : LPUART1 clock enable
   Set and cleared by software.
   0: Disable
   1: Enable
4. Bit 19 USART4EN : USART4 clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
5. Bit 18 USART3EN : USART3 clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
6. Bit 17 USART2EN : USART2 clock enable
   Set and cleared by software.
   0: Disable
   1: Enable
7. Bit 16 CRSEN : CRS clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
8. Bit 15 SPI3EN : SPI3 clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
9. Bit 14 SPI2EN : SPI2 clock enable
   Set and cleared by software.
   0: Disable
   1: Enable
10. Bit 13 USBEN : USB clock enable ⁽¹⁾
    Set and cleared by software.
    0: Disable
    1: Enable
11. Bit 12 FDCANEN : FDCAN clock enable ⁽¹⁾
    Set and cleared by software.
    0: Disable
    1: Enable

1. Bit 11 WWDGEN : WWDG clock enable
   Set by software to enable the window watchdog clock. Cleared by hardware system reset
   0: Disable
   1: Enable
   This bit can also be set by hardware if the WWDG_SW option bit is 0.
2. Bit 10 RTCAPBEN : RTC APB clock enable
   Set and cleared by software.
   0: Disable
   1: Enable
3. Bit 9 USART6EN : USART6 clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
4. Bit 8 USART5EN : USART5 clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
5. Bit 7 LPUART2EN : LPUART2 clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
6. Bit 6 Reserved, must be kept at reset value.
7. Bit 5 TIM7EN : TIM7 timer clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
8. Bit 4 TIM6EN : TIM6 timer clock enable ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
9. Bit 3 Reserved, must be kept at reset value.
10. Bit 2 TIM4EN : TIM4 timer clock enable ⁽¹⁾
    Set and cleared by software.
    0: Disable
    1: Enable
11. Bit 1 TIM3EN : TIM3 timer clock enable
    Set and cleared by software.
    0: Disable
    1: Enable
12. Bit 0 TIM2EN : TIM2 timer clock enable
    Set and cleared by software.
    0: Disable
    1: Enable

1. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

5.4.16 APB peripheral clock enable register 2(RCC_APBENR2)

Address offset: 0x40

Reset value: 0x0000 0000

This register individually enables clocks to APB peripherals. In Sleep and Stop modes, a clock enabled through this register is only supplied to the peripheral if the corresponding bit of the RCC_APBSMENR2 register is also set.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADCEN : ADC clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 19 Reserved, must be kept at reset value.

Bit 18 TIM17EN : TIM16 timer clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 17 TIM16EN : TIM16 timer clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 16 TIM15EN : TIM15 timer clock enable

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 15 TIM14EN : TIM14 timer clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 14 USART1EN : USART1 clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1EN : SPI1 clock enable

Set and cleared by software.

0: Disable

1: Enable

Bit 11 TIM1EN : TIM1 timer clock enable

Set and cleared by software.

0: Disable

1: Enable

Bits 10:1 Reserved, must be kept at reset value.

Bit 0 SYSCFGEN : SYSCFG, COMP and VREFBUF clock enable

Set and cleared by software.

0: Disable

1: Enable

5.4.17 I/O port in Sleep mode clock enable register (RCC_IOPSMENR)

Address offset: 0x44

Reset value: 0x0000 003F

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 GPIOFSMEN : I/O port F clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 4 GPIOESMEN : I/O port E clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 3 GIOPDSMEN : I/O port D clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 2 GPIOCSMEN : I/O port C clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 1 GPIOBSMEN : I/O port B clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 0 GPIOAMEN : I/O port A clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

5.4.18 AHB peripheral clock enable in Sleep/Stop mode register (RCC_AHBSMENR)

Address offset: 0x48

Reset value: 0x0005 1303

This register can individually program which AHB peripheral clocks are disabled (bit cleared) upon the device entering Sleep or Stop mode. When a bit of this register is set (enable), the corresponding peripheral clock is supplied in Sleep or Stop mode according to the setting of the RCC_AHBENR register.

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 RNGSMEN : RNG clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 17 Reserved, must be kept at reset value.

Bit 16 AESSMEN : AES hardware accelerator clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CRCSMEN : CRC clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bits 11:10 Reserved, must be kept at reset value.

Bit 9 SRAMSMEN : SRAM clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 8 FLASHSMEN : Flash memory interface clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 DMA2SMEN : DMA2 and DMAMUX clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 0 DMA1SMEN : DMA1 and DMAMUX clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.

5.4.19 APB peripheral clock enable in Sleep/Stop mode register 1 (RCC_APBSMENR1)

Address offset: 0x4C

Reset value: 0xFFFF FFB7

This register can individually program which APB peripheral clocks are disabled (bit cleared) upon the device entering Sleep or Stop mode. When a bit of this register is set (enable), the corresponding peripheral clock is supplied in Sleep or Stop mode according to the setting of the RCC_APBENR1 register.

Bit 31 LPTIM1SMEN : Low Power Timer 1 clock enable during Sleep and Stop modes

Set and cleared by software.

0: Disable

1: Enable

Bit 30 LPTIM2SMEN : Low Power Timer 2 clock enable during Sleep and Stop modes

Set and cleared by software.

0: Disable

1: Enable

Bit 29 DAC1SMEN : DAC1 interface clock enable during Sleep and Stop modes ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

Bit 28 PWRSMEN : Power interface clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 27 DBGSMEN : Debug support clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 26 UCPD2SMEN : UCPD2 clock enable during Sleep mode ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

Bit 25 UCPD1SMEN : UCPD1 clock enable during Sleep mode ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

Bit 24 CECSMEN : HDMI CEC clock enable during Sleep and Stop modes ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

Bit 23 I2C3SMEN : I2C3 clock enable during Sleep mode ⁽¹⁾

Set and cleared by software.

0: Disable

1: Enable

1. Bit 22 I2C2SMEN : I2C2 clock enable during Sleep mode
   Set and cleared by software.
   0: Disable
   1: Enable
2. Bit 21 I2C1SMEN : I2C1 clock enable during Sleep and Stop modes
   Set and cleared by software.
   0: Disable
   1: Enable
3. Bit 20 LPUART1SMEN : LPUART1 clock enable during Sleep and Stop modes
   Set and cleared by software.
   0: Disable
   1: Enable
4. Bit 19 USART4SMEN : USART4 clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
5. Bit 18 USART3SMEN : USART3 clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
6. Bit 17 USART2SMEN : USART2 clock enable during Sleep and Stop modes
   Set and cleared by software.
   0: Disable
   1: Enable
7. Bit 16 CRSSMEN : CRS clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
8. Bit 15 SPI3SMEN : SPI3 clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
9. Bit 14 SPI2SMEN : SPI2 clock enable during Sleep mode
   Set and cleared by software.
   0: Disable
   1: Enable
10. Bit 13 USBSMEN : USB clock enable during Sleep mode ⁽¹⁾
    Set and cleared by software.
    0: Disable
    1: Enable
11. Bit 12 FDCANSMEN : FDCAN clock enable during Sleep mode ⁽¹⁾
    Set and cleared by software.
    0: Disable
    1: Enable

1. Bit 11 WWDGSMEN : WWDG clock enable during Sleep mode
   Set and cleared by software.
   0: Disable
   1: Enable
2. Bit 10 RTCPBSMEN : RTC APB clock enable during Sleep mode
   Set and cleared by software.
   0: Disable
   1: Enable
3. Bit 9 USART6SMEN : USART6 clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
4. Bit 8 USART5SMEN : USART5 clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
5. Bit 7 LPUART2SMEN : LPUART2 clock enable during Sleep and Stop modes ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
6. Bit 6 Reserved, must be kept at reset value.
7. Bit 5 TIM7SMEN : TIM7 timer clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
8. Bit 4 TIM6SMEN : TIM6 timer clock enable during Sleep mode ⁽¹⁾
   Set and cleared by software.
   0: Disable
   1: Enable
9. Bit 3 Reserved, must be kept at reset value.
10. Bit 2 TIM4SMEN : TIM4 timer clock enable during Sleep mode ⁽¹⁾
    Set and cleared by software.
    0: Disable
    1: Enable
11. Bit 1 TIM3SMEN : TIM3 timer clock enable during Sleep mode
    Set and cleared by software.
    0: Disable
    1: Enable
12. Bit 0 TIM2SMEN : TIM2 timer clock enable during Sleep mode
    Set and cleared by software.
    0: Disable
    1: Enable

1. 1. Only significant on devices integrating the corresponding peripheral, otherwise reserved with zero reset value. Refer to Section 1.4: Availability of peripherals .

5.4.20 APB peripheral clock enable in Sleep/Stop mode register 2 (RCC_APBSMENR2)

Address offset: 0x50

Reset value: 0x0017 D801

This register can individually program which APB peripheral clocks are disabled (bit cleared) upon the device entering Sleep or Stop mode. When a bit of this register is set (enable), the corresponding peripheral clock is supplied in Sleep or Stop mode according to the setting of the RCC_APBENR2 register.

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ADC SMEN : ADC clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 19 Reserved, must be kept at reset value.

Bit 18 TIM17 SMEN : TIM16 timer clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 17 TIM16 SMEN : TIM16 timer clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 16 TIM15 SMEN : TIM15 timer clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Note: Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bit 15 TIM14 SMEN : TIM14 timer clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 14 USART1 SMEN : USART1 clock enable during Sleep and Stop modes

Set and cleared by software.

0: Disable

1: Enable

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1SMEN : SPI1 clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bit 11 TIM1SMEN : TIM1 timer clock enable during Sleep mode

Set and cleared by software.

0: Disable

1: Enable

Bits 10:1 Reserved, must be kept at reset value.

Bit 0 SYSCFGSMEN : SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes

Set and cleared by software.

0: Disable

1: Enable

5.4.21 Peripherals independent clock configuration register (RCC_CCIPR)

Address Offset: 0x54

Reset value: 0x0000 0000

Bits 31:30 ADCSEL[1:0] : ADCs clock source selection

This bitfield is controlled by software to select the clock source for ADC:

00: System clock

01: PLLPCLK

10: HSI16

11: Reserved

Bits 29:28 RNGDIV[1:0] : Division factor of RNG clock divider ⁽¹⁾

This bitfield is controlled by software to select the division factor as follows:

00: 1

01: 2

10: 4

11: 8

Bits 27:26 RNGSEL[1:0] : RNG clock source selection ⁽¹⁾

This bitfield is controlled by software to select the RNG clock as follows:

00: No clock

01: HSI16

10: SYSCLK

11: PLLQCLK

Bit 25 Reserved, must be kept at reset value.

Bit 24 TIM15SEL : TIM15 clock source selection ⁽¹⁾

This bit is set and cleared by software. It selects TIM15 clock source as follows:

0: TIMPCLK

1: PLLQCLK

Bit 23 Reserved, must be kept at reset value.

Bit 22 TIM1SEL : TIM1 clock source selection

This bit is set and cleared by software. It selects TIM1 clock source as follows:

0: TIMPCLK

1: PLLQCLK ⁽¹⁾

Bits 21:20 LPTIM2SEL[1:0] : LPTIM2 clock source selection

This bitfield is controlled by software to select LPTIM2 clock source as follows:

00: PCLK

01: LSI

10: HSI16

11: LSE

Bits 19:18 LPTIM1SEL[1:0] : LPTIM1 clock source selection

This bitfield is controlled by software to select LPTIM1 clock source as follows:

00: PCLK

01: LSI

10: HSI16

11: LSE

Bits 17:16 Reserved, must be kept at reset value.

Bits 15:14 I2C2I2S1SEL[1:0] : I2C2/I2S1 clock source selection

This bitfield is controlled by software to select I2S1/I2C2 clock source as follows:

00: PCLK/SYSCLK

01: SYSCLK/PLLPCLK

10: HSI16/HSI16

11: Reserved/I2S_CKIN

Note: On the STM32G0B1xx and STM32G0C1xx, the bitfield selects the clock to the I2C2 peripheral. On the other devices, it selects the clock to the I2S1 peripheral.

Bits 13:12 I2C1SEL[1:0] : I2C1 clock source selection

This bitfield is controlled by software to select I2C1 clock source as follows:

00: PCLK

01: SYSCLK

10: HSI16

11: Reserved

Bits 11:10 LPUART1SEL[1:0] : LPUART1 clock source selection

This bitfield is controlled by software to select LPUART1 clock source as follows:

00: PCLK

01: SYSCLK

10: HSI16

11: LSE

Bits 9:8 LPUART2SEL[1:0] : LPUART2 clock source selection ⁽¹⁾

This bitfield is controlled by software to select LPUART2 clock source as follows:

• 00: PCLK
• 01: SYSCLK
• 10: HSI16
• 11: LSE

Bit 7 Reserved, must be kept at reset value.

Bit 6 CECSEL : HDMI CEC clock source selection

This bit is set and cleared by software. It selects the HDMI CEC clock source as follows:

• 0: HSI16 divided by 488
• 1: LSE

Bits 5:4 USART3SEL[1:0] : USART3 clock source selection ⁽¹⁾

This bitfield is controlled by software to select USART2 clock source as follows:

• 00: PCLK
• 01: SYSCLK
• 10: HSI16
• 11: LSE

Bits 3:2 USART2SEL[1:0] : USART2 clock source selection ⁽¹⁾

This bitfield is controlled by software to select USART2 clock source as follows:

• 00: PCLK
• 01: SYSCLK
• 10: HSI16
• 11: LSE

Bits 1:0 USART1SEL[1:0] : USART1 clock source selection

This bitfield is controlled by software to select USART1 clock source as follows:

• 00: PCLK
• 01: SYSCLK
• 10: HSI16
• 11: LSE

1. Only significant on devices integrating the corresponding peripheral supporting independent clock selection (or supporting the corresponding function), otherwise reserved. Refer to Section 1.4: Availability of peripherals and Section 33.4: USART implementation .

5.4.22 Peripherals independent clock configuration register 2 (RCC_CCIPR2)

This register is only available on STM32G0B1xx and STM32G0C1xx. Reserved on the other devices.

Address Offset: 0x58

Reset value: 0x0000 0000

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:12 USBSEL[1:0] : USB clock source selection

This bitfield is controlled by software to select the USB clock as follows:

00: HSI48

01: HSE

10: PLLQCLK

11: Reserved

Note: This bitfield is only significant on devices integrating the corresponding peripheral and clock, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 11:10 Reserved, must be kept at reset value.

Bits 9:8 FDCANSEL[1:0] : FDCAN clock source selection

This bitfield is controlled by software to select the FDCAN clock as follows:

00: PCLK

01: PLLQCLK

10: HSE

11: Reserved

Note: This bitfield is only significant on devices integrating the corresponding peripheral and clock, otherwise reserved. Refer to Section 1.4: Availability of peripherals .

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:2 I2S2SEL[1:0] : I2S2 clock source selection

This bitfield is controlled by software to select I2S2 clock source as follows:

00: SYSCLK

01: PLLPCLK

10: HSI16

11: External I2S clock selected as I2S2

Bits 1:0 I2S1SEL[1:0] : I2S1 clock source selection

This bitfield is controlled by software to select I2S1 clock source as follows:

00: SYSCLK

01: PLLPCLK

10: HSI16

11: External I2S clock selected as I2S1

5.4.23 RTC domain control register (RCC_BDCR)

Up to three wait states are inserted in case of successive accesses to this register. As this register is outside of the \( V_{CORE} \) domain, it is write-protected upon reset. The DBP bit of the Power control register 1 (PWR_CR1) must be set to allow their modification. Refer to Section 4.1.2: Battery backup of RTC domain on page 115 for further information.

The register bits are only reset upon RTC domain reset (see Section 5.1.3: RTC domain reset ), except the LSCOSEL, LSCOEN, and BDRST bits that are only reset upon RTC domain power-on reset. Any internal or external reset has no effect on these bits.

Address offset: 0x5C

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LSCOSEL : Low-speed clock output selection

Set and cleared by software to select the low-speed output clock:

0: LSI

1: LSE

Bit 24 LSCOEN : Low-speed clock output (LSCO) enable

Set and cleared by software.

0: Disable

1: Enable

Bits 23:17 Reserved, must be kept at reset value.

Bit 16 BDRST : RTC domain software reset

Set and cleared by software to reset the RTC domain:

0: No effect

1: Reset

Bit 15 RTCEN : RTC clock enable

Set and cleared by software. The bit enables clock to RTC and TAMP.

0: Disable

1: Enable

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0] : RTC clock source selection

Set by software to select the clock source for the RTC as follows:

00: No clock

01: LSE

10: LSI

11: HSE divided by 32

Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00.

Bit 7 Reserved, must be kept at reset value.

Bit 6 LSECSSD : CSS on LSE failure Detection

Set by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):

0: No failure detected

1: Failure detected

Caution: When the LSECSSD bit is set, the LSE oscillator is held under reset and can't be restarted. To clear the LSECSSD bit, reset the RTC domain using BDRST bit.

Bit 5 LSECSSON : CSS on LSE enable

Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:

0: Disable
1: Enable

LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit.

Bits 4:3 LSEDRV[1:0] : LSE oscillator drive capability

Set by software to select the LSE oscillator drive capability as follows:

00: low driving capability
01: medium-low driving capability
10: medium-high driving capability
11: high driving capability

Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.

Bit 2 LSEBYP : LSE oscillator bypass

Set and cleared by software to bypass the LSE oscillator.

0: Not bypassed
1: Bypassed

This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0).

Bit 1 LSERDY : LSE oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):

0: Not ready
1: Ready

After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.

Bit 0 LSEON : LSE oscillator enable

Set and cleared by software to enable LSE oscillator:

0: Disable
1: Enable

5.4.24 Control/status register (RCC_CSR)

Up to three wait states are inserted in case of successive accesses to this register. The register is reset upon system reset, except for reset flags that are only reset upon power reset.

Address Offset: 0x60

Reset value: 0xXX00 0000

Bit 31 LPWRRSTF : Low-power reset flag

Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry.
Cleared by setting the RMVF bit.

0: No illegal mode reset occurred

1: Illegal mode reset occurred

This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared.

Bit 30 WWDGRSTF : Window watchdog reset flag

Set by hardware when a window watchdog reset occurs.

Cleared by setting the RMVF bit.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Bit 29 IWDGRSTF : Independent window watchdog reset flag

Set by hardware when an independent watchdog reset domain occurs.

Cleared by setting the RMVF bit.

0: No independent watchdog reset occurred

1: Independent watchdog reset occurred

Bit 28 SFTRSTF : Software reset flag

Set by hardware when a software reset occurs.

Cleared by setting the RMVF bit.

0: No software reset occurred

1: Software reset occurred

Bit 27 PWRRSTF : BOR or POR/PDR flag

Set by hardware when a BOR or POR/PDR occurs.

Cleared by setting the RMVF bit.

0: No BOR or POR occurred

1: BOR or POR occurred

Bit 26 PINRSTF : Pin or system reset flag

Set by hardware when a reset from the PF2-NRST pin occurs or when a system reset is triggered by any other source. Cleared by setting the RMVF bit.

0: No system reset occurred

1: System reset from PF2-NRST pin or from other source occurred

Bit 25 OBLRSTF : Option byte loader reset flag

Set by hardware when a reset from the Option byte loading occurs.

Cleared by setting the RMVF bit.

0: No reset from Option byte loading occurred

1: Reset from Option byte loading occurred

Bit 24 Reserved, must be kept at reset value.

Bit 23 RMVF : Remove reset flags

Set by software to clear the reset flags.

0: No effect

1: Clear reset flags

Bits 22:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY : LSI oscillator ready

Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):

0: Not ready

1: Ready

After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.

Bit 0 LSION : LSI oscillator enable

Set and cleared by software to enable/disable the LSI oscillator:

0: Disable

1: Enable

5.4.25 RCC register map

The following table gives the RCC register map and the reset values.

Table 37. RCC register map and reset values

Table 37. RCC register map and reset values (continued)

Table 37. RCC register map and reset values (continued)

Table 37. RCC register map and reset values (continued)

Refer to Section 2.2 on page 60 for the register boundary addresses.