4. Power control (PWR)

4.1 Power supplies

The STM32G0x1 devices require a 1.7 V to 3.6 V operating supply voltage ( \( V_{DD} \) ). Several different power supplies are provided to specific peripherals:

• • \( V_{DD} = 1.7 \text{ V (1.60 V) to } 3.6 \text{ V} \)

\( V_{DD} \) is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin.

Note that the minimum voltage of 1.7 V corresponds to power-on reset release threshold \( V_{POR(MAX)} \) . Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold \( V_{PDR(MIN)} \) .

• • \( V_{DDA} = 1.62 \text{ V (ADC and COMP) / } 1.8 \text{ V (DAC) / } 2.4 \text{ V (VREFBUF) to } 3.6 \text{ V} \)

\( V_{DDA} \) is the analog power supply for the A/D converter, D/A converters, voltage reference buffer and comparators. \( V_{DDA} \) voltage level is identical to \( V_{DD} \) voltage as it is provided externally through VDD/VDDA pin.

• • \( V_{DDIO1} = V_{DD} \)

\( V_{DDIO1} \) is the power supply for the I/Os. \( V_{DDIO1} \) voltage level is identical to \( V_{DD} \) voltage as it is provided externally through VDD/VDDA pin.

• • \( V_{DDIO2} = 1.6 \text{ to } 3.6 \text{ V (only available on STM32G0B1xx and STM32G0C1xx)} \)

\( V_{DDIO2} \) is the power supply from VDDIO2 pin for selected I/Os. Although \( V_{DDIO2} \) is independent of \( V_{DD} \) or \( V_{DDA} \) , it must not be applied without valid \( V_{DD} \) .

• • \( V_{BAT} = 1.55 \text{ V to } 3.6 \text{ V} \)

\( V_{BAT} \) is the power supply (through a power switch) for RTC, TAMP, low-speed external 32.768 kHz oscillator and backup registers when \( V_{DD} \) is not present. \( V_{BAT} \) is provided externally through VBAT pin. When this pin is not available on the package, it is internally bonded to VDD/VDDA.

• • \( V_{REF+} \) is the input reference voltage for the ADC and DAC, or the output of the internal voltage reference buffer (when enabled). When \( V_{DDA} < 2 \text{ V} \) , \( V_{REF+} \) must be equal to \( V_{DDA} \) . When \( V_{DDA} \geq 2 \text{ V} \) , \( V_{REF+} \) must be between 2 V and \( V_{DDA} \) . It can be grounded when the ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register:

• – \( V_{REF+} \) around 2.048 V (requiring \( V_{DDA} \) equal to or higher than 2.4 V)
• – \( V_{REF+} \) around 2.5 V (requiring \( V_{DDA} \) equal to or higher than 2.8 V)

\( V_{REF+} \) is delivered through VREF+ pin. On packages without VREF+ pin, \( V_{REF+} \) is internally connected with \( V_{DD} \) , and the internal voltage reference buffer must be kept disabled (refer to datasheets for package pinout description).

• • \( V_{CORE} \) is an internal supply for digital peripherals, SRAM and flash memory. It is produced by an embedded linear voltage regulator. On top of \( V_{CORE} \) , the flash memory is also powered from \( V_{DD} \) .

Figure 5. Power supply overview

4.1.1 ADC and DAC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to V _REF+ a separate reference voltage lower than V _DDA . V _REF+ is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal.

V _REF+ can be provided either by an external reference or by an internal buffered voltage reference (VREFBUF).

The internal buffered voltage reference is enabled by setting the ENVR bit in the VREFBUF control and status register (VREFBUF_CSR) . The internal buffered voltage reference is set to 2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal buffered voltage reference can also provide the voltage to external components through V _REF+ pin. Refer to the device datasheet and to Section 17: Voltage reference buffer (VREFBUF) for further information.

4.1.2 Battery backup of RTC domain

To retain the content of the backup registers and supply the RTC and TAMP functions when V _DD is turned off, the V _BAT pin can be connected to an optional backup voltage supplied by a battery or by another source.

The V _BAT pin powers the RTC and TAMP units, the LSE oscillator and the PC13 to PC15 I/Os, allowing the RTC and TAMP to operate even when the main power supply is turned off. The switch to the V _BAT supply is controlled by the power-down reset embedded in the Reset block.

Warning: During \( t_{RSTTEMPO} \) (temporization at \( V_{DD} \) startup) or after a PDR has been detected, the power switch between \( V_{BAT} \) and \( V_{DD} \) remains connected to \( V_{BAT} \) .
During the startup phase, if \( V_{DD} \) is established in less than \( t_{RSTTEMPO} \) (refer to the datasheet for the value of \( t_{RSTTEMPO} \) ) and \( V_{DD} > V_{BAT} + 0.6 \) V, a current may be injected into \( V_{BAT} \) through an internal diode connected between \( V_{DD} \) and the power switch ( \( V_{BAT} \) ).
If the power supply/battery connected to the VBAT pin cannot support this current injection, it is recommended to connect an external low-drop diode between this power supply and the VBAT pin.

If no external battery is used in the user application, it is recommended to connect VBAT pin externally to VDD/VDDA pin with a 100 nF external ceramic decoupling capacitor.

When the RTC domain is supplied by \( V_{DD} \) (power switch connected to \( V_{DD} \) ), all the related pin functions are available:

When the RTC domain is supplied by \( V_{BAT} \) (power switch connected to \( V_{BAT} \) because \( V_{DD} \) is not present), only the following functions are available:

• • PC13, PC14 and PC15 can be controlled only by RTC, TAMP or LSE (refer to Section 30.3: RTC functional description )
• • RTC_OUT1 function on PC13
• • RTC_TS function on PC13 or PA4
• • TAMP_IN1 function on PC13 or PA4 and TAMP_IN2 function on PA0

Note: Due to the fact that the power switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive a LED).

RTC domain access

After a system reset, the RTC domain (RTC registers and backup registers) is protected against possible unwanted write accesses. To enable access to the RTC domain, proceed as follows:

1. 1. Enable the power interface clock by setting the PWREN bits of the APB peripheral clock enable register 1 (RCC_APBENR1) .
2. 2. Set the DBP bit of the Power control register 1 (PWR_CR1) to enable access to the RTC domain.
3. 3. Select the RTC clock source in the RTC domain control register (RCC_BDCR) .
4. 4. Enable the RTC clock by setting the RTCEN bit in the RTC domain control register (RCC_BDCR) .

VBAT battery charging

When \( V_{DD} \) is present, it is possible to charge the external battery on VBAT through an internal resistance.

The VBAT charging is done either through a 5 k \( \Omega \) resistor or through a 1.55 k \( \Omega \) resistor depending on the VBRS bit value in the PWR_CR4 register.

The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is automatically disabled in VBAT mode.

4.1.3 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the RTC domain. The main regulator output voltage ( \( V_{CORE} \) ) can be programmed by software to two different power ranges (Range 1 and Range 2) in order to optimize the consumption depending on the system maximum operating frequency (refer to Section 5.2.8: Clock source frequency versus voltage scaling and to Section 3.3.4: FLASH read access latency ).

The voltage regulators are always enabled after a reset. Depending on the user application modes, the \( V_{CORE} \) supply is provided either by the main regulator (MR) or by the low-power regulator (LPR).

• • In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator (MR) supplies full power to the \( V_{CORE} \) domain (core, memories and digital peripherals).
• • In Low-power run and Low-power sleep modes, the main regulator is off and the low-power regulator (LPR) supplies low-power to the \( V_{CORE} \) domain, preserving the contents of the registers and SRAM.
• • In Stop 1 mode, the main regulator is off and the low-power regulator (LPR) supplies low-power to the \( V_{CORE} \) domain, preserving the contents of the registers and SRAM.
• • In Standby mode with SRAM content preserved (RRS bit is set in the PWR_CR3 register), the main regulator (MR) is off and the low-power regulator (LPR) provides the supply to SRAM only. The core and digital peripherals (except Standby circuitry and RTC domain) are powered off.
• • In Standby mode, both regulators are powered off. The contents of the registers and SRAM is lost except for the Standby circuitry and the RTC domain.
• • In Shutdown mode, both regulators are powered off. When exiting Shutdown mode, a power-on reset is generated. Consequently, the contents of the registers and SRAM is lost, except for the RTC domain.

4.1.4 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals ( \( V_{\text{CORE}} \) ), according to the application performance and power consumption needs.

Dynamic voltage scaling to increase \( V_{\text{CORE}} \) is known as overvolting. It allows to improve the device performance.

Dynamic voltage scaling to decrease \( V_{\text{CORE}} \) is known as undervolting. It is performed to save power, particularly in laptop and other mobile devices where the energy comes from a battery and is thus limited.

Two voltage ranges are available:

• • Range 1: High-performance range

The main regulator provides a typical output voltage at 1.2 V. The system clock frequency can be up to 64 MHz. The flash memory access time for read access is minimum, write and erase operations are possible.

• • Range 2: Low-power range

The main regulator provides a typical output voltage at 1.0 V. The system clock frequency can be up to 16 MHz. The flash memory access time for a read access is increased as compared to Range 1; write and erase operations are not possible.

The voltage scaling is selected through the VOS bit in the PWR_CR1 register.

The sequence to go from Range 1 to Range 2 is:

1. 1. Reduce the system frequency to a value lower than 16 MHz
2. 2. Adjust number of wait states according new frequency target in Range 2 (LATENCY bits in the FLASH_ACR).
3. 3. Program the VOS[1:0] bits to 10 in the Power control register 1 (PWR_CR1) .

The sequence to go from Range 2 to Range 1 is:

1. 1. Program the VOS[1:0] bits to 01 in the Power control register 1 (PWR_CR1) .
2. 2. Wait until the VOSF flag is cleared in the Power status register 2 (PWR_SR2) .
3. 3. Adjust number of wait states according new frequency target in Range 1 (LATENCY bits in the FLASH access control register (FLASH_ACR) ).
4. 4. Increase the system frequency.

4.2 Power supply supervisor

4.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR)

The device features an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The POR/PDR is active in all power modes. The BOR can be enabled or disabled only through option bytes. It is not available in Shutdown mode.

When the BOR is enabled, four BOR levels can be selected through option bytes, with independent configuration for rising and falling thresholds. During power-on, the BOR keeps the device under reset until the \( V_{DD} \) supply voltage reaches the specified BOR rising threshold ( \( V_{BORRx} \) ). At this point, the device reset is released and the system can start. During power-down, when \( V_{DD} \) drops below the selected BOR falling threshold ( \( V_{BORFx} \) ), the device is put under reset again.

Warning: It is not allowed to configure BOR falling threshold ( \( V_{BORFx} \) ) to a value higher than BOR rising threshold ( \( V_{BORRx} \) ).

Figure 6. POR, PDR, and BOR thresholds

1. 1. The reset temporization \( t_{RSTTEMPO} \) starts when \( V_{DD} \) crosses \( V_{POR} \) threshold, indifferently from the configuration of the BOR Option bits.

For more details on the brown-out reset thresholds, refer to the electrical characteristics section in the datasheet.

4.2.2 Programmable voltage detector (PVD)

The PVD can be used to monitor the \( V_{DD} \) power supply by comparing it to the thresholds selected through PVDRT[2:0] bits (rising thresholds) and PVDFT[2:0] bits (falling thresholds) in the Power control register 2 (PWR_CR2) . \( V_{PVDfx} \) should always be set to a lower voltage level than \( V_{PVDfx} \) .

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available in the Power status register 2 (PWR_SR2) . It indicates if \( V_{DD} \) is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when \( V_{DD} \) drops below the PVD threshold and/or when \( V_{DD} \) rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example, the service routine could perform emergency shutdown tasks.

Figure 7. PVD thresholds

MSV45390V2

4.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wake-up sources.

The device features seven low-power modes:

• • Sleep mode: CPU clock off, all peripherals including Cortex ^® -M0+ core peripherals such as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event occurs. Refer to Section 4.3.4: Sleep mode .
• • Low-power run mode: This mode is achieved when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or the flash memory. The regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 4.3.2: Low-power run mode (LP run) .
• • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex ^® -M0+ is off. Refer to Section 4.3.5: Low-power sleep mode (LP sleep) .
• • Stop 0 and Stop 1 modes: SRAM and all registers content are retained. All clocks in the \( V_{CORE} \) domain are stopped, the PLL, the HSI16 and the HSE are disabled. The LSI and the LSE can be kept running.

The RTC and TAMP can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with the wake-up capability can enable the HSI16 RC during the Stop mode to detect their wake-up condition.

In Stop 0 mode, the main regulator remains ON, which allows the fastest wake-up time but with higher consumption. The active peripherals and wake-up sources are the same as in Stop 1 mode.

The system clock, when exiting Stop 0 or Stop 1 mode, is the HSISYS clock. If the device is configured to wake up in Low-power run mode, the HSIDIV bits in RCC_CR register must be configured prior to entering Stop mode to provide a frequency not greater than 2 MHz.

Refer to Section 4.3.6: Stop 0 mode for details on Stop 0 mode.

• • Standby mode: \( V_{CORE} \) domain is powered off.

However, it is possible to preserve SRAM content:

• – Standby mode with SRAM retention when the bit RRS is set in PWR_CR3 register. In this case, SRAM is supplied by the low-power regulator.
• – Standby mode when the bit RRS is cleared in PWR_CR3 register. In this case the main regulator and the low-power regulator are powered off.

All clocks in the \( V_{CORE} \) domain are stopped and the PLL, the HSI16, and the HSE oscillators are disabled. The LSI and the LSE oscillators can be kept running.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The system clock, when exiting Standby mode, is the HSI16 oscillator clock.

Refer to Section 4.3.8: Standby mode .

• • Shutdown mode: \( V_{CORE} \) domain is powered off. All clocks in the \( V_{CORE} \) domain are stopped, the PLL, the HSI16, the LSI and the HSE oscillators are disabled. The LSE can be kept running. The system clock, when exiting Shutdown mode, is the HSI16 oscillator clock. In this mode, the supply voltage monitoring is disabled and the product

behavior is not guaranteed in case of a power voltage drop. Refer to Section 4.3.9: Shutdown mode .

In addition, the power consumption in Run mode can be reduced by one of the following means:

• • Slowing down the system clocks
• • Gating the clocks to the APB and AHB peripherals when they are unused.

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption.

To further reduce the power consumption in Sleep/Stop modes, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

The peripheral clock gating is controlled by the RCC_AHBENR and RCC_APBENRx registers.

Disabling the peripherals clocks in Sleep/Stop modes can be performed automatically by resetting the corresponding bit in the RCC_AHBSMENR and RCC_APBSMENRx registers.

Debug mode

By default, the debug connection is lost if the user application puts the device in Stop 0, Stop1, Shutdown, or Standby mode while the debug features are used. This is due to the fact that the Cortex ^® -M0+ core is no longer clocked.

However, by setting some configuration bits in the DBG_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 40.9.1: Debug support for low-power modes .

Figure 8. Low-power modes state diagram

MSV45391V2

Table 26. Low-power mode summary

1. Refer to Table 27: Functionalities depending on the working mode .

Table 27. Functionalities depending on the working mode ⁽¹⁾

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated ON or OFF.

4. SRAM content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put OFF when the peripheral does not need it anymore.

6. If CSS is used on HSE clock in Low power run or Low power sleep modes, configure HSIDIV such as not to drive SYSCLK clock above the maximum frequency for either mode, in case of external clock failure detection.

7. Refer to Table 183: Instance implementation on STM32G0x1 for USART instances supporting FULL and BASIC feature set.

8. USART and LPUART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or received frame event.

9. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.

10. Only for STM32G0B1xx and STM32G0C1xx. Refer to Table 165: I2C implementation for more detail.

11. USB bus state monitoring is functional in Stop mode. It generates a wake-up interrupt upon resume from USB suspend.

12. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

13. I/Os with wake-up from Standby/Shutdown mode capability (WKUPx).

1. 14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting Shutdown mode.

4.3.1 Run mode

Slowing down system clocks

In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering Sleep mode.

For more details, refer to Clock configuration register (RCC_CFGR) .

4.3.2 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed 2 MHz.

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering Low-power run mode

To enter Low-power run mode, proceed as follows:

1. 1. Optional: Jump into the SRAM and power-down the flash memory by setting the FPD_LPRUN bit in the Power control register 1 (PWR_CR1) .
2. 2. Decrease the system clock frequency below 2 MHz.
3. 3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.

Refer to Table 28: Low-power run on how to enter Low-power run mode.

Exiting Low-power run mode

To exit Low-power run mode, proceed as follows:

1. 1. Force the regulator in main mode by clearing the LPR bit in the Power control register 1 (PWR_CR1) .
2. 2. Wait until REGLPF bit is cleared in the Power status register 2 (PWR_SR2) .
3. 3. Increase the system clock frequency.

Refer to Table 28: Low-power run on how to exit Low-power run mode.

4.3.3 Low-power modes

Entering low-power modes

The device enters low-power modes by executing the WFI (wait for interrupt), or WFE (wait for event) instructions, or when the SLEEPONEXIT bit in the Cortex ^® -M0+ system control register is set on return from ISR.

Entering low-power mode through WFI or WFE is executed only if no interrupt is pending or no event is pending.

Exiting low-power modes

The device exits Sleep and Stop low-power modes in a way depending on how the low-power mode was entered:

• • If the WFI instruction or Return from ISR was used to enter low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
• • If the WFE instruction is used to enter low-power mode, the device exits low-power mode as soon as an event occurs. The wake-up event can be generated either by:
  • – NVIC IRQ interrupt.

When SEVONPEND = 0 in the Cortex ^® -M0+ system control register: by enabling an interrupt in the peripheral control register and in the NVIC. When the device resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

When SEVONPEND = 1 in the Cortex ^® -M0+ system control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC. When the device resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

All NVIC interrupts wake the device up, even the disabled ones.

• – Event

Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

The device exits Standby and Shutdown low-power modes upon an external reset (NRST pin), a rising or falling edge on one of enabled WKUPx pins, or upon an RTC or TAMP event. On top of these, it exits Standby mode also upon an IWDG reset. See Figure 282 :

After waking up from Standby or Shutdown mode, program execution restarts in the same way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

4.3.4 Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The device enters Sleep mode according to section Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is clear.

Refer to Table 29: Sleep mode summary for details on how to enter Sleep mode.

Exiting Sleep mode

The device exits Sleep mode according to Exiting low-power modes .

Refer to Table 29: Sleep mode summary for more details on how to exit Sleep mode.

Table 29. Sleep mode summary

4.3.5 Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

The device enters Low-power sleep mode from Low-power run mode according to Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is clear.

Refer to Table 30: Low-power sleep mode summary for details on how to enter Low-power sleep mode.

Exiting Low-power sleep mode

The device exits Low-power sleep mode according to Exiting low-power modes . When exiting Low-power sleep mode by issuing an interrupt or an event, the device is in Low-power run mode.

Refer to Table 30: Low-power sleep mode summary for details on how to exit Low-power sleep mode.

Table 30. Low-power sleep mode summary

4.3.6 Stop 0 mode

The Stop 0 mode is based on the Cortex ^® -M0+ deepsleep mode combined with the peripheral clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all clocks in the V _CORE domain are stopped; the PLL, the HSI16 and the HSE oscillators are disabled. Some peripherals with the wake-up capability (I2C1, USART1, USART2, and LPUART1) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wake-up frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.

SRAM and register contents are preserved.

The BOR is available in Stop 0 mode.

The BOR and PDR can be activated to sample periodically the supply voltage. This option enabled by setting the ENB_ULP bit of the PWR_CR3 register allows decreasing the current consumption in this mode, but any drop of the voltage below the operating conditions between two active periods of the supply detector results in a non-generation of PDR reset.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop 0 mode

The device enters Stop 0 mode according to section Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is set.

Refer to Table 31: Stop 0 mode summary for details on how to enter Stop 0 mode.

If the flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB access is finished.

In Stop 0 mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started, it cannot be stopped except upon a reset. See Section 28.3: IWDG functional description .
• • real-time clock (RTC): this is configured by the RTCEN bit in the RTC domain control register (RCC_BDCR) .
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC domain control register (RCC_BDCR) .

Several peripherals can be used in Stop 0 mode and can add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1, LPTIM2, USART1, USART2, LPUART, and I2C1.

The DAC, the comparators, and the PVD can be used in Stop 0 mode.

The ADC, the VREFBUF buffer, and the temperature sensor can consume power during the Stop 0 mode, unless they are disabled before entering this mode.

Exiting Stop 0 mode

The device exits Stop 0 mode according to section Entering low-power modes .

Refer to Table 31: Stop 0 mode summary for details on how to exit Stop 0 mode.

When exiting Stop 0 mode by issuing an interrupt or a wake-up event, the HSISYS oscillator is selected as system clock. If the device is configured to wake up in Low-power run mode, the HSIDIV bits in RCC_CR register must be configured prior to entering Stop 0 mode to provide a frequency not greater than 2 MHz.

When exiting Stop 0 mode, the device is either in Run mode (Range 1 or Range 2 depending on VOS bit in PWR_CR1) or in Low-power run mode if the bit LPR is set in the Power control register 1 (PWR_CR1) .

Table 31. Stop 0 mode summary

4.3.7 Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the main regulator is off, and only the low-power regulator is on. Stop 1 mode can be entered from Run mode and from Low-power run mode.

Refer to Table 32: Stop 1 mode summary for details on how to enter and exit Stop 1 mode.

Table 32. Stop 1 mode summary

4.3.8 Standby mode

The Standby mode allows to achieve the lowest power consumption with BOR. It is based on the Cortex ^® -M0+ deepsleep mode, with the voltage regulators disabled (except when the SRAM content is preserved). The PLL, the HS16 and the HSE oscillators are also switched off.

The content of the registers is lost except for the registers in the RTC domain and Standby circuitry (see Figure 5 ). The SRAM content is lost except if the RRS bit is set in the PWR_CR3 register. In this case the low-power regulator is on and provides the supply to the SRAM only.

The BOR is available in Standby mode.

The BOR and PDR can be activated to sample periodically the supply voltage. This option enabled by setting the ENB_ULP bit of the PWR_CR3 register allows to decrease the current consumption in this mode, but any drop of the voltage below the operating conditions between two active periods of the supply detector results in a non-generation of PDR reset.

I/O states in Standby mode

In the Standby mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers (x=A, B, C, D, F), or with a pull-down (refer to PWR_PDCRx registers (x=A, B, C, D, F)), or can be kept in analog mode.

The RTC outputs on PC13 and PA4 are functional in Standby mode. PC14 and PC15 used for LSE are also functional. Up to six wake-up pins (WKUPx, x = 1 to 6) and the two tampers are available.

Entering Standby mode

The device enters Standby mode according to Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is set.

Refer to Table 33: Standby mode summary for details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 28.3: IWDG functional description .
• • Real-time clock (RTC) and tamper (TAMP): this is configured by the RTCEN bit in the RTC domain control register (RCC_BDCR)
• • Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status register (RCC_CSR).
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC domain control register (RCC_BDCR)

Exiting Standby mode

The device exits Standby mode according to section Entering low-power modes . The SBF status flag in the Power status register 1 (PWR_SR1) indicates that the device was in Standby mode. All registers are reset after wake-up from Standby except for Power control register 3 (PWR_CR3) .

Refer to Table 33: Standby mode summary for more details on how to exit Standby mode.

Table 33. Standby mode summary

4.3.9 Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The \( V_{\text{CORE}} \) domain is consequently powered off. The PLL, the HSI16, the LSI and the HSE oscillators are also switched off.

SRAM and register contents are lost except for registers in the RTC domain. The POR/PDR and BOR are not available in Shutdown mode. No power voltage monitoring is possible in this mode. As a result, the switch of the RTC domain to \( V_{\text{BAT}} \) supply when \( V_{\text{DD}} \) supply is lost is not supported.

I/O states in Shutdown mode

In the Shutdown mode, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx registers ( \( x=A, B, C, D, F \) ), or with a pull-down (refer to PWR_PDCRx registers ( \( x=A, B, C, D, F \) )), or can be kept in analog state. However this configuration is lost when exiting Shutdown mode due to the power-on reset.

The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE are also functional. Up to six wake-up pins (WKUPx, \( x = 1 \) to 6) and the two tampers are available.

Entering Shutdown mode

The device enters Shutdown mode according to section Entering low-power modes , when the SLEEPDEEP bit in the Cortex ^® -M0+ System Control register is set.

Refer to Table 34: Shutdown mode summary for details on how to enter Shutdown mode.

In Shutdown mode, the following features can be selected by programming individual control bits:

• • Real-time clock (RTC) and tamper (TAMP): this is configured by the RTCEN bit in the RTC domain control register (RCC_BDCR) .
• • External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RTC domain control register (RCC_BDCR) .

Caution: The RTC domain content is lost when \( V_{\text{DD}} \) is powered down under Shutdown mode.

Exiting Shutdown mode

The device exits Shutdown mode according to section Exiting low-power modes . A power-on reset occurs when exiting from Shutdown mode. All registers (except for the ones in the RTC domain), the WUFx bits in PWR_SR1 register inclusive, are reset upon wake-up from Shutdown.

Refer to Table 34: Shutdown mode summary for more details on how to exit Shutdown mode.

Table 34. Shutdown mode summary

4.3.10 Auto-wake-up from low-power mode

The RTC can be used to wake-up the device from low-power mode without depending on an external interrupt (Auto-wake-up mode). The RTC provides a programmable time base for waking up from Stop (0, 1), Shutdown or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR) :

• • Low-power 32.768 kHz external crystal oscillator (LSE OSC)
  This clock source provides a precise time base with very low-power consumption.
• • Low-power internal RC Oscillator (LSI)
  This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption.

To wake up from Stop mode with an RTC alarm or an RTC wake-up event, it is necessary to:

• • Configure the EXTI Line 19 to be sensitive to rising edge.
• • Configure the RTC to generate the wake-up event.

To wake up from Standby or Shutdown mode, there is no need to configure the EXTI line 19.

4.4 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

4.4.1 Power control register 1 (PWR_CR1)

Address offset: 0x00

Reset value: 0x0000 0208

This register is reset after wake-up from Standby mode.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR : Low-power run

When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).

Bits 13:11 Reserved, must be kept at reset value.

Bits 10:9 VOS : Voltage scaling range selection

00: Cannot be written (forbidden by hardware)

01: Range 1

10: Range 2

11: Cannot be written (forbidden by hardware)

Bit 8 DBP : Disable RTC domain write protection

In reset state, the RTC and backup registers are protected against parasitic write access.

This bit must be set to enable write access to these registers.

0: Access to RTC and backup registers disabled

1: Access to RTC and backup registers enabled

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 FPD_LPSLP : Flash memory powered down during Low-power sleep mode

This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power sleep mode.

0: Flash memory idle

1: Flash memory powered down

Bit 4 FPD_LPRUN : Flash memory powered down during Low-power run mode

This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Low-power run mode. The flash memory can be put in power-down mode only when the user code is executed from SRAM.

0: Flash memory idle
1: Flash memory powered down

Bit 3 FPD_STOP : Flash memory powered down during Stop mode

This bit determines whether the flash memory is put in power-down mode or remains in idle mode when the device enters Stop mode.

0: Flash memory idle
1: Flash memory powered down

Bits 2:0 LPMS[2:0] : Low-power mode selection

These bits select the low-power mode entered when CPU enters deepsleep mode.

000: Stop 0 mode
001: Stop 1 mode
010: Reserved
011: Standby mode
1xx: Shutdown mode

Note: In Standby mode, SRAM contents are retained or not, depending on RRS bit setting in PWR_CR3.

4.4.2 Power control register 2 (PWR_CR2)

Address offset: 0x04

Reset value: 0x0000 0100

This register is reset when exiting Standby mode.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 PVM_VDDIO2[2:0] : V _DDIO2 supply voltage monitoring

This bitfield controls the voltage monitoring of V _DDIO2 with respect to 1.2 V threshold and the IOs in the V _DDIO2 domain.

000: Monitoring disabled; IOs in isolation mode

001: Monitoring enabled; IOs enabled or in isolation mode, according to V _DDIO2 level

110: Monitoring bypassed; IOs enabled

Other: Reserved

Note: This bitfield is only applicable on STM32G0B1xx and STM32G0C1xx. It is reserved on the other products.

Bit 7 PVMENDAC : DAC supply voltage monitoring enable

This bit enables the monitoring of the DAC supply with respect to 1.8 V threshold.

0: Disable

1: Enable

Bits 6:4 PVDRT[2:0] : Programmable voltage detector rising threshold selection.

These bits select the PVD rising threshold:

000: V _PVDR0 (around 2.1 V)

001: V _PVDR1 (around 2.2 V)

010: V _PVDR2 (around 2.5 V)

011: V _PVDR3 (around 2.6 V)

100: V _PVDR4 (around 2.7 V)

101: V _PVDR5 (around 2.9 V)

110: V _PVDR6 (around 3.0 V)

111: PVD_IN pin voltage

Note: If this bitfield is set to 111, the voltage on PVD_IN pin is internally compared with V _REFINT for both rising and falling threshold and the PVDFT[2:0] bitfield has no effect.

Note: These bits are write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset.

Bits 3:1 PVDFT[2:0] : Programmable voltage detector falling threshold selection.

These bits select the PVD falling threshold:

000: V _PVDF0 (around 2.0 V)

001: V _PVDF1 (around 2.2 V)

010: V _PVDF2 (around 2.4 V)

011: V _PVDF3 (around 2.5 V)

100: V _PVDF4 (around 2.6 V)

101: V _PVDF5 (around 2.8 V)

110: V _PVDF6 (around 2.9 V)

111: Not used

Note: The setting of this bitfield is ignored as long as the bitfield PVDRT[2:0] is set to 111.

Note: These bits are write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset.

Bit 0 PVDE : Programmable voltage detector enable

0: Programmable voltage detector disable.

1: Programmable voltage detector enable.

Note: This bit is write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2 register. The protection can be reset only by a system reset.

4.4.3 Power control register 3 (PWR_CR3)

Address offset: 0x08

Reset value: 0x0000 8000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 EIWUL : Enable internal wake-up line

0: Disable

1: Enable

Bits 14:11 Reserved, must be kept at reset value.

Bit 10 APC : Apply pull-up and pull-down configuration

This bit determines whether the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied.

0: Not applied

1: Applied

Bit 9 ENB_ULP : Ultra-low-power enable

Enable/disable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset.

0: Disable (the supply voltage is monitored continuously)

1: Enable

When set, the supply voltage is sampled for PDR/BOR reset condition only periodically and not continuously, in order to save power.

Caution: When enabled, and if the supply voltage drops below the minimum operating condition between two supply voltage samples, the reset condition is missed and no reset is generated.

Bit 8 RRS : SRAM retention in Standby mode

The bit determines whether the SRAM is powered (from low-power regulator) and retains its contents, or unpowered and loses its contents.

0: Unpowered - contents lost

1: Powered - contents retained

Bits 7:6 Reserved, must be kept at reset value.

When this bit is set, the WKUP6 external wake-up pin is enabled and triggers a wake-up from Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is configured through WP6 bit in the PWR_CR4 register.

When this bit is set, the WKUP5 external wake-up pin is enabled and triggers a wake-up from Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is configured via the WP5 bit in the PWR_CR4 register.

When this bit is set, the WKUP4 external wake-up pin is enabled and triggers a wake-up from Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register.

When this bit is set, the WKUP3 external wake-up pin is enabled and triggers a wake-up from Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is configured via the WP3 bit of the PWR_CR4 register.

When this bit is set, the WKUP2 external wake-up pin is enabled and triggers a wake-up from Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is configured via the WP2 bit of the PWR_CR4 register.

When this bit is set, the WKUP1 external wake-up pin is enabled and triggers a wake-up from Standby or Shutdown mode when a rising or a falling edge occurs. The active edge is configured via the WP1 bit of the PWR_CR4 register.

4.4.4 Power control register 4 (PWR_CR4)

Address offset: 0x0C

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 VBR : V _BAT battery charging resistor selection

0: 5 kΩ
1: 1.5 kΩ

Bit 8 VBE : V _BAT battery charging enable

0: Disable
1: Enable

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 WP6 : WKUP6 wake-up pin polarity

WKUP6 external wake-up signal polarity (level or edge) triggering wake-up event:
0: High level or rising edge
1: Low level or falling edge

Bit 4 WP5 : WKUP5 wake-up pin polarity

WKUP5 external wake-up signal polarity (level or edge) triggering wake-up event:
0: High level or rising edge
1: Low level or falling edge

Bit 3 WP4 : WKUP4 wake-up pin polarity

WKUP4 external wake-up signal polarity (level or edge) triggering wake-up event:
0: High level or rising edge
1: Low level or falling edge

Bit 2 WP3 : WKUP3 wake-up pin polarity

WKUP3 external wake-up signal polarity (level or edge) triggering wake-up event:
0: High level or rising edge
1: Low level or falling edge

Bit 1 WP2 : WKUP2 wake-up pin polarity

WKUP2 external wake-up signal polarity (level or edge) triggering wake-up event:
0: High level or rising edge
1: Low level or falling edge

Bit 0 WP1 : WKUP1 wake-up pin polarity

WKUP1 external wake-up signal polarity (level or edge) triggering wake-up event:
0: High level or rising edge
1: Low level or falling edge

4.4.5 Power status register 1 (PWR_SR1)

Address offset: 0x10

Reset value: 0x0000 0000

Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI : Wake-up flag internal

This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all internal wake-up sources are cleared.

Bits 14:9 Reserved, must be kept at reset value.

Bit 8 SBF : Standby flag

This bit is set by hardware when the device enters Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset.

0: The device did not enter Standby mode

1: The device entered Standby mode

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 WUF6 : Wake-up flag 6

This bit is set when a wake-up event is detected on WKUP6 wake-up pin. It is cleared by writing 1 in the CWUF6 bit of the PWR_SCR register.

Bit 4 WUF5 : Wake-up flag 5

This bit is set when a wake-up event is detected on WKUP5 wake-up pin. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register.

Bit 3 WUF4 : Wake-up flag 4

This bit is set when a wake-up event is detected on WKUP4 wake-up pin. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register.

Bit 2 WUF3 : Wake-up flag 3

This bit is set when a wake-up event is detected on WKUP3 wake-up pin. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register.

Bit 1 WUF2 : Wake-up flag 2

This bit is set when a wake-up event is detected on WKUP2 wake-up pin. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register.

Bit 0 WUF1 : Wake-up flag 1

This bit is set when a wake-up event is detected on WKUP1 wake-up pin. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register.

4.4.6 Power status register 2 (PWR_SR2)

Address offset: 0x14

Reset value: 0b0000 0000 0000 0000 X00X XXXX X000 0000 (The bits in this register reflect the actual status.)

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PVMODAC : \( V_{DDA} \) monitoring output flag

This flag indicates the readiness of the \( V_{DDA} \) supply voltage (excess of PWM threshold of about 1.8 V).

0: \( V_{DDA} \) ready

1: \( V_{DDA} \) not ready

The flag is cleared when the PWM of the DAC is disabled (PWMENDAC = 0).

Bit 14 Reserved, must be kept at reset value.

Bit 13 PVMOVDDIO2 : \( V_{DDIO2} \) supply voltage monitoring output flag

This flag indicates the readiness of the \( V_{DDIO2} \) supply voltage (excess of 1.2 V).

0: \( V_{DDIO2} \) ready

1: \( V_{DDIO2} \) not ready

The flag is cleared when the PWM of \( V_{DDIO2} \) is disabled (PWM_VDDIO2[0] = 0).

Note: This bitfield is only applicable on STM32G0B1xx and STM32G0C1xx. It is reserved on the other products.

Bit 12 Reserved, must be kept at reset value.

Bit 11 PVDO : Programmable voltage detector output

0: \( V_{DD} \) is above the selected PVD threshold

1: \( V_{DD} \) is below the selected PVD threshold

Bit 10 VOSF : Voltage scaling flag

A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.

0: The regulator is ready in the selected voltage range

1: The regulator output voltage is changing to the required voltage level

Bit 9 REGLPF : Low-power regulator flag

This flag is controlled by hardware. It indicates the regulator from which the core domain is currently supplied. The core domain is supplied from the low-power regulator (LPR) while the device is in Low-power run mode. Upon transiting to Run mode, it remains supplied from the LPR until the main regulator (MR) becomes ready. Poll this flag before increasing the product frequency.

0: The core domain is supplied from the main regulator (MR)

1: The core domain is supplied from the low-power regulator (LPR)

Bit 8 REGLPS : Low-power regulator started

This bit provides the information whether the low-power regulator is ready after a power-on reset or Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased.

0: The low-power regulator is not ready

1: The low-power regulator is ready

Bit 7 FLASH_RDY : Flash ready flag

This bit is set by hardware to indicate when the flash memory is ready to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STOP bits.

0: Flash memory in power-down

1: Flash memory ready to be accessed

Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is set, prior to jumping to flash memory.

Bits 6:0 Reserved, must be kept at reset value.

4.4.7 Power status clear register (PWR_SCR)

Address offset: 0x18

Reset value: 0x0000 0000

Access: three additional APB cycles are needed to write this register, compared to a standard APB write.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSBF : Clear standby flag

Setting this bit clears the SBF flag in the PWR_SR1 register.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 CWUF6 : Clear wake-up flag 6

Setting this bit clears the WUF6 flag in the PWR_SR1 register.

Bit 4 CWUF5 : Clear wake-up flag 5

Setting this bit clears the WUF5 flag in the PWR_SR1 register.

Bit 3 CWUF4 : Clear wake-up flag 4

Setting this bit clears the WUF4 flag in the PWR_SR1 register.

• Bit 2 CWUF3 : Clear wake-up flag 3
  Setting this bit clears the WUF3 flag in the PWR_SR1 register.
• Bit 1 CWUF2 : Clear wake-up flag 2
  Setting this bit clears the WUF2 flag in the PWR_SR1 register.
• Bit 0 CWUF1 : Clear wake-up flag 1
  Setting this bit clears the WUF1 flag in the PWR_SR1 register.

4.4.8 Power Port A pull-up control register (PWR_PUCRA)

Address offset: 0x20

Reset value: 0x0000 0000

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

Bits 31:16 Reserved, must be kept at reset value.

• Bits 15:0 PUy : Port A pull-up bit y (y = 15 to 0)
  Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PA[y] I/O.

4.4.9 Power Port A pull-down control register (PWR_PDCRA)

Address offset: 0x24

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port A pull-down bit y (y = 15 to 0)

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PA[y] I/O.

4.4.10 Power Port B pull-up control register (PWR_PUCRB)

Address offset: 0x28

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port B pull-up bit y (y = 15 to 0)

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PB[y] I/O.

4.4.11 Power Port B pull-down control register (PWR_PDCRB)

Address offset: 0x2C

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port B pull-down bit y (y = 15 to 0)

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PB[y] I/O.

4.4.12 Power Port C pull-up control register (PWR_PUCRC)

Address offset: 0x30

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port C pull-up bit y (y = 15 to 0) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PC[y] I/O.

1. 1. In STM32G031xx and STM32G041xx as well as STM32G051xx and STM32G061xx devices, the bits PD0 to PD5 and PD8 to PD12 are reserved.

4.4.13 Power Port C pull-down control register (PWR_PDCRC)

Address offset: 0x34

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port C pull-down bit y (y = 15 to 0) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PC[y] I/O.

1. 1. In STM32G031xx and STM32G041xx as well as STM32G051xx and STM32G061xx devices, the bits PD0 to PD5 and PD8 to PD12 are reserved.

4.4.14 Power Port D pull-up control register (PWR_PUCRD)

Address offset: 0x38

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port D pull-up bit y (y = 15 to 0) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PD[y] I/O.

1. 1. In STM32G071xx and STM32G081xx devices, the bits PU15 to PU10 and PU7 are reserved. In STM32G031xx and STM32G041xx as well as in STM32G051xx and STM32G061xx devices, PU15 to PU4 are reserved.

4.4.15 Power Port D pull-down control register (PWR_PDCRD)

Address offset: 0x3C

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port D pull-down bit y (y = 15 to 0) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PD[y] I/O.

1. 1. In STM32G071xx and STM32G081xx devices, the bits PD15 to PD10 and PD7 are reserved. In STM32G031xx and STM32G041xx as well as in STM32G051xx and STM32G061xx devices, PD15 to PD4 are reserved.

4.4.16 Power Port E pull-up control register (PWR_PUCRE)

Address offset: 0x40

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PUy : Port E pull-up bit y (y = 15 to 0) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PE[y] I/O.

1. 1. Only applies to STM32G0B1xx and STM32G0C1xx devices. Reserved for the other devices.

4.4.17 Power Port E pull-down control register (PWR_PDCRE)

Address offset: 0x44

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PDy : Port E pull-down bit y (y = 15 to 0) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PE[y] I/O.

1. 1. Only applies to STM32G0B1xx and STM32G0C1xx devices. Reserved for the other devices.

4.4.18 Power Port F pull-up control register (PWR_PUCRF)

Address offset: 0x48

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 PUy : Port F pull-up bit y (y = 13 to 0) ⁽¹⁾

Setting PUy bit while the corresponding PDy bit is zero and the APC bit of the PWR_CR3 register is set activates a pull-up device on the PF[y] I/O.

1. 1. Bits PU13 to PU3 only applies to STM32G0B1xx and STM32G0C1xx devices. Reserved for the other devices.

4.4.19 Power Port F pull-down control register (PWR_PDCRF)

Address offset: 0x4C

Reset value: 0x0000 0000

Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).

This register is neither reset upon exiting Standby mode nor with the PWRRST bit of the APB peripheral reset register 1 (RCC_APBSTR1) .

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 PDy : Port F pull-down bit y (y = 13 to 0) ⁽¹⁾

Setting PDy bit while the APC bit of the PWR_CR3 register is set activates a pull-down device on the PF[y] I/O.

1. 1. Bits PU13 to PU3 only applies to STM32G0B1xx and STM32G0C1xx devices. Reserved for the other devices.

4.4.20 PWR register map

Table 35. PWR register map and reset values

Table 35. PWR register map and reset values (continued)

Refer to Section 2.2 on page 60 for the register boundary addresses.